JP2002340950A - Semiconductor device test system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten processing time by simultaneously measuring harmonics to the n-th harmonics. SOLUTION: In the case of measuring the harmonics of a semiconductor device DUT, a contact of a switching means 10 is controlled in such a way as to switch to the side of a frequency multiplication mixing means 11 by a control signal from a processing device 2. A signal LO from an LO signal source 9 and a signal RF from the semiconductor device DUT are inputted to the frequency multiplication mixing means 11. The frequency multiplication mixing means 11 performs addition and subtraction on n-times the signal LO and a signal RF, and outputs an obtained value as an intermediate frequency signal IF. Only low frequencies of the signal IF are passed by an LPF and inputted to a transmitter tester 5. The transmitter tester 5 converts the signal IF into digital data and performs FFT analysis on the converted digital data. By this, a harmonic component is isolated to analyze frequencies and levels.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device test system for measuring various characteristics such as frequency characteristics and level (power) characteristics of a semiconductor device.

[0002]

2. Description of the Related Art For example, mobile communication equipment, ITS (intelli
For semiconductor devices composed of composite devices such as amplifiers, mixers, and switches of gent transport systems), frequency characteristics and level (power) characteristics are measured using a semiconductor device test system (hereinafter abbreviated as a test system). You.

FIG. 8 is a block diagram of a conventional test system. As shown in FIG. 8, in order to measure the frequency characteristics and level (power) characteristics of a semiconductor device, a processing device 50 such as a personal computer, a signal generator 51, and a transmitter tester (characteristic measuring device) 52 are GP-based. The test system 54 connected by the IB interface 53 is used.

[0004] The processing device 50 outputs setting information of the measurement frequency and the level to the signal generator 51 and the transmitter tester 52 by a GP-IB command, respectively. Signal generator 51
Generates a signal at the set frequency and level and outputs the signal to the semiconductor device. The transmitter tester 52 measures the characteristics of the semiconductor device at a frequency set similarly to the signal generator 51, and outputs the measured level to the processing device 50 in response to the level acquisition request.

[0005] The processing device 50 is provided with a frequency (for example, 1 MHz from 10 MHz to 3000 MHz) required for characteristic measurement.
The setting information of the measurement frequency and level of the signal generator 51 and the transmitter tester 52 is set by the GP-IB command for 300 times (0 MHz step).

Thus, the frequency characteristics and level characteristics of the semiconductor device are automatically measured over a predetermined frequency range.

By the way, in this type of test system 54, when measuring the harmonics of a semiconductor device, the frequencies of the signal generator and the transmitter tester are set to the fundamental wave, the second harmonic, the third harmonic, and so on. Then, the measurement was performed by sequentially switching the frequency.

FIG. 9 shows a PDC (Personal Digital).
5 shows an example of a time chart when a harmonic measurement of a (Cellular) is performed. That is, FIG.
(893 MHz), F2 (925 MHz), F3 (95
This is an example in which each of the frequencies F1 to F3 is measured up to the third harmonic using 8 MHz as a fundamental wave. In the example of FIG. 9, the frequency switching time is 40 ms, and the FF per frequency
The T (fast Fourier transform) calculation time is 30 ms.

As shown in FIG. 9, in the conventional test system 54, first, the frequency is switched to the frequency F1 in the first 70 ms, and the FFT operation is performed. Frequency F in the next 70 ms
FFT by switching to 1 * 2 (second harmonic of F1)
Perform the operation. Further, in the next 70 ms, the frequency F1 * 3
(3rd harmonic of F1) and perform FFT operation. Hereinafter, similarly, the frequency is changed to F2, F2 * 2 (F
2, 2nd harmonic), F2 * 3 (3rd harmonic of F2), F
3, F3 * 2 (second harmonic of F3) and F3 * 3 (third harmonic of F3) are set sequentially and FF is set for each frequency.
Perform T operation.

Therefore, in the conventional test system 54, when the harmonic measurement of the PDC as shown in FIG. 9 is performed, a total time of 70 ms of the frequency switching time and the FFT operation time is required for each frequency, and the whole time is required. Measurement time of 7
A time of 0 ms × 9 times = 630 ms was required.

[0011]

As described above, in the conventional test system 54, the harmonics are measured by sequentially switching and setting the frequency and performing the FFT operation. In addition to the fact that the frequency switching in the transmitter tester is slow, the entire measurement time becomes long, and the measurement of the nth harmonic cannot be performed at once.

Accordingly, the present invention has been made in view of the above problems, and has as its object to provide a semiconductor device test system capable of measuring up to the nth harmonic at a time and increasing the processing speed. And

[0013]

In order to achieve the above object, according to the first aspect of the present invention, a frequency of a local signal is set in accordance with a measured frequency of a signal from a semiconductor device DUT. In the semiconductor device test system 1 that mixes the signal from the semiconductor device and converts the signal into an intermediate frequency, and processes the converted intermediate frequency signal in a digital waveform, the frequency-multiplied signal and the signal from the semiconductor device are compared with each other. And a harmonic module 4 having a frequency multiplying means 11 for outputting an intermediate frequency signal obtained by mixing the frequency components, and a data processing for separating digital components of the intermediate frequency signal output from the harmonic module by FFT analysis to separate harmonic components. And a unit 25.

According to a second aspect of the present invention, in the semiconductor device test system of the first aspect, the data processing section 25 is provided.
A converts the intermediate frequency signal into digital data.
A plurality of pairs of a / D conversion unit 27 and a processing unit 28 including a processor that separates a harmonic component by performing FFT analysis on the digital data converted by the A / D conversion unit; A / D converter switching means 29 for electrically connecting any one of the A / D converters to the harmonic module is provided between the A / D converter 4 and the plurality of A / D converters. The plurality of A / D conversion units are sequentially switched and controlled, and the signal processing by the plurality of processing units is performed in parallel.

According to a third aspect of the present invention, in the semiconductor device test system of the first aspect, the data processing unit 25
A converts the intermediate frequency signal into digital data.
An A / D converter 27, and a plurality of processors 28 including a processor for performing FFT analysis on the digital data converted by the A / D converter and separating harmonic components, and performing signal processing by the plurality of processors. Are performed in parallel.

According to a fourth aspect of the present invention, in the semiconductor device test system according to any one of the first to third aspects, the frequency multiplying / mixing means 11 is a sampler, a harmonic mixer, or a combination of a multiplier and a mixer. It is characterized by comprising.

[0017]

FIG. 1 is a diagram showing a schematic configuration of a test system according to the present invention, FIG. 2 is a block diagram showing an internal configuration of the system, and FIG. 3 is a block diagram showing an internal configuration of a transmitter tester of the system. FIG.

The test system 1 of this embodiment includes a processing device 2
It comprises a signal generator 3, a harmonic module 4, and a transmitter tester (characteristic measuring device) 5.

Semiconductor device DUT as object to be measured
Are mobile communication devices, ITS (intelligent trans
port systems) composed of composite devices such as amplifiers, mixers, and switches. The semiconductor device DUT is electrically connected to a signal generator 3 via a signal cable in a state where the semiconductor device DUT is mounted on a test fixture (not shown), and is electrically connected to a transmitter tester 5 via a harmonic module 4. Connected.

The processing device 2 is constituted by a terminal device such as a personal computer, for example, and has a CPU 2a, a data storage means 2b for storing measurement data, a ROM and a RAM for storing a control program and the like.

Further, the processing device 2 is a GP-IB or RS2
An interface such as 23C is provided, and a control procedure (control method) is registered in each setting table of the signal generator 3, the harmonic module 4, and the transmitter tester 5.

That is, the processing device 2 transmits various parameters for initial setting based on the measurement conditions to the signal generator 3, the harmonic module 4, and the transmission unit through an interface such as GP-IB or RS223C before the start of the measurement. It is sent to the machine tester 5 and set. The parameters include a frequency band in which characteristics are measured, a measurement frequency step, a level at each frequency, and the like.

As shown in FIG. 2, the signal generator 3 includes signal generating means 6 for generating and outputting a test signal (measurement signal) supplied to the semiconductor device DUT. The signal generated and output from the signal generation means 6 is controlled based on the measurement conditions set in the procedure storage means 7.

The procedure storing means 7 sets a plurality of frequencies and levels of the signal output from the signal generating means 6 in a predetermined frequency band at predetermined frequency steps based on the parameters of the initial setting sent from the processing device 2. . This setting content is stored in the setting table 7a.

The synchronizing means 8 has a trigger interface, controls the start of measurement based on a trigger (single pulse trigger signal) from the processing device 2, and generates and outputs a signal from the signal generating means 6. Then, after the start of the measurement, the synchronization means 8 operates the processing device 2 via the trigger interface.
Each time a trigger is received, the frequency and level of the signal set in the setting table 7a are sequentially read out at each frequency step and output to the signal generating means 6 is repeated.

As shown in FIGS. 1 and 2, the harmonic module 4 includes a local signal source 9, a switching unit 10, and a frequency multiplication unit 11.

A local signal source (LO signal source) 9 is a local signal input to the frequency doubler 11 at the time of measuring a harmonic, or the transmitter tester 5 at the time of measuring the frequency characteristics and power (level) of a normal semiconductor device DUT. It generates and outputs a local signal to be input to. As shown in FIG. 2, the local signal source 9 includes a signal generation unit 12, a procedure storage unit 13, and a synchronization unit 14.

The signal generator 12 supplies a local signal to the frequency multiplier mixer 11 or the transmitter tester 5. The signal generating means 12 is provided with a procedure storing means 13
The signal to be generated and output is controlled based on the measurement conditions set in (1).

The procedure storing means 13 stores the signal generating means 1 based on the initial setting parameters sent from the processing device 2.
A plurality of frequencies and levels of the signal output from 2 are set for each predetermined frequency step in a predetermined frequency band. This setting content is stored in the setting table 13a.

The synchronizing means 14 has a trigger interface, controls the start of measurement based on a trigger from the processing device 2, and generates and outputs a signal from the signal generating means 12. Then, after the start of the measurement, the synchronization unit 14
Each time a trigger (single-pulse trigger signal) is received, the frequency and level of the signal set in the setting table 13a are sequentially read out at each frequency step and output to the signal generating means 12 is repeated.

The switching unit 10 switches between inputting the signal from the semiconductor device DUT directly to the transmitter tester 5 or inputting the signal to the transmitter tester 5 via the frequency multiplication unit 11. . The switching means 10 is switch-controlled by a control signal from the processing device 2. In this example, when performing the harmonic measurement of the semiconductor device DUT,
The contact of the switching means 10 is switched to the frequency multiplication means 11 side.

The frequency multiplication means 11 comprises a sampler,
It is composed of a single product such as a harmonic mixer, or a combination of a multiplier (frequency multiplier) and a mixer. The frequency multiplication unit 11 adds / subtracts n times the signal LO from the LO signal source 9 and the RF signal from the semiconductor device DUT, and outputs the result as an intermediate frequency signal IF.

For example, a signal RF input from a semiconductor device DUT has a frequency of 1000 MHz (fundamental wave), 2000 MHz
Hz (second harmonic) and 3000 Mz (third harmonic).

Now, let the signal LO mixed with the signal RF be 11
If 0.53 MHz is set, only the signals before and after the main part are extracted from IF = LO × n ± RF × m. IF0x = ABS (1000 MHz−110.53 MH
z × 10) = 105.3 MHz IF1x = ABS (1000 MHz−110.53 MH)
z × 9) = 5.32 MHz IF2x = ABS (1000 MHz−110.53 MH)
z × 8) = 115.76 MHz IF0y = ABS (1000 MHz−110.53 MH)
z × 10) = 100.07 MHz IF1y = ABS (1000 MHz−110.53 MH)
z × 9) = 10.46 MHz IF2y = ABS (1000 MHz−110.53 MH)
z × 8) = 120.99 MHz IF0z = ABS (1000 MHz−110.53 MH)
z × 10) = 94.84 MHz IF1z = ABS (1000 MHz−110.53 MH)
z × 9) = 15.69 MHz IF2z = ABS (1000 MHz−110.53 MH)
z × 8) = 126.22 MHz.

In the above description, it is assumed that a signal RF having a fundamental frequency of 1000 MHz is input from the semiconductor device DUT to the frequency doubling / mixing means 11 in order to make the description easy to understand. In the measurement, a signal having a fundamental wave of 893 MHz, 925 MHz, and 958 MHz is input from the semiconductor device DUT to the frequency doubler 11. Also, in the harmonic measurement of W-CDMA, 1920 MHz, 1950 MHz, 198
A signal having a fundamental wave of 0 MHz is input from the semiconductor device DUT to the frequency doubler 11.

When the signal IF output from the frequency doubler 11 is passed through the LPF, only the low frequency, which is an IFxyz component, is taken out, and a waveform in which the IFxyz component is synthesized is obtained.

After that, the above-mentioned waveform is fetched into a data processing section of the transmitter tester 5 to be described later, and an FFT (fast Fourier tr
If ansform (fast Fourier transform) operation is performed, signals from IFx to IFz can be separated, and the level of the signal RF can be converted from this value. As a result, up to the nth harmonic can be measured at high speed by a single data capture and FFT operation.

The signal IF output from the frequency multiplying / mixing means 11 has a higher signal level as the order (n) is lower, and a sufficient dynamic range cannot be obtained unless a signal having this higher level is cut. For this reason, it is preferable to provide an LPF for band limitation at the subsequent stage of the frequency doubler 11. The LPF in the above example cuts a signal near 100 MHz and passes a signal of 20 MHz or less.

The transmitter tester 4 includes a semiconductor device DUT including a harmonic measurement of the semiconductor device DUT based on the intermediate frequency signal IF from the frequency multiplying / mixing means 11.
Signal measuring means 15 for measuring the frequency characteristic and the level (power) characteristic of the signal. The signal measurement unit 15 performs measurement for each measurement frequency based on the measurement conditions set in the procedure storage unit 16.

The procedure storing means 16 stores the signal measuring means 1 based on the initial setting parameters sent from the processing device 2.
A plurality of signals to be measured in 5 are set for each predetermined frequency step in a predetermined frequency band. This setting content is stored in the setting table 16a.

The synchronizing means 17 has a trigger interface, and controls the start of measurement by the signal measuring means 15 based on a trigger (single pulse trigger signal) from the processing device 2. Then, after the start of the measurement, the synchronization means 17
Each time a trigger is received, the frequency of the signal set in the setting table 16a is sequentially read out at each frequency step and output to the signal measuring means 15 is repeated.

Further, the transmitter tester 5 includes a data processing section 25 and a display section 26 as shown in FIG.

The data processing unit 25 includes an A / D conversion unit 27,
A processing unit 28 is provided. The A / D converter 27 converts the intermediate frequency signal IF converted by the frequency multiplication means 11 and band-limited by the LPF, or the semiconductor device DU.
The intermediate frequency signal IF directly input from T and frequency-converted is converted into digital data.

The processing section 28 includes a data storage section 28a and a signal processing section 28b, and is constituted by a processor such as a DSP. The data storage unit 28a stores and stores digital data converted by the A / D conversion unit 27. The signal processing unit 28b processes the digital data stored in the data storage unit 28a, and displays the processing result on the display unit 26. Also, the signal processing unit 28b
When processing the signal IF input via the frequency multiplication means 11, the digital data from the A / D converter 27 is subjected to FFT analysis, and the time waveform obtained by combining the harmonics is plotted on the frequency axis. It converts and separates harmonic components, and analyzes frequency and level.

FIG. 4 is a flowchart showing the measuring operation of the test system 1 configured as described above.

In the test system 1 of this embodiment, when the processing device 2 outputs a trigger for starting the measurement at the start of the measurement, the signal generator 3 determines the starting frequency and level stored in the setting table 7a by the signal generating means 6. Set to. The signal generation means 6 generates and outputs a signal of this frequency and level (SP1).

The transmitter tester 5 sets the starting frequency stored in the setting table 16a in the signal measuring means 15 based on the input of the trigger output from the processing device 2.

The LO signal source 9 sets the starting frequency stored in the setting table 13a in the signal generating means 12 based on the input of the trigger output from the processing device 2. With the above settings, the signal measuring means 15 of the transmitter tester 5 measures the output level of the semiconductor device DUT at this frequency (SP2). Thereby, the measurement at the measurement start frequency is performed.

Next, the signal generator 3 generates a signal at the next frequency and level stored in the setting table 7a each time a trigger is input from the processing device 2. Also,
The LO signal source 9 sets the frequency stored in the setting table 13a to the signal generator 12 every time a trigger from the processing device 2 is input. And the transmitter tester 5
Each time a trigger of the processing apparatus 2 is input, measurement of the semiconductor device at the next frequency stored in the setting table 16a is performed.

Thereafter, when a trigger is input from the processing device 2 to the signal generator 3, the transmitter tester 5, and the LO signal source 9, measurement at predetermined frequency steps is automatically executed until the last set frequency is reached ( SP3).

In the above measurement, the semiconductor device DUT
When the higher harmonic measurement is performed, the contact point of the switching unit 10 is switched to the frequency double mixing unit 11 by the control signal from the processing device 2. As a result, the signal LO from the LO signal source 9 and the signal RF from the semiconductor device DUT are input to the frequency doubler 11. The frequency doubler 11 adds and subtracts n times the signal LO from the LO signal source 9 and the signal RF to generate an intermediate frequency signal IF.
Output as This intermediate frequency signal IF is input to the data processing unit 25 of the transmitter tester 5 after passing only the low frequency by the band limiting filter (low pass filter: LPF). In the A / D conversion unit 27 of the data processing unit 25,
The signal input from the LPF is converted into digital data. The converted digital data is sent to the signal processing unit 28
FFT analysis is performed by b. As a result, the frequency and level are analyzed by separating the harmonic components.

Here, FIG. 5 shows a test system of the present example including the transmitter tester 4 adopting the configuration of FIG. 3, in which harmonics are measured up to the third harmonic for each of the frequencies F1, F2 and F3. It is a time chart which shows an example of a wave measurement time.

FIG. 5 shows a PDC (Personal Digita).
l In the measurement of harmonics of Cellular), the frequency F1 (89
3MHz), F2 (925MHz), F3 (958MH)
This is an example in which each of the frequencies F1 to F3 is measured up to the third harmonic using z) as a fundamental wave.

FIG. 5 is a comparison with FIG.
Similarly to the above, the frequency switching time is 40 ms, and the FFT calculation time per frequency is 30 ms.

In the example of FIG. 5, first, the frequency is switched to F1 in the first 70 ms, and the FFT operation is performed. At this time, the second harmonic of the frequency F1 (F1 *
2) and the third harmonic (F1 * 3) are output to the data processing unit 25 of the transmitter tester 5 together with the measurement of the frequency F1. Thereby, harmonics F1 * 2, F1 of frequency F1
* 3 Frequency switching time is reduced, and in the next 60 ms F
The FFT operation of 1 * 2 and F1 * 3 is performed. Hereinafter, similarly, F2 and its second harmonic (F2 * 2) and third harmonic (F2 * 3), F3 and its second harmonic (F3 * 2) and third harmonic (F3 * 3) ) Is measured. In the case of this example, the processing time can be reduced by 210 ms as compared with the example of FIG.

In the test system 1 described above, a set of data processing units 2 of the transmitter tester 5 shown in FIG.
5, the intermediate frequency signal I from the harmonic module 4
Although the processing has been described as processing F, the signal processing may be performed by the configuration shown in FIG.

The data processing unit 25 in the example of FIG.
The / D conversion unit 27 and the processing unit 28 are provided in pairs and provided in three sets. Each A / D converter 27 (27A, 27B, 27
C) is set to L by the switching selection of the A / D converter switching means 29.
When connected to the PF, the frequency multiplication means 1
The signal IF inputted from 1 through the LPF is converted into digital data.

Each processing unit 28 (28A, 28B, 28C)
Includes a data storage unit 28a and a signal processing unit 28b, and is configured by, for example, a DSP. Data storage unit 28a
Stores and stores digital data converted by the paired A / D converter 27. The signal processing unit 28b
The digital data stored in the data storage unit 28a is subjected to signal processing (FFT (fast Fourier transform) operation), and the processing result is displayed on the display unit 26.

The A / D converter switching means 29 is constituted by a switch capable of high-speed switching, and is provided between the LPF and the plurality of A / D converters 27. A / D converter switching means 2
In 9, the contact is switched and controlled by a control signal from the processing device 2, and the LPF and one of the A / D converters 27 are electrically connected.

Here, FIG. 7 shows a test system including the transmitter tester 4 adopting the configuration of FIG. 6, in which the harmonics are measured up to the third harmonic for each of the frequencies F1, F2 and F3. It is a time chart which shows an example of a wave measurement time.

That is, FIG. 7 shows the frequency F1 (893 MHz) and the frequency F2 (925 MHz) in the harmonic measurement of the PDC.
z) and F3 (958 MHz) are used as fundamental waves, and the respective frequencies F1 to F3 are measured up to the third harmonic.

In the example of FIG. 7, the frequency switching time is set to 40 ms, and the FFT operation time per frequency is set to 30 ms, similarly to FIG. Further, the switching time of the A / D converter 27 is performed in a very short time (for example, about 1 ms) as compared with the switching time of the frequency, and thus is omitted in the drawing.

Then, in the example of FIG.
The frequency is switched to F1 during ms and the FFT operation is performed. At this time, the second harmonic of the frequency F1 (F1 *
2) and the third harmonic (F1 * 3) are output to the data processing unit 25 of the transmitter tester 5 together with the measurement of the frequency F1. Therefore, the A / D converter 27 (27A, 27B, 2
7C) is sequentially switched at a high speed, and the FFT calculation of F1 * 2 and F1 * 3 is performed in parallel with the FFT calculation of F1.
Hereinafter, similarly, F2 and its second harmonic (F2 * 2)
And measurement of the third harmonic (F2 * 3), F3 and its second harmonic (F3 * 2) and third harmonic (F3 * 3).

Therefore, according to the example of FIG. 7, the processing time can be further shortened as compared with the example of FIG. 5, and as compared with the example of FIG.
The processing time can be significantly reduced by 420 ms.

In the test system of the present embodiment, when the fundamental wave is set as the measurement frequency, the harmonics of the fundamental wave are output from the frequency doubler 11 together. / D converter switching means 29;
The A / D converters 27B and 27C may be omitted.
That is, the data processing unit 25 includes an A / D conversion unit 27,
It comprises a plurality of processing units 28 (28A, 28B, 28C). Thereby, the switching time of the A / D converter 27 can be reduced.

As described above, according to the test system 1 of the present embodiment, when the measurement is performed with the frequency set to the fundamental wave of the measurement frequency, the signal of the harmonic of the fundamental wave can be output together. For this reason, the switching time of the frequency with respect to the harmonic can be reduced, and the processing time can be reduced as compared with the related art. In addition, the frequency characteristic and the level (power) characteristic can be measured at high speed by a single process up to the nth harmonic.

Further, if the signal processing for separating the harmonic components by the FFT analysis is performed in parallel as in a test system including the transmitter tester 4 employing the configuration of FIG. 6, the measurement time can be further reduced. The speed of measurement can be increased.

In the above embodiment, the signal from the harmonic module 4 is input to the transmitter tester 5, and the data processing unit 25 in the transmitter tester 5 separates the signal into harmonic components for measurement. However, a configuration may be adopted in which a signal from the harmonic module 4 is input to the processing device 2, taken as digital data in the processing device 2, and separated into harmonic components by the control unit (DSP) for measurement.

In the test system of the present embodiment, a signal is supplied from the signal generator 3 to the semiconductor device, and the signal output from the semiconductor device is measured accordingly. The present invention can also be applied to a device that outputs a signal.

[0070]

As is apparent from the above description, according to the present invention, when a frequency is set to a fundamental wave of a measurement frequency and a measurement is performed, a harmonic signal of the fundamental wave is output together. Can be. For this reason, the switching time of the frequency with respect to the harmonic can be reduced, and the processing time can be reduced as compared with the related art. Moreover, it is possible to perform high-speed measurement up to the n-th harmonic by one process.

Further, by performing signal processing for separating harmonic components by FFT analysis in parallel, the measurement time can be further reduced, and the measurement can be speeded up.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a test system according to the present invention.

FIG. 2 is a block diagram showing an internal configuration of a test system according to the present invention.

FIG. 3 is a block diagram showing an internal configuration of a transmitter tester of the test system according to the present invention.

FIG. 4 is a flowchart showing a measurement operation of the test system according to the present invention.

FIG. 5 shows a test system according to the present invention including a transmitter tester employing the configuration of FIG.
Time chart showing an example of a harmonic measurement time when measuring up to the third harmonic for each of F3

FIG. 6 is a block diagram showing another example of the internal configuration of the transmitter tester.

FIG. 7 shows a test system according to the present invention including a transmitter tester employing the configuration of FIG.
Time chart showing an example of a harmonic measurement time when measuring up to the third harmonic for each of F3

FIG. 8 is a block diagram of a conventional test system.

FIG. 9 shows a conventional test system in which frequencies F1,
Time chart showing an example of a harmonic measurement time when measuring up to the third harmonic for each of F2 and F3

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Test system, 4 ... Harmonic module, 11 ... Frequency frequency mixing means, 25 ... Data processing part, 27 (27
A, 27B, 27C)... A / D converter, 28 (28A,
28B, 28C) ... processing unit, DUT ... semiconductor device.

Claims (4)

[Claims] 1. A frequency of a local signal is set according to a measurement frequency of a signal from a semiconductor device (DUT), and the set local signal and a signal from the semiconductor device are mixed and converted to an intermediate frequency. A semiconductor device test system (1) for digitally waveform processing the converted intermediate frequency signal, wherein a frequency multiplying means for outputting an intermediate frequency signal obtained by mixing the frequency multiplied signal and a signal from the semiconductor device; A harmonic module (4) having (11), and a data processing unit (25) for performing FFT analysis on digital data of an intermediate frequency signal output from the harmonic module to separate harmonic components. Characteristic semiconductor device test system. 2. The data processing section (25) includes an A / D conversion section (27) that converts the intermediate frequency signal into digital data, and performs an FFT analysis on the digital data converted by the A / D conversion section. And a plurality of pairs of processing units (28) each comprising a processor that separates a harmonic component, and any one of the pairs is provided between the harmonic module (4) and the plurality of A / D conversion units. A / D converter switching means (29) for electrically connecting one of the A / D converters to the harmonic module is provided. The plurality of A / D converters are sequentially switched and controlled. 2. The semiconductor device test system according to claim 1, wherein the signal processing by the processing unit is performed in parallel. 3. The data processing section (25) includes an A / D conversion section (27) that converts the intermediate frequency signal into digital data, and performs an FFT analysis on the digital data converted by the A / D conversion section. 2. The semiconductor device test system according to claim 1, further comprising: a plurality of processing units each including a processor that separates a harmonic component by performing the signal processing by the plurality of processing units in parallel. 4. The frequency double mixing means (11),
The semiconductor device test system according to any one of claims 1 to 3, wherein the semiconductor device test system is configured by one of a sampler, a harmonic mixer, and a combination of a multiplier and a mixer.