JP3553522B2 - Semiconductor device test system - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device test system for measuring various characteristics such as a frequency characteristic and a level (power) characteristic of a semiconductor device.
[0002]
[Prior art]
For example, a semiconductor device including a mobile communication device, a composite device such as an amplifier, a mixer, and a switch of ITS (intelligent transport systems) uses a semiconductor device test system (hereinafter, abbreviated as a test system) to obtain frequency characteristics and levels. (Power) characteristics and the like are measured.
[0003]
FIG. 8 is a block diagram of a conventional test system. As shown in FIG. 8, in order to measure the frequency characteristics and level (power) characteristics of a semiconductor device, a processing device 50 such as a personal computer, a signal generator 51, and a transmitter tester (characteristic measuring device) 52 are GP The test system 54 connected by the IB interface 53 is used.
[0004]
The processing device 50 outputs the setting information of the measurement frequency and the level to the signal generator 51 and the transmitter tester 52 by the GP-IB command, respectively. The signal generator 51 generates a signal at the set frequency and level and outputs the signal to the semiconductor device. The transmitter tester 52 measures the characteristics of the semiconductor device at the frequency set similarly to the signal generator 51, and outputs the measured level to the processing device 50 in response to the level acquisition request.
[0005]
Then, the processing device 50 transmits the measurement frequency and level setting information of the signal generator 51 and the transmitter tester 52 by the frequency required for the characteristic measurement (for example, 300 times of 10 MHz steps from 10 MHz to 3000 MHz) by the GP-IB command. Set with.
[0006]
Thus, the frequency characteristics and the level characteristics of the semiconductor device are automatically measured over a predetermined frequency range.
[0007]
By the way, when the harmonic measurement of the semiconductor device is performed in this type of test system 54, the frequencies of the signal generator and the transmitter tester are sequentially changed to a fundamental wave, a second harmonic, a third harmonic, and so on. The measurement was performed by switching the frequency.
[0008]
Here, FIG. 9 shows an example of a time chart in the case where a PDC (Personal Digital Cellular) harmonic measurement is performed. That is, FIG. 9 shows an example in which each of the frequencies F1 to F3 is measured up to the third harmonic using the frequencies F1 (893 MHz), F2 (925 MHz), and F3 (958 MHz) as fundamental waves. In the example of FIG. 9, the frequency switching time is 40 ms, and the FFT (fast Fourier transform: fast Fourier transform) calculation time per frequency is 30 ms.
[0009]
As shown in FIG. 9, in the conventional test system 54, first, the frequency is switched to the frequency F1 in the first 70 ms, and the FFT operation is performed. In the next 70 ms, the frequency is switched to F1 * 2 (second harmonic of F1) and the FFT operation is performed. Further, in the next 70 ms, the frequency is switched to F1 * 3 (the third harmonic of F1) and the FFT operation is performed. Hereinafter, similarly, the frequencies are changed to F2, F2 * 2 (second harmonic of F2), F2 * 3 (third harmonic of F2), F3, F3 * 2 (second harmonic of F3), F3 * 3 (the third harmonic of F3), and the FFT operation is performed for each frequency.
[0010]
Therefore, when the harmonic measurement of the PDC as shown in FIG. 9 is performed in the conventional test system 54, a total time of 70 ms of the frequency switching time and the FFT operation time is required for each frequency, and the entire measurement time is required. As a result, a time of 70 ms × 9 times = 630 ms was required.
[0011]
[Problems to be solved by the invention]
As described above, in the conventional test system 54, harmonics are measured by sequentially switching and setting the frequency and performing the FFT operation. In addition to the fact that the frequency switching in the transmitter tester is slow, the overall measurement time becomes longer, and the measurement of the nth harmonic cannot be performed at once.
[0012]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device test system capable of measuring up to the nth harmonic at a time and increasing the processing speed.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, the invention according to claim 1 changes the frequency of a local signal according to the measurement frequency of a signal from a semiconductor device DUT.A harmonic module 4 having frequency multiplying means 11 for outputting an intermediate frequency signal obtained by mixing the frequency multiplied signal and the signal from the semiconductor device;
A data processing unit 25 for performing FFT analysis on digital data of an intermediate frequency signal output from the harmonic module to separate harmonic components.In the semiconductor device test system 1,
The data processing unit includes an A / D conversion unit 27 that converts the intermediate frequency signal into digital data, and a processor that performs FFT analysis on the digital data converted by the A / D conversion unit to separate harmonic components. A plurality of processing units 28 are provided in pairs,
A / D converter switching means 29 for electrically connecting any one of the A / D converters to the harmonic module is provided between the harmonic module 4 and the plurality of A / D converters. Has been
The plurality of A / D converters are sequentially switched and controlled, and the signal processing by the plurality of processing units is performed in parallel.It is characterized by the following.
[0014]
The invention of claim 2 isFrequency multiplying means (11) for outputting an intermediate frequency signal obtained by mixing a signal obtained by multiplying the frequency of a local signal in accordance with a measured frequency of a signal from a semiconductor device (DUT) with a signal from the semiconductor device; A harmonic module (4) having
A semiconductor device test system (1) comprising: a data processing unit (25) for performing FFT analysis on digital data of an intermediate frequency signal output from the harmonic module to separate harmonic components;
An A / D converter for converting the intermediate frequency signal into digital data; and a processor for performing FFT analysis on the digital data converted by the A / D converter to separate harmonic components. And a plurality of processing units (28) comprising
Perform signal processing by the plurality of processing units in parallelIt is characterized by the following.
[0015]
The invention of claim 3 is the invention of claim 1Or claim 2In the semiconductor device test system of
The frequency multiplying means (11) is constituted by any of a sampler, a harmonic mixer, or a combination of a multiplier and a mixer.It is characterized by the following.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a diagram showing a schematic configuration of a test system according to the present invention, FIG. 2 is a block diagram showing an internal configuration of the system, and FIG. 3 is a block diagram showing an internal configuration of a transmitter tester of the system.
[0018]
The test system 1 of the present example includes a processing device 2, a signal generator 3, a harmonic module 4, and a transmitter tester (characteristic measuring device) 5.
[0019]
A semiconductor device DUT as an object to be measured is composed of, for example, a composite device such as a mobile communication device, an amplifier of ITS (intelligent transport systems), a mixer, and a switch. The semiconductor device DUT is electrically connected to a signal generator 3 via a signal cable in a state where the semiconductor device DUT is mounted on a test fixture (not shown), and is electrically connected to a transmitter tester 5 via a harmonic module 4. Connected.
[0020]
The processing device 2 is composed of, for example, a terminal device such as a personal computer, and has a CPU 2a, a data storage means 2b for storing measurement data, a ROM and a RAM for storing a control program and the like.
[0021]
The processing device 2 includes an interface such as GP-IB or RS223C, and registers a control procedure (control method) in each setting table of the signal generator 3, the harmonic module 4, and the transmitter tester 5.
[0022]
That is, the processing device 2 transmits various parameters for initial setting based on measurement conditions to the signal generator 3, the harmonic module 4, and the transmitter tester 5 through an interface such as GP-IB or RS223C before the start of measurement. Set to send. The parameters include a frequency band in which characteristics are measured, a measurement frequency step, a level at each frequency, and the like.
[0023]
As shown in FIG. 2, the signal generator 3 includes a signal generator 6 for generating and outputting a test signal (measurement signal) supplied to the semiconductor device DUT. The signal generated and output from the signal generator 6 is controlled based on the measurement conditions set in the procedure storage 7.
[0024]
The procedure storage means 7 sets a plurality of frequencies and levels of the signal output from the signal generation means 6 in a predetermined frequency band at predetermined frequency steps based on the parameters of the initial setting transmitted from the processing device 2. The setting contents are stored in the setting table 7a.
[0025]
The synchronizing means 8 has a trigger interface, controls the start of measurement based on a trigger (single pulse trigger signal) from the processing device 2, and generates and outputs a signal from the signal generating means 6. Then, every time a trigger is received from the processing device 2 via the trigger interface after the start of measurement, the synchronization means 8 sequentially reads out the frequency and level of the signal set in the setting table 7a at each frequency step to generate a signal. Outputting to the means 6 is repeated.
[0026]
As shown in FIGS. 1 and 2, the harmonic module 4 includes a local signal source 9, a switching unit 10, and a frequency multiplication unit 11.
[0027]
A local signal source (LO signal source) 9 is a local signal input to the frequency doubler 11 at the time of harmonic measurement, or is input to the transmitter tester 5 at the time of measuring the frequency characteristics and power (level) of an ordinary semiconductor device DUT. It generates and outputs a local signal. As shown in FIG. 2, the local signal source 9 includes a signal generation unit 12, a procedure storage unit 13, and a synchronization unit 14.
[0028]
The signal generator 12 supplies a local signal to the frequency multiplier mixer 11 or the transmitter tester 5. The signal generated and output from the signal generating means 12 is controlled based on the measurement conditions set in the procedure storing means 13.
[0029]
The procedure storage means 13 sets a plurality of frequencies and levels of the signal output from the signal generation means 12 in a predetermined frequency band at predetermined frequency steps based on the parameters of the initial setting transmitted from the processing device 2. This setting content is stored in the setting table 13a.
[0030]
The synchronizing means 14 has a trigger interface, controls the start of measurement based on a trigger from the processing device 2, and generates and outputs a signal from the signal generating means 12. Then, every time a trigger (single pulse trigger signal) is received from the processing device 2 after the start of the measurement, the synchronization means 14 sequentially reads out the frequency and level of the signal set in the setting table 13a for each frequency step. Outputting to the signal generating means 12 is repeated.
[0031]
The switching unit 10 switches between inputting the signal from the semiconductor device DUT directly to the transmitter tester 5 and inputting the signal to the transmitter tester 5 via the frequency multiplication unit 11. The switching means 10 is switch-controlled by a control signal from the processing device 2. In this example, when performing the harmonic measurement of the semiconductor device DUT, the contact point of the switching unit 10 is switched to the frequency double mixing unit 11 side.
[0032]
The frequency multiplier mixing means 11 is composed of a single product such as a sampler or a harmonic mixer, or a combination of a multiplier (frequency multiplier) and a mixer. The frequency multiplication unit 11 adds / subtracts n times the signal LO from the LO signal source 9 and the RF signal from the semiconductor device DUT, and outputs the result as an intermediate frequency signal IF.
[0033]
For example, it is assumed that the signal RF input from the semiconductor device DUT includes 1000 MHZ (fundamental wave), 2000 MHz (second harmonic), and 3000 Mz (third harmonic).
[0034]
Now, assuming that the signal LO mixed with the signal RF is 110.53 MHz, only the signals before and after the main part are extracted from IF = LO × n ± RF × m.
IF0x = ABS (1000 MHz−110.53 MHz × 10) = 105.3 MHz
IF1x = ABS (1000 MHz−110.53 MHz × 9) =5.23MHz
IF2x = ABS (1000 MHz−110.53 MHz × 8) = 115.76 MHz
IF0y = ABS (2000MHz-110.53MHz x19) = 100.07 MHz
IF1y = ABS (2000MHz-110.53MHz x18) = 10.46 MHz
IF2y = ABS (2000MHz-110.53MHz x17) = 120.99 MHz
IF0z = ABS (3000MHz-110.53MHz x28) = 94.84 MHz
IF1z = ABS (3000MHz-110.53MHz x27) = 15.69 MHz
IF2z = ABS (3000MHz-110.53MHz x26) = 126.22 MHz.
[0035]
In the above description, in order to make the description easy to understand, it is assumed that a signal RF having a fundamental frequency of 1000 MHz is input from the semiconductor device DUT to the frequency multiplying / mixing means 11, but in an actual PDC harmonic measurement, Signals having fundamental waves of 893 MHz, 925 MHz, and 958 MHz are input to the frequency doubler 11 from the semiconductor device DUT. In the harmonic measurement of W-CDMA, a signal having fundamental frequencies of 1920 MHz, 1950 MHz and 1980 MHz is input from the semiconductor device DUT to the frequency doubler 11.
[0036]
Then, when the signal IF output from the frequency doubler 11 is passed through the LPF, only the low frequency, which is the IFxyz component, is extracted, and a waveform in which the IFxyz component is synthesized is obtained.
[0037]
After that, if the above-mentioned waveform is taken into a data processing unit of the transmitter tester 5 to be described later and FFT (fast Fourier transform) operation is performed, signals from IFx to IFz can be separated, and the level of the signal RF can be separated from this value. Can be converted. As a result, up to the n-th harmonic can be measured at high speed by a single data capture and FFT operation.
[0038]
The signal IF output from the frequency multiplying / mixing means 11 has a higher signal level as the order (n) is lower, and a sufficient dynamic range cannot be obtained unless a signal having this higher level is cut. For this reason, it is preferable to provide an LPF for band limitation at the subsequent stage of the frequency doubler 11. The LPF in the above example cuts a signal near 100 MHz and passes a signal of 20 MHz or less.
[0039]
The transmitter tester 4 is a signal measuring unit 15 for measuring the frequency characteristics and level (power) characteristics of the semiconductor device DUT, including the harmonic measurement of the semiconductor device DUT based on the intermediate frequency signal IF from the frequency multiplication unit 11. It has. The signal measurement unit 15 performs measurement for each measurement frequency based on the measurement conditions set in the procedure storage unit 16.
[0040]
The procedure storage means 16 sets a plurality of signals to be measured by the signal measuring means 15 at predetermined frequency steps in a predetermined frequency band based on the parameters of the initial setting sent from the processing device 2. This setting content is stored in the setting table 16a.
[0041]
The synchronization unit 17 includes a trigger interface, and controls the start of measurement by the signal measurement unit 15 based on a trigger (a single-pulse trigger signal) from the processing device 2. Then, every time a trigger is received from the processing device 2 after the start of measurement, the synchronization unit 17 sequentially reads out the frequency of the signal set in the setting table 16a for each frequency step and outputs the signal to the signal measurement unit 15. repeat.
[0042]
Further, the transmitter tester 5 includes a data processing unit 25 and a display unit 26, as shown in FIG.
[0043]
The data processing unit 25 includes an A / D conversion unit 27 and a processing unit 28. The A / D converter 27 converts the intermediate frequency signal IF converted by the frequency multiplying means 11 and band-limited by the LPF or the intermediate frequency signal IF directly input from the semiconductor device DUT and frequency-converted into digital data. are doing.
[0044]
The processing unit 28 includes a data storage unit 28a and a signal processing unit 28b, and is configured by a processor such as a DSP, for example. The data storage unit 28a stores and stores digital data converted by the A / D conversion unit 27. The signal processing unit 28b processes the digital data stored in the data storage unit 28a, and displays the processing result on the display unit 26. Further, when processing the signal IF input via the frequency multiplication unit 11, the signal processing unit 28b performs an FFT analysis on the digital data from the A / D conversion unit 27 and calculates the time when the harmonic is synthesized. The waveform is converted on the frequency axis to separate harmonic components, and the frequency and level are analyzed.
[0045]
FIG. 4 is a flowchart showing the measurement operation of the test system 1 configured as described above.
[0046]
In the test system 1 of the present example, when the processing device 2 outputs a trigger to start measurement at the start of measurement, the signal generator 3 sets the starting frequency and level stored in the setting table 7a to the signal generating means 6. . The signal generator 6 generates and outputs a signal of this frequency and level (SP1).
[0047]
The transmitter tester 5 sets the starting frequency stored in the setting table 16a in the signal measuring means 15 based on the input of the trigger output from the processing device 2.
[0048]
The LO signal source 9 sets the starting frequency stored in the setting table 13a in the signal generating means 12 based on the input of the trigger output from the processing device 2. With the above settings, the signal measuring means 15 of the transmitter tester 5 measures the output level of the semiconductor device DUT at this frequency (SP2). Thereby, the measurement at the measurement start frequency is performed.
[0049]
Next, the signal generator 3 generates a signal at the next frequency and level stored in the setting table 7a each time a trigger is input from the processing device 2. Further, the LO signal source 9 sets the frequency stored in the setting table 13a to the signal generating means 12 each time a trigger is input from the processing device 2. Then, the transmitter tester 5 measures the semiconductor device at the next frequency stored in the setting table 16a each time a trigger of the processing device 2 is input.
[0050]
Thereafter, when a trigger is input from the processing device 2 to the signal generator 3, the transmitter tester 5, and the LO signal source 9, the measurement at a predetermined frequency step is automatically executed until the last set frequency is reached (SP3).
[0051]
In the above measurement, when performing the harmonic measurement of the semiconductor device DUT, the contact of the switching means 10 is switched and controlled to the frequency double mixing means 11 side by the control signal from the processing device 2. Thus, the signal LO from the LO signal source 9 and the signal RF from the semiconductor device DUT are input to the frequency doubler 11. The frequency doubler 11 adds and subtracts n times the signal LO from the LO signal source 9 and the signal RF, and outputs the result as an intermediate frequency signal IF. This intermediate frequency signal IF is input to the data processing unit 25 of the transmitter tester 5 by passing only a low frequency by a band limiting filter (low-pass filter: LPF). The A / D converter 27 of the data processor 25 converts a signal input from the LPF into digital data. The converted digital data is subjected to FFT analysis by the signal processing unit 28b. As a result, the harmonic components are separated and the frequency and level are analyzed.
[0052]
Here, FIG. 5 shows a harmonic measurement time when measuring up to the third harmonic for each of the frequencies F1, F2, and F3 in the test system of the present example including the transmitter tester 4 employing the configuration of FIG. 6 is a time chart showing an example of the above.
[0053]
That is, FIG. 5 shows that in the harmonic measurement of the PDC (Personal Digital Cellular), the frequencies F1 (893 MHz), F2 (925 MHz), and F3 (958 MHz) are used as fundamental waves, and the frequencies F1 to F3 are measured up to the third harmonic. This is an example of the case.
[0054]
In FIG. 5, as compared with FIG. 9, similarly to FIG. 9, the frequency switching time is 40 ms, and the FFT operation time per frequency is 30 ms.
[0055]
In the example of FIG. 5, first, the frequency is switched to F1 in the first 70 ms, and the FFT operation is performed. At this time, the second harmonic (F1 * 2) and the third harmonic (F1 * 3) of the frequency F1 are output to the data processing unit 25 of the transmitter tester 5 together with the measurement of the frequency F1. As a result, the frequency switching time of the frequency F1 to the harmonics F1 * 2 and F1 * 3 is reduced, and the FFT calculation of F1 * 2 and F1 * 3 is performed in the next 60 ms. Hereinafter, similarly, F2 and its second harmonic (F2 * 2) and third harmonic (F2 * 3), F3 and its second harmonic (F3 * 2) and third harmonic (F3 * 3) ) Is measured. In the case of this example, the processing time can be reduced by 210 ms as compared with the example of FIG.
[0056]
By the way, in the test system 1 described above, the description has been given assuming that the intermediate frequency signal IF from the harmonic module 4 is processed by the set of data processing units 25 of the transmitter tester 5 shown in FIG. The signal processing may be performed depending on the configuration.
[0057]
The data processing unit 25 in the example of FIG. 6 includes three sets of an A / D conversion unit 27 and a processing unit 28 in pairs. Each of the A / D conversion units 27 (27A, 27B, 27C) is input from the frequency multiplication unit 11 via the LPF when connected to the LPF by switching selection of the A / D conversion unit switching unit 29. Signal IF is converted to digital data.
[0058]
Each processing unit 28 (28A, 28B, 28C) includes a data storage unit 28a and a signal processing unit 28b, and is configured by, for example, a DSP. The data storage unit 28a stores and stores digital data converted by the A / D conversion unit 27 forming a pair. The signal processing unit 28b performs signal processing (FFT (fast Fourier transform) operation) on the digital data stored in the data storage unit 28a, and displays the processing result on the display unit 26.
[0059]
The A / D converter switching means 29 is constituted by a switch capable of high-speed switching, and is provided between the LPF and the plurality of A / D converters 27. The A / D converter switching means 29 has its contacts switched and controlled by a control signal from the processing device 2, and electrically connects the LPF to any one of the A / D converters 27.
[0060]
Here, FIG. 7 shows a harmonic measurement time when measuring up to the third harmonic for each of the frequencies F1, F2, and F3 in the test system of the present example including the transmitter tester 4 employing the configuration of FIG. 6 is a time chart showing an example of the above.
[0061]
That is, FIG. 7 shows an example in which the frequencies F1 (893 MHz), F2 (925 MHz), and F3 (958 MHz) are used as fundamental waves in the PDC harmonic measurement, and the frequencies F1 to F3 are measured up to the third harmonic. .
[0062]
In the example of FIG. 7, the frequency switching time is set to 40 ms, and the FFT operation time per frequency is set to 30 ms, similarly to FIG. 9 in comparison with FIG. 9. The switching time of the A / D converter 27 is very short (for example, about 1 ms) compared to the switching time of the frequency, and is therefore omitted in the drawing.
[0063]
Then, in the example of FIG. 7, first, the frequency is switched to F1 during the first 70 ms, and the FFT operation is performed. At this time, the second harmonic (F1 * 2) and the third harmonic (F1 * 3) of the frequency F1 are output to the data processing unit 25 of the transmitter tester 5 together with the measurement of the frequency F1. Therefore, the A / D converters 27 (27A, 27B, 27C) are sequentially switched at high speed, and the FFT calculations of F1 * 2 and F1 * 3 are performed in parallel with the FFT calculation of F1. Hereinafter, similarly, F2 and its second harmonic (F2 * 2) and third harmonic (F2 * 3), F3 and its second harmonic (F3 * 2) and third harmonic (F3 * 3) ) Is measured.
[0064]
Therefore, according to the example of FIG. 7, the processing time can be further shortened as compared with the example of FIG. 5, and the processing time can be significantly reduced by 420 ms as compared with the example of FIG.
[0065]
In the test system of this example, when the fundamental wave is set as the measurement frequency, the harmonics of the fundamental wave are output together from the frequency multiplication means 11, so that the A / D conversion in the configuration of FIG. The unit switching means 29 and the A / D converters 27B and 27C can be omitted. That is, the data processing unit 25 includes an A / D conversion unit 27 and a plurality of processing units 28 (28A, 28B, 28C). Thereby, the switching time of the A / D converter 27 can be reduced.
[0066]
As described above, according to the test system 1 of the present example, when the measurement is performed with the frequency set to the fundamental wave of the measurement frequency, a signal of a harmonic of the fundamental wave can be output together. For this reason, the switching time of the frequency with respect to the harmonic can be reduced, and the processing time can be reduced as compared with the related art. In addition, the frequency characteristic and the level (power) characteristic can be measured at high speed by a single process up to the nth harmonic.
[0067]
Further, if the signal processing for separating the harmonic components by the FFT analysis is performed in parallel as in a test system including the transmitter tester 4 employing the configuration of FIG. Can be speeded up.
[0068]
By the way, in the above embodiment, the signal from the harmonic module 4 is input to the transmitter tester 5, and the data processing unit 25 in the transmitter tester 5 separates the signal into harmonic components and performs measurement. A configuration may be adopted in which a signal from the harmonic module 4 is input to the processing device 2, taken as digital data in the processing device 2, and separated into harmonic components by the control unit (DSP) for measurement.
[0069]
In the test system of the present example, a signal is supplied from the signal generator 3 to the semiconductor device, and the signal output from the semiconductor device is measured accordingly. Can also be adopted for those that output.
[0070]
【The invention's effect】
As is clear from the above description, according to the present invention, when a measurement is performed with the frequency set to the fundamental wave of the measurement frequency, a signal of a harmonic of the fundamental wave can be output together. For this reason, the switching time of the frequency with respect to the harmonic can be reduced, and the processing time can be reduced as compared with the related art. In addition, it is possible to perform high-speed measurement up to the nth harmonic by one process.
[0071]
In addition, by performing signal processing for separating harmonic components by FFT analysis in parallel, the measurement time can be further reduced, and the measurement can be speeded up.
[Brief description of the drawings]
FIG. 1 is a diagram showing a schematic configuration of a test system according to the present invention.
FIG. 2 is a block diagram showing an internal configuration of a test system according to the present invention.
FIG. 3 is a block diagram showing an internal configuration of a transmitter tester of the test system according to the present invention.
FIG. 4 is a flowchart showing a measurement operation of the test system according to the present invention.
5 shows an example of a harmonic measurement time when measuring up to the third harmonic for each of the frequencies F1, F2, and F3 in the test system according to the present invention including the transmitter tester employing the configuration of FIG. Time chart shown
FIG. 6 is a block diagram showing another example of the internal configuration of the transmitter tester.
FIG. 7 is an example of a harmonic measurement time when measuring up to the third harmonic for each of the frequencies F1, F2, and F3 in the test system according to the present invention including the transmitter tester employing the configuration of FIG. Time chart shown
FIG. 8 is a block diagram of a conventional test system.
FIG. 9 is a time chart showing an example of a harmonic measurement time when measuring up to the third harmonic for each of the frequencies F1, F2, and F3 in the conventional test system.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Test system, 4 ... Harmonic module, 11 ... Frequency frequency mixing means, 25 ... Data processing part, 27 (27A, 27B, 27C) ... A / D conversion part, 28 (28A, 28B, 28C) ... Processing Section, DUT ... Semiconductor device.

Claims (3)

Frequency multiplying means (11) for outputting an intermediate frequency signal obtained by mixing a signal obtained by multiplying the frequency of a local signal in accordance with a measured frequency of a signal from a semiconductor device (DUT) with a signal from the semiconductor device; A harmonic module (4) having
A semiconductor device test system (1) comprising: a data processing unit (25) for performing FFT analysis on digital data of an intermediate frequency signal output from the harmonic module to separate harmonic components ;
An A / D converter for converting the intermediate frequency signal into digital data; and a processor for performing FFT analysis on the digital data converted by the A / D converter to separate harmonic components. A plurality of processing units (28) comprising
A / D converter switching means for electrically connecting any one of the A / D converters to the harmonic module between the harmonic module (4) and the plurality of A / D converters. 29) is provided,
A semiconductor device test system, wherein the plurality of A / D converters are sequentially switched and controlled, and signal processing by the plurality of processing units is performed in parallel . Frequency multiplying means (11) for outputting an intermediate frequency signal obtained by mixing a signal obtained by multiplying the frequency of a local signal in accordance with a measured frequency of a signal from a semiconductor device (DUT) with a signal from the semiconductor device; A harmonic module (4) having
A semiconductor device test system (1) comprising: a data processing unit (25) for performing FFT analysis on digital data of an intermediate frequency signal output from the harmonic module to separate harmonic components;
An A / D converter for converting the intermediate frequency signal into digital data; and a processor for performing FFT analysis on the digital data converted by the A / D converter to separate harmonic components. And a plurality of processing units (28) comprising
A semiconductor device test system, wherein the signal processing by the plurality of processing units is performed in parallel . 3. The semiconductor device test system according to claim 1, wherein the frequency multiplying means comprises one of a sampler, a harmonic mixer, and a combination of a multiplier and a mixer . 4.

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