JP2002333861A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress power consumption of a light-emission device. SOLUTION: Power consumption of this display device is suppressed, while preventing a current flowing into a light-emitting element from being increased according to the rising of temperature either by inverting the light and the darkness of an image according to the brightness of the image which is to be displayed on a pixel part or by reducing the number of bits while eliminating bits of a digital video signal which is to be inputted to the pixel part from a lower rank side or by making the magnitude of a current flowing into the light-emitting element provided in the pixel part to be kept always constant, even when the temperature of an organic compound layer is changed, while providing a light-emitting element for monitoring the temperature in the light- emission device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display panel in which a light emitting element formed on a substrate is sealed between the substrate and a cover material. Further, the present invention relates to a display module in which an IC is mounted on the display panel. In this specification,
The display panel and the display module are collectively referred to as a light emitting device. The invention further relates to an electronic device using the light emitting device.

[0002]

2. Description of the Related Art In recent years, the technology for forming a TFT on a substrate has been greatly advanced, and its application to an active matrix type display device has been developed. In particular, a TFT using a polysilicon film is a conventional TFT using an amorphous silicon film.
Since the field-effect mobility (also referred to as mobility) is higher than that of the FT, high-speed operation is possible. Therefore, the control of the pixel, which has been conventionally performed by the drive circuit outside the substrate, can be performed by the drive circuit formed on the same substrate as the pixel.

Such an active matrix type display device has various advantages such as reduction in manufacturing cost, downsizing of the display device, increase in yield, and reduction in throughput by forming various circuits and elements on the same substrate. Is obtained.

Further, active matrix type light emitting devices having a light emitting element as a self light emitting element have been actively studied. The light emitting device is an organic EL display (O
ELD: Organic EL Display or organic light emitting diode (OLED: Organic Light Emitting)
Diode).

The light emitting device is of a self-luminous type, unlike a liquid crystal display. A light-emitting element has a structure in which a layer containing an organic compound which emits luminescence by applying an electric field (hereinafter referred to as an organic compound layer) is sandwiched between a pair of electrodes (anode and cathode). The layers usually have a laminated structure. Typically, Kodak Eastman
"Hole transport layer / light emitting layer /
A layered structure called “electron transport layer” is exemplified. This structure has a very high luminous efficiency, and most light emitting devices currently under research and development are adopting this structure.

[0006] Luminescence in organic compounds includes:
Light emission when returning from singlet excited state to ground state (fluorescence) and light emission when returning from triplet excited state to ground state (phosphorescence)
However, the light emitting device of the present invention may use any one of the above-described light emissions, or may use both light emissions.

In addition, a hole injection layer / hole transport layer / light-emitting layer / electron transport layer, or a hole injection layer / hole transport layer / light-emitting layer / electron transport layer / electron injection layer may be provided on the anode. A structure in which layers are sequentially stacked may be used. The light emitting layer may be doped with a fluorescent dye or the like.

In this specification, all layers provided between a cathode and an anode are collectively called an organic compound layer. Therefore, the above-described hole injection layer, hole transport layer, light emitting layer, electron transport layer,
The electron injection layer and the like are all included in the organic compound layer.

Then, a predetermined voltage is applied to the organic compound layer having the above-mentioned structure from a pair of electrodes, whereby recombination of carriers occurs in the light emitting layer to emit light. Note that in this specification, light emission of a light-emitting element is referred to as driving of the light-emitting element. In this specification, a light-emitting element including an anode, an organic compound layer, and a cathode is referred to as a light-emitting element.

[0010]

Since the light-emitting device does not need to use a backlight, the thickness and weight of the display itself can be reduced as compared with a liquid crystal display. Therefore, in recent years, the light emitting device has been used for a display unit of a portable information terminal (mobile computer, mobile phone, portable game machine, electronic book, or the like) instead of a liquid crystal display.

[0011] In order to reduce the power consumption of the portable information terminal, it has been desired to reduce the power consumption of the light emitting device used for the display unit.

In recent years, in addition to digitization of broadcast stations such as televisions and radios, digitalization of home-use receivers, VTRs, and the like has been progressing. The next stage of digitalization of broadcast systems is the digitization of broadcast radio waves, that is, the realization of digital broadcasting, and R & D is being actively conducted for this purpose.

There is a time gray scale display in the digital driving of the light emitting device. Time gray scale display is a driving method for performing gray scale display by controlling the time during which a light emitting element emits light during one frame period.

When the light emitting device is digitally driven to perform time gray scale display, if the number of gray scales of an image to be displayed is increased, the number of times a digital video signal (digital video signal) having image information input to pixels is rewritten Increase.
Therefore, the power consumption of the driving circuit group for inputting the digital video signal to the pixel increases, and the power consumption of the light emitting device increases.

Further, since the light-emitting element is of a self-luminous type, the period in which the light-emitting element emits light during one frame period depends on an image to be displayed. Therefore, the power consumption of the light emitting device is
It depends on the image to be displayed.

Further, the magnitude of the current flowing through the light emitting element is also affected by the temperature. Even when the voltage applied between the electrodes of the light-emitting element is the same, the higher the temperature of the organic compound layer, the higher the current flowing through the light-emitting element due to the temperature characteristics of the light-emitting element. Therefore, the higher the ambient temperature at which the light emitting device is used, the higher the power consumption of the light emitting device and the higher the luminance of the light emitting element.

In view of the above, it is an object of the present invention to reduce power consumption of a light emitting device and an electronic device using the light emitting device for a display portion.

[0018]

According to a first aspect of the present invention, there is provided:
In the case where monochrome display is performed in a light-emitting device, the brightness of an image is inverted by an image displayed in a pixel portion.

According to the above configuration, the magnitude of the current flowing through the light emitting element can be suppressed to some extent, and the power consumption of the light emitting device can be suppressed.

According to a second configuration of the present invention, in a light-emitting device that performs digitally driven time-division gray scale display, a digital video signal input to a source signal line driving circuit of the light-emitting device is reduced in bit number. Input to the pixel portion after the delay. Specifically, the number of bits of the digital video signal input to the pixel portion is reduced by cutting down the digital video signal in order from the least significant bit.

According to the above configuration, the number of bits of the digital video signal input to the pixel is reduced, so that the number of times the digital video signal is written to the pixel by the source signal line driving circuit and the gate signal line driving circuit is reduced.
Therefore, power consumption of the source signal line driver circuit and the gate signal line driver circuit can be reduced, and power consumption of the light-emitting device can also be reduced.

In the third configuration of the present invention, the light emitting device is provided with a light emitting element for temperature monitoring. Then, one electrode of the light emitting element for temperature monitoring is connected to a constant current source. Then, the magnitude of the current flowing through the light emitting element of the pixel is kept constant by using the temperature characteristics of the light emitting element for monitoring.

With the above configuration, the magnitude of the current flowing through the light emitting element of the pixel can be kept constant even when the temperature of the organic compound layer changes. Therefore, even if the environmental temperature of the light emitting device rises, the power consumption of the light emitting device can be prevented from increasing, and the luminance can be kept constant.

According to the present invention, the power consumption of the light emitting device and the electronic equipment using the light emitting device can be suppressed by the above first to third structures. The present invention only needs to have any one of the first to third configurations. Further, a plurality of the first to third configurations may be provided, or all of the first to third configurations may be provided.

The configuration of the present invention will be described below.

According to the present invention, there is provided a display device having a plurality of pixels, wherein the brightness of the plurality of pixels is changed by inverting the polarity of a digital video signal input to the plurality of pixels. A display device is provided.

According to the present invention, there is provided a display device having a pixel portion having a plurality of pixels and a source signal line drive circuit, wherein the source signal line drive circuit has a switching circuit for switching output polarity. A digital video signal input to the switching circuit is inverted in polarity by the switching signal input to the switching circuit, and is input to the plurality of pixels.

According to the present invention, there is provided a display device having a pixel portion having a plurality of pixels and a source signal line driving circuit, wherein each of the plurality of pixels has a light emitting element.
The source signal line driver circuit includes a shift register, one or more latches, and a switching circuit, and the digital video signal input from the one or more latches to the switching circuit is provided for the switching. There is provided a display device, wherein the polarity is inverted by a switching signal input to a circuit, and input to the plurality of pixels.

According to the present invention, there is provided a display device having a pixel portion having a plurality of pixels and a source signal line driving circuit, wherein each of the plurality of pixels has a light emitting element.
The source signal line driver circuit includes a shift register, one or more latches, and a switching circuit, and the digital video signal input from the one or more latches to the switching circuit is provided for the switching. The polarity is inverted by the switching signal input to the circuit, the polarity is input to the plurality of pixels, and the average of the length of the light emitting period of all the light emitting elements in one frame period is equal to the average of all Wherein the length of the light emitting period of the light emitting element is equal to or less than half of the maximum value of the length of the light emitting period.

The switching circuit includes an inverter and a first
And a second analog switch. The digital video signal input to the switching circuit is input to the input terminal of the first analog switch via the inverter, and A digital video signal output from one or more latches is input to an input terminal of the second analog switch, and a switching signal is supplied to a first control input terminal of the first analog switch and the second analog switch. And a switching signal whose polarity is inverted is input from a second control input terminal of the first analog switch and a second control input terminal of the first analog switch. The signals output from the output terminals of the first analog switch and the second analog switch are output from the switching circuit. It may be characterized in that it is output.

The switching circuit comprises an inverter and a first
, A second NAND, and a NOR, a switching signal and a digital video signal are input to the first NAND via the inverter, and the second NAND A signal obtained by inverting the polarity of a switching signal and the digital video signal are input, and a signal output from the first NAND and the second N
And a signal output from the AND is input to the NOR,
The signal output from the NOR may be output from the switching circuit.

According to the present invention, there is provided a display device having a plurality of pixels and a source signal line driving circuit, wherein a digital video signal input to the source signal line driving circuit is
A display device is provided, wherein only the higher-bit digital video signal is input to the plurality of pixels.

According to the present invention, there is provided a display device including a pixel portion having a plurality of pixels and a source signal line driving circuit, wherein the source signal line driving circuit includes a shift register,
A first latch; a second latch; and a clock signal control circuit. When a clock signal is input to the shift register via the clock signal control circuit, a timing signal is output from the shift register. And a digital video signal is input to and held in the first latch by the timing signal, and a digital video signal held in the first latch is input to the second latch by the latch signal. The digital video signal held and input to and held by the second latch is input to the plurality of pixels, and the clock signal control circuit replaces the clock signal for a certain period of time.
By applying a fixed fixed potential to the shift register,
A display device is provided, wherein the number of bits of a digital video signal input to and held in the first latch is reduced.

The clock signal control circuit has a NAND and an inverter. A clock signal and a selection signal are input to the NAND, and a signal output from the NAND is supplied to the clock signal control circuit via the inverter. May be output.

The clock signal control circuit has a first analog switch, a second analog switch, and an inverter, and a second control input terminal of the first analog switch via the inverter. And a selection signal is inputted to a first control input terminal of the second analog switch, and a selection signal is inputted to a first control input terminal of the first analog switch and a second control input terminal of the second analog switch. A signal is input, and a clock signal is input to an input terminal of the first analog switch.
The fixed potential is given to the input terminal of the analog switch of
Signals output from output terminals of the first analog switch and the second analog switch may be output from the clock signal control circuit.

According to the invention, there is provided a display device including a pixel portion having a plurality of pixels and a source signal line driving circuit, wherein the source signal line driving circuit includes a shift register, a first latch, 2 and a timing signal control circuit, and a timing signal output from the shift register is input to the first latch via the timing signal control circuit, and is input to the first latch. A digital video signal is input to and held by the first latch according to the timing signal thus obtained, and a digital video signal held by the first latch is input to and held by the second latch according to the latch signal. The digital video signal input to and held in the second latch is input to the plurality of pixels, and the timing signal control circuit Period of time, instead of the timing signal output from the shift register, by giving a certain fixed potential to said first latch, said first
Wherein the number of bits of the digital video signal input to and held by the latch is reduced.

The timing signal control circuit has a NAND and an inverter. A timing signal and a selection signal are input to the NAND, and a signal output from the NAND is supplied to the timing signal control circuit via the inverter. May be output.

The timing signal control circuit has a first analog switch, a second analog switch, and an inverter, and a second control input terminal of the first analog switch via the inverter. And a selection signal is inputted to a first control input terminal of the second analog switch, and a selection signal is inputted to a first control input terminal of the first analog switch and a second control input terminal of the second analog switch. A signal is input, a timing signal is input to an input terminal of the first analog switch, a fixed potential is applied to an input terminal of the second analog switch, and the first analog switch and the second analog switch are input. The signal output from the output terminal may be output from the timing signal control circuit.

According to the present invention, there is provided a display device including a pixel portion having a plurality of pixels and a source signal line driving circuit, wherein the source signal line driving circuit includes a shift register,
A first latch, a second latch, and a start pulse signal control circuit, wherein a start pulse signal is input to the shift register via the start pulse signal control circuit, whereby the shift register A digital video signal is input to and held in the first latch by the timing signal, and the digital video signal held in the first latch is output to the second latch by the latch signal. The digital video signal input and held, input and held in the second latch is input to the plurality of pixels,
The start pulse signal control circuit supplies a fixed fixed potential to the shift register instead of the start pulse signal for a certain period, so that the number of bits of the digital video signal input to and held in the first latch is controlled. And a display device characterized in that the number is reduced.

The start pulse signal control circuit is NAN
D and an inverter, and a start pulse signal and a selection signal are input to the NAND, and the NAND
May be output from the start pulse signal control circuit via the inverter.

The start pulse signal control circuit has a first analog switch, a second analog switch, and an inverter.
A selection signal is input to a second control input terminal of the first analog switch and a first control input terminal of the second analog switch.
Control input terminal and the second analog switch
A selection signal is input to a control input terminal of the first analog switch, a start pulse signal is input to an input terminal of the first analog switch, a fixed potential is applied to an input terminal of the second analog switch, and the first analog switch is And the second
The signal output from the output terminal of the analog switch of
The signal may be output from the start pulse signal control circuit.

According to the present invention, there is provided a display device having a plurality of pixels having a plurality of light emitting elements and a monitor light emitting element, wherein a current flowing through the plurality of light emitting elements is obtained by using a temperature characteristic of the monitor light emitting element. The display device is characterized in that the size of is kept constant.

According to the present invention, there is provided a display device having a pixel portion having a plurality of pixels, a power supply line, a buffer amplifier, a light emitting element for monitoring, and a constant current source, wherein the plurality of pixels include a thin film transistor. A light-emitting element for monitoring, and the light-emitting element for monitoring and the light-emitting element each include a first electrode, a second electrode, and an organic light-emitting element provided between the first electrode and the second electrode. A first electrode of the monitor light emitting element and the constant current source, and a first electrode of the monitor light emitting element and a non-inverting input of the buffer amplifier. A terminal is connected, an output terminal of the buffer amplifier is connected to the power supply line, and a potential of the power supply line is applied to a first electrode of the light emitting element through the thin film transistor. Display device comprising Rukoto is provided.

According to the present invention, there is provided a display device including a pixel portion having a plurality of pixels, a power supply line, a buffer amplifier, a light emitting element for monitoring, a constant current source, and an adding circuit, wherein The pixel includes a thin film transistor and a light-emitting element, and the monitor light-emitting element and the light-emitting element are provided between a first electrode, a second electrode, and the first electrode and the second electrode. And a first electrode of the monitor light-emitting element and the constant current source are connected to each other, and the first electrode of the monitor light-emitting element and the buffer amplifier are provided. The non-inverting input terminal of the buffer amplifier is connected, the output terminal of the buffer amplifier is connected to the input terminal of the addition circuit, the output terminal of the addition circuit is connected to the power supply line, A display device, wherein the power terminal and the output terminal always have a constant potential difference, and the potential of the power supply line is given to the first electrode of the light emitting element via the thin film transistor. Is provided.

The present invention may be a video camera, an image reproducing apparatus, a head mounted display, a mobile phone or a portable information terminal using the display device.

[0046]

(Embodiment 1) A first configuration of the present invention will be described. FIG. 1 shows a block diagram of a light emitting device having the first structure of the present invention.

Reference numeral 101 denotes a pixel portion in which a plurality of pixels are provided in a matrix. 102 is a source signal line driving circuit, and 103 is a gate signal line driving circuit.

The source signal line driving circuit 102 has a shift register 102-1, a latch (A) 102-2, a latch (B) 102-3, and a switching circuit 102-4. Note that the source signal line driver circuit of the present invention may include a level shift, a buffer, and the like in addition to the above-described components.

Although not shown, the gate signal line driving circuit 103 has a shift register and a buffer. In some cases, a level shift may be provided in addition to the shift register and the buffer. The gate signal line is connected to the gate electrode of the pixel TFT for one line.
Since all pixel TFTs for a line must be turned on at the same time, a buffer capable of flowing a large current is used.

In the source signal line driving circuit 102, a clock signal (CLK) and a start pulse (SP) are input to the shift register 102-1. The shift register 102-1 sequentially generates a timing signal based on the clock signal (CLK) and the start pulse (SP), and sequentially supplies the timing signal to a subsequent circuit.

The timing signal output from the shift register 102-1 may be sequentially supplied to a subsequent circuit through a buffer or the like (not shown).
The timing signal from the shift register 102-1 is buffer-amplified by a buffer or the like. The wiring to which the timing signal is supplied has a large load capacitance (parasitic capacitance) because many circuits or elements are connected. This buffer is provided to prevent "dulling" of the rise or fall of the timing signal caused by the large load capacitance.

The timing signal output from the shift register 102-1 is supplied to the latch (A) 102-2. The latch (A) 102-2 has a plurality of stages of latches for processing n-bit digital video signals. Latch (A) 1
When the timing signal is input, 02-2 sequentially captures and holds an n-bit digital video signal supplied from outside the source signal line driving circuit 102.

When the digital video signal is taken into the latch (A) 102-2, the digital video signal may be sequentially input to the latches of a plurality of stages of the latch (A) 102-2. However, the present invention is not limited to this configuration. Latches of a plurality of stages included in the latch (A) 102-2 may be divided into several groups, and a so-called division drive in which digital video signals are input simultaneously in parallel for each group may be performed. The number of groups at this time is called a division number. For example, when the latch is divided into groups for every four stages, it is referred to as divided drive in four divisions.

The period until the writing of the digital video signal to the latches of all the stages of the latch (A) 102-2 is completed is called a line period. That is, from the time when the writing of the digital video signal is started to the latch of the leftmost stage in the latch (A) 102-2,
The time interval until the end of the writing of the digital video signal to the latch of the rightmost stage is the line period. Actually, the line period may include a period obtained by adding the horizontal retrace period to the line period.

When one line period ends, the latch (B)
Latch signals are supplied to 102-3. At this moment, the digital video signal written and held in the latch (A) 102-2 is shifted to the latch (B) 10-2.
The data is simultaneously transmitted to 2-3 and written and held in the latches of all the stages of the latch (B) 102-3.

The digital video signal is latched (B) 102
-3 has been sent to the latch (A) 102-2 based on the timing signal from the shift register 102-1.
Again, writing of the digital video signal supplied from outside the source signal line driving circuit 102 is sequentially performed.

During the second one line period, the digital video signals written and held in the latch (B) 102-2 are simultaneously input to the switching circuit 102-4. The switching circuit 102-4 outputs a switching signal (Shif
t Signals), the digital video signal input from the latch (B) 102-2 is inverted or output without being inverted.

The digital video signal is "0" or "1"
The digital video signals of “0” and “1” are signals having one Hi voltage and one Lo voltage. Inverting the polarity of a digital video signal means
Converting a digital video signal having information of "0" into a digital video signal having information of "1" and converting a digital video signal having information of "1" into a digital video signal having information of "0"; Means

The switching signal is supplied to the latch (B) 102
-2 is a signal for selecting whether or not to invert the polarity of the digital video signal input from -2. The average of the length of the light emitting period of all the light emitting elements in one frame period is longer than half the length of the light emitting period of the light emitting element in one frame period when the pixel portion 101 displays all white. When it becomes longer, the power consumption can be reduced by inverting the polarity of the digital video signal by the switching signal. Conversely, the average of the length of the light emitting period of all the light emitting elements in one frame period is the length of the light emitting period of the light emitting element in one frame period when the pixel portion 101 displays all white. When it's shorter than half,
The power consumption can be reduced by not inverting the polarity of the digital video signal by the switching signal.

Whether or not the polarity of the digital video signal is inverted by the switching signal may be selected by the user, or may be automatically selected depending on the displayed image.

The digital video signal output from the switching circuit 102-4 is input to a source signal line.

On the other hand, in the gate signal line driving circuit 103, a gate signal from a shift register (not shown) is input to a buffer (not shown) and input to a corresponding gate signal line (also referred to as a scanning line). .

According to the gate signal input to the gate signal line, the digital video signal input to the source signal line is input to the pixel.

In the present invention, the source signal line driving circuit 102 and the gate signal line driving circuit 103
1 may be formed on the same substrate, or may be formed on an IC chip and connected to the pixel portion 101 via FPC, TAB, or the like.

According to the above configuration of the present embodiment, when a light-emitting device that performs time-division gray scale display by digital driving performs monochrome display, the brightness of the image can be inverted by the image displayed in the pixel portion. Specifically, the average of the lengths of the light emitting periods of all the light emitting elements in one frame period is the length of the light emitting period of the light emitting elements in one frame period when the pixel portion 101 displays all white. In the case where the length is longer than half, the brightness of the image displayed in the pixel portion may be reversed. Conversely, the average of the length of the light emitting period of all the light emitting elements in one frame period is the length of the light emitting period of the light emitting element in one frame period when the pixel portion 101 displays all white. When the length is shorter than half, it is better not to invert the brightness of the image displayed on the pixel portion.

In this embodiment mode, the switching circuit is included in the source signal line driving circuit. However, the switching circuit is not included in the source signal line driving circuit. Is also good.

In this embodiment, only the case where a digital video signal is used has been described. However, the present invention can be applied to not only a digital video signal but also an analog video signal.

Therefore, according to the first configuration of the present invention, the magnitude of the current flowing through the light emitting element can be suppressed to some extent, and the power consumption of the light emitting device can be suppressed.

(Embodiment 2) Next, a second configuration of the present invention will be described. FIG. 2 is a block diagram of a light emitting device having the second configuration of the present invention. The same components as those shown in FIG. 1 are denoted by the same reference numerals as those in FIG.

In the light emitting device of this embodiment mode, the clock signal control circuit 106 can apply a constant potential to the shift register 102-1 instead of the clock signal (CLK).

Specifically, the clock signal control circuit 106
Thus, a constant potential (fixed potential) is input to the shift register 102-1 instead of the clock signal for a fixed period. With the above configuration, the first to m-th bits (m is 1
The timing signal for writing the digital video signals of lower bits from (an arbitrary integer from to n) to the latch (A) 102-2 is not input to the latch (A) 102-2. Therefore, out of the n bits of the digital video signal input from the outside of the source signal line driving circuit 102, only the digital video signals of the upper bits from the (m + 1) th bit to the nth bit are latched (A) 102-2
Can be written to.

The light emitting device of this embodiment is different from the light emitting device of FIG.
02-4. Therefore, the latch (B) 10
The digital video signal written and held in 2-3 is input to the source signal line by the latch signal input to the latch (B) 102-3.

In this embodiment mode, in a light-emitting device that performs time-division gray scale display by digital driving, a digital video signal input to a source signal line driver circuit of the light-emitting device is reduced in bit number before the pixel portion. Is being entered. Specifically, the number of bits of the digital video signal input to the pixel portion is reduced by cutting down the digital video signal in order from the least significant bit.

With the above structure, the number of bits of the digital video signal input to the pixel is reduced, so that the number of times the digital video signal is written to the pixel by the source signal line driving circuit and the gate signal line driving circuit is reduced.
Therefore, power consumption of the source signal line driver circuit and the gate signal line driver circuit can be reduced, and power consumption of the light-emitting device can also be reduced.

In this embodiment mode, the clock signal control circuit 106 may be formed on the same substrate as the pixel portion 101, or may be formed on an IC chip.

(Embodiment 3) Next, an example of a second configuration of the present invention, which is different from Embodiment 2, will be described. FIG. 3 is a block diagram of a light emitting device having the second configuration of the present invention. The same components as those shown in FIG. 1 are denoted by the same reference numerals as those in FIG.

In the light emitting device of this embodiment mode, the shift register 102-1 is controlled by the timing signal control circuit 107.
A constant potential can be applied to the latch (A) 102-2 instead of the timing signal output from the latch.

More specifically, the timing signal control circuit 10
7, a fixed potential (fixed potential) is applied to the latch (A) 102-2 instead of the timing signal output from the shift register 102-1 for a certain period. With the above configuration, only the timing signal for writing the digital video signal of the lower bits from the first bit to the m-th bit (m is an arbitrary integer from 1 to n) into the latch (A) 102-2 is latched (A) 102-2. -2 was not entered. Therefore, of the n bits of the digital video signal input from outside the source signal line driving circuit 102, m + 1
Only the digital video signal of the upper bits from the bit to the n-th bit can be written to the latch (A) 102-2.

In the present embodiment, the fixed potential needs to be such that a digital video signal is not written in the latch (A) 102-2.

In this embodiment mode, in a light-emitting device which performs time-division gray scale display of digital driving, a digital video signal input to a source signal line driving circuit of the light-emitting device is reduced in bit number before the pixel portion Is being entered. Specifically, the number of bits of the digital video signal input to the pixel portion is reduced by cutting down the digital video signal in order from the least significant bit.

According to the above structure, the number of bits of the digital video signal input to the pixel is reduced, so that the number of times the digital video signal is written to the pixel by the source signal line driving circuit and the gate signal line driving circuit is reduced.
Therefore, power consumption of the source signal line driver circuit and the gate signal line driver circuit can be reduced, and power consumption of the light-emitting device can also be reduced.

In this embodiment mode, the timing signal control circuit 107 may be formed on the same substrate as the pixel portion 101, or may be formed on an IC chip.

(Embodiment 4) Next, an example of a second configuration of the present invention, which is different from Embodiments 2 and 3, will be described. FIG. 4 shows a block diagram of a light emitting device having the second configuration of the present invention. Note that the same components as those shown in FIG.
The same reference numerals as in FIG.

In the light emitting device of this embodiment, the start pulse signal control circuit 108 applies a constant potential instead of the start pulse signal (SP) to the shift register 10.
2-1.

More specifically, only the timing signal for writing the digital video signal of the lower bits from the first bit to the m-th bit (m is an arbitrary integer from 1 to n) is latched. (A) The start pulse signal control circuit 108 applies a fixed potential (fixed potential) to the shift register 102-1 for a fixed period instead of the start pulse signal so as not to be input to the 102-2. Therefore, of the n bits of the digital video signal input from outside the source signal line driving circuit 102, (m + 1)
Only the digital video signal of the upper bits from the bit to the n-th bit can be written to the latch (A) 102-2.

In the present embodiment, the fixed potential needs to be such that no timing signal is output from shift register 102-1.

In this embodiment mode, in a light-emitting device that performs time-division gray scale display by digital driving, a digital video signal input to a source signal line driver circuit of the light-emitting device is reduced in bit number before the pixel portion. Is being entered. Specifically, the number of bits of the digital video signal input to the pixel portion is reduced by cutting down the digital video signal in order from the least significant bit.

With the above structure, the number of bits of the digital video signal input to the pixel is reduced, so that the number of times the digital video signal is written to the pixel by the source signal line driving circuit and the gate signal line driving circuit is reduced.
Therefore, power consumption of the source signal line driver circuit and the gate signal line driver circuit can be reduced, and power consumption of the light-emitting device can also be reduced.

In this embodiment, the start pulse signal control circuit 108 may be formed on the same substrate as the pixel portion 101 or may be formed on an IC chip.

(Embodiment 5) Next, a third configuration of the present invention will be described with reference to FIG. Reference numeral 501 denotes a power supply line. Note that a power supply line in this specification is a wiring for applying a predetermined potential to a pixel electrode included in a light-emitting element in a pixel portion by a digital video signal input to a source signal line. In this specification, the potential of the power supply line is referred to as a power supply potential.

Reference numeral 502 denotes a buffer amplifier (buffer amplifier); 503, a light emitting element for monitoring; and 504, a constant current source. One electrode of the monitor light emitting element 503 is connected to the constant current source 504,
A constant current always flows through 3. When the temperature of the organic compound layer included in the light-emitting element changes, the potential of the electrode of the monitor light-emitting element 503 connected to the constant current source 504 changes instead of the magnitude of the current flowing through the monitor light-emitting element 503 changing. Change.

On the other hand, the buffer amplifier 502 has two input terminals and one output terminal. One of the two input terminals is a non-inverted input terminal (+), and the other is an inverted input terminal (-). is there. The potential of one electrode of the monitor light emitting element 503 is supplied to a non-inverting input terminal of the buffer amplifier 502.

The buffer amplifier 502 includes a constant current source 504
Is a circuit that prevents the potential of the pixel electrode of the monitor light emitting element 503 connected to the power supply line 501 from being changed by a load such as a wiring capacity of the power supply line 501. Therefore, the buffer amplifier 50
2 is supplied to the power supply line 5
The signal is output from the output terminal without being changed by a load such as a wiring capacitance of No. 01, and is supplied to a power supply line as a power supply potential.

Therefore, even when the temperature of the monitor light emitting element 503 or the organic compound layer of the light emitting element in the pixel portion changes due to the change of the environmental temperature, the power supply potential changes so that a constant current flows through the light emitting element. Therefore, even if the environmental temperature of the light emitting device increases, it is possible to suppress an increase in power consumption of the light emitting device.

In the present embodiment, the buffer amplifier 502, the monitor light emitting element 503, the constant current source 504
May be formed on the same substrate as the pixel portion.
It may be formed on a C chip. The monitor light-emitting element 503 may be included in the pixel portion or may be provided separately from the pixel portion.

According to the present invention, it is possible to suppress the power consumption of the light emitting device and the electronic equipment using the light emitting device by the first to third configurations described above. The present invention only needs to have any one of the first to third configurations. Further, a plurality of the first to third configurations may be provided, or all of the first to third configurations may be provided.

According to the present invention, power consumption of the light emitting device can be suppressed by the above three configurations.

[0098]

Embodiments of the present invention will be described below.

(Embodiment 1) In this embodiment, a structure of a pixel portion of a light emitting device of the present invention and a driving method thereof will be described.

FIG. 6 is an enlarged view of the pixel portion 301 of the light emitting device of this embodiment. Source signal lines (S1 to Sx), power supply lines (V1 to Vx), and gate signal lines (G1 to Gy) are provided in the pixel portion 301.

In this example, the source signal lines (S1 to S
x), a power supply line (V1 to Vx), and a gate signal line (G1 to Gy). The pixel portion 301 includes a plurality of pixels 30 in a matrix.
4 will be arranged.

FIG. 7 is an enlarged view of the pixel 304. In FIG. 7, reference numeral 305 denotes a switching TFT. The gate electrode of the switching TFT 305 is connected to the gate signal line G.
(G1 to Gx). Switching TF
One of the source region and the drain region of T305 is connected to the source signal line S (S1 to Sx), and the other is connected to the current control TF.
Gate electrode of T306, capacitor 30 of each pixel
8 respectively.

The capacitor 308 is a switching TFT.
When 305 is in a non-selection state (off state), it is provided to hold a gate voltage (potential difference between a gate electrode and a source region) of the current control TFT 306. Note that although the structure in which the capacitor 308 is provided is described in this embodiment mode, the present invention is not limited to this structure.
May not be provided.

One of the source region and the drain region of the current controlling TFT 306 is connected to the power supply line V (V1 to V
x), and the other is connected to the light emitting element 307. The power supply line V is connected to the capacitor 308.

The light emitting element 307 includes an anode and a cathode, and an organic compound layer provided between the anode and the cathode. When the anode is connected to the source region or the drain region of the current controlling TFT 306, the anode serves as a pixel electrode and the cathode serves as a counter electrode. Conversely, when the cathode is connected to the source region or the drain region of the current controlling TFT 306, the cathode serves as a pixel electrode and the anode serves as a counter electrode.

The opposing potential of the opposing electrode of the light emitting element 307 is applied. The power supply line V is supplied with a power supply potential. The power supply potential and the counter potential are provided to the light emitting device of the present invention by a power supply provided by an external IC or the like.

As the switching TFT 305 and the current controlling TFT 306, either an n-channel TFT or a p-channel TFT can be used. However, when the source region or the drain region of the current control TFT 306 is connected to the anode of the light emitting element 307, the current control TFT 306 is preferably a p-channel TFT. When the source region or the drain region of the current control TFT 306 is connected to the cathode of the light emitting element 307, the current control TFT 306 is an n-channel TFT.
It is desirable that

The switching TFT 305 and the current control TFT 306 may have a multi-gate structure such as a double gate structure or a triple gate structure instead of a single gate structure.

Next, a method for driving the light emitting device of the present invention having the above-described configuration will be described with reference to FIG.

First, the power supply potential of the power supply line becomes the same as the potential of the counter electrode of the light emitting element. And the gate signal line G1
, A gate signal is input from the gate signal line driving circuit. As a result, the switching TFTs 3 of all pixels (pixels on the first line) connected to the gate signal line G1
05 is turned on.

At the same time, the source signal lines (S1 to S
x), the first bit digital video signal is input from the source signal line driving circuit. The digital video signal is supplied to the current control TFT 30 via the switching TFT 305.
6 is input to the gate electrode.

Next, at the same time when the input of the gate signal to G1 ends, the gate signal is similarly input to the gate signal line G2. Then, the switching TFTs 305 of all the pixels connected to the gate signal line G2 are turned on, and the first bit digital video signal is input to the pixels of the second line from the source signal lines (S1 to Sx). .

Then, all the gate signal lines (G1 to G1)
Gx) is input with a gate signal. The period from when all the gate signal lines (G1 to Gx) are selected and when the first bit digital video signal is input to the pixels on all the lines is the writing period Ta1.

When the writing period Ta1 ends, the light emission period Tr1 starts. In the light emitting period Tr1, the power supply potential of the power supply line becomes a potential having a potential difference between the power supply line and the counter electrode to such an extent that the light emitting element emits light when the power supply potential is applied to the pixel electrode of the light emitting element.

In this embodiment, when the digital video signal has information of “0”, the current control TFT 3
06 is off. Therefore, the light emitting element 307
No power supply potential is applied to the pixel electrodes. as a result,
The light emitting element 307 included in the pixel to which the digital video signal having the information “0” is input does not emit light.

Conversely, when the information has the information “1”, the current control TFT 306 is in the ON state. Therefore, a power supply potential is applied to the pixel electrode of the light-emitting element 307. As a result, the light emitting element 307 included in the pixel to which the digital video signal having the information “1” is input emits light.

As described above, in the display period Tr1, the light emitting element 307 emits light or does not emit light, and all the pixels perform display. A period during which the pixel performs display is called a display period Tr. In particular, a display period started when the first bit digital video signal is input to the pixel is referred to as Tr1. In FIG. 8, for the sake of simplicity, only the display period of the pixels on the first line is particularly shown. The timing at which the display periods of all the lines are started is the same.

When the display period Tr1 ends, the writing period Ta
The power supply potential of the power supply line becomes equal to the potential of the counter electrode of the light emitting element. Then, as in the case of the writing period Ta1, all the gate signal lines are sequentially selected, and the second bit digital video signal is input to all the pixels. A period until the digital video signal of the second bit is completely input to the pixels of all lines is referred to as a writing period Ta2.

When the writing period Ta2 ends, the display period Tr
2 and the power supply potential of the power supply line becomes a potential having a potential difference with the counter electrode to such an extent that the light emitting element emits light when the power supply potential is applied to the pixel electrode of the light emitting element. Then, all the pixels perform display.

The above operation is repeated until the n-th bit digital video signal is input to the pixel, and the writing period Ta and the display period Tr appear repeatedly. When all the display periods (Tr1 to Trn) end, one image can be displayed. In the driving method of the present invention, a period during which one image is displayed is referred to as one frame period (F).
When one frame period ends, the next frame period starts. Then, the writing period Ta1 appears again, and the above operation is repeated.

In a normal light emitting device, it is preferable to provide 60 or more frame periods per second. When the number of images displayed in one second is less than 60, flickering of the images may start to be noticeable.

In this embodiment, the sum of the lengths of all the writing periods is shorter than one frame period, and the length ratio of the display periods is Tr1: Tr2: Tr3:...: Tr (n−
1): Trn = 2 ⁰ : 2 ¹ : 2 ² : ...: 2 ^(n-2) : 2 ^(n-1)
It is necessary that A desired gradation display out of 2 ⁿ gradations can be performed by the combination of the display periods.

By calculating the sum of the lengths of the display periods in which the light-emitting elements emit light during one frame period, the gradation displayed by the pixel in the frame period is determined. For example, if n = 8 and the luminance when the pixel emits light in all display periods is 100%, when the pixel emits light in Tr1 and Tr2, 1% luminance can be expressed.
When Tr5 and Tr8 are selected, 60% luminance can be expressed.

The display periods Tr1 to Trn may appear in any order. For example, during one frame period, the display periods can appear in the order of Tr1, Tr5, Tr2,... Next to Tr1.

In this embodiment, the height of the power supply potential of the power supply line is changed between the writing period and the display period, but the present invention is not limited to this. A potential difference such that the light emitting element emits light when the power supply potential is applied to the pixel electrode of the light emitting element may always be provided between the power supply potential and the potential of the counter electrode. In that case, the light emitting element can emit light even in the writing period. Therefore, the gradation displayed by the pixel in the frame period is determined by the sum of the length of the writing period and the length of the display period in which the light-emitting element emits light in one frame period. In this case, the ratio of the sum of the lengths of the writing period and the display period corresponding to the digital video signal of each bit is (Ta1 + Tr1) :( Ta2 + Tr2) :( T
a3 + Tr3): ... :( Ta (n-1) + Tr (n-
1)): (Tan + Trn) = 2 ⁰ : 2 ¹ : 2 ² : ...: 2
^(n-2) : It is necessary to be 2 ^(n-1) .

(Embodiment 2) In this embodiment, the structure of the pixel portion of the light emitting device of the present invention and its driving method will be described in Embodiment 1.
An example different from the above will be described.

FIG. 9 shows an example of a block diagram of the light emitting device of this embodiment. The light emitting device shown in FIG.
The pixel portion 901 by FT, a source signal side drive circuit 902 arranged around the pixel portion, a write gate signal side drive circuit (first gate signal line drive circuit) 903a, and an erase gate signal line drive circuit (second gate) Signal line drive circuit)
903b. In this embodiment, the light emitting device has one source signal side drive circuit. However, in this embodiment, there may be two source signal side drive circuits.

The source signal side drive circuit 902 has at least one of the first to third configurations of the present invention.

In this embodiment, the source signal line drive circuit 902 and the write gate signal side drive circuit 903a
And the erasing gate signal line driving circuit 903b
01 may be formed on the same substrate, or may be formed on an IC chip and connected to the pixel portion 901 via a connector such as FPC or TAB.

FIG. 10 is an enlarged view of the pixel portion 901. Source signal lines (S1-Sx), power supply lines (V1-V
x), write gate signal line (first gate signal line)
(Ga1 to Gay) and an erasing gate signal line (second gate signal line) (Ge1 to Gey) are provided in the pixel portion 901.

A source signal line (S1 to Sx), a power supply line (V1 to Vx), and a write gate signal line (Ga1
To Gay) and the gate signal line for erasing (Ge1 to Gey)
Is a pixel 904. The pixel portion 901 includes a plurality of pixels 90 in a matrix.
4 will be arranged.

An enlarged view of the pixel 904 is shown in FIG. FIG.
In 1, reference numeral 907 denotes a switching TFT. The gate electrode of the switching TFT 907 is connected to a write gate signal line Ga (Ga1 to Gay). One of the source region and the drain region of the switching TFT 907 is connected to the source signal line S (S1 to Sx), the other is the gate electrode of the current control TFT 908, the capacitor 912 of each pixel, and the source region or drain of the erasing TFT 909. Each is connected to an area.

The capacitor 912 is a switching TFT.
When 907 is in a non-selection state (off state), it is provided to hold the gate voltage of the current control TFT 908. Although the structure in which the capacitor 912 is provided is described in this embodiment, the present embodiment is not limited to this structure, and a structure in which the capacitor 912 is not provided may be employed.

One of the source region and the drain region of the current controlling TFT 908 has one of the power supply lines V (V1 to V
x), and the other is connected to the light emitting element 910. The power supply line V is connected to the capacitor 912.

The other of the source and drain regions of the erasing TFT 909 that is not connected to the source or drain region of the switching TFT 907 is connected to the power supply line V. The erasing TFT 90
The gate electrode 9 is connected to the erasing gate signal line Ge.

The light emitting element 910 is composed of an anode and a cathode, and an organic compound layer provided between the anode and the cathode. When the anode is connected to the source region or the drain region of the current controlling TFT 908, the anode serves as a pixel electrode and the cathode serves as a counter electrode. Conversely, when the cathode is connected to the source region or the drain region of the current controlling TFT 908, the cathode serves as a pixel electrode and the anode serves as a counter electrode.

A counter electrode 911 of the light emitting element 910 is provided with a counter potential. The power supply line V is supplied with a power supply potential. The potential difference between the opposing potential and the power supply potential is always kept at such a level that the light emitting element emits light when the power supply potential is applied to the pixel electrode. The power supply potential and the counter potential are provided to the light emitting device of the present invention by a power supply provided by an external IC or the like.

In a current typical light emitting device, when the light emission amount per pixel light emitting area is 200 cd / m ² , a current per pixel area is required to be about several mA / cm ² . Therefore, particularly when the screen size becomes large, it becomes difficult to control the level of the potential given from the power supply provided in the IC with the switch. In this embodiment,
The power supply potential and the counter potential are always kept constant, and it is not necessary to control the height of the potential given from the power supply provided in the IC with a switch, which is useful for realizing a panel with a larger screen size.

The switching TFT 907, the current controlling TFT 908, and the erasing TFT 909 are n-channel TFTs.
Either FT or p-channel TFT can be used. However, when the source region or the drain region of the current control TFT 908 is connected to the anode of the light emitting element 910, the current control TFT 908 is a p-channel type TFT.
Preferably, it is FT. The current control TFT 9
08 is a light emitting element 910
Current control TFT 908 when connected to the
Is preferably an n-channel TFT.

The switching TFT 907, the current controlling TFT 908, and the erasing TFT 909 may have a multi-gate structure such as a double gate structure or a triple gate structure instead of a single gate structure.

Next, a method for driving the light emitting device of the present invention having the above-described configuration will be described with reference to FIG.

First, all the pixels (pixels on the first line) connected to the write gate signal line Ga1 are generated by the write gate signal input to the write gate signal line Ga1 from the write gate signal line drive circuit 903a. Of the switching TFT 907 is turned on. Note that in this specification, a state in which all the TFTs whose gate electrodes are connected to a signal line are turned on is referred to as a selected wiring. Therefore, in this case, the write gate signal line Ga1 is selected.

At the same time, the source signal lines (S1 to S
In x), the first bit digital video signal is input from the source signal line driver circuit 902 to the pixels on the first line.
Specifically, the digital video signal is a switching TFT
The signal is input to the gate electrode of the current control TFT 908 via the switch 907.

In this embodiment, when the digital video signal has information of “0”, the current control TFT 90
8 turns off. Therefore, no power supply potential is applied to the pixel electrode of the light-emitting element 910. As a result, the light emitting element 910 included in the pixel to which the digital video signal having the information “0” is input does not emit light.

Conversely, when the information has the information “1”, the current controlling TFT 908 is turned on. Therefore, a power supply potential is applied to the pixel electrode of the light-emitting element 910. As a result, the light emitting element 910 included in the pixel to which the digital video signal having the information “1” is input emits light.

As described above, at the same time when the digital video signal is input to the pixels on the first line, the light emitting element 910 emits light or does not emit light, and the pixels on the first line perform display. The period during which the pixel is displaying is defined as a display period Tr.
Call. In particular, a display period started when the first bit digital video signal is input to the pixel is referred to as Tr1. In FIG. 12, for the sake of simplicity, only the display period of the pixels on the first line is particularly shown. The timing at which the display period of each line is started has a time difference.

Next, at the same time when the selection of Ga1 is completed, the write gate signal line Ga2 is selected by the write gate signal. Then, the write gate signal line Ga
Switching TFT of all pixels connected to 2
907 is turned on, and the first bit digital video signal is input to the pixels of the second line from the source signal lines (S1 to Sx).

Then, all the write gate signal lines (Ga1 to Gax) are sequentially selected. The period from when all the write gate signal lines (Ga1 to Gax) are selected and when the first bit digital video signal is input to the pixels on all the lines is the write period Ta1.

On the other hand, before the digital video signal of the first bit is input to the pixels of all the lines, in other words, before the writing period Ta1 ends, the input of the digital video signal of the first bit to the pixels is performed in parallel. Thus, the erase gate signal line Ge1 is selected by the erase gate signal input from the erase gate signal line drive circuit 903b.

When the erasing gate signal line Ge1 is selected, the erasing TFTs 909 of all the pixels (pixels on the first line) connected to the erasing gate signal line Ge1 are turned on. Then, the power supply potential of the power supply lines (V1 to Vx) is supplied to the gate electrode of the current control TFT 908 of the pixel on the first line via the erasing TFT 909.

When the power supply potential is applied to the gate electrode of the current control TFT 908, the current control TFT 908 is turned off. Therefore, the power supply potential is not applied to the pixel electrode of the light-emitting element 910, and all the light-emitting elements included in the pixels in the first line do not emit light, and the pixels in the first line do not perform display. That is, the digital video signal held by the gate electrode of the current control TFT from when the write gate signal line Ga1 is selected is erased by applying the power supply potential to the gate electrode of the current control TFT. Therefore, the pixels on the first line do not perform display.

A period during which the pixel does not perform display is referred to as a non-display period T
Called d. The pixels on the first line are the gate signal lines G for erasing.
The display period Tr1 ends at the same time when the erase gate signal is input to e1, and the non-display period Td1 starts.

In FIG. 12, for the sake of simplicity, only the non-display period of the pixels on the first line is shown. Similarly to the display period, the start timing of the non-display period of each line has a time difference.

When the selection of Ge1 is completed,
The erasing gate signal line Ge2 is selected by the erasing gate signal, and the erasing TFTs 909 of all the pixels (pixels on the second line) connected to the erasing gate signal line Ge2.
Is turned on. And power supply lines (V1 to Vx)
Of the current control T through the erase TFT 909.
It is provided to the gate electrode of FT908. When the power supply potential is applied to the gate electrode of the current control TFT 908, the current control TFT 908 is turned off. Therefore, the power supply potential is not applied to the pixel electrode of the light emitting element 910. As a result, the light-emitting elements of the pixels on the second line are all in a non-light emitting state, and the pixels on the second line do not perform display and are in a non-display state.

Then, all the erasing gate signal lines are sequentially selected by the erasing gate signal. An erasing period Te1 is a period from when all the erasing gate signal lines (Ga1 to Gax) are selected until the first bit digital video signal held by the pixels on all the lines is erased.

On the other hand, before the first bit digital video signal held by the pixels of all the lines is erased, in other words, before the erasing period Te1 ends, the first bit digital video signal is applied to the pixels. In parallel with the erasing, the selection of the writing gate signal line Ga1 is performed again. As a result, the pixels on the first line perform display again, so that the non-display period Td1 ends and the display period Tr2 starts.

Similarly, all the write gate signal lines are sequentially selected, and the digital video signal of the second bit is input to all the pixels. A period until the digital video signal of the second bit is completely input to the pixels of all lines is referred to as a writing period Ta2.

On the other hand, before the digital video signal of the second bit is input to the pixels of all the lines, in other words, before the end of the writing period Ta2, the input of the digital video signal of the second bit to the pixels is performed in parallel. Then, the erasing gate signal line Ge2 is selected. Therefore, all the light emitting elements included in the pixels on the first line are in a non-light emitting state, and 1
The pixels on the line do not display. Accordingly, the display period Tr2 ends in the pixels on the first line, and the non-display period Td2 is set.

Then, all the erasing gate signal lines are sequentially selected. All erase gate signal lines (Ga1 to Ga
x) is selected and 2 held by the pixels of all lines
A period until the digital video signal of the bit is erased is an erase period Te2.

The above operation is repeated until the m-th bit digital video signal is input to the pixel, and the display period Tr and the non-display period Td appear repeatedly. The display period Tr1 is a period from the start of the write period Ta1 to the start of the erase period Te1. The non-display period Td1 is a period from the start of the erase period Te1 to the start of the display period Tr2. The display periods Tr2, Tr3,..., Tr (m-1) and the non-display period T
d2, Td3,..., Td (m-1) are also in the display period Tr1.
And the non-display period Td1, the writing period T
a1, Ta2,..., Tam and the erasing periods Te1, Te2,
, Te (m-1) defines the period.

After the m-bit digital video signal is input to the pixels on the first line, the erasing gate signal line Ge1 is not selected. For the sake of simplicity, the present embodiment will be described taking the case of m = n−2 as an example.
It goes without saying that the present invention is not limited to this. In the present invention, m can arbitrarily select a value from 2 to n.

When the (n-2) th bit digital video signal is input to the pixels on the first line, the pixels on the first line enter a display period Tr (n-2) to perform display. Until the next bit of the digital video signal is input, (n
-2) The digital video signal of the bit is held in the pixel.

Next, when the (n-1) th bit digital video signal is input to the pixel on the first line, the (n-2) th bit digital video signal held in the pixel is changed to (n) -1) Rewritten with the digital video signal of the bit. The pixels on the first line are in the display period Tr.
(N-1), and display is performed. The (n-2) th bit digital video signal is held in the pixel until the next bit digital video signal is input.

The above operation is repeated until the n-th bit digital video signal is input to the pixel. The display period Tr (n-2) is a period from the start of the writing period Ta (n-2) to the start of the writing period Ta (n-1). Then, the display period (Tr (n−
The periods 1) and Trn) are determined by the writing period Ta, similarly to the display period Tr (n-2).

In this embodiment, the sum of the lengths of all the writing periods is shorter than one frame period, and the length of the display period is Tr1: Tr2: Tr3: ...: Tr (n-
1): Trn = 2 ⁰ : 2 ¹ : 2 ² : ...: 2 ^(n-2) : 2 ^(n-1)
It is necessary to A desired gradation display out of 2 ⁿ gradations can be performed by the combination of the display periods.

When all display periods (Tr1 to Trn) are completed, one image can be displayed. In the driving method of the present invention, a period during which one image is displayed is referred to as one frame period (F).

After the end of one frame period, the digital video signal of the first bit is input to the pixels again, and the pixels of the first line again enter the display period Tr1. Then, the above operation is repeated again.

In a normal light emitting device, it is preferable to provide 60 or more frame periods per second. When the number of images displayed in one second is less than 60, flickering of the images may start to be noticeable.

By calculating the sum of the lengths of the display periods in which the light emitting elements emit light during one frame period, the displayed gray scale of the pixel in the frame period is determined. For example, if n = 8 and the luminance when the pixel emits light in all display periods is 100%, when the pixel emits light in Tr1 and Tr2, 1% luminance can be expressed.
When Tr5 and Tr8 are selected, 60% luminance can be expressed.

It is important that the writing period Tam in which the m-th bit digital video signal is written to the pixel is shorter than the length of the display period Trm. Therefore, the value of the bit number m is such that the writing period Tam is the display period T among 1 to n.
The value must be shorter than the length of rm.

The display periods (Tr1 to Trn) may appear in any order. For example, during one frame period, after Tr1, Tr4, Tr3, Tr2,.
It is also possible to make the display periods appear in this order.
However, the order in which the erasing periods (Te1 to Ten) do not overlap each other is more preferable.

In this embodiment, the display period Tr and the writing period Ta partially overlap. In other words, the pixels can be displayed even in the writing period. Therefore, the ratio (duty ratio) of the total length of the display periods in one frame period is not determined only by the length of the writing period.

(Embodiment 3) In this embodiment, the first embodiment will be described.
The detailed configuration of the source signal line driver circuit included in the light emitting device shown in FIG. FIG. 13 shows a circuit diagram of the source signal line drive circuit of this embodiment. Note that the same components as those shown in FIG. 1 are denoted by the same reference numerals.

Reference numeral 102-1 denotes a shift register, which stores a clock signal (CLK), a signal with inverted polarity of the clock signal (CLKB), a start pulse signal (SP), and a bidirectional switching signal (SL / R). Each is input from the indicated wiring.

102-2 is a latch (A).
-3 is a latch (B). In this embodiment, one set of latch (A) 102-2 and one set of latch (B) 102-2
Reference numeral 3 corresponds to four source signal lines. However, in this embodiment, the number of source signal lines corresponding to one set of latches (A) 102-2 and one set of latches (B) 102-3 is not limited to this. In this embodiment, the level shift for changing the amplitude of the voltage of the signal is not provided. However, the level shift may be appropriately provided by the designer.

A digital video signal (DV) input from outside the source signal line driving circuit is input to the latch (A) 102-2 from the wiring shown in the figure. Latch signal S_LAT, signal S_LA with inverted polarity of S_LAT
Tb is a value obtained from the wiring shown in FIG.
-3 is input.

The detailed configuration of the latch (A) 102-2 will be described by taking a part 801 of the latch (A) 102-2 as an example. Part 801 of latch (A) 102-2 is 2
It has one clocked inverter and two inverters.

FIG. 14 is a top view of a part 801 of the latch (A) 102-2. 831a and 831b are respectively
A portion 801 of the latch (A) 102-2 is an active layer of a TFT forming one of the inverters, and 836 is a common gate electrode of the TFT forming one of the inverters. Reference numerals 832a and 832b denote active layers of TFTs forming another inverter included in a part 801 of the latch (A) 102-2, respectively.
837b is a gate electrode provided on each of the active layers 832a and 832b. Note that the gate electrodes 837a and 837a
37b is electrically connected.

Each of 833a and 833b is an active layer of a TFT forming one of the clocked inverters included in a part 801 of the latch (A) 102-2. Gate electrodes 838a and 838b are provided on the active layer 833a, and have a double gate structure. On the active layer 833b, gate electrodes 838b and 839 are provided to form a double gate structure.

Reference numerals 834a and 834b denote active layers of TFTs forming another clocked inverter included in a part 801 of the latch (A) 102-2. Gate electrodes 839 and 840 are provided on the active layer 834a to form a double gate structure. Further, gate electrodes 840 and 841 are provided on the active layer 834b to form a double gate structure.

Reference numeral 102-4 denotes a switching circuit. FIGS. 15A and 15B are circuit diagrams of the switching circuit of this embodiment.

The switching circuit 102-4 of this embodiment shown in FIG. 15A has an inverter 851, a first analog switch 852, and a second analog switch 853. Also, the switching signal SS from the wiring shown in FIG.
And a signal SSB in which the polarity of the switching signal is inverted.

The first and second analog switches 852,
FIG. 16 shows an equivalent circuit diagram of the 853. The first and second analog switches 852 and 853 have an n-channel TFT and a p-channel TFT. A signal input from the input terminal (IN) is sampled by a signal input from the first control input terminal (Vin) or the second control input terminal (Vinb), and output from the output terminal (OUT).

The digital video signal from the latch (B) 102-3 is input to the first analog switch 852 from the input terminal (IN) via the inverter 851. At the same time, the digital video signal from the latch (B) 102-3 is input to the second analog switch 853 at the input terminal (I
N).

The switching signal SS and the signal SSB obtained by inverting the polarity of the switching signal are supplied to the first analog switch 852 and the second analog switch 853 via the first control input terminal (Vin) or the second control switch. Input terminal (V
inb). This switching signal S
The digital video signal is sampled by S, and the sampled digital video signal is output from the output terminals (OUT) of the first analog switch 852 and the second analog switch 853.

The digital video signal input to the switching circuit 102-4 is output from the switching circuit 102-4 as it is or with its polarity inverted.
Whether or not the polarity of the digital video signal is inverted in the switching circuit 102-4 is selected by the switching signal SS.

The switching circuit 102-4 of this embodiment shown in FIG. 15B comprises an inverter 861 and a first NAN.
D862, a second NAND 863, and a NOR 864. Also, the switching signal SS from the wiring shown in FIG.
And a signal SSB in which the polarity of the switching signal is inverted.

The digital video signal from the latch (B) 102-3 is passed through an inverter 861. At the same time, a signal SSB in which the polarity of the switching signal SS is inverted.
Is also input to the first NAND 862.

The digital video signal is supplied to the inverter 8
The digital video signal is input to the second NAND 863 at the same time when the digital video signal is input to the first NAND 862 via 61. At the same time, the switching signal SS also becomes the second NA
Input to ND863.

The signals output from the first and second NANDs 862 and 863 are simultaneously input to the NOR 864. The signal output from the NOR 864 is input to a source signal line.

The digital video signal input to the switching circuit 102-4 is output from the switching circuit 102-4 as it is or with its polarity inverted.
Whether or not the polarity of the digital video signal is inverted in the switching circuit 102-4 is selected by the switching signal SS.

Note that the switching circuit is not limited to the configuration shown in FIG. The switching circuit may have any configuration as long as the input digital video signal can be output as it is or with its polarity inverted.

This embodiment can be implemented by freely combining with Embodiments 1 and 2.

(Embodiment 4) In this embodiment, the second embodiment will be described.
The detailed configuration of the source signal line driver circuit included in the light emitting device shown in FIG. FIG. 17 shows a circuit diagram of the source signal line drive circuit of this embodiment. Note that the same components as those shown in FIG. 1 are denoted by the same reference numerals.

Reference numeral 102-1 denotes a shift register, which stores a clock signal (CLK), a signal (CLKB) having an inverted polarity of the clock signal, a start pulse signal (SP), and a bidirectional switching signal (SL / R). Each is input from the indicated wiring.

102-2 is a latch (A).
-3 is a latch (B). In this embodiment, one set of latch (A) 102-2 and one set of latch (B) 102-2
Reference numeral 3 corresponds to four source signal lines. However, in this embodiment, the number of source signal lines corresponding to one set of latches (A) 102-2 and one set of latches (B) 102-3 is not limited to this. In this embodiment, the level shift for changing the amplitude of the voltage of the signal is not provided. However, the level shift may be appropriately provided by the designer.

A digital video signal (DV) input from outside the source signal line driving circuit is input to the latch (A) 102-2 from the wiring shown in the figure. Latch signal S_LAT, signal S_LA with inverted polarity of S_LAT
Tb is a value obtained from the wiring shown in FIG.
-3 is input.

The detailed configuration of the latch (A) 102-2 is the same as that shown in FIG.

Reference numeral 106 denotes a clock signal control circuit which can apply a fixed potential (fixed potential) to the shift register 102-1 instead of the clock signal (CLK) for a fixed period.

Specifically, only the timing signal for writing the digital video signal of the lower 1st bit to the mth bit into the latch (A) 102-2 is the latch (A) 10-2.
In order not to input to 2-2, a fixed potential (fixed potential) is input to the shift register 102-1 instead of the clock signal by the clock signal control circuit 106 for a certain period. Therefore, among the n bits of the digital video signal input from outside the source signal line driving circuit, (m
Only the digital video signals of the upper bits from the (+1) th bit to the nth bit can be written to the latch (A) 102-2.

FIGS. 18A and 18B are detailed circuit diagrams of the clock signal control circuit 106 of this embodiment.

The clock signal control circuit 106 of this embodiment shown in FIG. 18A has a NAND 1801 and an inverter 1802. A selection signal is input from the wiring shown in the figure.

A clock signal input from outside the source signal line driving circuit is supplied from an input terminal (IN) to the NAND 180.
1 is input. At the same time, the selection signal is also supplied to the NAND 180
1 is input. The polarity of the signal output from the NAND 1801 is inverted by the inverter 1802, output from the output terminal (OUT), and input to the shift register 102-1.

The shift register 102 is selected by the selection signal.
Whether the clock signal is input to −1 or a constant potential (fixed potential) is applied is selected.

The clock signal control circuit 106 of the present embodiment shown in FIG.
, A second analog switch 1812, and an inverter 1813. A selection signal is input from the wiring shown in the figure.

First and second analog switches 181
1 and 1812 are the same as those shown in FIG. First and second analog switches 1811, 1
Reference numeral 812 includes an n-channel TFT and a p-channel TFT. First control input terminal (Vin) or second control input terminal (Vin)
The signal input from the input terminal (IN) is sampled by the signal input from the control input terminal (Vinb), and is output from the output terminal (OUT).

A selection signal is applied to the first and second analog switches 1811 and 1812 at the first control input terminal (Vin).
And a selection signal whose polarity is inverted by the inverter 1813 at the same time is supplied to the first and second analog switches 1811 and 1812 via the second control input terminal (V
inb). At the same time, the clock signal CLK input from outside the source signal line driving circuit
Is connected to the input terminal (I
N). A constant potential (fixed potential) is supplied to the second analog switch 1812 from an input terminal (IN).

First and second analog switches 181
1 and 1812 are output from the output terminal (OUT) of the clock signal control circuit 106.
T).

The shift register 102 is selected by the selection signal.
Whether the clock signal is input to −1 or a constant potential (fixed potential) is applied is selected.

Note that the clock signal control circuit is not limited to the configuration shown in FIG.

This embodiment can be implemented by freely combining with Embodiments 1 to 3.

(Embodiment 5) In this embodiment, the third embodiment will be described.
The detailed configuration of the source signal line driver circuit included in the light emitting device shown in FIG. FIG. 19 shows a circuit diagram of the source signal line drive circuit of this embodiment. Note that the same components as those shown in FIG. 1 are denoted by the same reference numerals.

Reference numeral 102-1 denotes a shift register, which stores a clock signal (CLK), a signal with inverted polarity of the clock signal (CLKB), a start pulse signal (SP), and a bidirectional switching signal (SL / R). Each is input from the indicated wiring.

102-2 is a latch (A).
-3 is a latch (B). In this embodiment, one set of latch (A) 102-2 and one set of latch (B) 102-2
Reference numeral 3 corresponds to four source signal lines. However, in this embodiment, the number of source signal lines corresponding to one set of latches (A) 102-2 and one set of latches (B) 102-3 is not limited to this. In this embodiment, the level shift for changing the amplitude of the voltage of the signal is not provided. However, the level shift may be appropriately provided by the designer.

A digital video signal (DV) input from outside the source signal line driving circuit is input to the latch (A) 102-2 from the wiring shown in the figure. Latch signal S_LAT, signal S_LA with inverted polarity of S_LAT
Tb is a value obtained from the wiring shown in FIG.
-3 is input.

The detailed configuration of the latch (A) 102-2 is the same as that shown in FIG. 14 and will not be described here.

Reference numeral 107 denotes a timing signal control circuit which can apply a fixed potential (fixed potential) to the latch (A) 102-2 instead of the timing signal for a fixed period.

More specifically, only the timing signal for writing the digital video signal of the lower 1st bit to the mth bit into the latch (A) 102-2 is provided by the latch (A) 10-2.
A fixed potential (fixed potential) is applied to the latch (A) 102-2 instead of the timing signal output from the shift register 102-1 by the timing signal control circuit 107 for a certain period so as not to input to the 2-2. I did it. Therefore, of the n bits of the digital video signal input from outside the source signal line driving circuit 102, (m + 1)
Only the digital video signal of the upper bits from the bit to the n-th bit can be written to the latch (A) 102-2.

Note that the timing signal control circuit 1 of this embodiment is
Since the configuration of 07 is the same as that shown in FIGS. 18A and 18B, the detailed description of the configuration of the timing signal control circuit 107 is given in the fourth embodiment. However, in this embodiment, the timing signal from the shift register 102-1 is input to the input terminal (IN) of the circuit illustrated in FIGS. A signal output from the output terminal (OUT) of the circuit illustrated in FIGS. 18A and 18B is input to the latch (A) 102-2. The selection signal selects whether a timing signal is input to the latch (A) 102-2 or whether a fixed potential (fixed potential) is applied.

Note that the timing signal control circuit is not limited to the configuration shown in FIG.

This embodiment can be implemented by freely combining with Embodiments 1 to 3.

(Embodiment 6) In this embodiment, Embodiment 4 will be described.
The detailed configuration of the source signal line driver circuit included in the light emitting device shown in FIG. FIG. 20 shows a circuit diagram of the source signal line driving circuit of this embodiment. Note that the same components as those shown in FIG. 1 are denoted by the same reference numerals.

Reference numeral 102-1 denotes a shift register, which stores a clock signal (CLK), a signal (CLKB) having an inverted polarity of the clock signal, a start pulse signal (SP), and a bidirectional switching signal (SL / R). Each is input from the indicated wiring.

102-2 is a latch (A).
-3 is a latch (B). In this embodiment, one set of latch (A) 102-2 and one set of latch (B) 102-2
Reference numeral 3 corresponds to four source signal lines. However, in this embodiment, the number of source signal lines corresponding to one set of latches (A) 102-2 and one set of latches (B) 102-3 is not limited to this. In this embodiment, the level shift for changing the amplitude of the voltage of the signal is not provided. However, the level shift may be appropriately provided by the designer.

A digital video signal (DV) input from outside the source signal line driving circuit is input to the latch (A) 102-2 from the wiring shown in the figure. Latch signal S_LAT, signal S_LA with inverted polarity of S_LAT
Tb is a value obtained from the wiring shown in FIG.
-3 is input.

The detailed configuration of the latch (A) 102-2 is the same as that shown in FIG. 14 and will not be described here.

Reference numeral 108 denotes a start pulse signal control circuit which supplies a fixed potential (fixed potential) to the shift register 102- instead of the start pulse signal (SP) for a fixed period.
1 can be given.

More specifically, only the timing signal for writing the digital video signal of the lower 1st bit to the mth bit into the latch (A) 102-2 is the latch (A) 10-2.
A fixed potential (fixed potential) is applied by the start pulse signal control circuit 108 instead of the start pulse signal by the start pulse signal control circuit 108 for a certain period so as not to be input to the shift register 102-2.
1 was given. Therefore, the source signal line driving circuit 1
02, among the n bits of the digital video signal input from the outside, only the higher-order digital video signals from the (m + 1) th bit to the nth bit are latched (A) 102
-2.

Since the configuration of the start pulse signal control circuit 108 of this embodiment is the same as that shown in FIGS. 18A and 18B, a detailed description of the configuration of the start pulse signal control circuit 108 will be given. Reference is made to Example 4. However, in this embodiment, a start pulse signal is input to the input terminal (IN) of the circuit shown in FIGS. Then, the output terminal (OU) of the circuit shown in FIGS.
T) is output from the shift register 102-1.
Is input to The selection signal selects whether a start pulse signal is input to the shift register 102-1 or whether a fixed potential (fixed potential) is applied.

The timing signal control circuit is not limited to the configuration shown in FIG.

This embodiment can be implemented by freely combining with Embodiments 1 to 3.

(Embodiment 7) In this embodiment, the third embodiment of the present invention will be described.
An example of the configuration different from that described in the fifth embodiment will be described with reference to FIG. In FIG. 21,
Note that the same components as those shown in FIG. 5 are denoted by the same reference numerals.

Reference numeral 501 denotes a power supply line, reference numeral 502 denotes a buffer amplifier (buffer amplifier), reference numeral 503 denotes a monitor light emitting element, reference numeral 504 denotes a constant current source, and reference numeral 505 denotes an addition circuit. One electrode of the monitor light emitting element 503 is connected to a constant current source 504, and a constant current always flows through the monitor light emitting element 503. When the temperature of the organic compound layer included in the light-emitting element changes, the monitor light-emitting element
, The potential of the electrode of the monitoring light emitting element 503 connected to the constant current source 504 changes.

The buffer amplifier 502 has two input terminals and one output terminal. One of the two input terminals is a non-inverted input terminal (+), and the other is an inverted input terminal (-). is there. The potential of one electrode of the monitor light emitting element 503 is supplied to a non-inverting input terminal of the buffer amplifier 502.

The buffer amplifier is a circuit that prevents the potential of the electrode of the monitor light emitting element 503 connected to the constant current source 504 from changing due to a load such as the wiring capacity of the power supply line 501. Therefore, the potential applied to the non-inverting input terminal of the buffer amplifier 502 is output from the output terminal without being changed by a load such as the power supply line 501 or the wiring capacitance of the addition circuit 505, and is applied to the addition circuit 505.

The potential of the output terminal of buffer amplifier 502 applied to addition circuit 505 is applied to power supply line 501 as a power supply potential after a certain potential difference is added or subtracted.

FIG. 22 is a detailed circuit diagram of the adder circuit of this embodiment. The adder circuit 505 includes a first resistor 521 and a second resistor 521.
522, a power supply 525 for an adder circuit, and a non-inverting amplifier circuit 520. The non-inverting amplifier circuit 520 includes a third resistor 523, a fourth resistor 524, a power supply 526 for the non-inverting amplifier circuit, and an amplifier 527.

One terminal of the first resistor 521 is an input terminal (IN) of the adder circuit. Then, the first resistor 521
Is connected to one terminal of the second resistor 522. The other terminal of the second resistor 522 is connected to the power supply 525 for the adding circuit. First resistor 52
The output from between the first and second resistors 522 is input to the non-inverting input terminal (+) of the amplifier 527 of the non-inverting amplifier circuit 520.

One terminal of the third resistor 523 is connected to the amplifier 5
27, and the other terminal of the third resistor 523 is connected to the inverting input terminal of the amplifier 527. Third
An output from between the resistor 523 and the inverting input terminal of the amplifier 527 is input to one terminal of the fourth resistor 524. The other terminal of the fourth resistor 524 is connected to the power supply 526 for the non-inverting amplifier circuit. The output from between the third resistor 523 and the output terminal of the amplifier 527 is
05 is output from the output terminal (OUT).

With the above structure, even when the temperature of the monitor light emitting element 503 or the organic compound layer of the light emitting element in the pixel portion changes due to a change in environmental temperature, the power supply potential is changed so that a constant current flows through the light emitting element. I do. Therefore, even if the environmental temperature of the light emitting device increases, the power consumption of the light emitting device can be prevented from increasing, and the luminance of the light emitting element can be kept constant. And the addition circuit 505
Is provided, it is not necessary to make the potential of the power supply line 501 the same as the potential of the electrode connected to the constant current source 504 of the monitoring light emitting element 503. Therefore, the buffer amplifier 502, the monitor light emitting element 503, and the constant current source 5
04 can be suppressed in magnitude, and as a result, power consumption can be suppressed.

[0241] The addition circuit 505 is not limited to the configuration shown in FIG.

This embodiment can be implemented by freely combining with Embodiments 1 to 6.

(Embodiment 8) In this embodiment, a method for simultaneously manufacturing a pixel portion and a TFT (an n-channel TFT and a p-channel TFT) of a driver circuit around the pixel portion on the same substrate will be described in detail. I do.

First, as shown in FIG. 23A, a substrate 4 made of glass such as barium borosilicate glass or aluminoborosilicate glass typified by Corning # 7059 glass or # 1737 glass, or a quartz substrate.
A base film 401 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate. For example, SiH ₄ , NH ₃ , N
₁₀ to 200 n of silicon oxynitride film made from ₂ O
m (preferably 50 to 100 nm) and Si
A silicon oxynitride hydride film formed from H ₄ and N ₂ O is formed in a thickness of 50 to 200 nm (preferably 100 to 150 nm). Note that in FIG. 23A, the base film is illustrated as one layer. Although the base film 401 has a two-layer structure in this embodiment, the base film 401 may be formed as a single-layer film of the insulating film or a structure in which two or more layers are stacked.

The semiconductor layers 402 to 405 are formed of a semiconductor film having an amorphous structure by using a crystalline semiconductor film manufactured by a laser crystallization method or a known thermal crystallization method. The semiconductor layers 402 to 405 have a thickness of 25 to 80 nm (preferably 30 to 60 nm). The material of the crystalline semiconductor film is not limited, but is preferably formed of silicon or a silicon germanium (SiGe) alloy.

Known crystallization methods include a thermal crystallization method using an electric furnace, a laser annealing crystallization method using laser light, a lamp annealing crystallization method using infrared light,
There is a crystallization method using a catalyst metal.

In order to form a crystalline semiconductor film by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or a YVO ₄ laser is used.
In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is set to 300 Hz, and the laser energy density is set to 100 to 400 mJ / cm ² (typically, ² to 400 mJ / cm 2).
00 to 300 mJ / cm ² ). When a YAG laser is used, its second harmonic is used, the pulse oscillation frequency is 30 to 300 kHz, and the laser energy density is 3
00 to 600 mJ / cm ² (typically 350 to 500 mJ / cm ² )
It is good to Then, a laser beam condensed linearly with a width of 100 to 1000 μm, for example, 400 μm, is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser light at this time is set to 50 to 90%.

Next, a gate insulating film 406 which covers the semiconductor layers 402 to 405 is formed. The gate insulating film 406 has a thickness of 40 to 40
The insulating film containing silicon is formed to have a thickness of 150 nm. In this embodiment, a silicon oxynitride film is formed with a thickness of 120 nm. Needless to say, the gate insulating film 406 is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ are mixed by a plasma CVD method, the reaction pressure is 40 Pa, and the substrate temperature is 300 to 4.
00 ° C., high frequency (13.56 MHz) power density 0.5
It can be formed by discharging at 0.8 W / cm ² . The silicon oxide film thus manufactured is
Good characteristics as a gate insulating film can be obtained by thermal annealing at 0 to 500 ° C.

[0249] Then, a first conductive film 407 and a second conductive film 408 for forming a gate electrode are formed over the gate insulating film 406. In the present embodiment, the first conductive film 40
7 is formed of Ta to a thickness of 50 to 100 nm, and the second conductive film 408 is formed of W to a thickness of 100 to 300 nm.

A Ta film is formed by a sputtering method, and a Ta target is sputtered with Ar. In this case, when an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relaxed and the film can be prevented from peeling. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used for the gate electrode, but the resistivity of the β-phase Ta film is about 180 μΩcm and is not suitable for the gate electrode. α phase T
If a film of tantalum nitride having a crystal structure close to that of the α phase of Ta is formed on a base of Ta with a thickness of about 10 to 50 nm to form the a film, a Ta film of the α phase can be easily obtained. .

When forming a W film, it is formed by a sputtering method using W as a target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to lower the resistance in order to use it as a gate electrode.
It is desirable to set the resistance to Ωcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when the W film contains many impurity elements such as oxygen, the crystallization is inhibited and the resistance is increased. Accordingly, in the case of using the sputtering method, a W target having a purity of 99.99% or 99.9999% is used, and further, a W film is formed with sufficient care so as not to mix impurities from the gas phase during film formation. Thereby, a resistivity of 9 to 20 μΩcm can be realized.

In this embodiment, the first conductive film 407 is used.
Is Ta, and the second conductive film 408 is W. However, there is no particular limitation, and any of them is an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material containing the above element as a main component or It may be formed of a compound material. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Another example of the combination other than the present embodiment is that the first conductive film is formed of tantalum nitride (Ta).
N), the second conductive film is made of W, the first conductive film is made of tantalum nitride (TaN), the second conductive film is made of Al, and the first conductive film is nitrided. The second conductive film is preferably formed using tantalum (TaN) in combination with Cu. (FIG. 23
(B))

Next, resist masks 409 to 41 are used.
2 and a first etching process for forming electrodes and wirings is performed. In this embodiment, the ICP (Inductively
Coupled Plasma: Inductively coupled plasma) etching method, CF ₄ and Cl ₂ are mixed in an etching gas, and 1 Pa
500W RF (13.56MHz) to coil type electrode at pressure of
Power is supplied to generate plasma. 100 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage) and a substantially negative self-bias voltage is applied. CF ₄
When Cl and Cl ₂ are mixed, both the W film and the Ta film are etched to the same extent.

Although not shown in FIG. 23C,
Under the above etching conditions, by making the shape of the resist mask appropriate, the edges of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. Angle of taper part is 15 ~
45 °. In order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased by about 10 to 20%. Since the selectivity of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the exposed surface of the silicon oxynitride film is etched by about 20 to 50 nm by the over-etching process. Although not shown in FIG. 23C, the region of the gate insulating film 406 which is not covered with the first shape conductive layers 414 to 417 by the etching is 20 to 5.
It was etched by about 0 nm and became thin.

Thus, by the first etching process, the first shape conductive layers 414 to 417 (the first conductive layers 414 a to 417 a and the second conductive layer 414 b) formed of the first conductive layer and the second conductive layer are formed. To 417b).

Next, a second etching process is performed as shown in FIG. Similarly, using an ICP etching method, CF ₄ , Cl ₂ and O ₂ are mixed in an etching gas,
RF power of 500 W (13.
(56 MHz) to generate plasma. RF power (13.56 MHz) of 50 W is applied to the substrate side (sample stage), and a lower self-bias voltage is applied than in the first etching process. Under such conditions, the W film is anisotropically etched, and Ta, which is the first conductive layer, is anisotropically etched at a lower etching rate to form the second shape conductive layers 419-422 (first Conductive layers 419a to 422a
And second conductive layers 419b to 422b). Although not shown in FIG. 23D, the gate insulating film 40
6 is a second shape conductive layer 41 formed by the etching.
The region not covered by 9 to 422 was further etched by about 20 to 50 nm and became thinner.

An etching reaction of a W film or a Ta film by a mixed gas of CF ₄ and Cl ₂ can be estimated from generated radicals or ionic species and a vapor pressure of a reaction product.
Comparing the vapor pressures of fluorides and chlorides of W and Ta, W
WF ₆ is extremely high and other WC
l ₅ , TaF ₅ and TaCl ₅ are comparable. Therefore, C
With the mixed gas of F ₄ and Cl ₂ , both the W film and the Ta film are etched. However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂ react to form CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure increases. On the other hand, in Ta, the increase in the etching rate is relatively small even if F increases. Further, since Ta is more easily oxidized than W, the surface of Ta is oxidized by adding O ₂ .
Since the oxide of Ta does not react with fluorine or chlorine,
The etching rate of the a film decreases. Therefore, the W film and Ta
It is possible to make a difference in the etching rate with the film, and it is possible to make the etching rate of the W film larger than that of the Ta film.

Then, the masks 409a to 412a
Is removed, a first doping process is performed as shown in FIG. 24A, and an n-type impurity element is added. For example, the acceleration voltage is set to 70 to 120 keV, and 1 × 10 ¹³
/ cm ² dose. The doping is performed using the second shape conductive layers 419 to 422 as a mask for the impurity element, so that the impurity element is added to the region below the second conductive layers 419a to 422a. Thus, first impurity regions 425 to 428 overlapping with second conductive layers 419 a to 422 a and second impurity regions 429 to 432 having a higher impurity concentration than the first impurity region are formed. In this embodiment, the masks 409a to 409
Although the impurity element imparting n-type is added after removing 2a, the present invention is not limited to this. The masks 409a to 412a may be removed after the impurity element imparting n-type is added in the step of FIG.

Next, a mask 4 made of resist is formed on the semiconductor layer 404 so as to cover the second conductive layers 421a and 421b.
33 are formed. The mask 433 partially overlaps with the second impurity region 431 with the gate insulating film 406 interposed therebetween. Then, a second doping process is performed to add an impurity element imparting n-type. In this case, the dose is set higher than that of the first doping process, and n
Doping with an impurity element for giving a mold. (FIG. 24
(B) The doping method may be an ion doping method or an ion implantation method. The ion doping method is performed under the conditions of a dose of 1 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² and an acceleration voltage of 60 to 100 keV. An element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is used as the n-type impurity element. Here, phosphorus (P) is used. In this case, the second shape conductive layer 419
422 serve as a mask for the impurity element imparting n-type, and source regions 434 to 437, drain regions 438 to 441, and Lov regions 442 to 445 are formed in a self-aligned manner. Further, the Loff region 44 is formed by the mask 433.
6 are formed. The source regions 434 to 437 and the drain regions 438 to 441 have 1 × 10 ²⁰ to 1 × 10 ²¹ atomic.
An impurity element imparting n-type is added in a concentration range of / cm ³ .

In this embodiment, the length of the Loff area 446 can be freely set by controlling the size of the mask 433.

In this specification, an LDD region overlapping with a gate electrode via a gate insulating film is called a Lov region. An LDD region that does not overlap with the gate electrode via the gate insulating film is called a Loff region.

The impurity element imparting n-type is a Loff region.
1 × 10 in area¹⁷~ 1 × 10¹⁹atoms / cm ^ThreeIt will be the concentration of
1 × 10 in Lov area¹⁶~ 1 × 10¹⁸atoms / cm
^ThreeConcentration.

In FIG. 24B, before or after doping with the impurity element imparting n-type under the conditions described above, the acceleration voltage is set to 70 to 120 keV with the mask 433 formed on the semiconductor layer 404. An impurity element imparting n-type may be doped. Through the above steps, the concentration of the impurity element imparting n-type in the portion 446 serving as the Loff region of the switching TFT can be suppressed.
Part 4 to be Lov region of TFT used for drive circuit
It is possible to increase the concentration of the impurity element imparting the n-type of 42 or 443. The off-state current of the switching TFT can be suggested by suppressing the concentration of the impurity element imparting n-type in the portion 446 to be the Loff region of the switching TFT. In addition, by increasing the concentration of an impurity element imparting n-type in a portion 443 to be an Lov region of an n-channel TFT used in a driving circuit, hot carriers generated by a high electric field near a drain due to a hot carrier effect are deteriorated. Can be prevented.

Then, after removing the mask 453, FIG.
As shown in FIG. 4C, the semiconductor layers 402 and 405 forming the p-channel type TFT have source regions 447 and 448 having conductivity types opposite to one conductivity type and drain regions 449 and 45.
0 and Lov regions 451 and 452 are formed. Using the conductive layers 419 and 422 having the second shape as masks for impurity elements, impurity regions are formed in a self-aligned manner. At this time, the semiconductor layers 402 and 403 forming the n-channel TFT are entirely covered with a resist mask 453. Source regions 447 and 448 and drain region 4
Phosphorus is added at different concentrations to the 49 and 450 and the Lov regions 451 and 452, respectively, but they are formed by ion doping using diborane (B ₂ H ₆ ). From 2 × 10 ^{20 to} 2 × 10
It should be ²¹ atoms / cm ³ .

By the above steps, each semiconductor layer 40
The impurity regions (source region, drain region,
Lov area and Loff area) are formed. The second conductive layers 419 to 422 overlapping with the semiconductor layer function as gate electrodes.

For the purpose of controlling the conductivity type, a step of activating the impurity element added to each semiconductor layer is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. Oxygen concentration is 1ppm by thermal annealing
Or less, preferably in a nitrogen atmosphere of 0.1 ppm or less.
The heat treatment is performed at 00 to 700 ° C., typically 500 to 600 ° C. In this embodiment, the heat treatment is performed at 500 ° C. for 4 hours. However, when the wiring material used in 419 to 422 is weak to heat, it is preferable to activate after forming an interlayer insulating film (mainly composed of silicon) in order to protect the wiring and the like.

Further, a heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the semiconductor layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. Plasma hydrogenation (using hydrogen excited by plasma) as another means of hydrogenation
May be performed.

Next, the first interlayer insulating film 455 is formed from a silicon oxynitride film to a thickness of 100 to 200 nm. (FIG. 25A) A second interlayer insulating film 458 made of an organic insulating material is formed thereon.

Then, contact holes are formed in the gate insulating film 406, the first interlayer insulating film 455, and the second interlayer insulating film 458, and are in contact with the source regions 447, 435, 436, and 448 through the contact holes. Source wirings 459 to 462 were formed as described above. Similarly, drain wirings 463 to 465 in contact with the drain regions 449, 439, 440, and 450 are formed (FIG. 25B).

If the gate insulating film 406, the first interlayer insulating film 455, and the second interlayer insulating film 458 are SiO ₂ films or SiON films, contact holes are formed by dry etching using CF ₄ and O _2. Preferably, it is formed. Further, the gate insulating film 406, the first interlayer insulating film 455, the second
When the interlayer insulating film 458 is an organic resin film, dry etching using CHF ₃ or BHF (buffered hydrofluoric acid: H
It is preferable to form a contact hole with F + NH ₄ F). The gate insulating film 406 and the first interlayer insulating film 45
5. When the second interlayer insulating film 458 is formed of a different material, it is preferable to change an etching method and a type of an etchant or an etching gas to be used for each film. The contact holes may be formed in the same manner.

Next, a third interlayer insulating film 4 made of an organic resin
67 is formed. As the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used. In particular, since the third interlayer insulating film 467 has a strong meaning of flattening, acrylic having excellent flatness is preferable. In this embodiment, an acrylic film is formed with a thickness that can sufficiently flatten a step formed by a TFT. The thickness is preferably 1 to 5 μm (more preferably 2 to 4 μm).

Next, a contact hole reaching the drain wiring 465 is formed in the third interlayer insulating film 467, and a pixel electrode 468 is formed. In this embodiment, a pixel electrode 468 is formed by forming an indium tin oxide (ITO) film to a thickness of 110 nm and performing patterning. Alternatively, a transparent conductive film in which 2 to 20% of zinc oxide (ZnO) is mixed with indium oxide may be used. This pixel electrode 468 becomes the anode of the light emitting element. (FIG. 25 (C))

Next, a first bank 469 and a second bank 470 made of a resin material are formed. The first bank 469 and the second bank 470 are provided for separating an organic compound layer and a cathode to be formed later between adjacent pixels. Therefore, it is preferable that the second bank 470 be configured to protrude laterally more than the first bank 469. The total thickness of the first bank 469 and the second bank 470 is 1 to
The thickness is preferably about 2 μm, but is not limited to this thickness as long as the organic compound layer and the cathode formed later can be separated between adjacent pixels. The first bank 469
The second bank 470 needs to be formed of an insulating film, and can be formed of, for example, an oxide, a resin, or the like. The first bank 469 and the second bank 470 may be formed of the same material or may be formed of different materials. First bank 469 and second bank
The banks 470 are formed in stripes between pixels. The first bank 469 and the second bank 470 may be formed along a source wiring (source signal line),
It may be formed along the gate wiring (gate signal line). Note that the first bank 469 and the second bank 470 may be formed by mixing a resin or the like with a resin. (FIG. 26
(A))

Next, the organic compound layer 471 and the cathode (Mg
An Ag electrode 472 is continuously formed using a vacuum deposition method without opening to the atmosphere. Note that the thickness of the organic compound layer 471 is 800 to 200 nm (typically 100 to 120 nm).
m), the thickness of the cathode 472 may be 180 to 300 nm (typically 200 to 250 nm). Although only one pixel is shown in this embodiment, an organic compound layer that emits red light, an organic compound layer that emits green light, and an organic compound layer that emits blue light are formed at the same time. Note that a material for forming the organic compound layer and the cathode is partially stacked over the bank 470, but these are not included in the organic compound layer 471 and the cathode 472 in this specification.

In this step, an organic compound layer 471 and a cathode 472 are sequentially formed for a pixel corresponding to red, a pixel corresponding to green, and a pixel corresponding to blue. However, since the organic compound layer 471 has poor resistance to a solution, it must be formed individually for each color without using a photolithography technique. Therefore, it is preferable that a portion other than the desired pixel is hidden using a metal mask, and the organic compound layer 471 and the cathode 472 are selectively formed only at necessary portions.

That is, first, a mask for hiding all pixels other than the pixels corresponding to red is set, and an organic compound layer for emitting red light is selectively formed using the mask. Next, a mask for hiding all pixels other than pixels corresponding to green is set, and an organic compound layer emitting green light is selectively formed using the mask.
Next, a mask for covering all pixels other than the pixels corresponding to blue is set, and an organic compound layer for emitting blue light is selectively formed using the mask. Note that all the masks are described herein as being different, but the same mask may be used again. In addition, it is preferable to perform processing without breaking vacuum until an organic compound layer and a cathode are formed in all pixels.

In this embodiment, the organic compound layer 471 has a single-layer structure composed only of the light emitting layer. However, the organic compound layer is formed of a hole transport layer, a hole injection layer, an electron transport layer, an electron It may have an injection layer or the like. Various examples of such combinations have already been reported, and any of these configurations may be used. As the organic compound layer 471, a known material can be used. Known materials include:
It is preferable to use an organic material in consideration of the driving voltage of the light emitting element.

Next, a cathode 472 is formed. In this embodiment, an example in which an MgAg electrode is used as a cathode of a light emitting element is described, but other known materials can be used.

Thus, an active matrix substrate having a structure as shown in FIG. 26B is completed. After forming the first bank 469 and the second bank 470, the cathode 472 is formed.
It is effective to continuously process the process up to the formation of the film using a multi-chamber type (or in-line type) thin film forming apparatus without opening to the atmosphere.

In this embodiment, the switching TFT
The semiconductor layer 501 includes a source region 504, a drain region 505, a Loff region 506, a Lov region 507, and a channel formation region 508. Loff area 506
Are provided so as not to overlap with the gate electrode 421 via the gate insulating film 406. The Lov region 507 is provided so as to overlap with the gate electrode 421 via the gate insulating film 406. Such a structure is very effective in reducing off-state current.

In this embodiment, the switching TFT
Although 501 has a single gate structure, in the present invention, the switching TFT may have a double gate structure or another multi-gate structure. The double gate structure has a structure in which substantially two TFTs are connected in series, and has an advantage that the off-state current can be further reduced.

In this embodiment, the switching TFT 5
01 is an n-channel TFT, but a p-channel TF
It can be T.

The semiconductor layer of the current controlling TFT 502 includes a source region 510, a drain region 511, and a Lov region 51.
2. It includes a channel forming region 513. The Lov region 512 has a gate electrode 422 through the gate insulating film 406.
And are provided so as to overlap. In this embodiment, the current control TFT 502 does not have the Loff region, but may have a configuration having the Loff region.

In this embodiment, the current control TFT 502
Is a p-channel TFT, but may be an n-channel TFT.

Note that the active matrix substrate of this embodiment has a T structure having an optimum structure not only for the pixel portion but also for the drive circuit portion.
By placing the FT, it shows very high reliability,
Operating characteristics can also be improved.

First, a TFT having a structure in which hot carrier injection is reduced so as not to reduce the operation speed as much as possible,
N-channel type TF of CMOS circuit forming drive circuit section
Used as T503. Note that the drive circuit here includes a shift register, a buffer, a level shifter, a sampling circuit (a sample and hold circuit), and the like. When digital driving is performed, a signal conversion circuit such as a D / A converter may be included.

In this embodiment, the semiconductor layer of the n-channel TFT 503 of the CMOS circuit includes a source region 521, a drain region 522, a Lov region 523, and a channel forming region 524.

In the case of this embodiment, the semiconductor layer of the p-channel type TFT 504 of the CMOS circuit is the source region 53.
1, a drain region 532, a Lov region 533, and a channel forming region 534.

Actually, when completed up to FIG. 26B, a protective film (laminate film, ultraviolet curable resin film, etc.) with high airtightness and low degassing so as not to be exposed to the outside air, It is preferable to package (enclose) with a sealing material. At this time, the reliability of the light emitting element is improved by setting the inside of the sealing material to an inert atmosphere or disposing a hygroscopic material (for example, barium oxide) inside.

When the airtightness is enhanced by processing such as packaging, a connector (flexible printed circuit: FPC) for connecting terminals routed from elements or circuits formed on the substrate to external signal terminals. To complete the product. Such a state up to shipment can be referred to as a light emitting device in this specification.

As described above, in the manufacturing process of this embodiment,
Since the length of the gate electrode in the channel length direction (hereinafter simply referred to as the width of the gate electrode) is different, ion implantation is performed using the gate electrode as a mask, so that the penetration depth of ions due to the difference in the thickness of the gate electrode. By utilizing the difference, the ion concentration in the semiconductor layer located under the first gate electrode can be made lower than the ion concentration in the semiconductor layer not located under the first gate electrode. .

In order to form a Loff region using a mask, it is necessary to control the etching by etching.
It is only the width of the ov area, and it is easy to control the positions of the Loff area and the Lov area.

In this embodiment, an example in which light emitted from the organic compound layer is directed to the substrate is described. However, the present invention is not limited to this, and light emitted from the organic compound layer is directed to the substrate. The configuration may be as follows.
In this case, it is desirable that the cathode of the light emitting element be a pixel electrode and the current control TFT be an n-channel TFT.

In this embodiment, the pixel is a switching T
The case where two TFTs of the FT and the current control TFT are provided has been described. However, this embodiment is not limited to this. This embodiment can be applied to a case where a pixel has three or more TFTs.

[0295] The method for manufacturing the light-emitting device of the present invention is not limited to the manufacturing method described in this embodiment, and any other manufacturing method can be used.

This embodiment can be implemented by freely combining with Embodiments 1 to 7.

(Embodiment 9) A light emitting device formed by carrying out the present invention is of a self-luminous type, so that it has better visibility in a bright place and a wider viewing angle than a liquid crystal display device. Therefore, it can be used for display portions of various electronic devices.
For example, to view a TV broadcast or the like on a large screen, the light emitting device of the present invention is used as a display unit of a display device in which a light emitting device having a diagonal size of 30 inches or more (typically 40 inches or more) is incorporated in a housing. Good. The light emitting device of the present invention can be used as a display portion of various electronic devices.

Examples of such electronic equipment of the present invention include a video camera, a digital camera, a goggle-type display (head-mounted display), a navigation system, a sound reproducing device (car audio, audio component, etc.), a notebook personal computer, a game Devices, personal digital assistants (mobile computers, mobile phones,
An image reproducing apparatus provided with a recording medium (specifically, a digital video disc (D
VD) and the like, which reproduces a recording medium and has a display capable of displaying the image. In particular, it is desirable to use a light-emitting device for a portable information terminal that is often viewed from an oblique direction, since a wide viewing angle is regarded as important. Specific examples of these electronic devices are shown in FIGS.

FIG. 27A shows a portable information terminal.
01 is a display panel, and 2702 is an operation panel.
The display panel 2701 and the operation panel 2702 are connected at a connection portion 2703. And the connection part 27
03, the display unit 2704 of the display panel 2701
Can be arbitrarily changed between the surface on which is provided and the surface of the operation panel 2702 on which the operation keys 2706 are provided.

[0300] The display panel 2701 has a display portion 2704. The portable information terminal illustrated in FIG. 27A has a function of a telephone, and has a display panel 2701.
Has an audio output unit 2705, and audio is output from the audio output unit 2705. The light emitting device of the present invention is used for the display portion 2704.

The operation panel 2702 has an operation key 270
6, power switch 2707, voice input unit 2708, CC
D light receiving section 2709 is provided. Although the operation key 2706 and the power switch 2707 are provided separately in FIG. 27A, the power switch 2707 is included in the operation key 2706.
May be included.

[0302] In the voice input unit 2707, voice is input. The image input at the CCD light receiving section 2709 is taken into the portable information terminal as electronic data.

In FIG. 27A, the display panel 270 is shown.
1 has an audio output unit 2705 and the operation panel has an audio input unit 2708, but the present embodiment is not limited to this configuration. The display panel 2701 is a voice input unit 270
8 and the operation panel may have a sound output unit 2705. The audio output unit 2705 and the audio input unit 27
08 may be provided on the display panel 2701, or the audio output unit 2705 and the audio input unit 2708 may be both provided on the operation panel 2702.

[0304] Although the portable information terminal does not have an antenna in FIG. 27A, an antenna may be provided as necessary.

FIG. 27B shows a mobile phone,
01, audio output unit 2602, audio input unit 2603, display unit 2604, operation switch 2605, antenna 2606
including. The light emitting device of the present invention can be used for the display portion 2604. Note that the display portion 2604 can display power of the mobile phone by displaying white characters on a black background.

[0306] The light emitting device of the present invention can reduce power consumption, and is particularly effective in portable electronic equipment.

[0307] FIG. 28A illustrates a display device including a light-emitting device, which includes a housing 2001, a support base 2002, and a display portion 200.
3 and so on. The light emitting device of the present invention can be used for the display portion 2003. Since the light-emitting device is a self-luminous type, it does not require a backlight and can have a thinner display portion than a liquid crystal display device.

FIG. 28B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6 and so on. The light emitting device of the present invention can be used for the display portion 2102.

FIG. 28C shows a part (right side) of a head-mounted electronic device, which includes a main body 2201, a signal cable 2202, a head fixing band 2203, and a screen section 22.
04, an optical system 2205, a display unit 2206, and the like. The light emitting device of the present invention can be used for the display portion 2206.

FIG. 28D shows an image reproducing apparatus (specifically, a DVD reproducing apparatus) provided with a recording medium.
1, recording medium (DVD or the like) 2302, operation switch 23
03, a display unit (a) 2304, a display unit (b) 2305, and the like. The display portion (a) 2304 mainly displays image information, and the display portion (b) 2305 mainly displays character information. The light emitting device of the present invention employs these display portions (a),
(B) It can be used for 2304 and 2305. Note that the image reproducing device provided with the recording medium includes a home game machine and the like.

FIG. 28E shows a goggle type display (head-mounted display).
1, a display unit 2402, and an arm unit 2403. The light emitting device of the present invention can be used for the display portion 2402.

FIG. 28F shows a personal computer, which includes a main body 2501, a housing 2502, a display portion 2503,
A keyboard 2504 and the like are included. The light-emitting device of the present invention can be used for the display portion 2503.

If the light emission luminance of the organic material becomes high in the future, it becomes possible to enlarge and project the light including the output image information with a lens or the like and use it for a front or rear projector.

[0314] Further, the electronic device is the Internet or C.
Information distributed through an electronic communication line such as an ATV (cable television) is frequently displayed, and in particular, opportunities to display moving image information are increasing. Since the response speed of the organic material is extremely high, the light-emitting device is preferable for displaying moving images.

[0315] Since the light emitting device consumes power in the light emitting portion, it is desirable to display information so that the light emitting portion is reduced as much as possible. Therefore, when a light emitting device is used for a portable information terminal, particularly a display portion mainly for character information such as a mobile phone or a sound reproducing device, the light emitting portion is driven to form character information with a non-light emitting portion as a background. It is desirable to do.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be used for electronic devices in various fields. This embodiment can be implemented in any combination with Embodiments 1 to 8.

(Embodiment 10) In this embodiment, a more specific configuration of the third configuration of the present invention and a change in luminance due to temperature will be described based on actually measured values.

FIG. 29A shows the connection of the monitor light emitting element included in the light emitting device of this embodiment. 701
Denotes a power supply line, 702 denotes a buffer amplifier, 703 denotes a monitor light emitting element, 704 denotes a constant current source, and 705 denotes one of light emitting elements in a pixel portion.

In FIG. 29, the driving TFT of the pixel portion is shown.
Is in an ON state, the driving TFT is not shown, and the pixel electrode of the light emitting element 705 in the pixel portion is directly connected to the power supply line 701.

[0320] In FIG. 29A, the anode of the light emitting element 705 in the pixel portion is used as a pixel electrode; however, this embodiment is not limited to this structure. A cathode may be used as a pixel electrode.

[0321] The constant current source 704 of this embodiment includes an amplifier,
It has a variable resistor and a bipolar transistor. V
1 and V2 mean application of a predetermined voltage, and satisfy the relationship of voltage applied to the anode <V2 <V1.
Note that the relationship between the voltage applied to the anode, V2, and V1 changes depending on whether an anode or a cathode is used for the pixel electrode. The relationship between the voltage applied to the anode, V2, and V1 is appropriately set so that a forward bias current flows through the light-emitting element. Further, the constant current source 704 is provided as shown in FIG.
The configuration is not limited to the configuration illustrated in FIG. 1A, and a known constant current source can be used.

The output terminal of the constant current source 704 is connected to the pixel electrode of the monitor light emitting element 703. Note that in the case where an anode is used as a pixel electrode in the light-emitting element 705 in the pixel portion, the anode is also used as a pixel electrode in the light-emitting element 703 for monitoring. Conversely, the light emitting element 70 of the pixel portion
When the cathode is used as a pixel electrode in 5, the cathode is also used as a pixel electrode in the monitor light emitting element 703. In FIG. 29A, the monitor light emitting element 703 is used.
, An anode is used as a pixel electrode.

When the output terminal of the constant current source 704 is connected to the pixel electrode of the monitor light emitting element 703, when a current flows through the monitor light emitting element 703, the value is always kept constant. . When the temperature of the organic compound layer included in the light-emitting element changes, the magnitude of the current flowing through the monitor light-emitting element 703 does not change, but the pixel electrode of the monitor light-emitting element 703 connected to the constant current source 704. Changes.

The buffer amplifier 702 has two input terminals and one output terminal. One of the two input terminals is a non-inverting input terminal (+), and the other is an inverting input terminal (-). is there. The potential of the pixel electrode of the monitor light emitting element 703 is supplied to a non-inverting input terminal of the buffer amplifier 702.

The buffer amplifier 702 includes a constant current source 704
Is a circuit for preventing the potential of the pixel electrode of the monitor light emitting element 703 connected to the power supply line 701 from being changed by the load such as the wiring capacitance of the power supply line 701. Therefore, the buffer amplifier 70
2 is supplied to the power supply line 7
The light is output from the output terminal without being changed by the load such as the wiring capacitance of No. 01 and is supplied to the pixel electrode of the light emitting element 705 in the pixel portion. Therefore, the current flowing through the monitor light emitting element 703 is equal to the current flowing through the light emitting element 705 in the pixel portion.

Even if the temperature of the organic compound layer of the light emitting element for monitoring 703 or the light emitting element 705 in the pixel portion changes due to a change in environmental temperature, a constant current flows through each light emitting element. Therefore, even if the environmental temperature of the light emitting device increases, it is possible to suppress an increase in power consumption of the light emitting device.

[0327] FIG. 29B shows measured values of a change in luminance of the light-emitting element 705 in the pixel portion with temperature which is included in the light-emitting device having the structure shown in FIG. The graph with correction is the measured value of the light emitting device of the present invention, and the graph without correction is the measured value of the light emitting device without the third configuration of the present invention.

As is clear from FIG. 29A, in the graph without correction, the luminance increases as the temperature increases. However, in the graph with correction, the luminance is kept almost constant even when the temperature rises. Since the current and the luminance are in a proportional relationship, it can be seen that in the light emitting device of the present invention, the current can be kept constant even when the temperature rises, and the power consumption can be suppressed.

In the light-emitting element, the luminance is lowered due to the deterioration of the organic light-emitting layer. Even if the light-emitting element is deteriorated to the same extent, it is better to maintain a constant current flowing between the cathode and the anode. The decrease in luminance is smaller than when the voltage applied during the period is kept constant. Therefore, the light-emitting device of the present invention can maintain a constant current flowing through the light-emitting element, and thus can suppress a decrease in luminance due to deterioration.

This embodiment can be implemented by freely combining with the structures of Embodiments 1 to 9.

[0331]

According to the first structure of the present invention, the magnitude of the current flowing through the light emitting element can be suppressed to some extent, and the power consumption of the light emitting device can be suppressed. Further, according to the second configuration of the present invention, the number of bits of a digital video signal input to a pixel is reduced, so that the number of times a digital video signal is written to a pixel by a source signal line driver circuit and a gate signal line driver circuit is reduced. . Therefore, power consumption of the source signal line driver circuit and the gate signal line driver circuit can be reduced, and power consumption of the light-emitting device can also be reduced. Further, according to the third structure of the present invention, the magnitude of current flowing through the light emitting element can be kept constant even when the temperature of the organic compound layer changes. Therefore, it is possible to suppress an increase in environmental temperature of the light emitting device and an increase in power consumption of the light emitting device.

According to the present invention, with the first to third configurations, it is possible to suppress the power consumption of the light emitting device and the electronic equipment using the light emitting device. The present invention only needs to have any one of the first to third configurations. Further, a plurality of the first to third configurations may be provided, or all of the first to third configurations may be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of a light emitting device of the present invention.

FIG. 2 is a block diagram of a light emitting device of the present invention.

FIG. 3 is a block diagram of a light emitting device of the present invention.

FIG. 4 is a block diagram of a light emitting device of the present invention.

FIG. 5 is a diagram showing a state of connection between a power supply line of a light emitting device of the present invention and a light emitting element for monitoring.

FIG. 6 illustrates a pixel portion of a light emitting device of the present invention.

FIG. 7 is an enlarged view of a pixel of the light emitting device of the present invention.

FIG. 8 illustrates a method for driving a light emitting device of the present invention.

FIG. 9 is a block diagram of a light emitting device of the present invention.

FIG. 10 illustrates a pixel portion of a light-emitting device of the present invention.

FIG. 11 is an enlarged view of a pixel of the light emitting device of the present invention.

FIG. 12 illustrates a method for driving a light emitting device of the present invention.

FIG. 13 is a circuit diagram of a source signal line driver circuit of the light emitting device of the present invention.

FIG. 14 is a top view of a part of the latch (A).

FIG. 15 is a circuit diagram of a switching circuit.

FIG. 16 is an equivalent circuit diagram of an analog switch.

FIG. 17 is a circuit diagram of a source signal line driver circuit of a light emitting device of the present invention.

FIG. 18 is a circuit diagram of a clock signal control circuit, a timing signal control circuit, and a start pulse signal control circuit.

FIG. 19 is a circuit diagram of a source signal line driver circuit of a light emitting device of the present invention.

FIG. 20 is a circuit diagram of a source signal line driver circuit of the light emitting device of the present invention.

FIG. 21 is a diagram showing a state of connection between a power supply line of a light emitting device of the present invention and a light emitting element for monitoring.

FIG. 22 is a circuit diagram of an addition circuit.

FIG 23 illustrates a method for manufacturing a light-emitting device.

FIG 24 illustrates a method for manufacturing a light-emitting device.

FIG 25 illustrates a method for manufacturing a light-emitting device.

FIG 26 illustrates a method for manufacturing a light-emitting device.

FIG. 27 is a diagram of an electronic device using the light-emitting device of the present invention.

FIG. 28 is a diagram of an electronic device using the light-emitting device of the present invention.

29A and 29B are diagrams illustrating a state of connection between a power supply line of a light-emitting device of the present invention and a light-emitting element for monitoring, and a graph illustrating luminance characteristics with respect to temperature of the light-emitting element.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 623 G09G 3/20 623G 623H 624 624B 641 641P 670 670L 680 680A 680S 680T 680V H05B 33/12 33/12 B 33/14 33/14 A (72) Inventor Mai Mai Nagata 398 Hase, Atsugi-shi, Kanagawa F-term in the Semiconductor Energy Research Institute, Inc. (reference) 3K007 AB02 AB04 AB05 AB14 AB17 BA06 CA01 CB01 DA01 DB03 EB00 GA04 5C080 AA06 BB05 DD03 DD26 EE29 FF11 GG01 JJ02 JJ03 JJ06 KK07 5C094 AA07 AA08 AA22 AA31 AA53 AA54 AA56 BA03 BA12 BA27 CA19 CA24 CA25 DA09 DA13 DB01 DB04 DB10 EA04 EA05 EB02 FA01 FA02 FB01 FB01

Claims (24)

[Claims] 1. A display device having a plurality of pixels, wherein the brightness of the plurality of pixels is changed by inverting the polarity of a video signal input to the plurality of pixels. 2. A display device including a pixel portion having a plurality of pixels and a source signal line driving circuit, wherein the source signal line driving circuit has a switching circuit for switching output polarity, A display device, wherein a video signal input to a circuit is inverted in polarity by a switching signal input to the switching circuit, and is input to the plurality of pixels. 3. A display device including a pixel portion having a plurality of pixels and a source signal line driving circuit, wherein each of the plurality of pixels has a light-emitting element, and the source signal line driving circuit has a shift function. A register, one or more latches, and a switching circuit, wherein the digital video signal input to the switching circuit from the one or more latches is changed by a switching signal input to the switching circuit. A display device in which the polarity is inverted and input to the plurality of pixels. 4. A display device including a pixel portion having a plurality of pixels and a source signal line driving circuit, wherein each of the plurality of pixels has a light emitting element, and wherein the source signal line driving circuit has a shift function. A register, one or more latches, and a switching circuit, wherein the digital video signal input to the switching circuit from the one or more latches is changed by a switching signal input to the switching circuit. The polarity is inverted and input to the plurality of pixels, and the average of the length of the light emitting period of all the light emitting elements during one frame period is the period during which all the light emitting elements emit light during the one frame period A display device, wherein the length is not more than half of the maximum value of the length. 5. The switching circuit according to claim 2, wherein the switching circuit has an inverter, a first analog switch, and a second analog switch. The input video signal is input to the input terminal of the first analog switch via the inverter, and the video signal input to the switching circuit is input to the second analog switch.
And a switching signal is input from a first control input terminal of the first analog switch and a second control input terminal of the second analog switch, and the polarity of the switching signal is An inverted signal is input from a second control input terminal of the first analog switch and a second control input terminal of the first analog switch, and an output of the first analog switch and an output of the second analog switch A display device, wherein a signal output from a terminal is output from the switching circuit. 6. The switching circuit according to claim 2, wherein the switching circuit includes an inverter and a first NAND.
, A second NAND, and a NOR, a switching signal and a video signal are input to the first NAND through the inverter, and the switching signal of the switching signal is input to the second NAND. A signal with inverted polarity and the video signal are input, a signal output from the first NAND, and a signal output from the second NAND are input to the NOR, and an output from the NOR A display device, wherein the output signal is output from the switching circuit. 7. A display device having a plurality of pixels and a source signal line driving circuit, wherein, among video signals input to the source signal line driving circuit, only higher order video signals are transmitted to the plurality of pixels. A display device characterized by being input. 8. A display device including a pixel portion having a plurality of pixels and a source signal line driving circuit, wherein the source signal line driving circuit includes a shift register,
, A second latch, and a clock signal control circuit. When a clock signal is input to the shift register via the clock signal control circuit, a timing signal is output from the shift register. A video signal is input to and held in the first latch by the timing signal, and a video signal held in the first latch is input to and held by the second latch by the latch signal. The video signal input to and held by the second latch is input to the plurality of pixels, and the clock signal control circuit applies a fixed fixed potential to the shift register instead of the clock signal for a fixed period. Wherein the number of bits of the video signal input to and held by the first latch is reduced. . 9. The clock signal control circuit according to claim 8, wherein the clock signal control circuit includes a NAND and an inverter, wherein a clock signal and a selection signal are input to the NAND, and a signal output from the NAND controls the inverter. A display device, which is output from the clock signal control circuit through the display device. 10. The clock signal control circuit according to claim 8, wherein the clock signal control circuit has a first analog switch, a second analog switch, and an inverter, and the first analog switch is connected via the inverter. A selection signal is input to a second control input terminal of the first analog switch and a first control input terminal of the second analog switch; a first control input terminal of the first analog switch and a second control input terminal of the second analog switch; 2, a selection signal is input to a control input terminal of the second analog switch; a clock signal is input to an input terminal of the first analog switch; a fixed potential is applied to an input terminal of the second analog switch; And a signal output from an output terminal of the second analog switch is output from the clock signal control circuit. Display devices. 11. A display device comprising: a pixel portion having a plurality of pixels; and a source signal line drive circuit, wherein the source signal line drive circuit includes a shift register,
, A second latch, and a timing signal control circuit, wherein a timing signal output from the shift register is input to the first latch via the timing signal control circuit, The video signal is input to the first latch and held by the timing signal input to the first latch, and the video signal held by the first latch is input to the second latch by the latch signal The video signal input to and held by the second latch is input to the plurality of pixels, and the timing signal control circuit outputs the timing signal output from the shift register for a certain period. Instead of applying a fixed potential to the first latch, the bit of the video signal that is input to and held in the first latch is Display device, characterized in that to reduce the. 12. The timing signal control circuit according to claim 11, wherein the timing signal control circuit includes a NAND and an inverter, wherein a timing signal and a selection signal are input to the NAND, and a signal output from the NAND controls the inverter. A display device which is output from the timing signal control circuit through the display device. 13. The first analog switch according to claim 11, wherein the timing signal control circuit has a first analog switch, a second analog switch, and an inverter. A selection signal is input to a second control input terminal of the first analog switch and a first control input terminal of the second analog switch, and a first control input terminal of the first analog switch and a second control input terminal of the second analog switch. 2, a selection signal is input to a control input terminal of the second analog switch; a timing signal is input to an input terminal of the first analog switch; a fixed potential is applied to an input terminal of the second analog switch; And the signal output from the output terminal of the second analog switch is output from the timing signal control circuit. To the display apparatus. 14. A display device comprising: a pixel portion having a plurality of pixels; and a source signal line driving circuit, wherein the source signal line driving circuit includes a shift register,
, A second latch, and a start pulse signal control circuit. When a start pulse signal is input to the shift register via the start pulse signal control circuit, a timing is output from the shift register. A video signal is input to and held in the first latch by the timing signal; and a video signal held in the first latch is input to and held by the second latch by the latch signal. The video signal input to and held by the second latch is input to the plurality of pixels, and the start pulse signal control circuit replaces the start pulse signal for a predetermined period with a fixed potential. To the shift register, thereby reducing the number of bits of the video signal input to and held in the first latch. Display device comprising has. 15. The start pulse signal control circuit according to claim 14, wherein the start pulse signal control circuit includes a NAND and an inverter, wherein the start pulse signal and the selection signal are input to the NAND, and the signal output from the NAND is A display device output from the start pulse signal control circuit via an inverter. 16. The first pulse signal control circuit according to claim 14, wherein said start pulse signal control circuit has a first analog switch, a second analog switch, and an inverter, and said first analog switch is connected to said first analog switch via said inverter. A selection signal is input to a second control input terminal of the switch and a first control input terminal of the second analog switch, and a first control input terminal of the first analog switch and a selection signal of the second analog switch. A selection signal is input to a second control input terminal; a start pulse signal is input to an input terminal of the first analog switch; a fixed potential is applied to an input terminal of the second analog switch; The signals output from the output terminals of the analog switch and the second analog switch are output from the start pulse signal control circuit. Display device according to claim Rukoto. 17. A plurality of pixels having a plurality of light emitting elements,
A display device comprising: a monitor light-emitting element; wherein a change in temperature of a current flowing through the plurality of light-emitting elements due to a temperature is reduced by using a temperature characteristic of the monitor light-emitting element. 18. A display device comprising a pixel portion having a plurality of pixels, a power supply line, a buffer amplifier, a light emitting element for monitoring, and a constant current source, wherein the plurality of pixels are a thin film transistor and a light emitting element. Wherein each of the monitor light-emitting element and the light-emitting element has a first electrode, a second electrode, and an organic compound layer provided between the first electrode and the second electrode. A first electrode of the light emitting element for monitoring and the constant current source are connected, and a first electrode of the light emitting element for monitoring and a non-inverting input terminal of the buffer amplifier are connected to each other. The output terminal of the buffer amplifier is connected to the power supply line, and the potential of the power supply line is given to the first electrode of the light emitting element via the thin film transistor. The display device according to symptoms. 19. A display device comprising a pixel portion having a plurality of pixels, a power supply line, a buffer amplifier, a monitor light emitting element, a constant current source, and an adder circuit, wherein the plurality of pixels are A thin film transistor and a light emitting element, wherein the monitoring light emitting element and the light emitting element are provided between a first electrode, a second electrode, and the first and second electrodes. A first electrode of the light emitting element for monitoring and the constant current source are connected to each other, and a first electrode of the light emitting element for monitoring and a non-connected electrode of the buffer amplifier are connected to each other. An inverting input terminal is connected, an output terminal of the buffer amplifier is connected to an input terminal of an addition circuit, an output terminal of the addition circuit is connected to the power supply line, and an input terminal of the addition circuit. When The display device, wherein the output terminal always has a constant potential difference, and the potential of the power supply line is supplied to a first electrode of the light emitting element through the thin film transistor. 20. A video camera using the display device according to claim 1. Description: 21. An image reproducing apparatus using the display device according to claim 1. Description: 22. A head-mounted display using the display device according to claim 1. Description: 23. A mobile phone using the display device according to any one of claims 1 to 19. 24. A portable information terminal using the display device according to any one of claims 1 to 19.