JP4731846B2 - Display device - Google Patents

Description

The present invention relates to a display panel in which a light emitting element formed on a substrate is enclosed between the substrate and a cover material. The present invention also relates to a display module in which an IC is mounted on the display panel. In this specification, the display panel and the display module are collectively referred to as a light emitting device. The present invention further relates to an electronic apparatus using the light emitting device.

In recent years, a technology for forming a TFT on a substrate has greatly advanced, and application development to an active matrix display device has been advanced. In particular, TF using polysilicon film
T has a higher field effect mobility (also referred to as mobility) than a TFT using a conventional amorphous silicon film, and thus can operate at high speed. For this reason, it is possible to control a pixel, which has been conventionally performed by a drive circuit outside the substrate, with a drive circuit formed on the same substrate as the pixel.

Such an active matrix display device has various advantages such as a reduction in manufacturing cost, a reduction in size of the display device, an increase in yield, and a reduction in throughput by forming various circuits and elements on the same substrate. .

In addition, active matrix light-emitting devices having light-emitting elements as self-light-emitting elements are being actively researched. The light emitting device is an organic EL display (OEL)
D: Organic EL Display) or organic light emitting diode (OLED)
: Organic Light Emitting Diode).

Unlike a liquid crystal display, the light emitting device is a self-luminous type. A light-emitting element has a structure in which a layer containing an organic compound that generates luminescence when an electric field is applied (hereinafter referred to as an organic compound layer) is sandwiched between a pair of electrodes (anode and cathode). The layer usually has a laminated structure. A typical example is a “hole transport layer / light emitting layer / electron transport layer” stacked structure proposed by Tang et al. Of Kodak Eastman Company. This structure has very high luminous efficiency, and most of the light emitting devices that are currently under research and development employ this structure.

Luminescence in organic compounds includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. Any one of the above-described light emission may be used, or both light emission may be used.

In addition, the hole injection layer / hole transport layer / light emitting layer / electron transport layer, or hole injection layer / hole transport layer / light emitting layer / electron transport layer / electron injection layer are laminated in this order on the anode. Structure may be sufficient. You may dope a fluorescent pigment | dye etc. with respect to a light emitting layer.

In this specification, all layers provided between the cathode and the anode are collectively referred to as an organic compound layer. Therefore, the above-described hole injection layer, hole transport layer, light emitting layer, electron transport layer, electron injection layer, and the like are all included in the organic compound layer.

A predetermined voltage is applied to the organic compound layer having the above structure from the pair of electrodes, whereby recombination of carriers occurs in the light emitting layer to emit light. Note that in this specification, light emission of a light-emitting element is referred to as driving of the light-emitting element. In this specification, a light-emitting element formed using an anode, an organic compound layer, and a cathode is referred to as a light-emitting element.

Since the light emitting device does not need to use a backlight, the thickness and weight of the display itself can be suppressed as compared with a liquid crystal display. Therefore, in recent years, a light emitting device has been used for a display unit of a portable information terminal (such as a mobile computer, a mobile phone, a portable game machine, or an electronic book) instead of a liquid crystal display.

In order to reduce the power consumption of the portable information terminal, it has been desired to reduce the power consumption of the light emitting device used for the display unit.

In recent years, in addition to the digitization of broadcasting stations such as televisions and radios, home receivers and VTRs are also being digitized. The next stage of digitalization of the broadcasting system is the digitization of broadcast radio waves, that is, the realization of digital broadcasting, and research and development are actively conducted for this purpose.

There is a time gradation display in digital driving of a light emitting device. Time gradation display is a driving method for performing gradation display by controlling the time during which a light emitting element emits light during one frame period.

When time gradation display is performed on a light emitting device by digital driving, if the number of gradations of an image to be displayed is increased, the number of times that a digital video signal (digital video signal) having image information input to a pixel is rewritten increases. . Therefore, the power consumption of the drive circuit group for inputting the digital video signal to the pixel is increased, and the power consumption of the light emitting device is increased.

Further, since the light-emitting element is a self-luminous type, a period during which the light-emitting element emits light during one frame period depends on an image to be displayed. Therefore, the power consumption of the light emitting device depends on the image to be displayed.

Further, the magnitude of the current flowing through the light emitting element also depends on the temperature. Even if the voltage applied between the electrodes of the light-emitting element is the same, the current flowing through the light-emitting element increases as the temperature of the organic compound layer increases due to the temperature characteristics of the light-emitting element. Therefore, the higher the environmental temperature at which the light emitting device is used, the greater the power consumption of the light emitting device and the higher the luminance of the light emitting element.

In view of the above, it is an object of the present invention to suppress power consumption of a light-emitting device and an electronic device using the light-emitting device for a display portion.

The first configuration of the present invention is characterized in that in the light emitting device, when performing monochrome display, the lightness and darkness of the image is inverted by the image displayed on the pixel portion.

With the above structure, the current flowing through the light-emitting element can be suppressed to some extent, and the power consumption of the light-emitting device can be suppressed.

According to a second configuration of the present invention, in a light-emitting device that performs time division gray scale display of digital driving, a digital video signal input to a source signal line driving circuit included in the light-emitting device is reduced in the number of bits before the pixel It is characterized by being input to the section. Specifically, the number of bits of the digital video signal input to the pixel portion is decreased by sequentially discarding the digital video signal of the least significant bit.

With the above structure, the number of bits of the digital video signal input to the pixel is reduced, so that the number of times the digital video signal is written to the pixel by the source signal line driver circuit and the gate signal line driver circuit is reduced. Therefore, power consumption of the source signal line driver circuit and the gate signal line driver circuit can be suppressed, and power consumption of the light-emitting device can also be suppressed.

In the third configuration of the present invention, the light emitting device is provided with a light emitting element for temperature monitoring. Then, one electrode of the temperature monitoring light emitting element is connected to a constant current source. Then, using the temperature characteristics of the light emitting element for monitoring, the magnitude of the current flowing through the light emitting element of the pixel is kept constant.

With the above structure, even when the temperature of the organic compound layer changes, the magnitude of the current flowing through the light emitting element of the pixel can be kept constant. Therefore, even when the environmental temperature of the light emitting device rises, the power consumption of the light emitting device can be prevented from increasing, and the luminance can be kept constant.

According to the first to third configurations of the present invention, the power consumption of the light emitting device and the electronic device using the light emitting device can be suppressed. Note that the present invention only needs to have one of the first to third configurations. Moreover, you may have a some structure of 1st to 3rd structures, and may have all.

  The configuration of the present invention is shown below.

According to the present invention,
A display device having a plurality of pixels,
There is provided a display device characterized in that the luminance of the plurality of pixels is changed by inverting the polarity of a digital video signal input to the plurality of pixels.

According to the present invention,
A display device having a pixel portion having a plurality of pixels and a source signal line driver circuit,
The source signal line driving circuit has a switching circuit for switching the polarity of the output,
A digital video signal input to the switching circuit is inverted in polarity by the switching signal input to the switching circuit and is input to the plurality of pixels.

According to the present invention,
A display device having a pixel portion having a plurality of pixels and a source signal line driver circuit,
Each of the plurality of pixels has a light emitting element,
The source signal line driver circuit includes a shift register, one or more latches,
And a switching circuit,
The digital video signal input from the one or more latches to the switching circuit is inverted in polarity by the switching signal input to the switching circuit,
A display device is provided that inputs to the plurality of pixels.

According to the present invention,
A display device having a pixel portion having a plurality of pixels and a source signal line driver circuit,
Each of the plurality of pixels has a light emitting element,
The source signal line driver circuit includes a shift register, one or more latches,
And a switching circuit,
The digital video signal input from the one or more latches to the switching circuit is inverted in polarity by the switching signal input to the switching circuit,
Input to the plurality of pixels,
The average length of the light emitting periods of all the light emitting elements in one frame period is less than or equal to half of the maximum value of the length of the light emitting period of all of the light emitting elements in one frame period. A display device is provided.

The switching circuit includes an inverter, a first analog switch, and a second analog switch,
The digital video signal input to the switching circuit is input to the input terminal of the first analog switch via the inverter,
The digital video signal output from the one or more latches is input to an input terminal of the second analog switch,
A switching signal is input from a first control input terminal of the first analog switch and a second control input terminal of the second analog switch;
A signal obtained by inverting the polarity of the switching signal is a second signal of the first analog switch.
Input from the control input terminal of the second analog switch and the first control input terminal of the second analog switch,
Signals output from output terminals of the first analog switch and the second analog switch may be output from the switching circuit.

The switching circuit includes an inverter, a first NAND, a second NAND,
NOR and
A switching signal and a digital video signal are input to the first NAND via the inverter,
A signal obtained by inverting the polarity of the switching signal and the digital video signal are input to the second NAND,
The signal output from the first NAND and the signal output from the second NAND are input to the NOR,
The signal output from the NOR may be output from the switching circuit.

According to the present invention,
A display device having a plurality of pixels and a source signal line driving circuit,
Of the digital video signals input to the source signal line driver circuit, only the upper bit digital video signal is input to the plurality of pixels.

According to the present invention,
A display device having a pixel portion having a plurality of pixels and a source signal line driver circuit,
The source signal line driver circuit includes a shift register, a first latch, a second latch, and a clock signal control circuit,
When a clock signal is input to the shift register via the clock signal control circuit, a timing signal is output from the shift register,
A digital video signal is input and held in the first latch by the timing signal,
The digital video signal held in the first latch is input and held in the second latch by the latch signal,
The digital video signal input and held in the second latch is input to the plurality of pixels,
The clock signal control circuit reduces the number of bits of the digital video signal that is input to and held in the first latch by applying a constant fixed potential to the shift register instead of the clock signal for a certain period. A display device is provided.

The clock signal control circuit has a NAND and an inverter,
A clock signal and a selection signal are input to the NAND,
The signal output from the NAND may be output from the clock signal control circuit via the inverter.

The clock signal control circuit includes a first analog switch, a second analog switch, and an inverter.
A selection signal is input to the second control input terminal of the first analog switch and the first control input terminal of the second analog switch via the inverter.
A selection signal is input to the first control input terminal of the first analog switch and the second control input terminal of the second analog switch,
A clock signal is input to an input terminal of the first analog switch;
A fixed potential is applied to an input terminal of the second analog switch;
The signals output from the output terminals of the first analog switch and the second analog switch may be output from the clock signal control circuit.

According to the present invention,
A display device having a pixel portion having a plurality of pixels and a source signal line driver circuit,
The source signal line driver circuit includes a shift register, a first latch, a second latch, and a timing signal control circuit.
The timing signal output from the shift register is input to the first latch via the timing signal control circuit,
According to the timing signal input to the first latch, a digital video signal is input and held in the first latch,
The digital video signal held in the first latch is input and held in the second latch by the latch signal,
The digital video signal input and held in the second latch is input to the plurality of pixels,
The timing signal control circuit inputs and holds the first latch by supplying a constant fixed potential to the first latch instead of the timing signal output from the shift register for a certain period. There is provided a display device characterized in that the number of bits of the digital video signal to be reduced is reduced.

The timing signal control circuit has a NAND and an inverter,
A timing signal and a selection signal are input to the NAND,
The signal output from the NAND may be output from the timing signal control circuit via the inverter.

The timing signal control circuit includes a first analog switch, a second analog switch, and an inverter.
A selection signal is input to the second control input terminal of the first analog switch and the first control input terminal of the second analog switch via the inverter.
A selection signal is input to the first control input terminal of the first analog switch and the second control input terminal of the second analog switch,
A timing signal is input to an input terminal of the first analog switch;
A fixed potential is applied to an input terminal of the second analog switch;
The signals output from the output terminals of the first analog switch and the second analog switch may be output from the timing signal control circuit.

According to the present invention,
A display device having a pixel portion having a plurality of pixels and a source signal line driver circuit,
The source signal line driver circuit includes a shift register, a first latch, a second latch, and a start pulse signal control circuit.
When a start pulse signal is input to the shift register via the start pulse signal control circuit, a timing signal is output from the shift register,
A digital video signal is input and held in the first latch by the timing signal,
The digital video signal held in the first latch is input and held in the second latch by the latch signal,
The digital video signal input and held in the second latch is input to the plurality of pixels,
The start pulse signal control circuit supplies a constant fixed potential to the shift register instead of the start pulse signal for a certain period, thereby inputting the number of bits of the digital video signal to be held in the first latch There is provided a display device that is characterized in that

The start pulse signal control circuit has a NAND and an inverter,
A start pulse signal and a selection signal are input to the NAND,
The signal output from the NAND may be output from the start pulse signal control circuit via the inverter.

The start pulse signal control circuit includes a first analog switch, a second analog switch, and an inverter.
A selection signal is input to the second control input terminal of the first analog switch and the first control input terminal of the second analog switch via the inverter.
A selection signal is input to the first control input terminal of the first analog switch and the second control input terminal of the second analog switch,
A start pulse signal is input to an input terminal of the first analog switch;
A fixed potential is applied to an input terminal of the second analog switch;
The signals output from the output terminals of the first analog switch and the second analog switch may be output from the start pulse signal control circuit.

According to the present invention,
A display device having a plurality of pixels each having a plurality of light-emitting elements and a monitor light-emitting element, and maintaining a constant magnitude of a current flowing through the plurality of light-emitting elements using temperature characteristics of the monitor light-emitting elements. A display device is provided.

According to the present invention,
A display device having a pixel portion having a plurality of pixels, a power supply line, a buffer amplifier, a monitor light emitting element, and a constant current source,
The plurality of pixels each have a thin film transistor and a light emitting element,
The monitor light-emitting element and the light-emitting element each have a first electrode, a second electrode, and an organic compound layer provided between the first electrode and the second electrode. ,
The first electrode of the monitor light emitting element and the constant current source are connected,
A first electrode of the monitor light emitting element and a non-inverting input terminal of the buffer amplifier are connected;
The output terminal of the buffer amplifier is connected to the power supply line,
A display device is provided in which the potential of the power supply line is supplied to the first electrode of the light-emitting element through the thin film transistor.

According to the present invention,
A display device having a pixel portion having a plurality of pixels, a power supply line, a buffer amplifier, a monitor light emitting element, a constant current source, and an adder circuit,
The plurality of pixels each have a thin film transistor and a light emitting element,
The monitor light-emitting element and the light-emitting element each have a first electrode, a second electrode, and an organic compound layer provided between the first electrode and the second electrode. ,
The first electrode of the monitor light emitting element and the constant current source are connected,
A first electrode of the monitor light emitting element and a non-inverting input terminal of the buffer amplifier are connected;
The output terminal of the buffer amplifier is connected to the input terminal of the adder circuit,
An output terminal of the adder circuit is connected to the power supply line;
The input terminal and output terminal of the adder circuit always have a constant potential difference,
A display device is provided in which the potential of the power supply line is supplied to the first electrode of the light-emitting element through the thin film transistor.

The present invention may be a video camera, an image reproducing device, a head mounted display, a mobile phone, or a portable information terminal using the display device.

According to the first configuration of the present invention, the magnitude of the current flowing through the light emitting element can be suppressed to some extent, and the power consumption of the light emitting device can be suppressed. In addition, since the number of bits of the digital video signal input to the pixel is reduced by the second configuration of the present invention, the number of times the digital video signal is written to the pixel by the source signal line driver circuit and the gate signal line driver circuit is reduced. . Therefore, power consumption of the source signal line driver circuit and the gate signal line driver circuit can be suppressed, and power consumption of the light-emitting device can also be suppressed. In addition, according to the third configuration of the present invention, the magnitude of the current flowing through the light emitting element can be kept constant even when the temperature of the organic compound layer changes. Therefore, it is possible to suppress an increase in the environmental temperature of the light emitting device and an increase in power consumption of the light emitting device.

According to the first to third configurations of the present invention, the power consumption of the light emitting device and the electronic device using the light emitting device can be suppressed. Note that the present invention only needs to have one of the first to third configurations. Moreover, you may have a some structure of 1st to 3rd structures, and may have all.

(Embodiment 1)
The first configuration of the present invention will be described. A block diagram of a light emitting device having the first configuration of the present invention is shown in FIG.

Reference numeral 101 denotes a pixel portion, and a plurality of pixels are provided in a matrix. 102
Is a source signal line driving circuit, and 103 is a gate signal line driving circuit.

The source signal line driver circuit 102 includes a shift register 102-1 and a latch (A) 10
2-2, latch (B) 102-3, and switching circuit 102-4. Note that the source signal line driver circuit of the present invention may have a level shift, a buffer, and the like in addition to the above.

Although not shown, the gate signal line driver circuit 103 includes a shift register and a buffer. In some cases, a level shift may be provided in addition to the shift register and the buffer. The gate signal line is connected to the gate electrode of the pixel TFT for one line, and all the pixel TFTs for one line must be turned on at the same time, so that the buffer can flow a large current. Used.

In the source signal line driver circuit 102, a clock signal (CLK) and a start pulse (SP) are input to the shift register 102-1. Shift register 1
02-1 sequentially generates timing signals based on the clock signal (CLK) and the start pulse (SP), and sequentially supplies the timing signals to the subsequent circuit.

Note that the timing signal output from the shift register 102-1 may be sequentially supplied to a subsequent circuit through a buffer or the like (not shown). The timing signal from the shift register 102-1 is buffered and amplified by a buffer or the like. Since many circuits or elements are connected to the wiring to which the timing signal is supplied, the load capacitance (parasitic capacitance) is large. This buffer is provided in order to prevent “blunting” of the rising edge or falling edge of the timing signal caused by the large load capacity.

The timing signal output from the shift register 102-1 is latched (A) 1
02-2. The latch (A) 102-2 has a plurality of stages of latches for processing n-bit digital video signals. When the timing signal is input, the latch (A) 102-2 sequentially captures and holds n-bit digital video signals supplied from the outside of the source signal line driver circuit 102.

Note that when the digital video signal is taken into the latch (A) 102-2, the digital video signal may be sequentially input to the latches of a plurality of stages included in the latch (A) 102-2. However, the present invention is not limited to this configuration. Latch (A) 10
A so-called divided drive may be performed in which latches of a plurality of stages of 2-2 are divided into several groups, and digital video signals are input simultaneously in parallel for each group. Note that the number of groups at this time is called the number of divisions. For example, when the latches are divided into groups for every four stages, it is said that the driving is divided into four.

A period until writing of digital video signals to all the latches of the latch (A) 102-2 is called a line period. That is, the latch (
A) A time interval from the time when writing of the digital video signal is started to the leftmost stage latch in 102-2 to the time when writing of the digital video signal is finished to the rightmost stage latch is a line. It is a period. Actually, the line period may include a period obtained by adding a horizontal blanking period to the line period.

When one line period ends, the latch signal (Latch Si) is sent to the latch (B) 102-3.
gnals) is supplied. At this moment, the digital video signal written and held in the latch (A) 102-2 is sent all at once to the latch (B) 102-3 and written to all the latches of the latch (B) 102-3. , Retained.

Latch (A) 1 that has finished sending the digital video signal to latch (B) 102-3
In 02-2, digital video signals supplied from the outside of the source signal line driver circuit 102 are sequentially written again based on the timing signal from the shift register 102-1.

During the second line of one line, the digital video signals written and held in the latch (B) 102-2 are input to the switching circuit 102-4 all at once. The switching circuit 102-4 inverts the polarity of the digital video signal input from the latch (B) 102-2 according to the switching signal (Shift Signals) or outputs the inverted signal.

The digital video signal has information of “0” or “1”, and “0” and “1”
”Is a signal having a voltage of one Hi and one Lo. The inversion of the polarity of the digital video signal means that a digital video signal having information “0” is converted into a digital video signal having information “1”, and the digital video signal having information “1” is converted to “0”. It is converted into a digital video signal having the following information.

The switching signal is a signal for selecting whether to invert the polarity of the digital video signal input from the latch (B) 102-2. The average length of the light emission period of all the light emitting elements in one frame period is more than half the length of the light emission period of the light emitting elements in one frame period when all white is displayed on the pixel portion 101. When it becomes longer, the power consumption can be reduced by inverting the polarity of the digital video signal by the switching signal. On the other hand, the average length of the light emission periods of all the light emitting elements in one frame period is the length of the light emission period of the light emitting elements in one frame period when all white is displayed on the pixel portion 101. When the length is shorter than half, the power consumption can be reduced if the polarity of the digital video signal is not inverted by the switching signal.

Whether the polarity of the digital video signal is inverted by the switching signal may be selected by the user or may be automatically selected according to the displayed image.

The digital video signal output from the switching circuit 102-4 is input to the source signal line.

On the other hand, in the gate signal line driver circuit 103, a gate signal from a shift register (not shown) is inputted to a buffer (not shown) and inputted to a corresponding gate signal line (also called a scanning line).

The digital video signal input to the source signal line is input to the pixel by the gate signal input to the gate signal line.

In the present invention, the source signal line driver circuit 102 and the gate signal line driver circuit 1
03 may be formed on the same substrate as the pixel portion 101, or may be formed on an IC chip and connected to the pixel portion 101 via FPC, TAB, or the like.

With the above structure of this embodiment mode, when a light-emitting device that performs digital-driven time-division gradation display performs monochrome display, light and darkness of an image can be reversed by an image displayed in a pixel portion. Specifically, the average length of the light emitting periods of all the light emitting elements in one frame period is 1 when all white is displayed on the pixel portion 101.
When it is longer than half the length of the light emitting element during the frame period, the brightness and darkness of the image displayed on the pixel portion may be reversed. On the other hand, the average length of the light emitting periods of all the light emitting elements in one frame period is the pixel portion 101.
It is better not to reverse the brightness of the image displayed in the pixel portion when it becomes shorter than half the length of the light emitting period of the light emitting element in one frame period when all white is displayed.

Note that in this embodiment, the switching circuit is included in the source signal line driver circuit, but the switching circuit may not be included in the source signal line driver circuit.

In this embodiment, only the case of using a digital video signal has been described. However, the present invention can be applied not only to a digital video signal but also to an analog video signal.

Therefore, with the first structure of the present invention, the magnitude of the current flowing through the light emitting element can be suppressed to some extent, and the power consumption of the light emitting device can be suppressed.

(Embodiment 2)
Next, the second configuration of the present invention will be described. FIG. 2 shows a block diagram of a light emitting device having the second configuration of the present invention. 1 is the same as that shown in FIG.
The same reference numerals are used.

In the light-emitting device of this embodiment mode, the clock signal control circuit 106 can supply a constant potential to the shift register 102-1 instead of the clock signal (CLK).

Specifically, the clock signal control circuit 106 inputs a fixed potential (fixed potential) to the shift register 102-1 instead of the clock signal for a fixed period. With the above configuration, the timing signal for writing the digital video signal of the lower bits from the 1st to mth bits (m is an arbitrary integer from 1 to n) to the latch (A) 102-2 is latched (A). It was made not to input into 102-2. Therefore, of the digital video signal n bits input from the outside of the source signal line driver circuit 102, only the higher-order digital video signal from the (m + 1) th bit to the nth bit is written to the latch (A) 102-2. Can do.

Note that the light-emitting device of this embodiment differs from that in FIG.
2 does not have the switching circuit 102-4. Therefore, latch (B) 102-
3 is held in the latch (B) 102-
3 is input to the source signal line by the latch signal input to 3.

In this embodiment mode, in a light-emitting device that performs digital-driven time-division gradation display,
The digital video signal input to the source signal line driver circuit included in the light emitting device is input to the pixel portion after the number of bits is reduced. Specifically, the number of bits of the digital video signal input to the pixel portion is decreased by sequentially discarding the digital video signal of the least significant bit.

With the above structure, the number of bits of the digital video signal input to the pixel is reduced, so that the number of times the digital video signal is written to the pixel by the source signal line driver circuit and the gate signal line driver circuit is reduced. Therefore, power consumption of the source signal line driver circuit and the gate signal line driver circuit can be suppressed, and power consumption of the light-emitting device can also be suppressed.

Note that in this embodiment, the clock signal control circuit 106 may be formed over the same substrate as the pixel portion 101 or may be formed over an IC chip.

(Embodiment 3)
Next, an example different from the second embodiment of the second configuration of the present invention will be described.
A block diagram of a light emitting device having the second configuration of the present invention is shown in FIG. The same components as those shown in FIG. 1 are denoted by the same reference numerals as those in FIG.

In the light-emitting device of this embodiment, the timing signal control circuit 107 can supply a constant potential to the latch (A) 102-2 instead of the timing signal output from the shift register 102-1. .

Specifically, the timing signal control circuit 107 applies a fixed potential (fixed potential) to the latch (A) 102-2 instead of the timing signal output from the shift register 102-1 for a fixed period. . With the above configuration, only the timing signal for writing the digital video signal of the lower bits from the 1st to mth bits (m is an arbitrary integer from 1 to n) to the latch (A) 102-2 is latched (A
) Do not input to 102-2. Therefore, among the n bits of the digital video signal input from the outside of the source signal line driver circuit 102, only the upper bit digital video signals from the (m + 1) th bit to the nth bit can be written to the latch (A) 102-2. .

Note that in this embodiment mode, the fixed potential needs to be a potential at which a digital video signal is not written to the latch (A) 102-2.

In this embodiment mode, in a light-emitting device that performs digital-driven time-division gradation display,
The digital video signal input to the source signal line driver circuit included in the light emitting device is input to the pixel portion after the number of bits is reduced. Specifically, the number of bits of the digital video signal input to the pixel portion is decreased by sequentially discarding the digital video signal of the least significant bit.

With the above structure, the number of bits of the digital video signal input to the pixel is reduced, so that the number of times the digital video signal is written to the pixel by the source signal line driver circuit and the gate signal line driver circuit is reduced. Therefore, power consumption of the source signal line driver circuit and the gate signal line driver circuit can be suppressed, and power consumption of the light-emitting device can also be suppressed.

Note that in this embodiment mode, the timing signal control circuit 107 includes the pixel portion 101.
It may be formed on the same substrate as that described above, or may be formed on an IC chip.

(Embodiment 4)
Next, an example of the second configuration of the present invention that is different from the second and third embodiments will be described. A block diagram of a light emitting device having the second configuration of the present invention is shown in FIG. The same components as those shown in FIG. 1 are denoted by the same reference numerals as those in FIG.

In the light-emitting device of this embodiment, the start pulse signal control circuit 108 applies a constant potential instead of the start pulse signal (SP) to the shift register 102-1.
To be able to give to.

Specifically, only the timing signal for writing the digital video signal of the lower bits from the 1st to mth bits (m is an arbitrary integer from 1 to n) to the latch (A) 102-2 is latched (A). A constant potential (fixed potential) is used instead of the start pulse signal by the start pulse signal control circuit 108 so that it is not input to 102-2.
Is supplied to the shift register 102-1 for a certain period. Therefore, of the n bits of the digital video signal input from the outside of the source signal line driver circuit 102, (
Only the digital video signals of the upper bits from the (m + 1) th bit to the nth bit can be written to the latch (A) 102-2.

Note that in this embodiment mode, the fixed potential needs to be a potential at which a timing signal is not output from the shift register 102-1.

In this embodiment mode, in a light-emitting device that performs digital-driven time-division gradation display,
The digital video signal input to the source signal line driver circuit included in the light emitting device is input to the pixel portion after the number of bits is reduced. Specifically, the number of bits of the digital video signal input to the pixel portion is decreased by sequentially discarding the digital video signal of the least significant bit.

With the above structure, the number of bits of the digital video signal input to the pixel is reduced, so that the number of times the digital video signal is written to the pixel by the source signal line driver circuit and the gate signal line driver circuit is reduced. Therefore, power consumption of the source signal line driver circuit and the gate signal line driver circuit can be suppressed, and power consumption of the light-emitting device can also be suppressed.

Note that in this embodiment, the start pulse signal control circuit 108 includes the pixel portion 1
It may be formed on the same substrate as 01, or may be formed on an IC chip.

(Embodiment 5)
Next, a third configuration of the present invention will be described with reference to FIG. Reference numeral 501 denotes a power supply line. Note that in this specification, a power supply line is a wiring for applying a predetermined potential to a pixel electrode included in a light-emitting element of a pixel portion by a digital video signal input to a source signal line. In this specification, the potential of the power supply line is referred to as a power supply potential.

Reference numeral 502 denotes a buffer amplifier (buffer amplifier), reference numeral 503 denotes a monitor light emitting element, and reference numeral 504 denotes a constant current source. One electrode of the monitor light emitting element 503 is connected to a constant current source 504, and a constant current always flows through the monitor light emitting element 503. When the temperature of the organic compound layer included in the light emitting element is changed, the potential of the electrode of the monitoring light emitting element 503 connected to the constant current source 504 is changed, instead of the magnitude of the current flowing through the monitoring light emitting element 503 being changed. Change.

On the other hand, the buffer amplifier 502 has two input terminals and one output terminal. One of the two input terminals is a non-inverting input terminal (+) and the other is an inverting input terminal (−). The potential of one electrode of the monitoring light emitting element 503 is applied to the non-inverting input terminal of the buffer amplifier 502.

The buffer amplifier 502 includes the monitor light emitting element 5 connected to the constant current source 504.
This is a circuit that prevents the potential of the pixel electrode 03 from being changed by a load such as a wiring capacity of the power supply line 501. Therefore, the potential applied to the non-inverting input terminal of the buffer amplifier 502 is output from the output terminal without being changed by a load such as the wiring capacity of the power supply line 501 and is applied to the power supply line as a power supply potential.

Therefore, even if the temperature of the organic light emitting element 503 or the organic compound layer of the light emitting element of the pixel portion changes due to the change of the environmental temperature, the power supply potential changes so that a constant current flows through the light emitting element. Therefore, increase in power consumption of the light emitting device can be suppressed even if the environmental temperature of the light emitting device is increased.

In this embodiment, the buffer amplifier 502 and the monitor light emitting element 50 are used.
3. The constant current source 504 may be formed on the same substrate as the pixel portion, or may be formed on an IC chip. The monitor light emitting element 503 may be included in the pixel portion or may be provided separately from the pixel portion.

According to the first to third configurations of the present invention, the power consumption of the light emitting device and the electronic device using the light emitting device can be suppressed. Note that the present invention only needs to have one of the first to third configurations. Moreover, you may have a some structure of 1st to 3rd structures, and may have all.

According to the present invention, the power consumption of the light emitting device can be suppressed by the above three configurations.

  Examples of the present invention will be described below.

Example 1
In this embodiment, a structure of a pixel portion of a light emitting device of the present invention and a driving method thereof will be described.

An enlarged view of the pixel portion 301 of the light emitting device of this embodiment is shown in FIG. Source signal line (S
1 to Sx), power supply lines (V1 to Vx), and gate signal lines (G1 to Gy) are provided in the pixel portion 301.

In this example, the pixel 304 is a region provided with one source signal line (S1 to Sx), one power supply line (V1 to Vx), and one gate signal line (G1 to Gy). A plurality of pixels 304 are arranged in a matrix in the pixel portion 301.

An enlarged view of the pixel 304 is shown in FIG. In FIG. 7, reference numeral 305 denotes a switching T.
FT. The gate electrode of the switching TFT 305 is a gate signal line G (G
1 to Gx). One of the source region and the drain region of the switching TFT 305 is the source signal line S (S1 to Sx), and the other is the current control T.
The gate electrode of the FT 306 is connected to the capacitor 308 included in each pixel.

The capacitor 308 is provided to hold the gate voltage (potential difference between the gate electrode and the source region) of the current control TFT 306 when the switching TFT 305 is in a non-selected state (off state). In this embodiment, the capacitor 30
However, the present invention is not limited to this configuration, and the capacitor 308 is provided.
It is also possible to adopt a configuration in which no is provided.

One of the source region and the drain region of the current control TFT 306 is connected to the power supply line V (V1 to Vx), and the other is connected to the light emitting element 307. The power supply line V is connected to the capacitor 308.

The light emitting element 307 includes an anode, a cathode, and an organic compound layer provided between the anode and the cathode. When the anode is connected to the source region or drain region of the current control TFT 306, the anode serves as a pixel electrode and the cathode serves as a counter electrode. Conversely, when the cathode is connected to the source region or drain region of the current control TFT 306, the cathode serves as the pixel electrode and the anode serves as the counter electrode.

A counter potential is applied to the counter electrode of the light emitting element 307. Power supply line V
Is supplied with a power supply potential. The power source potential and the counter potential are supplied to the light emitting device of the present invention by a power source provided by an external IC or the like.

The switching TFT 305 and the current control TFT 306 are n-channel type TF.
Either T or p-channel TFT can be used. However, when the source region or drain region of the current control TFT 306 is connected to the anode of the light emitting element 307, the current control TFT 306 is preferably a p-channel TFT. In addition, when the source region or the drain region of the current control TFT 306 is connected to the cathode of the light emitting element 307, the current control TFT 306 is preferably an n-channel TFT.

Further, the switching TFT 305 and the current control TFT 306 may have a multi-gate structure such as a double gate structure or a triple gate structure instead of a single gate structure.

Next, a driving method of the light emitting device of the present invention having the above-described configuration will be described with reference to FIG.

First, the power supply potential of the power supply line is the same as the potential of the counter electrode of the light emitting element. A gate signal is input to the gate signal line G1 from the gate signal line driving circuit. As a result, the switching TFTs 305 of all the pixels (pixels on the first line) connected to the gate signal line G1 are turned on.

At the same time, the source signal lines (S1 to Sx) 1
The bit-th digital video signal is input. The digital video signal is input to the gate electrode of the current control TFT 306 via the switching TFT 305.

Next, at the same time as the input of the gate signal to G1, the gate signal is similarly input to the gate signal line G2. Then, the switching TFTs 305 of all the pixels connected to the gate signal line G2 are turned on, and the digital video signal of the first bit is input from the source signal lines (S1 to Sx) to the pixels of the second line. .

In turn, gate signals are inputted to all the gate signal lines (G1 to Gx). The period until all the gate signal lines (G1 to Gx) are selected and the digital video signal of the first bit is input to the pixels of all the lines is the writing period Ta1.

When the writing period Ta1 ends, the light emission period Tr1 is reached next. In the light emission period Tr1, the power supply potential of the power supply line is a potential having a potential difference with the counter electrode to the extent that the light emitting element emits light when the power supply potential is applied to the pixel electrode of the light emitting element.

In this embodiment, when the digital video signal has information “0”,
The current control TFT 306 is off. Therefore, no power supply potential is applied to the pixel electrode of the light emitting element 307. As a result, the light-emitting element 307 included in the pixel to which the digital video signal having the information “0” is input does not emit light.

On the other hand, when the information “1” is included, the current control TFT 306 is in an on state. Accordingly, a power supply potential is applied to the pixel electrode of the light emitting element 307. As a result, the light emitting element 307 included in the pixel to which the digital video signal having the information “1” is input emits light.

Thus, in the display period Tr1, the light emitting element 307 emits light or does not emit light, and all the pixels perform display. The period during which the pixel is displaying is the display period Tr
Call it. In particular, a display period that starts when a digital video signal of the first bit is input to the pixel is referred to as Tr1. In FIG. 8, only the display period of the pixels in the first line is shown for the sake of simplicity. The timing at which the display period of all lines is started is the same.

When the display period Tr1 ends, the writing period Ta2 starts, and the power supply potential of the power supply line becomes the same as the potential of the counter electrode of the light emitting element. In the same manner as in the writing period Ta1, all the gate signal lines are sequentially selected, and the second bit digital video signal is input to all the pixels. A period until the second bit digital video signal is completely input to the pixels of all the lines is referred to as a writing period Ta2.

When the writing period Ta2 ends, the display period Tr2 starts. The power supply potential of the power supply line is different from that of the counter electrode so that the light emitting element emits light when the power supply potential is applied to the pixel electrode of the light emitting element. It becomes the electric potential which has. All pixels display.

The above-described operation is repeated until the n-th digital video signal is input to the pixel, and the writing period Ta and the display period Tr appear repeatedly. When all the display periods (Tr1 to Trn) are completed, one image can be displayed. In the driving method of the present invention, a period for displaying one image is referred to as one frame period (F). When one frame period ends, the next frame period starts. Then, the writing period Ta1 appears again, and the above-described operation is repeated.

In a normal light emitting device, it is preferable to provide 60 or more frame periods per second. When the number of images displayed per second is less than 60, flickering of images may start to be noticeable visually.

In this embodiment, the sum of the lengths of all writing periods is shorter than one frame period,
In addition, the length ratio of the display periods is Tr1: Tr2: Tr3:...: Tr (n-1):
It is necessary that Trn = 2 ⁰ : 2 ¹ : 2 ² :...: 2 ⁽ⁿ⁻²⁾ : 2 ⁽ⁿ⁻¹⁾ . A desired gradation display among 2 ⁿ gradations can be performed by combining the display periods.

By obtaining the sum of the lengths of the display periods during which the light emitting element emits light during one frame period, the gradation displayed by the pixel in the frame period is determined. For example,
When n = 8 and the luminance when the pixel emits light in the entire display period is 100%, the luminance of 1% can be expressed when the pixel emits light in Tr1 and Tr2.
When 3 and Tr5 and Tr8 are selected, 60% luminance can be expressed.

The display periods Tr1 to Trn may appear in any order. For example, in one frame period, it is possible to cause the display period to appear in the order of Tr3, Tr5, Tr2,.

In this embodiment, the power supply potential of the power supply line is changed between the writing period and the display period. However, the present invention is not limited to this. A potential difference such that the light emitting element emits light when the power supply potential is applied to the pixel electrode of the light emitting element may be always present between the power supply potential and the potential of the counter electrode. In that case, the light-emitting element can emit light even in the writing period. Therefore, the gray level displayed by the pixel in the frame period is determined by the sum of the length of the writing period and the display period during which the light emitting element emits light during one frame period. In this case, the ratio of the sum of the length of the writing period and the display period corresponding to the digital video signal of each bit is (Ta1 + Tr1) :( Ta2 +
Tr2) :( Ta3 + Tr3): ... :( Ta (n-1) + Tr (n-1)) :(
Tan + Trn) = 2 ⁰ : 2 ¹ : 2 ² :...: 2 ⁽ⁿ⁻²⁾ : 2 ⁽ⁿ⁻¹⁾ .

(Example 2)
In this embodiment, an example different from the first embodiment will be described with respect to the structure of the pixel portion of the light emitting device of the present invention and the driving method thereof.

FIG. 9 shows an example of a block diagram of the light emitting device of this embodiment. The light-emitting device of FIG. 9 includes a pixel portion 901, a source signal side driver circuit 902 disposed around the pixel portion, and a writing gate signal side driver circuit (first gate signal line driver circuit) by TFTs formed on a substrate. 903a and an erasing gate signal line driver circuit (second gate signal line driver circuit) 903b. In this embodiment, the light emitting device has one source signal side driver circuit. However, in this embodiment, there may be two source signal side driver circuits.

The source signal side drive circuit 902 has at least one of the first to third configurations of the present invention.

Note that in this embodiment, the source signal line driver circuit 902, the write gate signal side driver circuit 903a, and the erase gate signal line driver circuit 903b include a pixel portion 901.
May be formed on the same substrate as the FPC, TA
The pixel unit 901 may be connected via a connector such as B.

An enlarged view of the pixel portion 901 is shown in FIG. Source signal lines (S1 to Sx), power supply lines (V1 to Vx), write gate signal lines (first gate signal lines) (Ga1
Gay) and an erasing gate signal line (second gate signal line) (Ge1 to Gey) are provided in the pixel portion 901.

At least one source signal line (S1 to Sx), a power supply line (V1 to Vx), a write gate signal line (Ga1 to Gay), and an erase gate signal line (Ge1 to Gey) are provided. The area is a pixel 904. In the pixel portion 901, a plurality of pixels 904 are arranged in a matrix.

An enlarged view of the pixel 904 is shown in FIG. In FIG. 11, reference numeral 907 denotes a switching TFT. The gate electrode of the switching TFT 907 is connected to the write gate signal line Ga (Ga1 to Gay). Switching TFT90
7, one of the source region and the drain region is the source signal line S (S1 to Sx), the other is the gate electrode of the current control TFT 908, and the capacitor 91 included in each pixel.
2 and the source region or drain region of the erasing TFT 909.

The capacitor 912 is provided to hold the gate voltage of the current control TFT 908 when the switching TFT 907 is in a non-selected state (off state). Note that although a configuration in which the capacitor 912 is provided is shown in this embodiment, the present embodiment is not limited to this configuration, and a configuration without the capacitor 912 may be employed.

One of the source region and the drain region of the current control TFT 908 is connected to the power supply line V (V 1 to Vx), and the other is connected to the light emitting element 910. The power supply line V is connected to the capacitor 912.

Of the source region and drain region of the erasing TFT 909, the one not connected to the source region or drain region of the switching TFT 907 is connected to the power supply line V. The gate electrode of the erasing TFT 909 is connected to the erasing gate signal line Ge.

The light-emitting element 910 includes an anode, a cathode, and an organic compound layer provided between the anode and the cathode. When the anode is connected to the source region or drain region of the current control TFT 908, the anode serves as a pixel electrode and the cathode serves as a counter electrode. Conversely, when the cathode is connected to the source region or drain region of the current control TFT 908, the cathode serves as the pixel electrode and the anode serves as the counter electrode.

A counter potential is applied to the counter electrode 911 of the light emitting element 910. The power supply line V is given a power supply potential. The potential difference between the counter potential and the power supply potential is always kept at such a potential difference that the light emitting element emits light when the power supply potential is applied to the pixel electrode. The power source potential and the counter potential are supplied to the light emitting device of the present invention by a power source provided by an external IC or the like.

The current typical light emitting device has a light emission amount of 200 c per pixel emitting area.
In the case of d / m ² , the current per area of the pixel portion needs to be about several mA / cm ² . Therefore, especially when the screen size is increased, it becomes difficult to control the height of the potential applied from the power source provided in the IC with a switch. In this example,
The power supply potential and the counter potential are always kept constant, and it is not necessary to control the height of the potential supplied from the power supply provided in the IC with a switch, which is useful for realizing a panel with a larger screen size.

Switching TFT 907, current control TFT 908, erasing TFT 909
Either an n-channel TFT or a p-channel TFT can be used. However, when the source region or the drain region of the current control TFT 908 is connected to the anode of the light emitting element 910, the current control TFT 908 is preferably a p-channel TFT. Further, when the source region or the drain region of the current control TFT 908 is connected to the cathode of the light emitting element 910, the current control TF
T908 is preferably an n-channel TFT.

Also, a switching TFT 907, a current control TFT 908, an erasing TFT 9
09 may not have a single gate structure but may have a multi-gate structure such as a double gate structure or a triple gate structure.

Next, a method for driving the light emitting device of the present invention having the above-described configuration will be described with reference to FIG.

First, for switching all the pixels (pixels in the first line) connected to the write gate signal line Ga1 by the write gate signal input to the write gate signal line Ga1 from the write gate signal line drive circuit 903a. TF
T907 is turned on. In this specification, the fact that all TFTs whose gate electrodes are connected to signal lines is turned on is referred to as selection of the wiring. Therefore, in this case, the write gate signal line Ga1 is selected.

At the same time, the digital video signal of the first bit is input to the pixels of the first line from the source signal line driver circuit 902 to the source signal lines (S1 to Sx). Specifically, the digital video signal is sent to the current control TF via the switching TFT 907.
Input to the gate electrode of T908.

In this embodiment, when the digital video signal has information of “0”, the current control TFT 908 is turned off. Therefore, no power supply potential is applied to the pixel electrode of the light emitting element 910. As a result, the light-emitting element 910 included in the pixel to which the digital video signal having the information “0” is input does not emit light.

On the contrary, when the information “1” is included, the current control TFT 908 is turned on. Accordingly, a power supply potential is applied to the pixel electrode of the light emitting element 910. As a result, the light-emitting element 910 included in the pixel to which the digital video signal having the information “1” is input emits light.

In this way, the digital video signal is input to the pixels on the first line,
The light emitting element 910 emits light or does not emit light, and the pixels on the first line perform display. A period during which the pixels are displaying is referred to as a display period Tr. In particular, a display period that starts when a digital video signal of the first bit is input to the pixel is referred to as Tr1.
In FIG. 12, only the display period of the pixels in the first line is shown for the sake of simplicity. The timing at which the display period of each line is started has a time difference.

Next, simultaneously with the selection of Ga1, the write gate signal line Ga2 is selected by the write gate signal. Then, the switching TFTs 907 of all the pixels connected to the writing gate signal line Ga2 are turned on,
A digital video signal of the first bit is input from the source signal lines (S1 to Sx) to the pixels of the second line.

In turn, all the write gate signal lines (Ga1 to Gax) are selected. A period until all the gate signal lines for writing (Ga1 to Gax) are selected and the digital video signal of the first bit is input to the pixels of all the lines is a writing period Ta1.

On the other hand, before the first bit digital video signal is input to the pixels of all the lines, in other words, before the writing period Ta1 ends, in parallel with the input of the first bit digital video signal to the pixels. The erase gate signal line Ge1 is selected by the erase gate signal input from the gate signal line drive circuit 903b.

When the erasing gate signal line Ge1 is selected, the erasing TFTs 909 of all the pixels (pixels in the first line) connected to the erasing gate signal line Ge1 are turned on. The power supply potential of the power supply lines (V1 to Vx) is applied to the gate electrode of the current control TFT 908 of the pixel on the first line via the erasing TFT 909.

When the power supply potential is applied to the gate electrode of the current control TFT 908, the current control TFT 908 is turned off. Accordingly, the power supply potential is not applied to the pixel electrode of the light emitting element 910, and all the light emitting elements included in the pixels on the first line are in a non-light emitting state, and the pixels on the first line do not display. That is, the digital video signal held by the gate electrode of the current control TFT from when the write gate signal line Ga1 is selected is erased by applying the power supply potential to the gate electrode of the current control TFT. Therefore, the pixels on the first line do not display.

A period in which the pixels do not display is called a non-display period Td. The pixels on the first line display the display period Tr at the same time as the erase gate signal is input to the erase gate signal line Ge1.
1 ends and the non-display period Td1 is reached.

In FIG. 12, only the non-display period of the pixels on the first line is shown for the sake of simplicity. Similar to the display period, the timing at which the non-display period of each line is started has a time difference.

At the same time as the selection of Ge1, the erasing gate signal line Ge2 is selected by the erasing gate signal, and the erasing TFTs 909 of all the pixels (second line pixels) connected to the erasing gate signal line Ge2 are selected. Turns on. The power supply potential of the power supply lines (V1 to Vx) is applied to the gate electrode of the current control TFT 908 via the erasing TFT 909. When the power supply potential is applied to the gate electrode of the current control TFT 908, the current control TFT 908 is turned off. Accordingly, the power supply potential is not applied to the pixel electrode of the light emitting element 910. As a result, all the light-emitting elements included in the pixels on the second line are in a non-light emitting state, and the pixels on the second line are not displayed and are not displayed.

In turn, all the erase gate signal lines are selected by the erase gate signal. An erasing period Te1 is a period until all the erasing gate signal lines (Ga1 to Gax) are selected and the first bit digital video signals held in the pixels of all the lines are erased.

On the other hand, before the first bit digital video signal held by the pixels of all the lines is erased, in other words, before the erase period Te1 ends, in parallel with the erase of the first bit digital video signal to the pixels. Then, the write gate signal line Ga1 again
Is selected. As a result, the pixels on the first line perform display again, so the non-display period Td1 ends and the display period Tr2 starts.

Similarly, all the gate signal lines for writing are sequentially selected, and the second bit digital video signal is input to all the pixels. A period until the second bit digital video signal is completely input to the pixels of all the lines is referred to as a writing period Ta2.

On the other hand, before the second bit digital video signal is input to the pixels of all lines, in other words, before the writing period Ta2 ends, in parallel with the input of the second bit digital video signal to the pixels, The erase gate signal line Ge2 is selected. Therefore, all the light emitting elements included in the pixels on the first line are in a non-light emitting state,
The pixels on the first line do not display. Therefore, the display period Tr2 ends in the pixels on the first line, and becomes a non-display period Td2.

In turn, all the erasing gate signal lines are selected. An erasing period Te2 is a period until all the erasing gate signal lines (Ga1 to Gax) are selected and the second bit digital video signals held by the pixels of all the lines are erased.

The above-described operation is repeated until the m-bit digital video signal is input to the pixel, and the display period Tr and the non-display period Td appear repeatedly. Display period T
r1 is a period from the start of the writing period Ta1 to the start of the erasing period Te1. The non-display period Td1 is a period from the start of the erase period Te1 to the start of the display period Tr2. And the display periods Tr2, Tr3,.
, Tr (m−1) and non-display periods Td2, Td3,..., Td (m−1) are also written periods Ta1, Ta2, and Td (m−1), respectively, similarly to the display period Tr1 and the non-display period Td1.
..., Tam and erase periods Te1, Te2, ..., Te (m-1) define the period.

After the m-bit digital video signal is input to the pixels on the first line, the erasing gate signal line Ge1 is not selected. In order to simplify the explanation, the present embodiment will be described by taking the case of m = n−2 as an example, but it goes without saying that the present invention is not limited to this. In the present invention, m can be arbitrarily selected from 2 to n.

When the digital video signal of the (n-2) th bit is input to the pixels on the first line, the pixels on the first line are displayed during the display period Tr (n-2). Until the next bit digital video signal is input, the digital video signal of the (n-2) th bit is held in the pixel.

Then, when the (n-1) -bit digital video signal is input to the pixel on the first line, the (n-2) -bit digital video signal held in the pixel is (n-1) It is rewritten to the digital video signal of the bit. The pixels on the first line enter the display period Tr (n−1) and display is performed. The digital video signal of the (n-2) th bit is held in the pixel until the digital video signal of the next bit is input.

The above-described operation is repeated until the n-th digital video signal is input to the pixel. The display period Tr (n-2) is a period from the start of the writing period Ta (n-2) to the start of the writing period Ta (n-1). The display period (Tr (n−1), Trn) is determined by the writing period Ta in the same manner as the display period Tr (n−2).

In this embodiment, the sum of the lengths of all the writing periods is shorter than one frame period, and the length of the display period is Tr1: Tr2: Tr3:...: Tr (n−1):
Trn = 2 ⁰ : 2 ¹ : 2 ² :...: 2 ⁽ⁿ⁻²⁾ : 2 ⁽ⁿ⁻¹⁾ is required. A desired gradation display among 2 ⁿ gradations can be performed by combining the display periods.

When all the display periods (Tr1 to Trn) are completed, one image can be displayed. In the driving method of the present invention, a period for displaying one image is referred to as one frame period (F).

After the end of one frame period, the digital video signal of the first bit is input again to the pixels, and the pixels on the first line again become the display period Tr1. Then, the above-described operation is repeated again.

In a normal light emitting device, it is preferable to provide 60 or more frame periods per second. When the number of images displayed per second is less than 60, flickering of images may start to be noticeable visually.

By obtaining the sum of the lengths of the display periods during which the light emitting element emits light during one frame period, the gradation displayed by the pixel in the frame period is determined. For example,
When n = 8 and the luminance when the pixel emits light in the entire display period is 100%, the luminance of 1% can be expressed when the pixel emits light in Tr1 and Tr2.
When 3 and Tr5 and Tr8 are selected, 60% luminance can be expressed.

It is important that the writing period Tam in which the m-bit digital video signal is written to the pixel is shorter than the length of the display period Trm. Therefore, the value of the number of bits m needs to be a value from 1 to n such that the writing period Tam is shorter than the length of the display period Trm.

The display periods (Tr1 to Trn) may appear in any order. For example, in one frame period, it is possible to cause the display period to appear in the order of Tr4, Tr3, Tr2,. However, the erasing period (Te1
The order in which Ten) does not overlap each other is more preferred.

In this embodiment, the display period Tr and the writing period Ta partially overlap. In other words, it is possible to display pixels even in the writing period. Therefore, the ratio (duty ratio) of the total length of the display periods in one frame period is not determined only by the length of the writing period.

(Example 3)
In this example, a detailed structure of a source signal line driver circuit included in the light-emitting device described in Embodiment Mode 1 will be described. FIG. 13 shows a circuit diagram of the source signal line driving circuit of this embodiment. In addition, the same thing as what was shown in FIG. 1 is shown with the same code | symbol.

Reference numeral 102-1 denotes a shift register, in which the clock signal (CLK), the signal (CLKB) in which the polarity of the clock signal is inverted, the start pulse signal (SP), and the bidirectional switching signal (SL / R) are shown in the diagram. Each is input from.

Reference numeral 102-2 denotes a latch (A), and reference numeral 102-3 denotes a latch (B). In this embodiment, one set of latches (A) 102-2 and one set of latches (B) 102-3 correspond to four source signal lines. However, in this embodiment, the number of source signal lines corresponding to one set of latches (A) 102-2 and one set of latches (B) 102-3 is not limited to this. In this embodiment, the level shift for changing the amplitude range of the voltage of the signal is not provided. However, the designer may appropriately provide it.

Digital video signals (DV) input from outside the source signal line driver circuit
Is input to the latch (A) 102-2 from the wiring shown in the drawing. Latch signal S_
A signal S_LATb in which the polarities of LAT and S_LAT are inverted is input to the latch (B) 102-3 from the wiring shown in the drawing.

A detailed configuration of the latch (A) 102-2 will be described by taking a part 801 of the latch (A) 102-2 as an example. A part 801 of the latch (A) 102-2 has two clocked inverters and two inverters.

A top view of a part 801 of the latch (A) 102-2 is shown in FIG. 831a, 8
Reference numeral 31b denotes an active layer of a TFT that forms one of the inverters included in a part 801 of the latch (A) 102-2. Reference numeral 836 denotes a common gate electrode of the TFTs that form one of the inverters. Each of 832a and 832b forms another inverter included in a part 801 of the latch (A) 102-2.
FT active layers 837a and 837b are gate electrodes provided on the active layers 832a and 832b, respectively. Note that the gate electrodes 837a and 837b are electrically connected.

Reference numerals 833a and 833b denote active layers of TFTs that form one of the clocked inverters included in the part 801 of the latch (A) 102-2. Active layer 833
Gate electrodes 838a and 838b are provided on a and have a double gate structure. Gate electrodes 838b and 839 are provided on the active layer 833b to form a double gate structure.

Reference numerals 834a and 834b denote active layers of TFTs that form another clocked inverter included in the part 801 of the latch (A) 102-2. Active layer 8
Gate electrodes 839 and 840 are provided on 34a to form a double gate structure. Further, gate electrodes 840 and 841 are provided on the active layer 834b to form a double gate structure.

Reference numeral 102-4 denotes a switching circuit. FIGS. 15A and 15B are circuit diagrams of the switching circuit of this embodiment.

The switching circuit 102-4 of this embodiment shown in FIG.
1, a first analog switch 852, and a second analog switch 853. A switching signal SS and a signal SSB in which the polarity of the switching signal is inverted are input from the wiring shown in the drawing.

An equivalent circuit diagram of the first and second analog switches 852 and 853 is shown in FIG. The first and second analog switches 852 and 853 have an n-channel TFT and a p-channel TFT. A signal input from the input terminal (IN) is sampled by a signal input from the first control input terminal (Vin) or the second control input terminal (Vinb), and is output from the output terminal (OUT).

The digital video signal from the latch (B) 102-3 is input from the input terminal (IN) to the first analog switch 852 via the inverter 851. At the same time, the digital video signal from the latch (B) 102-3 is input to the second analog switch 853 from the input terminal (IN).

The switching signal SS and the signal SSB obtained by inverting the polarity of the switching signal are
The first analog switch 852 and the second analog switch 853 are input from the first control input terminal (Vin) or the second control input terminal (Vinb), respectively. The digital video signal is sampled by this switching signal SS,
The output terminals (O of the first analog switch 852 and the second analog switch 853
A digital video signal sampled from (UT) is output.

The digital video signal input to the switching circuit 102-4 is output from the switching circuit 102-4 as it is or with its polarity inverted. Whether or not the polarity of the digital video signal is inverted in the switching circuit 102-4 is selected by the switching signal SS.

The switching circuit 102-4 of this embodiment shown in FIG.
1, a first NAND 862, a second NAND 863, and a NOR 864. A switching signal SS and a signal SSB in which the polarity of the switching signal is inverted are input from the wiring shown in the drawing.

The digital video signal from the latch (B) 102-3 is sent through the inverter 861. At the same time, a signal SSB obtained by inverting the polarity of the switching signal SS is also input to the first NAND 862.

In addition, the digital video signal is transmitted through the inverter 861 to the first NAND 862.
At the same time, a digital video signal is input to the second NAND 863. At the same time, the switching signal SS is also input to the second NAND 863.

The signals output from the first and second NANDs 862 and 863 are simultaneously NOR.
864. The signal output from NOR864 is input to the source signal line.

The digital video signal input to the switching circuit 102-4 is output from the switching circuit 102-4 as it is or with its polarity inverted. Whether or not the polarity of the digital video signal is inverted in the switching circuit 102-4 is selected by the switching signal SS.

The switching circuit is not limited to the configuration shown in FIG. The switching circuit may have any configuration as long as the input digital video signal can be output as it is or with its polarity inverted.

Note that this embodiment can be implemented by being freely combined with Embodiment 1 or 2.

Example 4
In this example, a detailed structure of a source signal line driver circuit included in the light-emitting device described in Embodiment Mode 2 will be described. FIG. 17 shows a circuit diagram of the source signal line driver circuit of this embodiment. In addition, the same thing as what was shown in FIG. 1 is shown with the same code | symbol.

Reference numeral 102-1 denotes a shift register, in which the clock signal (CLK), the signal (CLKB) in which the polarity of the clock signal is inverted, the start pulse signal (SP), and the bidirectional switching signal (SL / R) are shown in the diagram. Each is input from.

Reference numeral 102-2 denotes a latch (A), and reference numeral 102-3 denotes a latch (B). In this embodiment, one set of latches (A) 102-2 and one set of latches (B) 102-3 correspond to four source signal lines. However, in this embodiment, the number of source signal lines corresponding to one set of latches (A) 102-2 and one set of latches (B) 102-3 is not limited to this. In this embodiment, the level shift for changing the amplitude range of the voltage of the signal is not provided. However, the designer may appropriately provide it.

Digital video signals (DV) input from outside the source signal line driver circuit
Is input to the latch (A) 102-2 from the wiring shown in the drawing. Latch signal S_
A signal S_LATb in which the polarities of LAT and S_LAT are inverted is input to the latch (B) 102-3 from the wiring shown in the drawing.

The detailed configuration of the latch (A) 102-2 is the same as that shown in FIG.

A clock signal control circuit 106 can supply a constant potential (fixed potential) to the shift register 102-1 instead of the clock signal (CLK) for a certain period.

Specifically, only the timing signal for writing the low-order bit digital video signals from the 1st to m-th bits into the latch (A) 102-2 is latched (A) 102-.
The clock signal control circuit 106 inputs a constant potential (fixed potential) to the shift register 102-1 instead of the clock signal so that it is not input to 2. Therefore, among the n bits of the digital video signal input from the outside of the source signal line driver circuit, only the upper bit digital video signal from the (m + 1) th bit to the nth bit can be written to the latch (A) 102-2. it can.

18A and 18B are detailed circuit diagrams of the clock signal control circuit 106 of this embodiment.

The clock signal control circuit 106 of this embodiment shown in FIG.
01 and an inverter 1802. A selection signal is input from the wiring shown in the figure.

The clock signal input from the outside of the source signal line driver circuit is input terminal (IN)
Are input to the NAND 1801. At the same time, a selection signal is also input to the NAND 1801. The signal output from the NAND 1801 is the inverter 18.
The polarity is inverted by 02, output from the output terminal (OUT), and input to the shift register 102-1.

A selection signal selects whether a clock signal is input to the shift register 102-1 or a constant potential (fixed potential) is applied.

The clock signal control circuit 106 of this embodiment shown in FIG. 18B includes a first analog switch 1811, a second analog switch 1812, and an inverter 18.
13. A selection signal is input from the wiring shown in the figure.

The equivalent circuit diagram of the first and second analog switches 1811 and 1812 is the same as that shown in FIG. First and second analog switches 1811 and 1812
Has an n-channel TFT and a p-channel TFT. A signal input from the input terminal (IN) is sampled by a signal input from the first control input terminal (Vin) or the second control input terminal (Vinb), and the output terminal (OUT
) Is output.

A selection signal is input from the first control input terminal (Vin) to the first and second analog switches 1811 and 1812, and at the same time, the selection signal whose polarity is inverted by the inverter 1813 is the first and second analog switches 1811. , 1812
Are input from the second control input terminal (Vinb). At the same time, the clock signal CLK input from the outside of the source signal line driver circuit is input to the first analog switch 1811 from the input terminal (IN). Second analog switch 18
12, a constant potential (fixed potential) is applied from the input terminal (IN).

Signals output from the output terminals (OUT) of the first and second analog switches 1811 and 1812 are both output from the output terminal (OUT) of the clock signal control circuit 106.

A selection signal selects whether a clock signal is input to the shift register 102-1 or a constant potential (fixed potential) is applied.

  The clock signal control circuit is not limited to the configuration shown in FIG.

In addition, a present Example can be implemented combining freely with Examples 1-3.

(Example 5)
In this example, a detailed structure of a source signal line driver circuit included in the light-emitting device described in Embodiment Mode 3 will be described. FIG. 19 shows a circuit diagram of the source signal line driving circuit of this embodiment. In addition, the same thing as what was shown in FIG. 1 is shown with the same code | symbol.

Reference numeral 102-1 denotes a shift register, in which the clock signal (CLK), the signal (CLKB) in which the polarity of the clock signal is inverted, the start pulse signal (SP), and the bidirectional switching signal (SL / R) are shown in the diagram. Each is input from.

Reference numeral 102-2 denotes a latch (A), and reference numeral 102-3 denotes a latch (B). In this embodiment, one set of latches (A) 102-2 and one set of latches (B) 102-3 correspond to four source signal lines. However, in this embodiment, the number of source signal lines corresponding to one set of latches (A) 102-2 and one set of latches (B) 102-3 is not limited to this. In this embodiment, the level shift for changing the amplitude range of the voltage of the signal is not provided. However, the designer may appropriately provide it.

Digital video signals (DV) input from outside the source signal line driver circuit
Is input to the latch (A) 102-2 from the wiring shown in the drawing. Latch signal S_
A signal S_LATb in which the polarities of LAT and S_LAT are inverted is input to the latch (B) 102-3 from the wiring shown in the drawing.

The detailed configuration of the latch (A) 102-2 is the same as that shown in FIG.

Reference numeral 107 denotes a timing signal control circuit, which can supply a constant potential (fixed potential) to the latch (A) 102-2 instead of a timing signal for a fixed period.

Specifically, digital video signals of lower bits from the 1st to mth bits are latched (
A) Only the timing signal for writing to 102-2 is latched (A) 102-2
So that a constant potential (fixed potential) is applied to the latch (A) 102-2 instead of the timing signal output from the shift register 102-1 by the timing signal control circuit 107 for a certain period. . Therefore, of the n bits of the digital video signal input from the outside of the source signal line driver circuit 102, (m +
1) Only the high-order digital video signals from the bit to the n-th bit can be written to the latch (A) 102-2.

Note that the configuration of the timing signal control circuit 107 of this embodiment is shown in FIGS.
Therefore, the fourth embodiment is referred to for a detailed description of the configuration of the timing signal control circuit 107. However, in this embodiment, FIGS. 18 (A) and 18 (B)
The timing signal from the shift register 102-1 is input to the input terminal (IN) of the circuit shown in FIG. The output terminals (OUT) of the circuit shown in FIGS.
) Is input to the latch (A) 102-2. The selection signal selects whether a timing signal is input to the latch (A) 102-2 or a constant potential (fixed potential) is applied.

  The timing signal control circuit is not limited to the configuration shown in FIG.

In addition, a present Example can be implemented combining freely with Examples 1-3.

(Example 6)
In this example, a detailed structure of a source signal line driver circuit included in the light-emitting device described in Embodiment Mode 4 will be described. FIG. 20 shows a circuit diagram of the source signal line driving circuit of this embodiment. In addition, the same thing as what was shown in FIG. 1 is shown with the same code | symbol.

Reference numeral 102-1 denotes a shift register, in which the clock signal (CLK), the signal (CLKB) in which the polarity of the clock signal is inverted, the start pulse signal (SP), and the bidirectional switching signal (SL / R) are shown in the diagram. Each is input from.

Reference numeral 102-2 denotes a latch (A), and reference numeral 102-3 denotes a latch (B). In this embodiment, one set of latches (A) 102-2 and one set of latches (B) 102-3 correspond to four source signal lines. However, in this embodiment, the number of source signal lines corresponding to one set of latches (A) 102-2 and one set of latches (B) 102-3 is not limited to this. In this embodiment, the level shift for changing the amplitude range of the voltage of the signal is not provided. However, the designer may appropriately provide it.

Digital video signals (DV) input from outside the source signal line driver circuit
Is input to the latch (A) 102-2 from the wiring shown in the drawing. Latch signal S_
A signal S_LATb in which the polarities of LAT and S_LAT are inverted is input to the latch (B) 102-3 from the wiring shown in the drawing.

The detailed configuration of the latch (A) 102-2 is the same as that shown in FIG.

Reference numeral 108 denotes a start pulse signal control circuit, which can supply a constant potential (fixed potential) to the shift register 102-1 instead of the start pulse signal (SP) for a certain period.

Specifically, only the timing signal for writing the low-order bit digital video signals from the 1st to m-th bits into the latch (A) 102-2 is latched (A) 102-.
2, a constant potential (fixed potential) is applied instead of the start pulse signal by the start pulse signal control circuit 108 for a certain period so as not to input to the shift register 102
−1. Therefore, of the digital video signal n bits input from the outside of the source signal line driver circuit 102, only the higher-order digital video signal from the (m + 1) th bit to the nth bit is written to the latch (A) 102-2. Can do.

Note that the configuration of the start pulse signal control circuit 108 of this embodiment is shown in FIG.
Since it is the same as that shown in B), the fourth embodiment is referred to for a detailed description of the configuration of the start pulse signal control circuit 108. However, in this embodiment, FIG.
) A start pulse signal is input to the input terminal (IN) of the circuit shown in (B).
A signal output from the output terminal (OUT) of the circuit illustrated in FIGS. 18A and 18B is input to the shift register 102-1. The selection signal selects whether a start pulse signal is input to the shift register 102-1 or a constant potential (fixed potential) is applied.

  The timing signal control circuit is not limited to the configuration shown in FIG.

In addition, a present Example can be implemented combining freely with Examples 1-3.

(Example 7)
In this example, an example of the third configuration of the present invention that is different from the configuration shown in Embodiment Mode 5 will be described with reference to FIG. In FIG. 21, the same components as those shown in FIG.

501 is a power supply line, 502 is a buffer amplifier (buffer amplifier), 503
Is a light emitting element for monitoring, 504 is a constant current source, and 505 is an adding circuit. One electrode of the monitor light emitting element 503 is connected to a constant current source 504, and a constant current always flows through the monitor light emitting element 503. When the temperature of the organic compound layer of the light emitting element changes, the magnitude of the current flowing through the monitoring light emitting element 503 does not change, but the monitoring light emitting element 5 connected to the constant current source 504 is changed.
The potential of the electrode 03 changes.

On the other hand, the buffer amplifier 502 has two input terminals and one output terminal. One of the two input terminals is a non-inverting input terminal (+) and the other is an inverting input terminal (−). The potential of one electrode of the monitoring light emitting element 503 is applied to the non-inverting input terminal of the buffer amplifier 502.

The buffer amplifier is a circuit that prevents the potential of the electrode of the monitor light emitting element 503 connected to the constant current source 504 from changing due to a load such as a wiring capacity of the power supply line 501. Therefore, the potential applied to the non-inverting input terminal of the buffer amplifier 502 is output from the output terminal without being changed by a load such as the wiring capacity of the power supply line 501 or the addition circuit 505 and is applied to the addition circuit 505.

The potential of the output terminal of the buffer amplifier 502 applied to the adder circuit 505 is applied to the power supply line 501 as a power supply potential after a certain potential difference is added or subtracted.

FIG. 22 shows a detailed circuit diagram of the adder circuit of this embodiment. The adder circuit 505 includes a first resistor 521, a second resistor 522, an adder circuit power supply 525, and a non-inverting amplifier circuit 520. The non-inverting amplifier circuit 520 includes a third resistor 523, a fourth resistor 524, a non-inverting amplifier circuit power source 526, and an amplifier 527.

One terminal of the first resistor 521 is an input terminal (IN) of the adder circuit. The other terminal of the first resistor 521 is connected to one terminal of the second resistor 522. The other terminal of the second resistor 522 is connected to the adding circuit power source 525. An output from between the first resistor 521 and the second resistor 522 is input to the non-inverting input terminal (+) of the amplifier 527 of the non-inverting amplifier circuit 520.

One terminal of the third resistor 523 is connected to the output terminal of the amplifier 527, and the third resistor 52
The other terminal of 3 is connected to the inverting input terminal of the amplifier 527. An output from between the third resistor 523 and the inverting input terminal of the amplifier 527 is input to one terminal of the fourth resistor 524. The other terminal of the fourth resistor 524 is connected to the non-inverting amplifier circuit power source 526. An output from between the third resistor 523 and the output terminal of the amplifier 527 is output from the output terminal (OUT) of the adder circuit 505.

With the above structure, the power supply potential changes so that a constant current flows through the light emitting element even when the temperature of the organic compound layer of the light emitting element for monitoring 503 or the light emitting element of the pixel portion changes due to a change in environmental temperature. Therefore, even when the environmental temperature of the light emitting device rises, the power consumption of the light emitting device can be suppressed and the luminance of the light emitting element can be kept constant. Further, by providing the addition circuit 505, the potential of the power supply line 501 does not need to be the same as the potential of the electrode connected to the constant current source 504 of the monitor light emitting element 503. Therefore, the magnitude of current flowing through the buffer amplifier 502, the monitor light emitting element 503, and the constant current source 504 can be suppressed, and as a result, power consumption can be suppressed.

  The adding circuit 505 is not limited to the configuration shown in FIG.

In addition, this embodiment can be implemented in combination with Embodiments 1 to 6.

(Example 8)
In this embodiment, the TFT (n) of the pixel portion and the driving circuit around the pixel portion on the same substrate.
A method for simultaneously manufacturing a channel type TFT and a p-channel type TFT will be described in detail.

First, as shown in FIG. 23A, Corning # 7059 glass or # 17
A base film 401 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film over a substrate 400 made of glass such as barium borosilicate glass or alumino borosilicate glass typified by 37 glass. Form. For example, a silicon oxynitride film formed from SiH ₄ , NH ₃ , and N ₂ O by plasma CVD is formed to a thickness of 10 to 200 nm (preferably 50 to 100 nm), and similarly oxidized from SiH ₄ and N ₂ O. 50 to 200 nm of hydrogenated silicon nitride film
The layers are formed to have a thickness (preferably 100 to 150 nm). Note that in FIG. 23A, the base film is shown as one layer. In this embodiment, the base film 401 is shown as a two-layer structure;

The semiconductor layers 402 to 405 are formed using a crystalline semiconductor film in which a semiconductor film having an amorphous structure is formed using a laser crystallization method or a known thermal crystallization method. The semiconductor layers 402 to 405 are formed to a thickness of 25 to 80 nm (preferably 30 to 60 nm). There is no limitation on the material of the crystalline semiconductor film, but the crystalline semiconductor film is preferably formed of silicon or a silicon germanium (SiGe) alloy.

Known crystallization methods include a thermal crystallization method using an electric furnace, a laser annealing crystallization method using laser light, a lamp annealing crystallization method using infrared light, and a crystallization method using a catalytic metal. is there.

In order to manufacture a crystalline semiconductor film by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, YAG laser, or YVO ₄ laser is used. When these lasers are used, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. The conditions for crystallization are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 300 Hz and the laser energy density is 100 to 400 mJ / cm ² (typically 200 to 300 mJ / cm ^2). ). When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is 30 to 300 kHz, and the laser energy density is preferably 300 to 600 mJ / cm ² (typically 350 to 500 mJ / cm ² ). Then, a laser beam condensed in a linear shape with a width of 100 to 1000 μm, for example, 400 μm is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser beam at this time is set to 50 to 90%.

Next, a gate insulating film 406 that covers the semiconductor layers 402 to 405 is formed. The gate insulating film 406 is formed by plasma CVD or sputtering, and has a thickness of 40-15.
The insulating film containing silicon is formed to have a thickness of 0 nm. In this embodiment, a silicon oxynitride film is formed with a thickness of 120 nm. Needless to say, the gate insulating film 406 is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when using a silicon oxide film,
TEOS (Tetraethyl Orthosilicate) and O ₂ are mixed by plasma CVD,
It can be formed by discharging at a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm ² . The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.

Then, the first conductive film 4 for forming a gate electrode on the gate insulating film 406 is formed.
07 and a second conductive film 408 are formed. In this embodiment, the first conductive film 407 is made of Ta to a thickness of 50 to 100 nm, and the second conductive film 408 is made of W to 100 to 3 nm.
It is formed to a thickness of 00 nm.

The Ta film is formed by sputtering, and a Ta target is sputtered with Ar. In this case, when an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relieved and peeling of the film can be prevented. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used as a gate electrode, but the resistivity of the β-phase Ta film is 180 μΩcm.
This is not suitable for a gate electrode. In order to form an α-phase Ta film, tantalum nitride having a crystal structure close to Ta's α-phase is formed on a Ta base with a thickness of about 10 to 50 nm, so that an α-phase Ta film can be easily obtained. be able to.

When forming a W film, it is formed by sputtering using W as a target. In addition, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and the resistivity of the W film is desirably 20 μΩcm or less. The resistivity of the W film can be reduced by increasing the crystal grains. However, when there are many impurity elements such as oxygen in the W film, the crystallization is hindered and the resistance is increased. Therefore, when sputtering is used, a W target having a purity of 99.99% or 99.9999% is used, and a W film is formed with sufficient consideration so that impurities are not mixed in the gas phase during film formation. Thus, a resistivity of 9 to 20 μΩcm can be realized.

In this embodiment, the first conductive film 407 is Ta and the second conductive film 408 is W. However, the present invention is not particularly limited, and any of these is selected from Ta, W, Ti, Mo, Al, and Cu. You may form with an element or the alloy material or compound material which has the said element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. An example of another combination other than the present embodiment is the first
A combination of forming the first conductive film with tantalum nitride (TaN) and forming the second conductive film with Al. It is preferable that the first conductive film is formed using tantalum nitride (TaN) and the second conductive film is formed using Cu. (FIG. 23 (B))

Next, resist masks 409 to 412 are formed, and a first etching process is performed to form electrodes and wirings. In this embodiment, ICP (Inductively Coup
led Plasma: Inductively coupled plasma) Etching method and etching gas C
F ₄ and Cl ₂ are mixed, and 500 W RF (13.56 MHz) is applied to the coil type electrode at a pressure of 1 Pa.
) Power is applied to generate plasma. 100 on the substrate side (sample stage)
Apply RF (13.56 MHz) power of W and apply a substantially negative self-bias voltage. When CF ₄ and Cl ₂ are mixed, the W film and the Ta film are etched to the same extent.

Although not shown in FIG. 23C, the first conductive layer and the second conductive layer are formed by the effect of the bias voltage applied to the substrate side by making the shape of the resist mask suitable under the above etching conditions. The end portion of the conductive layer is tapered.
The angle of the tapered portion is 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%. Selectivity ratio of silicon oxynitride film to W film is 2-4 (typically 3)
Therefore, the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 nm by the over-etching process. Although not shown in FIG. 23C, the gate insulating film 406 is thinned by etching about 20 to 50 nm in a region not covered with the first shape conductive layers 414 to 417 by the etching.

Thus, the first shape conductive layers 414 to 417 (first conductive layers 414 a to 417 a and second conductive layers 414 b to 417 b) composed of the first conductive layer and the second conductive layer by the first etching treatment. Form.

Next, a second etching process is performed as shown in FIG. Similarly ICP
Using an etching method, CF ₄ , Cl _2, and O ₂ are mixed in an etching gas, and 500 W of RF power (13.56 MHz) is supplied to a coil-type electrode at a pressure of 1 Pa to generate plasma. 50 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a lower self-bias voltage is applied than in the first etching process. Under such conditions, the W film is anisotropically etched, and Ta, which is the first conductive layer, is anisotropically etched at a slower etching rate to form the second shape conductive layers 419 to 42.
2 (first conductive layers 419a to 422a and second conductive layers 419b to 422b) are formed. Although not shown in FIG. 23D, the gate insulating film 406 is thinned by further etching about 20 to 50 nm in a region not covered with the second shape conductive layers 419 to 422 by the above etching.

The etching reaction of the W film or Ta film with the mixed gas of CF ₄ and Cl ₂ can be estimated from the generated radical or ion species and the vapor pressure of the reaction product. When the vapor pressures of W and Ta fluorides and chlorides are compared, WF ₆ which is a fluoride of W is extremely high, and other WCl ₅ , TaF ₅ and TaCl ₅ are similar. Therefore, C
Both the W film and the Ta film are etched with a mixed gas of F ₄ and Cl ₂ . However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂ react to form CO and F, and a large amount of F radicals or F ions are generated. As a result, W has a high vapor pressure of fluoride.
The etching rate of the film is increased. On the other hand, the increase in etching rate of Ta is relatively small even when F increases. Further, since Ta is more easily oxidized than W, the surface of Ta is oxidized by adding O ₂ . Since the Ta oxide does not react with fluorine or chlorine, the etching rate of the Ta film further decreases. Therefore, it is possible to make a difference in the etching rate between the W film and the Ta film, and the etching rate of the W film can be made larger than that of the Ta film.

Then, the masks 409a to 412a are removed, and first doping treatment is performed as shown in FIG. 24A to add an impurity element imparting n-type conductivity. For example, the acceleration voltage is 70 to 120 keV, and the dose is 1 × 10 ¹³ / cm ² . Doping is performed using the second shape conductive layers 419 to 422 as masks against the impurity elements so that the impurity elements are also added to the lower regions of the second conductive layers 419 a to 422 a. Thus, first impurity regions 425 to 428 overlapping with the second conductive layers 419a to 422a and second impurity regions 429 to 432 having a higher impurity concentration than the first impurity regions are formed. Note that although the impurity element imparting n-type conductivity is added after removing the masks 409a to 412a in this embodiment, the present invention is not limited to this. In the step of FIG. 24A, the mask element 409a to the mask 412a may be removed after an impurity element imparting n-type conductivity is added.

Next, a mask 433 made of a resist is formed over the semiconductor layer 404 so as to cover the second conductive layers 421a and 421b. The mask 433 partially overlaps with the second impurity region 431 with the gate insulating film 406 interposed therebetween. Then, an impurity element imparting n-type is added by performing a second doping process. In this case, an impurity element imparting n-type conductivity is doped as a condition of a low acceleration voltage by raising the dose amount compared to the first doping treatment. (FIG. 24B) The doping may be performed by ion doping or ion implantation. The condition of the ion doping method is that the dose is 1 × 10 ¹³ to
5 × 10 ¹⁴ atoms / cm ² and an acceleration voltage of 60 to 100 keV. As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but phosphorus (P) is used. In this case, the second shape conductive layers 419 to 422 serve as a mask for the impurity element imparting n-type, and source regions 434 to 437, drain regions 438 to 441, and Lov regions 442 to 445 are formed in a self-aligned manner. . Further, a Loff region 446 is formed by the mask 433. The source regions 434 to 437 and the drain regions 438 to 441 have 1 ×
An impurity element imparting n-type conductivity is added in a concentration range of 10 ²⁰ to 1 × 10 ²¹ atomic / cm ³ .

In this embodiment, the length of the Loff region 446 can be freely set by controlling the size of the mask 433.

Note that in this specification, an LDD region overlapping with a gate electrode through a gate insulating film is referred to as a Lov region. LDD that does not overlap the gate electrode through the gate insulating film
The region is called a Loff region.

An impurity element imparting n-type conductivity is 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atoms / cm in the Loff region.
The concentration is ^{3 and} the concentration is 1 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ³ in the Lov region.

Note that in FIG. 24B, before or after doping the impurity element imparting n-type under the above-described conditions, the acceleration voltage is set to 70 to 120 keV and the n-type is changed with the mask 433 formed over the semiconductor layer 404. An impurity element to be added may be doped. Impurities imparting the n-type of the portions 442 and 443 that serve as the Lov regions of the TFTs used in the driver circuit while suppressing the concentration of the impurity element that imparts the n-type of the portion 446 serving as the Loff region of the switching TFT by the above process. The concentration of the element can be increased. A portion 44 to be a Loff region of the switching TFT
By suppressing the concentration of the impurity element imparting n-type 6, it is possible to propose an off-current of the switching TFT. In addition, by increasing the concentration of an impurity element imparting n-type conductivity in the portion 443 serving as the Lov region of the n-channel TFT used in the driver circuit, hot carriers generated by a high electric field near the drain due to the hot carrier effect are deteriorated. Can be prevented.

After the mask 453 is removed, as shown in FIG. 24C, the semiconductor layers 402 and 405 for forming the p-channel TFT have source regions 447 and 448 having a conductivity type opposite to the one conductivity type, and drains. Regions 449 and 450 and Lov regions 451 and 4
52 is formed. Using the conductive layers 419 and 422 having the second shape as masks against the impurity element, impurity regions are formed in a self-aligning manner. At this time, the semiconductor layers 402 and 403 forming the n-channel TFT are entirely covered with a resist mask 453. Source regions 447 and 448 and drain regions 449 and 450;
Phosphorus is added to the Lov regions 451 and 452 at different concentrations, but they are formed by ion doping using diborane (B ₂ H ₆ ), and the impurity concentration in each region is 2 × 10 ^20. ˜2 × 10 ²¹ atoms / cm ³ .

Through the above steps, impurity regions (source region, drain region, Lov region, Loff region) are formed in each of the semiconductor layers 402 to 405. The second conductive layers 419 to 422 overlapping with the semiconductor layer function as gate electrodes.

Thus, for the purpose of controlling the conductivity type, a step of activating the impurity element added to each semiconductor layer is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 1pp
m or less, preferably in a nitrogen atmosphere of 0.1 ppm or less at 400 to 700 ° C., typically 500 to 600 ° C. In this embodiment, heat treatment is performed at 500 ° C. for 4 hours. However, when the wiring material used for 419 to 422 is weak against heat, activation is preferably performed after an interlayer insulating film (mainly composed of silicon) is formed in order to protect the wiring and the like.

Furthermore, in an atmosphere containing 3 to 100% hydrogen, 1 to 12 at 300 to 450 ° C.
A process of hydrogenating the semiconductor layer is performed by performing heat treatment for a period of time. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. Plasma hydrogenation (using hydrogen excited by plasma) as another means of hydrogenation
May be performed.

Next, the first interlayer insulating film 455 is formed from a silicon oxynitride film to 100 to 200 n.
It is formed with a thickness of m. (FIG. 25A) A second interlayer insulating film 458 made of an organic insulating material is formed thereon.

Then, the gate insulating film 406, the first interlayer insulating film 455, the second interlayer insulating film 4
58, a contact hole is formed, and the source region 4 is formed through the contact hole.
Source wirings 459 to 462 were formed so as to be in contact with 47, 435, 436, and 448. Similarly, drain wirings 463 to 465 in contact with the drain regions 449, 439, 440, and 450 are formed (FIG. 25B).

The gate insulating film 406, the first interlayer insulating film 455, and the second interlayer insulating film 45
When 8 is a SiO ₂ film or a SiON film, the contact hole is preferably formed by dry etching using CF ₄ and O ₂ . In addition, the gate insulating film 406, the first
When the interlayer insulating film 455 and the second interlayer insulating film 458 are organic resin films, contact holes are preferably formed by dry etching using CHF ₃ or BHF (buffered hydrofluoric acid: HF + NH ₄ F). In the case where the gate insulating film 406, the first interlayer insulating film 455, and the second interlayer insulating film 458 are formed using different materials, it is preferable to change the etching method and the type of etchant or etching gas used for each film. However, the contact hole may be formed by using the same etching method and the same etchant and etching gas.

Next, a third interlayer insulating film 467 made of an organic resin is formed. As the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used. In particular, since the third interlayer insulating film 467 has a strong meaning of planarization,
Acrylic having excellent flatness is preferred. In this embodiment, the acrylic film is formed with a film thickness that can sufficiently flatten the step formed by the TFT. Preferably 1-5 μm (
More preferably, the thickness may be 2 to 4 μm.

Next, a contact hole reaching the drain wiring 465 is formed in the third interlayer insulating film 467, and a pixel electrode 468 is formed. In this example, indium tin oxide (I
(TO) film is formed to a thickness of 110 nm, and patterning is performed to form a pixel electrode 468. Alternatively, a transparent conductive film in which 2 to 20% zinc oxide (ZnO) is mixed with indium oxide may be used. This pixel electrode 468 becomes the anode of the light emitting element. (Fig. 25 (C))

Next, a first bank 469 and a second bank 470 made of a resin material are formed. The first bank 469 and the second bank 470 are provided to separate an organic compound layer and a cathode to be formed later between adjacent pixels. Therefore, it is desirable that the second bank 470 protrude laterally than the first bank 469. First
The total thickness of the bank 469 and the second bank 470 is preferably about 1 to 2 μm. However, if the organic compound layer and the cathode to be formed later can be separated between adjacent pixels, this thickness is set. Not exclusively. The first bank 469 and the second bank 470 need to be formed of an insulating film, and can be formed of an oxide, a resin, or the like, for example. The first bank 469 and the second bank 470 may be formed of the same material or different materials. First
The bank 469 and the second bank 470 are formed in a stripe shape between pixels. The first bank 469 and the second bank 470 may be formed along the source wiring (source signal line) or may be formed along the gate wiring (gate signal line). Note that the first bank 469 and the second bank 470 may be formed of a resin mixed with a pigment or the like. (FIG. 26 (A))

Next, the organic compound layer 471 and the cathode (MgAg electrode) 472 are continuously formed using a vacuum deposition method without being released to the atmosphere. Note that the thickness of the organic compound layer 471 is 80.
0 to 200 nm (typically 100 to 120 nm), the thickness of the cathode 472 is 180
It may be set to ˜300 nm (typically 200 to 250 nm). Although only one pixel is shown in this embodiment, an organic compound layer that emits red light, an organic compound layer that emits green light, and an organic compound layer that emits blue light are formed at the same time. Note that a part of the material for forming the organic compound layer and the cathode is stacked over the bank 470, but these are not included in the organic compound layer 471 and the cathode 472 in this specification.

In this step, the organic compound layer 471 and the cathode 472 are sequentially formed for the pixel corresponding to red, the pixel corresponding to green, and the pixel corresponding to blue. However, since the organic compound layer 471 has poor resistance to a solution, it must be formed for each color individually without using a photolithography technique. Therefore, it is preferable to hide other than the desired pixels using a metal mask and selectively form the organic compound layer 471 and the cathode 472 only at necessary portions.

That is, first, a mask that hides all pixels other than those corresponding to red is set, and an organic compound layer that emits red light is selectively formed using the mask. Next, a mask that hides all pixels other than those corresponding to green is set, and an organic compound layer that emits green light is selectively formed using the mask. Next, similarly, a mask for hiding all but the pixels corresponding to blue is set, and a blue light-emitting organic compound layer is selectively formed using the mask. Note that although all the different masks are described here, the same mask may be used. Moreover, it is preferable to process without breaking a vacuum until an organic compound layer and a cathode are formed on all pixels.

In this embodiment, the organic compound layer 471 has a single-layer structure composed of only a light emitting layer. The organic compound layer includes a hole transport layer, a hole injection layer, an electron transport layer, an electron injection layer, etc. in addition to the light emitting layer. You may have. As described above, various examples of combinations have already been reported, and any of the configurations may be used. A known material can be used for the organic compound layer 471. As the known material, an organic material is preferably used in consideration of the driving voltage of the light emitting element.

Next, a cathode 472 is formed. In this embodiment, an example in which an MgAg electrode is used as a cathode of a light emitting element is shown, but other known materials can be used.

Thus, an active matrix substrate having a structure as shown in FIG. 26B is completed. Note that the processes from the formation of the first bank 469 and the second bank 470 to the formation of the cathode 472 are continuously performed using a multi-chamber type (or in-line type) thin film forming apparatus without releasing the atmosphere. It is effective to do.

In this embodiment, the semiconductor layer of the switching TFT 501 is the source region 5.
04, a drain region 505, a Loff region 506, a Lov region 507, and a channel formation region 508. The Loff region 506 is provided so as not to overlap with the gate electrode 421 with the gate insulating film 406 interposed therebetween. Also, the Lov area 507
Is provided so as to overlap with the gate electrode 421 with the gate insulating film 406 interposed therebetween. Such a structure is very effective in reducing off current.

In this embodiment, the switching TFT 501 has a single gate structure. However, in the present invention, the switching TFT may have a double gate structure or another multi-gate structure. The double gate structure has a structure in which two TFTs are substantially connected in series, and there is an advantage that the off-current can be further reduced.

In this embodiment, the switching TFT 501 is an n-channel TFT, but may be a p-channel TFT.

The semiconductor layer of the current control TFT 502 includes a source region 510 and a drain region 51.
1, a Lov region 512, and a channel formation region 513. Lov area 51
2 is provided so as to overlap the gate electrode 422 with the gate insulating film 406 interposed therebetween. In this embodiment, the current control TFT 502 does not have a Loff region, but may have a structure having a Loff region.

In this embodiment, the current control TFT 502 is a p-channel TFT.
A channel type TFT may also be used.

Note that the active matrix substrate of this embodiment can exhibit extremely high reliability and improve operating characteristics by arranging TFTs having an optimal structure not only in the pixel portion but also in the drive circuit portion.

First, a TFT having a structure for reducing hot carrier injection so as not to reduce the operating speed as much as possible is replaced with an n-channel TFT 5 of a CMOS circuit forming a drive circuit portion.
Used as 03. Note that the drive circuit here includes a shift register, a buffer, a level shifter, a sampling circuit (sample and hold circuit), and the like. In the case of performing digital driving, a signal conversion circuit such as a D / A converter may be included.

In this embodiment, the semiconductor layer of the n-channel TFT 503 of the CMOS circuit includes a source region 521, a drain region 522, a Lov region 523, and a channel formation region 524.

In this embodiment, the semiconductor layer of the p-channel TFT 504 of the CMOS circuit includes a source region 531, a drain region 532, a Lov region 533, and a channel formation region 534.

In fact, when completed up to FIG. 26 (B), a protective film (laminate film, ultraviolet curable resin film, etc.) or a light-transmitting sealing material that is highly airtight and less degassed so as not to be exposed to the outside air. It is preferable to package (enclose). At that time, if the inside of the sealing material is made an inert atmosphere or a hygroscopic material (for example, barium oxide) is arranged inside, the reliability of the light emitting element is improved.

In addition, when the airtightness is improved by processing such as packaging, a connector (flexible printed circuit: FPC) for connecting the terminal routed from the element or circuit formed on the substrate and the external signal terminal is attached. Completed as a product. In this specification, such a state that can be shipped is referred to as a light emitting device.

As described above, since the length of the gate electrode in the channel length direction (hereinafter simply referred to as the width of the gate electrode) is different in the manufacturing process of this embodiment, ion implantation is performed using the gate electrode as a mask. A semiconductor layer that is not located under the first gate electrode by using the difference in ion penetration depth due to the difference in electrode thickness to change the ion concentration in the semiconductor layer located under the first gate electrode. It is possible to make it lower than the ion concentration inside.

Further, since the Loff region is formed using the mask, only the width of the Lov region has to be controlled by etching, and the positions of the Loff region and the Lov region can be easily controlled.

In this embodiment, the example in which the light emitted from the organic compound layer is directed toward the substrate has been described. However, the present invention is not limited to this, and the light emitted from the organic compound layer is directed toward the substrate. It may be a simple configuration. In this case, it is desirable that the cathode of the light emitting element is a pixel electrode, and the current control TFT is an n-channel TFT.

In this embodiment, the pixel has two Ts, a switching TFT and a current control TFT.
The case where it has FT was demonstrated. However, the present embodiment is not limited to this. Even when a pixel has three or more TFTs, this embodiment can be applied.

The manufacturing method of the light-emitting device of the present invention is not limited to the manufacturing method shown in this embodiment, and any other manufacturing method can be used.

In addition, this embodiment can be implemented by freely combining with Embodiments 1 to 7.

Example 9
A light-emitting device formed by implementing the present invention is a self-luminous type, so that it has excellent visibility in a bright place as compared with a liquid crystal display device and has a wide viewing angle. Therefore, it can be used for display portions of various electronic devices. For example, when viewing a TV broadcast or the like on a large screen, the light emitting device of the present invention is used as a display unit of a display device in which a light emitting device having a diagonal size of 30 inches or more (typically 40 inches or more) is incorporated in a housing. Good. The light emitting device of the present invention can be used as a display portion of various electronic devices.

Such an electronic device of the present invention includes a video camera, a digital camera, a goggle type display (head mounted display), a navigation system,
Sound playback device (car audio, audio component, etc.), notebook personal computer, game machine, portable information terminal (mobile computer, mobile phone, portable game machine, electronic book, etc.), image playback device (specific) Specifically, a device equipped with a display capable of reproducing a recording medium such as a digital video disc (DVD) and displaying the image thereof) may be used. In particular, a portable information terminal that is often viewed from an oblique direction emphasizes the wide viewing angle, and thus it is desirable to use a light emitting device. Specific examples of these electronic devices are shown in FIGS.

FIG. 27A shows a portable information terminal, 2701 is a display panel, and 2702 is an operation panel. The display panel 2701 and the operation panel 2702 are connected to the connection portion 2.
Connected at 703. In the connection portion 2703, the angle θ between the surface of the display panel 2701 on which the display portion 2704 is provided and the surface of the operation panel 2702 on which the operation key 2706 is provided can be arbitrarily changed.

The display panel 2701 has a display portion 2704. The portable information terminal shown in FIG. 27A has a function as a telephone, the display panel 2701 has an audio output unit 2705, and audio is output from the audio output unit 2705. The light emitting device of the present invention is used for the display portion 2704.

The operation panel 2702 has operation keys 2706, a power switch 2707, a voice input unit 2708, and a CCD light receiving unit 2709. Note that although the operation key 2706 and the power switch 2707 are provided separately in FIG. 27A, the operation key 2706 may include the power switch 2707.

The voice input unit 2707 inputs voice. An image input in the CCD light receiving unit 2709 is taken into the portable information terminal as electronic data.

In FIG. 27A, the display panel 2701 has an audio output unit 2705 and the operation panel has an audio input unit 2708; however, this embodiment is not limited to this configuration. The display panel 2701 may have a voice input unit 2708 and the operation panel may have a voice output unit 2705. Also, an audio output unit 2705 and an audio input unit 2
708 may be provided on the display panel 2701 or the audio output unit 2.
705 and the voice input unit 2708 may both be provided on the operation panel 2702.

Note that although the portable information terminal does not include an antenna in FIG. 27A, an antenna may be provided as necessary.

FIG. 27B illustrates a mobile phone, which includes a main body 2601, an audio output portion 2602, an audio input portion 2603, a display portion 2604, operation switches 2605, and an antenna 2606. The light-emitting device of the present invention can be used for the display portion 2604. Display unit 2
By displaying white characters on a black background 604, power consumption of the mobile phone can be suppressed.

Since the light-emitting device of the present invention can reduce power consumption, it is particularly effective for portable electronic devices.

FIG. 28A illustrates a display device including a light-emitting device, which includes a housing 2001 and a support base 20.
02, a display unit 2003, and the like. The light emitting device of the present invention can be used for the display portion 2003. Since the light-emitting device is a self-luminous type, a backlight is not necessary and a display portion thinner than a liquid crystal display device can be obtained.

FIG. 28B illustrates a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, an image receiving portion 2106, and the like. The light emitting device of the present invention can be used for the display portion 2102.

FIG. 28C shows a part of the head-mounted electronic device (on the right side).
01, signal cable 2202, head fixing band 2203, screen portion 2204
, An optical system 2205, a display unit 2206, and the like. The light emitting device of the present invention includes the display unit 220.
6 can be used.

FIG. 28D shows an image reproducing apparatus (specifically, a DVD reproducing apparatus) provided with a recording medium.
A main body 2301, a recording medium (DVD or the like) 2302, and an operation switch 2303.
, Display unit (a) 2304, display unit (b) 2305, and the like. Display unit (a) 230
Reference numeral 4 mainly displays image information, and the display unit (b) 2305 mainly displays character information. The light emitting device of the present invention has these display units (a), (b) 2304, 2305.
Can be used. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.

FIG. 28E illustrates a goggle type display (head mounted display), which includes a main body 2401, a display portion 2402, and an arm portion 2403. The light emitting device of the present invention can be used for the display portion 2402.

FIG. 28F illustrates a personal computer, which includes a main body 2501 and a housing 2502.
, A display portion 2503, a keyboard 2504, and the like. The light emitting device of the present invention has a display unit 2
503 can be used.

If the emission luminance of the organic material is increased in the future, the light including the output image information can be enlarged and projected by a lens or the like and used for a front type or rear type projector.

In addition, the electronic devices often display information distributed through electronic communication lines such as the Internet and CATV (cable television), and in particular, opportunities to display moving image information are increasing. Since the response speed of the organic material is very high, the light-emitting device is preferable for displaying moving images.

In addition, since the light emitting device consumes power in the light emitting portion, it is desirable to display information so that the light emitting portion is minimized. Therefore, when a light emitting device is used for a display unit mainly including character information, such as a portable information terminal, particularly a mobile phone or a sound reproduction device, it is driven so that character information is formed by the light emitting part with the non-light emitting part as the background It is desirable to do.

As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields. In addition, this embodiment can be implemented in combination with Embodiments 1-8.

(Example 10)
In the present embodiment, a more specific configuration of the third configuration of the present invention and a change in luminance due to temperature will be described based on actually measured values.

FIG. 29A shows a connection state of a monitor light-emitting element included in the light-emitting device of this example. Reference numeral 701 denotes a power supply line, 702 denotes a buffer amplifier, 703 denotes a light emitting element for monitoring, 704 denotes a constant current source, and 705 denotes one of the light emitting elements in the pixel portion.

Note that FIG. 29 illustrates the case where the driving TFT in the pixel portion is in an on state, and the driving TFT is not illustrated, and the pixel electrode of the light emitting element 705 in the pixel portion, the power supply line 701, and the like. Are connected directly.

In FIG. 29A, the anode of the light-emitting element 705 in the pixel portion is used as a pixel electrode; however, this embodiment is not limited to this structure. The cathode may be used as the pixel electrode.

The constant current source 704 of this embodiment includes an amplifier, a variable resistor, and a bipolar transistor. V1 and V2 mean application of a predetermined voltage, and satisfies the relationship of voltage <V2 <V1 applied to the anode. Note that the relationship between the voltage applied to the anode and V2 and V1 varies depending on whether an anode or a cathode is used for the pixel electrode. The relationship between the voltage applied to the anode, V2, and V1 is set as appropriate so that a forward bias current flows through the light emitting element. Further, the constant current source 704 is the same as that shown in FIG.
It is not limited to the structure shown to 9 (A), A well-known constant current source can be used.

The output terminal of the constant current source 704 is connected to the pixel electrode of the monitor light emitting element 703. Note that when the anode is used as the pixel electrode in the light-emitting element 705 of the pixel portion, the anode is also used as the pixel electrode in the monitor light-emitting element 703. Conversely, when the cathode is used as the pixel electrode in the light emitting element 705 in the pixel portion, the cathode is also used as the pixel electrode in the monitor light emitting element 703. FIG. 29 (A)
Then, in the monitor light emitting element 703, the anode is used as the pixel electrode.

By connecting the output terminal of the constant current source 704 to the pixel electrode of the monitor light emitting element 703, when a current flows through the monitor light emitting element 703, the value is always kept constant. In addition, when the temperature of the organic compound layer included in the light emitting element changes, the pixel electrode of the monitoring light emitting element 703 connected to the constant current source 704 is not changed, although the magnitude of the current flowing through the monitoring light emitting element 703 does not change. The potential of changes.

On the other hand, the buffer amplifier 702 has two input terminals and one output terminal. One of the two input terminals is a non-inverting input terminal (+) and the other is an inverting input terminal (−). The potential of the pixel electrode of the monitor light emitting element 703 is supplied to the non-inverting input terminal of the buffer amplifier 702.

The buffer amplifier 702 includes the monitor light emitting element 7 connected to the constant current source 704.
This is a circuit that prevents the potential of the pixel electrode 03 from being changed by a load such as a wiring capacity of the power supply line 701. Therefore, the potential applied to the non-inverting input terminal of the buffer amplifier 702 is output from the output terminal without being changed by a load such as the wiring capacity of the power supply line 701 and is applied to the pixel electrode of the light emitting element 705 in the pixel portion. Therefore, the current flowing through the monitoring light emitting element 703 is equal to the current flowing through the light emitting element 705 in the pixel portion.

Even if the temperature of the organic compound layer of the monitor light emitting element 703 or the light emitting element 705 in the pixel portion is changed due to the change in environmental temperature, a constant current flows through each light emitting element. Therefore, increase in power consumption of the light emitting device can be suppressed even if the environmental temperature of the light emitting device is increased.

The light-emitting element 70 in the pixel portion included in the light-emitting device having the structure illustrated in FIG.
FIG. 29B shows the measured value of the change in luminance due to temperature in FIG. The graph with correction is the measured value of the light emitting device of the present invention, and the graph without correction is the third value of the present invention.
It is the measured value of the light-emitting device which does not have the structure of.

As is clear from FIG. 29A, in the graph without correction, the luminance increases as the temperature increases. However, in the corrected graph, the brightness is kept almost constant even when the temperature rises. Since the current and the luminance are in a proportional relationship, it can be seen that the light emitting device of the present invention can keep the current constant even when the temperature rises and can suppress power consumption.

Moreover, although the light emitting element causes a decrease in luminance due to deterioration of the organic light emitting layer,
Even with the same degree of deterioration, the brightness decrease is smaller when the current flowing between the cathode and the anode is kept constant than when the voltage applied between the cathode and the anode is kept constant. Therefore, since the light-emitting device of the present invention can keep the current flowing through the light-emitting element constant, it can be said that a reduction in luminance due to deterioration can be suppressed.

The present embodiment can be implemented by freely combining with the configurations of the first to ninth embodiments.

1 is a block diagram of a light emitting device of the present invention. 1 is a block diagram of a light emitting device of the present invention. 1 is a block diagram of a light emitting device of the present invention. 1 is a block diagram of a light emitting device of the present invention. FIG. 6 shows a state of connection between a power supply line of a light emitting device of the present invention and a monitor light emitting element. FIG. 9 illustrates a pixel portion of a light-emitting device of the present invention. FIG. 3 is an enlarged view of a pixel of the light emitting device of the present invention. 4A and 4B illustrate a driving method of a light-emitting device of the present invention. 1 is a block diagram of a light emitting device of the present invention. FIG. 9 illustrates a pixel portion of a light-emitting device of the present invention. FIG. 3 is an enlarged view of a pixel of the light emitting device of the present invention. 4A and 4B illustrate a driving method of a light-emitting device of the present invention. 3 is a circuit diagram of a source signal line driver circuit of a light emitting device of the present invention. FIG. The top view of a part of latch (A). The circuit diagram of a switching circuit. The equivalent circuit diagram of an analog switch. 3 is a circuit diagram of a source signal line driver circuit of a light emitting device of the present invention. FIG. The circuit diagram of a clock signal control circuit, a timing signal control circuit, and a start pulse signal control circuit. 3 is a circuit diagram of a source signal line driver circuit of a light emitting device of the present invention. FIG. 3 is a circuit diagram of a source signal line driver circuit of a light emitting device of the present invention. FIG. FIG. 6 shows a state of connection between a power supply line of a light emitting device of the present invention and a monitor light emitting element. The circuit diagram of an addition circuit. 4A and 4B illustrate a method for manufacturing a light-emitting device. 4A and 4B illustrate a method for manufacturing a light-emitting device. 4A and 4B illustrate a method for manufacturing a light-emitting device. 4A and 4B illustrate a method for manufacturing a light-emitting device. FIG. 14 is a diagram of an electronic device using the light-emitting device of the present invention. FIG. 14 is a diagram of an electronic device using the light-emitting device of the present invention. 5A and 5B are a diagram illustrating a state of connection between a power supply line of a light emitting device of the present invention and a monitor light emitting element, and a graph illustrating luminance characteristics depending on the temperature of the light emitting element.

Claims (5)

A pixel portion having a plurality of pixels and a source signal line driver circuit;
Each of the plurality of pixels has a light emitting element having an anode, a cathode, and a layer containing an organic compound sandwiched between the anode and the cathode,
The source signal line driving circuit has a switching circuit,
The switching circuit includes an inverter, a first NAND, a second NAND, and a NOR,
The digital video signal is input to the first NAND through the inverter,
The digital video signal is input to the second NAND,
The switching signal is input to the first NAND,
A signal obtained by inverting the polarity of the switching signal is input to the second NAND,
The signal output from the first NAND and the signal output from the second NAND are input to the NOR,
The signal output from the NOR is input to the plurality of pixels,
When the average length of the light emitting periods of all the light emitting elements in one frame period is longer than half the maximum value of the length of the light emitting elements in one frame period, the switching circuit The polarity of the digital video signal is inverted, and the inverted digital video signal is input to the plurality of pixels,
When the average length of the light emitting periods of all the light emitting elements in one frame period is shorter than half the maximum value of the length of the light emitting elements in one frame period, the switching circuit The display device, wherein the digital video signal is input to the plurality of pixels without inverting the polarity of the digital video signal. A pixel portion having a plurality of pixels and a source signal line driver circuit;
Each of the plurality of pixels has a light emitting element having an anode, a cathode, and a layer containing an organic compound sandwiched between the anode and the cathode,
The source signal line driver circuit includes a shift register, a first latch, a second latch, and a switching circuit,
The output of the shift register and the input of the first latch are electrically connected,
An output of the first latch and an input of the second latch are electrically connected;
An output of the second latch and an input of the switching circuit are electrically connected;
The switching circuit includes an inverter, a first NAND, a second NAND, and a NOR,
The digital video signal output from the second latch is input to the first NAND through the inverter,
The digital video signal is input to the second NAND,
The switching signal is input to the first NAND,
A signal obtained by inverting the polarity of the switching signal is input to the second NAND,
The signal output from the first NAND and the signal output from the second NAND are input to the NOR,
The signal output from the NOR is input to the plurality of pixels,
When the average length of the light emitting periods of all the light emitting elements in one frame period is longer than half the maximum value of the length of the light emitting elements in one frame period, the switching circuit The polarity of the digital video signal is inverted, and the inverted digital video signal is input to the plurality of pixels,
When the average length of the light emitting periods of all the light emitting elements in one frame period is shorter than half the maximum value of the length of the light emitting elements in one frame period, the switching circuit The display device, wherein the digital video signal is input to the plurality of pixels without inverting the polarity of the digital video signal. In claim 1 or claim 2 ,
A constant current source;
A circuit that outputs a potential equal to the input potential;
Light emission for monitoring, which has two electrodes, and one of the two electrodes is electrically connected to the output of the constant current source and the input of a circuit that outputs a potential equal to the input potential Having an element,
The display device, wherein one of the anode and the cathode is electrically connected to an output of a circuit that outputs a potential equal to the input potential. In claim 1 or claim 2 ,
A constant current source;
A circuit that outputs a potential equal to the input potential;
Light emission for monitoring, which has two electrodes, and one of the two electrodes is electrically connected to the output of the constant current source and the input of a circuit that outputs a potential equal to the input potential Having an element,
The display device according to claim 1, wherein the light emitting element is provided with an output potential of a circuit that outputs a potential equal to the input potential to one of the anode and the cathode. In claim 3 or claim 4 ,
The display device, wherein the light emitting element for monitoring is formed on the same substrate as the substrate on which the pixel portion is formed.

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