JP2002324809A - Thin film transistor and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor consisting an inexpensive non-anneal glass as a substrate, having high reliability at a process temperature of less than 500 deg.C, and showing a superior characteristic. SOLUTION: In order to resolve the problem mentioned above, a mixed gas consisting of a ozone gas and H2 O, or N2 O is supplied at the processing temperature of less than 500 deg.C to a polycrystalline silicon film crystallized by a laser irradiation or a silicon oxide film with more than 4 nm in thickness on a surface of the polycrystalline silicon film by performing an ozone oxidation processing after processing using a solution such as ozone water or a NH3 hydrogen peroxide aqueous solution, etc. It is possible to manufacture the small thin film transistor on the non-anneal glass substrate with small characteristic change by performing the processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used for a liquid crystal display and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, in a liquid crystal display used as a display device of a notebook personal computer, a portable device, or the like, a driving system has been changed from a simple matrix system to an active matrix system. TFT: Thin Film Tra
The TFT active matrix driving method in which an nistor is formed is becoming mainstream. Among the TFT driving methods, a TFT using a polycrystalline silicon layer has a higher electron mobility than that of an amorphous silicon layer, so that not only a transistor in a display pixel portion but also a glass transistor as a driving transistor is used. It can be built on a substrate.

Conventionally, the formation of polycrystalline silicon is 1000
Since a high temperature of about ° C is required, an expensive quartz glass substrate must be used for the substrate. Recently, technology has been developed to form polycrystalline silicon at a process temperature of about 600 ° C., and glass materials other than quartz substrates can be used.
According to this method, only the amorphous silicon film can be heated and crystallized by irradiating the amorphous silicon film formed on the glass substrate with a laser without increasing the substrate temperature.

On the other hand, in an integrated circuit device using a single crystal silicon substrate, a thermal oxide film of silicon (thickness: several nm) is used.
数 10 nm) is used as a gate insulating film.
However, the formation of this thermal oxide film of silicon requires about 1
A heat treatment at 000 ° C. is required, and this process cannot be used for the above-described process of manufacturing a polycrystalline polysilicon TFT requiring a process temperature of 600 ° C. or less.

In a TFT manufacturing process, TEO is usually used.
Using S (Tetraethoxysilane) as a raw material, an SiO ₂ film (thickness: about 100 nm) formed by a plasma CVD method or the like is used as a gate insulating film. However, the SiO ₂ film (hereinafter referred to as a TEOS film) formed by the plasma CVD method has a high interface state density, and when used directly as a gate insulating film, TFT characteristics such as fluctuation in threshold voltage are remarkable. This will result in reduced performance. Furthermore, in such a case, TF
The breakdown voltage of T causes severe degradation over time, and as a result, dielectric breakdown of the TFT may occur. Therefore, at the interface between the TFT gate insulating film and the silicon layer,
It is desired to form an oxide film having a low interface state density comparable to a thermal oxide film formed by thermal oxidation of silicon.

In order to solve the above problem, for example, Japanese Patent Laid-Open No.
195494 discloses a method for manufacturing a polycrystalline silicon TFT using a normal high heat-resistant glass substrate at a process temperature of 600 ° C. or lower.

[0007]

The above-mentioned JP-A-8-1
According to Japanese Patent No. 95494, a polycrystalline silicon layer is formed at a temperature of about 600 ° C., so that usable glass substrates are limited to annealed glass substrates. Therefore, when an unannealed glass substrate is used instead of an annealed glass substrate, a temperature condition of about 600 ° C. causes shrinkage of the glass substrate, which causes warpage and distortion of the glass substrate, and in the worst case This causes inconveniences such as cracking of the glass substrate itself and film peeling. In general, the higher the strain point of glass, the higher the thermal stability, but the more difficult it is to melt, shape, and process in the glass substrate manufacturing process, and the higher the manufacturing cost. Therefore, in order to suppress the cost, a manufacturing method that has a low strain point and enables the use of inexpensive glass is essential.

Usually, the strain point of an alkali-free glass substrate used as a substrate of a thin film transistor is about 600 ° C., and the compaction (thermal shrinkage) of glass rapidly increases due to a thermal history slightly higher than the strain point. For example, Corning 7059 manufactured by Corning without annealing
F (strain point 593 ° C) is 600 ° C, 1 hour, cooling rate 1
There is about 800 ppm compaction due to the thermal history in ° C./min. Also, Corning 1735F with a high strain point (strain point 6
65 ° C.), the same thermal history as above adds 173
Shows compaction in ppm. And 660 ° C in advance
By performing the annealing treatment for / 1 hr, it is possible to reduce the compaction due to the same thermal history to about 10 ppm.

A substrate for a polycrystalline TFT panel usually has two
Since a heat shrinkage of 0 ppm or less is required, the use of an annealed glass substrate has been indispensable so far (supervised by Takashi Shimada, published by Science Forum: Liquid Crystal Display Manufacturing Technology Handbook, pp. 191-199). Therefore, the upper limit of the process temperature is simply set to a temperature at which shrinkage of the non-annealed glass substrate can be ignored, for example, 450 to 500.
When the temperature is lowered to ° C., the following problems occur.

That is, as a gate insulating layer formed on a polycrystalline silicon layer, generally, TEOS (Tetraethox) is used.
ysilane) as a source gas for plasma CVD (Chemical
SiO ₂ film (hereinafter referred to as T
EOS film) is formed with a thickness of about 100 nm. However, since the interface state density is large at the interface between the polycrystalline silicon layer and the insulating layer made of TEOS, TF
The threshold voltage as T tends to fluctuate, and the withstand voltage characteristics as the gate insulating layer significantly deteriorates with time.
There is a major problem in TFT reliability. Therefore, assuming that an unannealed glass substrate is used, the upper limit of the process temperature is set to about 450 to 500 ° C., and the interface state density between the polycrystalline silicon layer and the gate insulating layer is set to the silicon oxide layer by the thermal oxidation method. It is important to devise a similar reduction.

An object of the present invention is to solve the above-mentioned problems and to form a TFT using a highly reliable polycrystalline silicon layer on a non-annealed glass substrate under low-temperature process conditions. In the present invention, a glass substrate having a compaction of 30 ppm or more when the glass substrate is cooled at 1 ° C./min after heat treatment at 600 ° C. for 1 hour is defined as an unannealed glass substrate.

[0012]

According to the present invention, a polysilicon crystal layer for forming a channel region, a source region, and a drain region above an unannealed glass substrate is provided. And the second insulating layer are formed. And a gate electrode and a source electrode for electrically connecting a gate region on the second insulating layer at a position corresponding to the channel region and each of the gate region, the source region, and the drain region. A drain electrode was formed. At this time, the first insulating layer is a silicon oxide layer formed by oxidizing the surface of the channel region at a temperature of 500 ° C. or less, and is formed so as to cover at least the surface of the channel region. Was 4 nm or more.

Further, the present invention provides a method for oxidizing the surface of a polycrystalline silicon layer in an atmosphere containing at least ozone, an atmosphere containing ozone and H ₂ O, or an atmosphere containing ozone and N ₂ O. A silicon oxide layer, which is the first insulating layer, was formed. Furthermore, the present invention provides the first
Forming a first silicon oxide layer on the surface of the polycrystalline silicon layer using an oxygen-donating solution in the step of forming the first silicon layer and the polycrystalline silicon layer in an atmosphere containing ozone. A second silicon oxide layer was formed between the layers. In the present invention, the second insulating layer provided above the first insulating layer is formed using at least a chemical deposition method, a physical deposition method, or a spin coating method.

As described above, the surface of the polycrystalline silicon layer is oxidized in an ozone atmosphere containing H ₂ O or N ₂ O to form the silicon oxide layer. The interface can be kept in a good state. Moreover, since it is possible to form a silicon oxide film at a lower process temperature than before,
A relatively inexpensive non-annealed glass can be used as the substrate.

In other words, the thin film transistor manufactured by the above method has a good interface between the surface of the channel region made of polycrystalline silicon and the gate insulating layer formed thereon, so that the interface state there Since characteristics of a thin film transistor which is closely related to density, for example, fluctuation of a threshold voltage can be reduced, excellent TFT characteristics can be exhibited as a result. And
Since an unannealed glass substrate can be used as the substrate, it is possible to manufacture a TFT with a larger area and at lower cost than quartz glass or the like. In the above solution, the insulating layer has a two-layer structure. However, the insulating layer does not necessarily have to have a two-layer structure.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a structural diagram showing a cross section of a main part of a thin film transistor according to a first embodiment. On a diffusion prevention layer 2 formed on an unannealed glass substrate 1, a source region 8, a drain region 9, and a channel region 12 made of a polycrystalline silicon layer are formed. On the channel region 12, a gate insulating layer 6 composed of an SiO ₂ layer 6a formed by oxidizing a polycrystalline silicon layer and an insulating layer 6b formed by a deposition method is arranged. A gate region 7 is formed above gate insulating layer 6 at a position corresponding to channel region 12, and an interlayer insulating layer 10 is formed to cover a part of the surface of gate region 7. The source region 8, the drain region 9 and the gate region 7 are formed through openings provided in the interlayer insulating layer 10.
Are electrically connected by the respective electrodes 11.

Next, a method of manufacturing the structure shown in FIG. 1 will be described with reference to a process flow shown in FIG. First, a normal plasma CV is placed on an unannealed glass substrate 1.
D (Chemical Vapor Depositi
on) method, a diffusion preventing layer 2 made of a SiN film or a SiO ₂ film is formed. Thereafter, an amorphous silicon film 3 (film thickness: 50 nm) is formed by using the CVD method (FIG. 2A). Next, the surface of the amorphous silicon film 3 is irradiated with excimer laser light 5 to crystallize part or all of the amorphous silicon film 3 to obtain a polycrystalline silicon layer 4 (FIG. 2B). Since the excimer laser light 5 is absorbed by the amorphous silicon film 3 and is heated and crystallized, the non-annealed glass substrate 1 is not heated to 450 ° C. or more by the irradiation of the excimer laser light 5. In FIG. 2B, for the sake of convenience, the entire surface of the glass substrate 1 is illustrated as if it were irradiated with laser light. However, in practice, the excimer laser light 5 condensed in a strip shape is scanned so as to be scanned. Have been.

The surface of the polycrystalline silicon layer 4 thus formed is oxidized to form a silicon oxide layer 6a (first insulating layer) of 4 nm or more. Next, a silicon insulating layer 6b (second insulating layer) having a thickness of about 90 nm is formed using a deposition method such as CVD, and a gate insulating layer 6 having a total thickness of about 100 nm is formed (FIG. 2C). A gate region 7 is formed on the gate insulating layer 6 and processed into a desired shape (FIG. 2D). As a material for the gate region, a conductive material such as an impurity-doped silicon film, a metal, or a metal compound (TiN, TiW, or the like) is used.

Next, using the processed gate region 7 as a mask, impurity ions are implanted into the polycrystalline silicon layer 4 to form a source region 8 and a drain region 9, and then RTA (Rapid) for activating the impurity. Therma
l Annealing) treatment. In addition, this RT
Even in the process A, only the polycrystalline silicon layer 4 is heated, so that the temperature of the underlying unannealed glass substrate does not increase.

Next, the interlayer insulating layer 1 is formed on the gate insulating film 6 so as to cover the surface of the gate region 7 shown in FIG.
0, an opening for making electrical connection with the gate region 7, the source region 8, and the drain region 9 is formed at a predetermined position of the interlayer insulating layer 10, and the gate region 7 is formed through the opening. Then, each electrode 11 connected to the source region 8 and the drain region 9 is formed, and the thin film transistor shown in FIG. 1 is completed.

The thickness of the first insulating film shown in FIG. 2C will be described. FIG. 3 shows a thermal oxide film / TEOS
3 shows the relationship between the thickness of the thermal oxide film (first insulating film) and the flat band voltage in the MOS transistor having the two-layer gate insulating film structure. As is apparent from this figure, when the thermal oxide film thickness is less than 4 nm, the flat band voltage in the MOS transistor decreases. This phenomenon is caused by a high interface state density at the interface between the thermal oxide film and the underlying silicon layer, and it becomes impossible to exhibit desired transistor characteristics by capturing electrons at the interface state. That's why. On the other hand, if the thermal oxide film thickness is 4 nm or more, the flat band voltage shows a substantially constant value, and it becomes possible to secure desired transistor characteristics.

It is not necessary to stipulate the upper limit of the thermal oxide film thickness.
In the case of a layer structure, it is not necessary to increase the thickness more than necessary.
That is, in consideration of the productivity of the thin film transistor, the upper limit of the film thickness is, for example, about 20 nm, considering that the thermal oxidation method is a method in which an oxide film is formed at a low speed.

In the first embodiment, the gate insulating layer 6
Has been described as having two layers, but may have a one-layer structure as shown in FIG. In this case, it is only necessary to omit the step of forming the second insulating layer 6b in the above steps.

Next, a method for forming a silicon oxide layer 6a obtained by oxidizing the surface of the polycrystalline silicon layer 4 will be described in detail below. (1) Forming Method of Introducing Water Vapor into Ozone Atmosphere A sample in which the polycrystalline silicon layer 4 is formed on the non-annealed glass substrate 1 is carried into the first processing chamber, and the sample is thermally treated with respect to the unannealed glass substrate 1. The heating is performed at a temperature that does not adversely affect the temperature, for example, about 450 ° C. On the other hand, ozone (about 10 SLM) and steam (about 100 SCCM) are introduced into a second processing chamber adjacent to and separated from the first processing chamber,
The inside of the second processing chamber was controlled at about 700 Torr. Ozone is pure oxygen gas (10 SLM) and trace amount of N ₂ gas (55S).
Using a mixed gas with CCM) as a raw material, 100 g / Nm ³ (ozone concentration of about 5%) ozone was generated using a well-known silent discharge type ozonizer. The water vapor was heated to 100 to 200 ° C. by heating pure water filled in a pressure-resistant container, and steam having a pressure higher than the atmospheric pressure was produced in the pressure-resistant container.
It was introduced into the second processing chamber at the rate of CCM.

From the first processing chamber to the second processing chamber in the oxidation processing atmosphere in which steam is introduced into ozone, 45
The sample heated to 0 ° C. is loaded. By performing such processing, the surface of the polycrystalline silicon layer 4 is oxidized, and as a result, a first insulating layer 6a having a thickness of 4 nm or more, that is, a SiO ₂ layer is formed on the surface.

In the above-described embodiment, the supply pressure is set to a pressure lower than the atmospheric pressure, for example, 700 Torr in order to stably supply the steam to the second processing chamber. However, a stable supply of the steam can be performed. , The supply pressure is 7
It is not limited to 00 Torr.

(2) Forming method of introducing N ₂ O gas into ozone atmosphere As in the case of (1) above, 100 g / Nm ³ ozone atmosphere is supplied with N ₂ O gas instead of water vapor for 100 S / Nm ^3.
Supply CCM. Then, in the oxidizing atmosphere described above,
By loading the sample heated to about 450 ° C., the first insulating layer 6 a having a thickness of 4 nm or more can be formed on the surface of the polycrystalline silicon layer 4. In this case, nitrogen (N) is mixed in the insulating layer, and the oxynitride layer (SiN
_x O _y ). When this embodiment is used, SiN _x
About 0.5 at% of nitrogen segregates at the O _y / p-Si interface. The oxynitride film also has the effect of terminating dangling bonds in the SiO ₂ film and improving the reliability of the gate insulating film.

(3) A method in which an oxide film having a thickness of about 1 nm is formed, and then ozone oxidation is performed.
After forming an ultra-thin oxide film having a thickness of about 4 nm, the surface of the polycrystalline silicon layer 4 is treated by performing treatment in an atmosphere containing ozone.
The first gate insulating layer 6a (Si
O ₂ layer). A method for forming an oxide film having a thickness of about 1 nm is obtained, for example, by immersing the sample on which the polycrystalline silicon layer 4 is formed in ozone water in which ozone gas is bubbled in pure water.
Further, the above-described sample may be immersed in an ammonia / hydrogen peroxide aqueous solution instead of the ozone water. The thickness of the silicon oxide film previously formed on the silicon surface is about 1 n.
The thickness is not limited to about m, and may serve as a site for adsorbing a large number of oxidizing species such as ozone flying on the surface of the oxide film. Therefore, it is advantageous that the thickness of the oxide film to form a state where the density is small is about 0.1 to 1 nm.

Next, the mechanism of oxidation of the silicon layer will be briefly described. When the surface of silicon is exposed to an atmosphere of an oxidizing species, the oxidizing species first adsorbs on the surface of the silicon, and an oxidation reaction starts. When a silicon oxide film is provided on the surface of silicon, the oxidizing species adsorbed on the surface of the silicon oxide film diffuses in the silicon oxide film. When the diffusion of the oxidizing species proceeds and reaches the silicon oxide film / silicon interface, a reaction between the silicon and the oxidizing species occurs, and the silicon oxide film grows. Therefore, the silicon oxide film formed by the oxidation reaction becomes somewhat thick,
Under conditions where the diffusion of the oxidizing species is more rate-determining than the oxidation reaction, the higher the diffusion rate of the oxidizing species in the silicon oxide film, the higher the rate of formation of the silicon oxide film.

On the other hand, since the diffusion rate of the oxidizing species is proportional to the concentration gradient of the oxidizing species in the silicon oxide film, the diffusion rate can be increased by increasing the concentration of the oxidizing species on the outermost surface of the silicon oxide film. In order to increase the concentration of oxidized species on the outermost surface, the number of adsorption sites may be increased. An oxide film of about 1 nm formed by exposing the silicon surface to ozone water or an aqueous solution of ammonia / hydrogen peroxide is not as dense as a generally used thermal oxide film, and has many adsorption sites on the outermost surface. . Therefore, forming a silicon oxide film of about 1 nm in advance on the silicon surface has the effect of adsorbing a large number of oxidizing species and increasing the oxidizing species concentration on the surface.

Next, the ozone supply method described in the above embodiment will be described in detail. Ozone usually decomposes at 200 ° C. or higher. For this reason, when ozone is supplied to a substrate heated to a temperature of about 450 ° C., most of the supplied ozone is easily decomposed by heat radiation from the substrate. When the supply amount of ozone is increased to avoid this inconvenience, a large amount of ozone gas lowers the substrate surface temperature, resulting in inhibition of the oxidation reaction on the substrate surface. Therefore, in such a case, an oxide film is not formed as much as expected from an increase in the supply amount of ozone.

In order to accelerate the oxidation reaction on the substrate surface, it is necessary to prevent the decomposition of ozone itself and the decrease in the temperature of the substrate surface before reaching the substrate surface. In other words, the temperature in the ozone gas transport path is 200 ° C. or less, which is a level at which ozone is not decomposed, and is preferably 1 ° C.
It is important to keep the temperature at 50 ° C. or lower and keep only the substrate surface at a high temperature. In order to satisfy these requirements, the inventors analyzed in detail the temperature change of the substrate surface when ozone was supplied to the substrate surface, and studied a method of controlling the temperature of the substrate surface based on the knowledge.

Generally, when a gas is supplied to the surface of a substrate while holding the substrate on a stage whose temperature is controlled using a general-purpose heater, the temperature of the substrate surface changes as shown in FIG. . That is, FIG. 5 shows the time lapse on the horizontal axis,
The vertical axis represents the heater input, the temperature inside the stage where the heater is mounted, and the temperature change on the substrate surface. When a predetermined input is made to the heater, the temperature inside the stage and the temperature on the substrate surface both maintain the predetermined temperature. However, when the supply of gas is started, the temperature of the substrate surface starts to decrease rapidly at almost the same time. When the temperature inside the stage starts to decrease after the time t1, the feedback mechanism of the heater operates. After the elapse of the time t2, the input to the heater increases, whereby the temperature inside the stage gradually recovers. After the temperature inside the heater returns to the steady state at the set temperature again, the supplied gas loses some heat, so the input of the heater becomes slightly larger than before the gas supply,
The substrate surface temperature reaches a steady state at a lower temperature than before gas supply.

In FIG. 5, T1 is the temperature decrease caused by the supply of gas to the substrate surface, and t1 is the time from the start of gas supply until the substrate surface temperature becomes minimum. As described above, in the oxidation reaction process using ozone, the formation rate of the oxide film is high at the initial stage of the oxidation reaction. Therefore, it is important to minimize the temperature drop on the substrate surface immediately after the supply of ozone in order to promote the oxidation reaction. That is, the key to the growth of the oxide film is how much the above-mentioned temperature decrease amount T1 on the substrate surface and the time t1 until the temperature is completely reduced can be suppressed.

FIG. 6 schematically shows a substrate heating stage improved by the inventors. FIG. 6A is a plan view of FIG.
(B) is a side view. The substrate stage 13 was manufactured using aluminum nitride (AlN) having good thermal conductivity, and a heat source 14 as a heater was built in near the surface of the substrate stage 13. Further, a temperature detector 15 for controlling a heat source is provided.
Was mounted near the surface of the substrate stage 13. Further P
By optimizing the ID control parameters, the heat source 1
The thermal time constant interposed between the substrate 4 and the substrate stage 13 was minimized.

FIG. 7 shows the result of performing the same experiment as that shown in FIG. 5 using this substrate heating stage. As a result, when the gas is supplied to the substrate surface, the amount of decrease (T1) in the substrate surface temperature and the time (t1) until the substrate temperature is completely reduced can be much reduced as compared with the case shown in FIG. Became. In the above-described embodiment, AlN is used as the material of the substrate stage. However, the material is not limited to this as long as the same effect as that shown in FIG. 7 can be obtained.

The _second insulating layer 6a (SiO ₂ layer) formed by oxidizing the surface of the polycrystalline silicon layer 4 is formed.
The insulating layer 6b is formed by, for example, a CVD method, a PVD method, or a spin coating method. In case of CVD method, TEOS
And a method of utilizing thermal decomposition using monosilane or disilane as a source gas. In the case of the PVD method, there are a sputtering method, an evaporation method, and the like. For example, using an SiO ₂ target, Ar /
By performing RF sputtering in an O ₂ mixed gas, a dense SiO ₂ film can be obtained. In the spin coating method,
There is an SOG (Spin On Glass) method or the like. The gate insulating layer 6 is completed by the method described above.

Using the above-described process, the T formed at a low temperature of 450 ° C. or less on an unannealed glass substrate.
The FT has 4 above the channel region, which is a polycrystalline silicon layer.
By using a SiO ₂ layer formed by oxidizing a polycrystalline silicon layer as a gate insulating film having a gate insulating film of nm or more, the interface state density can be reduced. It has been confirmed that the variation with time of the threshold voltage Vth, which is one of the characteristics, can be reduced.

[0039]

As described above, a thin film transistor for liquid crystal display can be formed on an inexpensive non-annealed glass substrate by using the surface treatment of a polycrystalline silicon film using ozone oxidation.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view illustrating a thin film transistor according to a first embodiment.

FIG. 2 is a process chart for explaining a method of manufacturing the thin film transistor according to the first embodiment.

FIG. 3 is an explanatory diagram showing a relationship between a thermal oxide film thickness and a flat band voltage.

FIG. 4 is a schematic sectional view illustrating a thin film transistor according to a second embodiment.

FIG. 5 is an explanatory diagram for explaining a conventional substrate heating method.

FIG. 6 is a schematic diagram for explaining a substrate heating mechanism for carrying out the present invention. .

FIG. 7 is a schematic diagram for explaining a change in surface temperature of a substrate in the present embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Unannealed glass substrate, 2 ... Diffusion prevention layer, 3 ... Amorphous silicon layer, 4 ... Polycrystalline silicon layer, 5 ... Excimer laser beam, 6a ... 1st insulating layer, 6b ... 2nd insulating layer, 7 ... Gate region, 8 source region, 9 drain region, 10 interlayer insulating layer, 11 electrode, 12 channel region, 13 substrate stage, 14 heat source, 15 temperature detector

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/316 H01L 29/78 617V 29/786 617U 617T (72) Inventor Takuo Tamura Totsuka-ku, Yokohama-shi, Kanagawa Prefecture 292 Yoshida-cho, Hitachi, Ltd.Production Technology Laboratory (72) Inventor Miwako Nakahara 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref. 3300 Hayano Hitachi Display Co., Ltd. (72) Inventor Ryoji Oritsuki 3300 Hayano Mobara, Chiba Prefecture Hitachi Display Co., Ltd. Hitachi Central Research Laboratory (72) Inventor Kamo 3300 Hayano, Mobara-shi, Chiba Prefecture, Hitachi, Ltd. Display Group, Hitachi, Ltd. (72) Inventor Osamu 3300, Hayano, Mobara-shi, Chiba Prefecture, Hitachi, Ltd. GA13 LA12 2H092 JA24 JA34 JA37 JA41 JB56 KA04 KA05 KB25 MA25 MA30 NA29 PA01 PA07 5F058 BA20 BB07 BC02 BC11 BD01 BF53 BF62 BF63 BF69 BJ10 5F110 AA14 AA17 AA30 BB01 CC02 DD02 DD13 FF29 FF02 FF01 FF02 FF01 FF02 FF02 FF01 FF02 FF GG02 GG13 GG25 GG44 HJ13 HJ23 NN02 PP03 QQ11

Claims (21)

[Claims] 1. A semiconductor device comprising: a channel region, a source region, a drain region, a first insulating layer, a second insulating layer, and an electrode formed of a polycrystalline silicon formed above a glass substrate. A thin film transistor, which is a non-annealed glass substrate, wherein the first insulating layer is formed so as to cover a channel. 2. The thin film transistor according to claim 1, wherein said first insulating layer has a thickness of 4 nm or more. 3. The thin film transistor according to claim 1, wherein said first insulating layer is a silicon oxide layer formed by oxidizing a surface of said channel region at a temperature of 500 ° C. or lower. 4. The thin film transistor according to claim 1, wherein said first insulating layer is a silicon oxynitride layer formed by oxynitriding the surface of said channel region at a temperature of 500 ° C. or less. 5. The thin film transistor according to claim 1, wherein said second insulating layer is provided above said first insulating layer, and is formed by using a chemical deposition method. 6. The thin film transistor according to claim 1, wherein said second insulating layer is provided above said first insulating layer, and is formed by using a physical deposition method. 7. The thin film transistor according to claim 1, wherein said second insulating layer is disposed above said first insulating layer and formed by using a spin coating method. 8. The method according to claim 1, wherein a diffusion preventing film is formed on a surface of the non-annealed glass substrate on a side where the channel region, the source region, and the drain region are formed. Thin film transistor. 9. A semiconductor device comprising: a channel region made of polycrystalline silicon formed above a glass substrate; a source region and a drain region; an insulating layer and an electrode; wherein the glass substrate is a non-annealed glass substrate; A thin film transistor, wherein the layer is formed so as to cover a channel. 10. The thin film transistor according to claim 9, wherein said insulating layer is formed at a temperature of 500 ° C. or less. 11. The thin film transistor according to claim 9, wherein said insulating layer is a silicon oxide layer formed by oxidizing a surface of said channel region at a temperature of 500 ° C. or lower. 12. The thin film transistor according to claim 9, wherein said insulating layer is a silicon oxynitride layer formed by oxynitriding the surface of said channel region at a temperature of 500 ° C. or lower. 13. A method for manufacturing a thin film transistor, comprising:
(1) a step of forming an amorphous silicon layer above an unannealed glass substrate; and (2) a step of irradiating the amorphous silicon layer with a laser beam to form a polycrystalline silicon layer;
(3) forming a channel region, a source region, and a drain region at predetermined positions of the polycrystalline silicon layer;
(4) a step of oxidizing at least a surface of the channel region of the polycrystalline silicon layer at a temperature of 500 ° C. or less to form a first insulating layer; and (5) forming a first insulating layer on the first insulating layer. (6) a step of forming a gate region on the second insulating layer at a position corresponding to the channel region, and (7) a step of covering the gate region. Forming an interlayer insulating layer, and forming respective electrodes so as to electrically connect the source region, the drain region, and the gate region. Method. 14. The method according to claim 14, wherein in the step of forming the first insulating layer, the surface of the polycrystalline silicon layer is oxidized in an atmosphere containing at least ozone to form the first insulating layer. The method for manufacturing a thin film transistor according to claim 13. 15. The step of forming the first insulating layer, wherein the surface of the polycrystalline silicon layer is oxidized in an atmosphere containing ozone and H ₂ O to form the first insulating layer. The method for manufacturing a thin film transistor according to claim 13, wherein: 16. The step of forming the first insulating layer, wherein the surface of the polycrystalline silicon layer is oxidized in an atmosphere containing ozone and N ₂ O to form the first insulating layer. The method for manufacturing a thin film transistor according to claim 13, wherein: 17. In the step of forming the first insulating layer, after forming a first silicon oxide layer on the surface of the polycrystalline silicon layer using an oxygen donating solution, the first silicon oxide layer is formed in an atmosphere containing ozone. 14. The method according to claim 13, wherein a second silicon oxide layer is formed between the first silicon layer and the polycrystalline silicon layer. 18. The method according to claim 14, wherein the ozone gas or the gas containing ozone supplied to the surface of the polycrystalline silicon layer is heated to a temperature lower than the decomposition temperature of the ozone. A method for manufacturing the thin film transistor according to the above. 19. The method according to claim 14, wherein the ozone gas or the gas containing ozone is heated to a temperature of 150 ° C. or less. 20. In the step of forming the first insulating layer, after forming a low density first silicon oxide layer on the surface of the polycrystalline silicon layer, the first silicon oxide layer and the polycrystalline silicon 14. A high density second silicon oxide layer is formed between the silicon oxide layer and the silicon layer.
3. The method for manufacturing a thin film transistor according to item 1. 21. The first silicon oxide layer has a thickness of 0.1 mm.
22. The method for manufacturing a thin film transistor according to claim 17, wherein the thickness is in a range of 1 to 1 nm.