JP2002320103A - Horizontal deflection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain a breakdown voltage of an element constituting an output circuit of a horizontal deflection circuit to be low, and to reduce the horizontal deflection power. SOLUTION: In figure, a reference numeral 1 shows a horizontal drive circuit, a numeral 2 shows a horizontal output transistor driven by a driving signal of the drive circuit, the numeral 3 shows a dumper diode, the numeral 4 shows a resonance capacitor, the numeral 5 shows a linearity coil, the numeral 6 shows an S-shape correction capacitor, the code 7 is a horizontal deflection output circuit constituted of the numerals 2, 3, 4, 5, 6, 8 is a main power source circuit, 9 is an FBT, 10 is a deflection yoke, 11 is a CRT, the numeral 12 shows a line memory, 13 is a write-enable signal, the numeral 14 shows a read-enable signal, 15 is an A/D converter, 16 is a D/A converter, and 20 is a read-enable signal control means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a cathode ray tube (hereinafter, referred to as a cathode ray tube).
The present invention relates to a horizontal deflection circuit using a technique of expanding and compressing a video signal of a monitor or a television receiver using a CRT).

[0002]

2. Description of the Related Art A horizontal deflection circuit of a monitor or a television receiver using a conventional CRT will be described below.

FIG. 5 shows a horizontal deflection circuit using a conventional video signal expansion / compression technique. In FIG. 5, 1
Is a horizontal drive circuit, driven by a drive signal output therefrom, 2 is a horizontal output transistor, 3 is a damper diode, 4 is a resonance capacitor, 5 is a linearity coil, 6 is an S-shaped correction capacitor, and 7 is the above horizontal output. Transistor 2, damper diode 3, resonance capacitor 4, linearity coil 5, S-shaped correction capacitor 6
, A horizontal deflection output circuit comprising: 8, a main power supply circuit, 9: FB
T, 10 is a deflection yoke, 11 is a CRT, 12 is a line memory, 13 is a write enable signal, 14 is a read enable signal, 15 is an A / D converter, and 16 is D
-A converter.

The operation of the horizontal deflection circuit configured as described above will be described with reference to FIGS. 3, 4, 6, and 7. FIG.

[0005] First, a horizontal synchronizing signal which is separated from an input video signal and shaped is input to a horizontal drive circuit 1, and a horizontal output transistor 2, a damper diode 3, and a resonance capacitor are generated by a drive pulse waveform amplified by the horizontal drive circuit 1. 4, a horizontal deflection output circuit 7 including a linearity coil 5 and an S-shaped correction capacitor 6 and a switching circuit including a deflection yoke 10 are driven, and the deflection yoke 1
The horizontal deflection current flows to 0, and a high-voltage pulse of FBP (FIG. 3F) having a peak value (Vcp) of about 1500 V and a pulse width (Tr) of about 4.5 us is generated during the LC resonance operation (FIG. 3F). HD signal reception).

The driving power supply for the horizontal deflection output circuit 7 is an FBT 9
The power is supplied from the main power supply circuit 8 via the. FBP for passing beam current to CRT 11 in the secondary winding of FBT 9
Is generated and supplied to the CRT 11.

The linearity coil 5 and the S-shaped correction capacitor 6 of the horizontal deflection output circuit 7 are elements for correcting the horizontal linearity of the image received on the CRT 11.

The basic operation of the horizontal deflection circuit is as described above. On the other hand, the video signal processing section for displaying an image on the CRT 11 requires a horizontal period (Th) of about 30 μs of the HD signal as a condition of the input signal. , The horizontal display period (Ts) is 2
Let it be 5.5 us (FIG. 4 (i)). Horizontal retrace period (T
r) is set to 4.5 us from the above. Under these conditions, the video signal digitally converted by the A / D converter 15 which converts the input video signal into a digital signal (FIG. 7)
(M)) a write enable signal 13 for writing a signal to the line memory 12 for compression processing (FIG. 7 (n))
Is 30 MHz, the line memory 1
When the operation clock of the read enable signal 14 (FIG. 7 (o)) is read at the same 30 MHz as the write enable signal 13, the video is read as shown in FIG. 6 (a). The DA converter 1 maintains the horizontal image amplitude without being compressed.
6 to be converted into an analog video signal and received on the CRT 11.

On the other hand, the read enable signal 14
When the operation clock of FIG. 7 (p) is simply doubled to 60 MHz, the digital video signal is converted into an analog video signal by the DA converter 16 which reconverts the digital video signal into an analog video signal, and the video received on the CRT 11 is obtained. When the original video signal at the time of the full screen mode is (FIG. 6A), the video signal whose horizontal amplitude is halved (FIG.
(B)). The video signal compression technique based on the setting of the read enable signal 14 with respect to the write enable signal 13 is a normal (aspect ratio) when switching the screen mode in a television receiver (hereinafter, referred to as TV) having an aspect ratio of 16: 9. 4: 3) Also used for screen images (FIG. 6C).

[0010] By introducing this system, wide TV
It is possible to display a two-screen function (16: 9 aspect ratio) or a normal mode of screen mode switching, which is one function of TV, without switching the deflection circuit.

[0011]

However, in such a conventional signal decompression / compression system, only by using this technology as one function of the TV set, the withstand voltage of the circuit element of the horizontal deflection circuit can be reduced and the power can be reduced. Nobody used this technology.

The present invention solves the above-mentioned problems, and uses a signal expansion / compression technique to design each component to optimize the peak value and pulse width of the FBP output from the horizontal deflection output circuit. By performing the setting, the withstand voltage of these components can be reduced and the power consumption can be reduced.

[0013]

In order to achieve this object, a circuit configuration according to the present invention is a horizontal drive circuit for shaping a drive signal for driving a horizontal output circuit from a horizontal synchronization signal, and is driven by the drive signal. , A horizontal output transistor that flows a sawtooth current through the deflection yoke, a horizontal deflection output circuit including a damper diode, a resonance capacitor, a linearity coil, and an S-shaped correction capacitor; a main power supply circuit and a horizontal deflection output circuit that supply a power supply voltage to the horizontal deflection output circuit A horizontal deflection circuit including an FBT that generates a high voltage using the generated FBP and supplies the high voltage to a CRT, an A / D converter that converts a video signal for displaying a video on the CRT into a digital signal, A line memory for compressing / expanding the video signal and enabling writing to the line memory Signal, read enable signal for reading out a signal to operate at a faster than write enable signal clock, converts the digital video signal to an analog D-
It has a horizontal deflection circuit configuration called an A converter.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the first aspect of the present invention, a horizontal deflection circuit in a television receiver using a CRT forms a drive signal for driving a horizontal output circuit from a horizontal synchronization signal. A horizontal drive circuit, a horizontal output transistor driven by the drive signal and flowing a sawtooth current through the deflection yoke, a horizontal deflection output circuit including a damper diode, a resonance capacitor, a linearity coil, and an S-shaped correction capacitor, and a power supply voltage to the horizontal deflection output circuit. A high voltage is generated by using a main power supply circuit for supplying power and a FBP generated by a horizontal deflection output circuit, and the high voltage is generated by a CR.
A horizontal deflection circuit composed of an FBT to be supplied to T, an A / D converter for converting a video signal for displaying a video on a CRT into a digital signal, a line memory for compressing and expanding the video signal, and a line memory for the line memory A write enable signal, a read enable signal that operates with a faster clock than the write enable signal and reads the signal,
A digital-to-analog (D / A) converter that converts a digital video signal into an analog signal and a video read speed that is faster than an actual signal shortens the horizontal scanning period of the video, thereby setting the horizontal retrace period (Tr) longer.

If the horizontal retrace period Tr becomes longer, F
Since the peak value of the BP decreases, the breakdown voltage of each component constituting the horizontal deflection output circuit can be reduced.

According to a second aspect of the present invention, a CRT
In a horizontal deflection circuit in a television receiver using a horizontal drive circuit for shaping a drive signal for driving a horizontal output circuit from a horizontal synchronization signal, a horizontal drive circuit driven by the drive signal and flowing a sawtooth current to a deflection yoke A horizontal deflection output circuit including an output transistor, a damper diode, a resonance capacitor, a linearity coil, and an S-shaped correction capacitor, a main power supply circuit for supplying a power supply voltage to the horizontal deflection output circuit, and an FBP generated by the horizontal deflection output circuit
, A horizontal deflection circuit composed of an FBT for generating a high voltage and supplying the high voltage to a CRT, an A / D converter for converting a video signal for displaying a video on the CRT into a digital signal, A line memory for compression / expansion processing, a write enable signal to the line memory, a DA converter for converting a digital video signal to analog, a read enable signal that operates with a faster clock than the write enable signal and reads the signal, a video The horizontal scanning period of the image is shortened by reading the read speed faster than the actual signal, and the horizontal retrace period can be set longer, thereby increasing the horizontal winding inductance value of the deflection yoke. The power supply voltage output of the main power supply circuit is also set high so that the deflection yoke performs the same amount of horizontal deflection as the current.

As a result, the deflection current for determining the power consumption of the horizontal deflection circuit is reduced, so that the power consumption of the horizontal deflection circuit can be reduced.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a horizontal deflection circuit according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram of a horizontal deflection circuit according to an embodiment of the present invention.

In FIG. 1, 1 is a horizontal drive circuit, 2 is a horizontal output transistor driven by the drive signal, 3 is a damper diode, 4 is a resonance capacitor,
Is a linearity coil, 6 is an S-shaped correction capacitor, 7 is a horizontal deflection output circuit including these horizontal output transistor 2, damper diode 3, resonance capacitor 4, linearity coil 5, and S-shaped correction capacitor 6, 8 is a main power supply circuit, 9 is an FBT, 10 is a deflection yoke, 11 is a CRT,
12 is a line memory, 13 is a write enable signal,
14 is a read enable signal, 15 is an A / D converter, 16 is a DA converter, and 20 is a read enable signal control means for changing the frequency of the read enable signal and outputting it.

The operation of the horizontal deflection circuit configured as described above will be described with reference to FIGS.

First, a horizontal synchronizing signal, which is separated from a video signal and shaped into a waveform, is input to a horizontal drive circuit 1 and a horizontal output transistor 2, a damper diode 3, a resonance capacitor 4, Horizontal deflection output circuit 7 including linearity coil 5 and S-shaped correction capacitor 6 and deflection yoke 10
, The horizontal deflection current flows through the deflection yoke 10, and the peak value (Vcp) during the LC resonance operation.
A high-voltage pulse of about 1500 V and a pulse width (Tr) of about 4.5 us is generated (at the time of receiving an HD signal) called FBP (FIG. 3F). The drive power for the horizontal deflection output circuit 7 is supplied from the main power supply circuit 8 via the FBT 9.

A high voltage is generated in the secondary winding of the FBT 9 to cause a beam current to flow through the CRT whose FBP has been boosted, and is supplied to the CRT. The linearity coil 5 and the S-shaped correction capacitor 6 in the horizontal deflection output circuit 7 are elements for correcting the horizontal linearity of the image received on the CRT.

The basic operation of the horizontal deflection circuit is as described above. On the other hand, the video signal processing section for displaying a video on the CRT 11 has a horizontal period (Th) of about 30 μs of the HD signal as a condition of the input signal. And Horizontal display period (T
s) is 25.5 us (i). Horizontal retrace period (T
r) is set to 4.5 us from the above.

Under these conditions, a line memory 1 for compressing a video signal digitally converted by an A / D converter 15 for converting the video signal into a digital signal.
In the case where the clock of the write enable signal 13 for writing a signal to the second 2 is 60 MHz, to shorten the horizontal display period Ts (from 25.5 us to 23.5 us), the operation clock of the read enable signal 21 is the write enable signal. Therefore, the operation clock of the read enable signal 21 is 60 MHz · 1.0
8 = 64.8 MHz. Changing the frequency or cycle of the read enable signal 21 by the read enable signal control means 21 speeds up the video reading, so that the horizontal display period (k) of the video is shortened (T
s: 23.5 us) The digital video signal is converted into an analog video signal by a DA converter 16 which reconverts the digital video signal into an analog video signal, and is received by the CRT 11. Thereby, the horizontal retrace period can be set longer (Tr: 6.5).
us), the peak value of FBP (g) (1500v → 950)
v) is reduced, and the breakdown voltage of each component constituting the horizontal deflection output circuit can be reduced.

From Vcp = B · π / 2 (Ts / Tr + 1), Ts / Tr becomes about 63% of the original value, so that Vcp = 1500 · 0.63 = 950v.

(Embodiment 2) FIG. 2 is a block diagram of a horizontal deflection circuit according to a second embodiment of the present invention.

In FIG. 2, 1 is a horizontal drive circuit, 2 is a horizontal output transistor driven by the drive signal, 3 is a damper diode, 4 is a resonance capacitor,
Is a linearity coil, 6 is an S-shaped correction capacitor, 7 is a horizontal deflection output circuit composed of 2, 3, 4, 5, and 6, 8 is a main power supply circuit, 9 is an FBT, 10 is a deflection yoke, and 11 is a CR.
T and 12 are line memories, 13 is a write enable signal, 14 is a read enable signal, 15 is an AD converter, and 16 is a DA converter.

The operation of the horizontal deflection circuit configured as described above will be described with reference to FIGS.

First, a horizontal synchronizing signal, which is separated from a video signal and shaped into a waveform, is input to a horizontal drive circuit 1 and a horizontal output transistor 2, a damper diode 3, a resonance capacitor 4, Horizontal deflection output circuit 7 including linearity coil 5 and S-shaped correction capacitor 6 and deflection yoke 10
, The horizontal deflection current flows through the deflection yoke 10, and the peak value (Vcp) during the LC resonance operation.
A high-voltage pulse of about 1500 V and a pulse width (Tr) of about 4.5 us is generated (at the time of receiving an HD signal) called FBP (FIG. 3F). The drive power for the horizontal deflection output circuit 7 is supplied from the main power supply circuit 8 via the FBT 9.

In the secondary winding of the FBT 9, a high voltage generated by boosting the FBP for causing a beam current to flow through the CRT 11 is generated.
It is supplied to T11. The linearity coil 5 and the S-shaped correction capacitor 6 in the horizontal deflection output circuit 7
This is an element for correcting the horizontal linearity of the video image received on the LCD. The basic operation of the horizontal deflection circuit is as described above. On the other hand, the video signal processing unit for displaying the video on the CRT 11 sets the condition of the input signal to the horizontal period (Th) of the HD signal to about 30 μs. Horizontal display period (Ts)
Is 25.5 us. The horizontal retrace period (Tr) is set to 4.5 us from the above.

Under these conditions, a line memory 1 for compressing a video signal digitally converted by an A / D converter 15 for converting the video signal into a digital signal.
In the case where the clock of the write enable signal 13 for writing a signal to the second 2 is 60 MHz, to shorten the horizontal display period Ts (25.5 us → 23.5 us), the operation clock of the read enable signal 14 is the write enable signal. Therefore, the operation clock of the read enable signal 14 is 60 MHz · 1.0
8 = 64.8 MHz. Since the readout of the video becomes faster, the horizontal display period (k) of the video becomes shorter (Ts: 23.
5us) The digital video signal is converted into an analog video signal by a DA converter 16 which reconverts the digital video signal into an analog video signal, and is received on a CRT. Thus, the horizontal retrace period can be set long (Tr: 6.5 us).

By taking advantage of the fact that the horizontal retrace period can be set long, the power supply voltage is increased, and the inductance value (Ly) of the deflection yoke 10 is increased to reduce the deflection current. FBP (h) remains at 1500 Vpp. First, clarify formulas and numerical values to explain that power reduction can be achieved. Deflection sensitivity (LI ² ) = LH · Iy ² [mHA ² ] ··· Formula Deflection current (Iy) = B · Ts / LH [Ap-p] ··· Formula FBP (Vcp) = B · π / 2 (Ts / Tr + 1) ··· Formula Deflection sensitivity (LI ² ): 50 mHA ² ∴LH: deflection yoke horizontal inductance value Iy: horizontal deflection current B: power supply voltage Th: horizontal period Ts: horizontal display period Tr: horizontal flyback period 1: first power supply Find the voltage (B).

From the formula, 1500 V = B · π / 2 (23.5 us / 6.5 us +
1) B = 208V.

2: Determine the horizontal impedance value of the deflection yoke.

The official, become more ^{LH = (B · Ts) 2} / LI 2 = (208V · 23.5us) 2 / 50mHA 2 = 478uH.

3: Find horizontal deflection current.

[0038] an official from the ^{LI 2 = LH · Iy 2 Iy} = √LI 2 / LH = √50mHA 2 / 478uH = 10.2Ap-p (l).

The deflection current at the present time (the horizontal scanning period is 4.5 μs) is 14 Ap-p (j) according to the formula. Therefore, since the deflection current can be reduced by about 30%, the power can be reduced in proportion thereto.

[0040]

As is apparent from the above embodiments, the horizontal deflection circuit configuration of the present invention can set the withstand voltage of the horizontal deflection output circuit components low, and can reduce the horizontal impedance value of the deflection yoke. By increasing the current, the horizontal deflection current can be reduced and the power can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a horizontal deflection circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a horizontal deflection circuit according to a second embodiment of the present invention;

FIG. 3 shows an FB according to an embodiment of the present invention and a conventional example.
Peak value of P and timing waveform diagram

FIG. 4 is a signal compression waveform diagram of a video signal and a horizontal deflection current according to claims 1 and 2 of the present invention and a conventional example.

FIG. 5 is a block diagram of a conventional horizontal deflection circuit using a video signal expansion / compression technique.

FIG. 6 is a diagram of a video image received using a conventional video signal decompression / compression technique.

FIG. 7 is a clock frequency image diagram of each enable signal for an A-D video signal of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Horizontal drive circuit 2 Horizontal output transistor 3 Damper diode 4 Resonance capacitor 5 Linearity coil 6 S-shaped correction capacitor 7 Horizontal deflection output circuit 8 Main power supply circuit 9 FBT 10 Deflection yoke 11 CRT 12 Line memory 13 Write enable signal 14 Read enable signal 15 AD converter 16 DA converter 20 Read enable signal control means

Claims (2)

[Claims] 1. A horizontal drive circuit for forming a drive signal for driving a horizontal output circuit from a horizontal synchronization signal, a horizontal output transistor and a damper driven by the drive signal output from the drive circuit and supplying a sawtooth current to a deflection yoke. A horizontal deflection output circuit including a diode, a resonance capacitor, a linearity coil, and an S-shaped correction capacitor; a main power supply circuit for supplying a power supply voltage to the horizontal deflection output circuit; and a high voltage using an FBP generated by the horizontal deflection output circuit. A horizontal deflection circuit comprising an FBT to be supplied to a CRT, wherein the A / D converter converts a video signal for displaying an image on the CRT into a digital signal, and compresses and expands an output of the A / D converter. A line memory for storing data on the basis of a write enable signal, A read enable signal controlling means for outputting a read enable signal for reading out operation and the signal at a faster than enable signal clock writing to Li,
A horizontal deflection circuit comprising: a DA converter that converts a digital video signal read from the line memory into an analog signal. 2. The horizontal deflection circuit according to claim 1, wherein the horizontal winding inductance value of the deflection yoke is controlled to be large.