JP2000293126A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a power increase in the output circuit of a horizontal deflection circuit which becomes a problem at the time a horizontal frequency displays a higher signal and to make power sources of the horizontal circuit and a video circuit to be used in common. SOLUTION: A signal processing circuit 8 converting the horizontal display period of an input video signal is provided at the front stage of a video circuit 5 and, also, the ratio of a horizontal blanking period to a horizontal period is set based on a converted video signal which is outputted from the circuit 8 in a horizontal deflection circuit. Moreover, in a video signal whose horizontal frequency is different, the voltage of the power source of a horizontal deflection output circuit 13 is held constant by changing the value of a first resonance capacitor so that the ratio of the horizontal blanking period to a horizontal period becomes constant.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a television receiver using a cathode ray tube and a display device such as a display device for a computer terminal. In the present invention, such devices are collectively referred to as display devices.

[0002]

2. Description of the Related Art The horizontal frequency of an interlaced (interlaced scanning) NTSC signal is set to 15.75 kHz. On the other hand, the horizontal frequency of the NTSC signal converted to the progressive (sequential scanning) method is 31.47.
kHz. By using this progressive method, it is possible to provide a display device capable of reducing flickering of a display image and displaying a high-quality image. A conventional example for realizing such a progressive system is disclosed in Japanese Patent Application Laid-Open No. 3-76493.

[0003]

By using the above conventional example, a progressive system can be realized. Furthermore, the above-mentioned conventional example describes that the time axis of a video signal in a horizontal cycle can be compressed and an NTSC signal can be displayed on a high-definition display without switching the horizontal deflection current while maintaining its linearity. .

[0004] However, when the NTSC signal is converted to the progressive system, the horizontal frequency must be increased to about twice that of the interlace system. For this reason, the current flowing through the horizontal deflection coil of the deflection yoke needs to be increased by about twice, and an increase in power at the output section of the horizontal deflection circuit becomes a problem. However, in the above-mentioned conventional example, no solution to the increase in power at the output section of the horizontal deflection circuit has been considered.

An object of the present invention is to provide a display device capable of reducing power consumption generated at an output section of a horizontal deflection circuit.

Another object of the present invention is to provide a display device that can be used in common as a power supply for a horizontal deflection output circuit and a power supply for a video circuit.

[0007]

In order to achieve the above object, a display device according to the present invention comprises a horizontal deflection circuit having a horizontal deflection output circuit for driving a horizontal deflection coil of a cathode ray tube, and a vertical deflection coil of the cathode ray tube. In a display device provided with a vertical deflection circuit for driving and a video circuit for driving a cathode electrode of a cathode ray tube, a signal processing circuit for converting a horizontal display period of an input video signal is provided at a stage preceding the video circuit, and the horizontal deflection is provided. In the output circuit, the ratio of the horizontal retrace period to the horizontal period is set based on the converted video signal output from the signal processing circuit.

In order to achieve the object of the present invention, a display device according to the present invention comprises a horizontal deflection circuit having a horizontal deflection output circuit for driving a horizontal deflection coil of a cathode ray tube, and a vertical deflection coil for driving a cathode ray tube. A vertical deflection circuit and a video circuit for driving a cathode electrode of a cathode ray tube, a signal processing circuit for converting a horizontal display period of an input video signal is provided at a stage preceding the video circuit. If there are several types of horizontal frequencies of the converted video signal output from, the ratio between the horizontal display period and the horizontal retrace period at any horizontal frequency is set so as to be substantially constant, and the resonance capacitor of the horizontal deflection circuit and The power of the horizontal deflection circuit is kept constant by changing at least one of the values of the horizontal deflection coil.

In this display device, the horizontal frequency of the converted video signal output from the signal processing circuit is approximately 31.5 kHz and approximately 33.75 kHz, and when the horizontal frequency is approximately 31.5 kHz, the horizontal retrace period is approximately 9 .1μs
When the horizontal frequency is approximately 33.75 kHz, the horizontal blanking period is set to approximately 8.5 μs, and the ratio between the horizontal display period and the horizontal blanking period is set to be substantially constant. Preferably, the power supply voltage of the horizontal deflection output circuit of the circuit is constant.

In this display device, it is further preferable that a power supply voltage of the video circuit for driving a cathode electrode of the cathode ray tube is substantially equal to a power supply voltage of the horizontal deflection output circuit. In these display devices, it is preferable that the ratio of the horizontal retrace period to the horizontal cycle be approximately 20% or more. It is also preferable that the signal processing circuit has a function of converting an interlaced video signal into a progressive video signal.

The horizontal frequency of one of the converted video signals output from the signal processing circuit is approximately 31.5 kHz.
It is preferable that the horizontal retrace period in the horizontal deflection output circuit is 6.3 μs or more. More preferably, the other horizontal frequency of the converted video signal output from the signal processing circuit is approximately 33.75 kHz, and the horizontal retrace period in the horizontal deflection output circuit is 5.9 μs or more.

In order to achieve the object of the present invention, a display device according to the present invention comprises a horizontal deflection circuit having a horizontal deflection output circuit for driving a horizontal deflection coil of a cathode ray tube, and a vertical deflection circuit for driving a vertical deflection coil of the cathode ray tube. In a display device including a deflection circuit and a video circuit for driving a cathode electrode of a cathode ray tube, a signal processing circuit for converting a horizontal display period of an input video signal is provided at a stage preceding the video circuit, and an output from the signal processing circuit is provided. When the converted video signal has several horizontal frequencies, the horizontal retrace period is set to be substantially constant at any horizontal frequency, and the power supply voltage of the horizontal deflection output circuit is changed to change the horizontal deflection output circuit. The anode voltage is kept almost constant.

In this display apparatus, at one of several horizontal frequencies, the power supply voltage of the video circuit for driving the cathode electrode of the cathode ray tube is made equal to the power supply voltage of the horizontal deflection output circuit in the horizontal deflection circuit. It is suitable.

In this display device, it is preferable that the ratio of the horizontal retrace period to the horizontal period be approximately 20% or more. In this display device,
It is preferable that the signal processing circuit has a function of converting an interlaced video signal into a progressive video signal. The horizontal frequency of one of the converted video signals output from the signal processing circuit is set to approximately 31.5.
kHz, and the horizontal retrace period in the horizontal deflection output circuit is preferably 6.3 μs or more. More preferably, the other horizontal frequency of the converted video signal output from the signal processing circuit is approximately 33.75 kHz, and the horizontal retrace period in the horizontal deflection output circuit is 5.9 μs or more.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings using some examples.
In the description of the embodiments, components, circuits, and blocks having the same function are denoted by the same reference numerals in each drawing, and repeated description is omitted. FIG. 1 is a block diagram showing a first embodiment of the display device according to the present invention. In FIG. 1, 1 is a video signal input terminal, 2 is a vertical synchronization signal input terminal, 3 is a horizontal synchronization signal input terminal, 4 is a power supply input terminal, 5
Is a video circuit, 6 is a vertical deflection circuit, 7 is a horizontal deflection circuit,
8 is a signal processing circuit, 9 is a cathode ray tube, 10 is a deflection yoke,
11 is a horizontal oscillation circuit, 12 is a horizontal drive circuit, 13 is a horizontal deflection output circuit, 55 is a horizontal size control circuit, 17 is a flyback transformer, and 21 is a horizontal size control signal input terminal. 1, the horizontal deflection circuit 7 includes a horizontal oscillation circuit 11, a horizontal drive circuit 12, a horizontal deflection output circuit 13, and a horizontal size control circuit 55.

Here, the operation of the following circuit will be described, where the input video signal is Vin, the vertical synchronizing signal is VD, the horizontal synchronizing signal is HD, the horizontal size control signal is VS, and the power supply voltage is EB. The signal processing circuit 8 converts a horizontal display period in a horizontal cycle of the input video signal Vin input from the video signal input terminal 1, and outputs the converted video signal as a converted video signal Vbs. In the video circuit 5, the converted video signal Vb
s is amplified and supplied to the cathode electrode of the cathode ray tube 9 as a cathode voltage. The vertical deflection circuit 6 has a function of flowing a vertical deflection current synchronized with the vertical synchronization signal VD input from the vertical synchronization signal input terminal 2 to a vertical deflection coil constituting the deflection yoke 10. The horizontal deflection circuit 7 includes a horizontal oscillation circuit 11 that outputs a horizontal oscillation signal synchronized with the horizontal synchronization signal HD input from the horizontal synchronization signal input terminal 3, a horizontal drive circuit 12 that amplifies the horizontal oscillation signal, and a horizontal drive circuit 12. A horizontal deflection output circuit 13 to which a horizontal drive pulse output from a circuit 12 is input to generate a horizontal deflection current
And a horizontal size control circuit 55 to which a horizontal size control signal VS is supplied and connected to the horizontal deflection output circuit 13, and serves to flow a horizontal deflection current to a horizontal deflection coil constituting the deflection yoke 10. I have. In the horizontal deflection circuit 7, the amplitude of the horizontal deflection current is controlled by a horizontal size control signal VS input to a horizontal size control circuit 55 connected to the horizontal deflection output circuit 13.

An important point in the first embodiment shown in FIG. 1 is that an input video signal Vin is provided before the video circuit 5.
A signal processing circuit 8 for converting the horizontal display period, and setting the ratio of the horizontal retrace period to the horizontal period in the horizontal deflection circuit 7 based on the converted video signal Vbs output from the signal processing circuit 8. is there.

Hereinafter, the signal processing circuit 8 and the horizontal deflection circuit 7 will be described in detail. FIG. 2 is a block diagram showing one embodiment of the signal processing circuit of FIG. In FIG.
0 is an A / D converter, 71 is a memory, 72 is a time axis converter, 73 is a CPU, 74 is a D / A converter, and 75 is a converted video signal output terminal. In the figure, an A / D converter 70 performs an A / D conversion (analog / digital conversion) of an input video signal Vin input from a video signal input terminal 1 and supplies it to a time axis conversion unit 72. The time axis conversion circuit includes a memory 71, a time axis conversion unit 72,
PU73, and the time axis conversion unit 72
The digital signal output from the A / D converter 70 is written in the memory 71 according to the instruction from U73. Further, the time axis conversion unit 72 reads out the digitized video signal written in the memory 71 in accordance with an instruction from the CPU 73 and supplies it to the D / A converter 74. In the D / A converter 74, the time axis conversion unit 72
Is converted into an analog signal and supplied to a converted video signal output terminal 75.

In the circuit shown in FIG. 2, the time axis conversion unit 72 can convert the horizontal display period by changing the speed of writing to the memory 71 and the speed of reading from the memory 71. For example, if the reading speed from the memory 71 is made faster than the writing speed to the memory 71, the horizontal display period becomes shorter.

FIG. 3 is a block diagram showing another embodiment of the signal processing circuit of FIG. In FIG. 3, reference numeral 76 denotes a memory;
77 is an interlace / progressive conversion unit (hereinafter, referred to as
I / P converter). The signal processing circuit 8 shown in FIG. 3 has a function of converting the input video signal Vin into a progressive system (line-sequential system) when the system is an interlace system. The I / P conversion circuit is an I / P conversion unit 77
, A CPU 73, and a memory 76.
This I / P conversion is performed by an instruction from the CPU 73 using the I / P converter 77 and the memory 76. Further, the horizontal display period is converted by using the time axis conversion unit 72 and the memory 71, converted into an analog signal by the D / A converter 74, and then output to the converted video signal output terminal 75. By using the circuit shown in FIG.
It is possible to convert an interlaced signal such as C into a progressive signal and to convert a horizontal display period.

Next, a first embodiment of the horizontal deflection output circuit 13 and the horizontal size control circuit 55 in the horizontal deflection circuit 7 of FIG. 1 will be described with reference to FIG. FIG. 4 is a circuit diagram showing one embodiment of the horizontal deflection output circuit and the horizontal size control circuit of FIG. 4, the flyback transformer 17 shown in FIG. 1 includes a primary winding 17A and a secondary winding 17B. The horizontal deflection output circuit 13 connected to the horizontal drive pulse input terminal 20 includes a horizontal output transistor 26, a damper diode 27, a modulation diode 28,
It comprises a first resonance capacitor 29, a second resonance capacitor 30, a horizontal deflection coil 31, a first S-shaped capacitor 32, a modulation coil 33, and a second S-shaped capacitor 34. Through the anode voltage output terminal 22.

The horizontal size control circuit 55 includes a differential amplifier 5
6, resistors 57, 58 and 59. Also,
4, VDR is a horizontal drive pulse, Vcp is a collector voltage of the horizontal output transistor 26, Vm is a modulation voltage, IDY is a horizontal deflection current, and Vcs is a voltage between both ends of the second S-shaped capacitor 34 (horizontal size control circuit 55 Output voltage).

In FIG. 4, the horizontal output transistor 26 is switched based on the horizontal drive pulse VDR input from the horizontal drive pulse input terminal 20, and
A sawtooth horizontal deflection current ID is applied to the horizontal deflection coil 31.
It works to flow Y. When the horizontal output transistor 26 is turned off, the horizontal deflection coil 31
And a first resonance frequency determined by the inductance LH of the first resonance capacitor and the capacitance CR1 of the first resonance capacitor 29,
A sinusoidal first resonance pulse is generated (collector voltage Vcp). This first resonance pulse is called a flyback pulse.

In the circuit shown in FIG. 4, a sinusoidal wave is provided to the cathode terminal of the modulation diode 28 based on the inductance Lm of the modulation coil 33 and the second resonance frequency determined by the capacitance CR2 of the second resonance capacitor 30. A second resonance pulse is generated (modulation voltage Vm).

In the horizontal deflection output circuit 13 shown in FIG.
The pulse width of the first resonance pulse is set substantially equal to the pulse width of the second resonance pulse.
It is called a diode modulation circuit. In this diode modulation circuit, the voltage V between both ends of the second S-shaped capacitor 34
By changing cs, the amplitude of the horizontal deflection current IDY can be controlled. In the circuit shown in FIG.
The horizontal size control circuit 55 configured using the differential amplifier circuit 56 changes the voltage Vcs between both ends of the second S-shaped capacitor 34, controls the horizontal deflection current IDY, and eliminates pincushion distortion. .

Further, in the circuit shown in FIG.
The resonance pulse (flyback pulse) is boosted by the flyback transformer 17 and rectified by the diode 36 to form an anode voltage EHV to be supplied to the anode terminal 22 of the cathode ray tube. Further, by rectifying the pulse in the opposite direction of the first resonance pulse by the diode 27, the first half current of the horizontal deflection current is formed.

The characteristics of the circuit shown in FIG. 4 will be described below with reference to the operation waveform diagram in the horizontal cycle of FIG. FIG.
(A)-(f) is a waveform diagram of each part of the horizontal deflection output circuit of FIG. In FIG. 5, (a) shows the input video signal Vi.
n and (b) are the collector voltage Vcp1 of the horizontal output transistor 26 during the horizontal display period and horizontal blanking period corresponding to the input video signal Vin, (c) is the horizontal deflection current IDY1, and (d) is the output of the signal processing circuit 8. It is a waveform diagram of the conversion video signal Vbs which is a voltage. (E)
Is the horizontal output transistor 2 when the horizontal display period is changed
6 is a waveform diagram of the horizontal deflection current IDY2 when the horizontal display period is changed with the collector voltage Vcp2, (f).
(B) and (c) are waveform diagrams in a conventional display device, and (e) and (f) are waveform diagrams in a display device of the present invention.

5A to 5F, TH is a horizontal cycle, Ts1 is a horizontal display period of the input video signal Vin,
Tb1 is a horizontal blanking period of the input video signal Vin, Tr1 is a horizontal retrace period in the conventional display device, Ts2 is a horizontal display period of the converted video signal Vbs,
Tb2 is a horizontal blanking period of the converted video signal Vin, and Tr2 is a horizontal blanking period in the display device of the present invention.

In the conventional display device, the horizontal period T
The ratio of the horizontal retrace period Tr1 to H was set to about 15%. The reason is that the horizontal display period Ts1 shown in FIG. 5A is determined by the input video signal Vin, and the horizontal blanking period Tr1 is designed based on the input video signal Vin. For example, NTS
In the C method, the horizontal cycle TH is set to 63.5 μs, and the horizontal display period Ts1 is set to 52.7 μs. For this reason,
The horizontal blanking period Tb1 is 10.8 μs, and the ratio (Tb1 / TH) of the horizontal blanking period Tb1 to the horizontal cycle TH is 17%. Therefore, in the conventional display device, when designing the ratio (Tr1 / TH) of the horizontal retrace period Tr1 to the horizontal period TH, the above T
Considering a margin of about 2% for b1 / TH = 17%,
Tr1 / TH is designed to be about 15%.

On the other hand, in the display device of the present invention shown in FIG.
As shown in (d), the horizontal display period Ts2 of the converted video signal Vbs can be set to an arbitrary value. As a result, the horizontal blanking period Tr2 can be arbitrarily set by converting the input video signal Vin into the converted video signal Vbs regardless of the horizontal display period Ts1.

In the horizontal deflection circuit 7, the horizontal retrace period Tr2
Is increased, the horizontal deflection current IDY2 can be reduced, and the power consumption in the horizontal deflection output circuit 13 can be reduced. Hereinafter, this principle will be described using mathematical expressions and figures. The operation of the horizontal deflection output circuit 13 is as follows.
It can be expressed by the following basic formulas (1) to (4). In addition,
In Equations 1 to 4, Vcp is the collector voltage of the transistor 26, EB is the power supply voltage, TH is the horizontal cycle, LH is the inductance of the horizontal deflection coil 31, IDY is the horizontal deflection current, Tr is the horizontal retrace period, and PH is the horizontal flyback period. Deflection power index,
VDY is the voltage across the first S-shaped capacitor 32, and Vcs is the voltage across the second S-shaped capacitor 34.

Vcp = EB (π / 2 × (TH / Tr−1) +1) (Equation 1) EB = LH × IDY / (TH−Tr) (Equation ² ) PH = LH × IDY ² (Equation ² ) 3) EB = VDY + Vcs (Equation 4) In Equations 1 to 4, the horizontal period TH is determined by the specification of the input signal, the horizontal deflection power index PH is determined by the specification of the deflection yoke, and the second S-shaped capacitor 34 is used.
Is determined by the operation margin of the circuit. For example, when an NTSC signal is input to a wide TV of about 32 type and displayed in a progressive system, the horizontal period TH is 31.8 μs and the horizontal deflection power index PH is 40.
mHA ² , the voltage Vc across the second S-shaped capacitor 34
s becomes 10V. These values are substituted into the above four equations to obtain the ratio Tr of the horizontal retrace period Tr to the horizontal period TH.
The relationship between / TH (%) and the power supply voltage EB, the inductance LH of the horizontal deflection coil, and the horizontal deflection current IDY can be expressed as shown in FIG. 6, FIG. 7, and FIG.

FIG. 6 is a characteristic diagram of the power supply voltage with respect to the ratio of the horizontal retrace period and the horizontal cycle, FIG. 7 is a characteristic diagram of the inductance of the horizontal deflection coil with respect to the ratio of the horizontal retrace period and the horizontal period, and FIG. FIG. 6 is a characteristic diagram of a deflection current with respect to a ratio of a period and a horizontal cycle. In these figures, the horizontal axis represents the ratio Tr / TH of the horizontal retrace period Tr to the horizontal period TH.
(%). The vertical axis is the power supply voltage EB in FIG.
(V), FIG. 7 shows the inductance LH (μH) of the horizontal deflection coil 31, and FIG. 8 shows the deflection current IDY (A). 6 to 8, the ratio Tr / of the horizontal retrace period Tr to the horizontal period TH is shown.
TH (%) is set from 20% to 30%, and the interval is shown as an example of the present invention.

As shown in FIGS. 6, 7 and 8, in the display device of the present invention, the ratio Tr / TH (%) of the horizontal retrace period Tr to the horizontal period TH is increased, and the power supply voltage EB and the horizontal It is understood that the horizontal deflection current IDY can be reduced by increasing the inductance LH of the deflection coil 31. For example, in the circuit shown in FIG. 4, the ratio Tr / TH (%) of the horizontal retrace period Tr to the horizontal period TH.
Is set to 20% or more, the horizontal deflection current IDY can be reduced from 13.3 A to 10.2 A or less.

By reducing the horizontal deflection current IDY, the horizontal output transistor 26 and the damper diode 27
Current flowing through the horizontal deflection output circuit 13 can be reduced. However, when the power supply voltage EB is increased, it is necessary to increase the withstand voltage of the power supply circuit that forms the power supply voltage EB, and it is necessary to increase the size of the switching transformer and the smoothing capacitor in the power supply circuit. In the embodiment of the present invention shown in FIG. 4, the ratio Tr / TH (%) of the horizontal retrace period Tr to the horizontal period TH is set to 20% or more and 30% or less as a practical use area.

The power supply voltage EB is changed from 200 V to 250
By setting the voltage to about V, the power supply voltage of the video circuit 5 in FIG. 1 can be shared. That is, since the conventional power supply voltage EB is 110 V to 140 V and the voltage of the video circuit 5 is about 200 V, the power supply voltage EB and the power supply of the video circuit 5 cannot be shared, but in the present invention, 200V power supply voltage EB
To 250 V from the power supply voltage E
B and the power supply of the video circuit can be used.

As described above, the horizontal processing period of the input video signal Vin is converted by the signal processing circuit 8, and the horizontal deflection output circuit is designed so as to be adaptable to the converted video signal Vbs. There is an effect that power consumption in the deflection circuit 7 can be reduced. As described above, the power consumption in the horizontal deflection circuit 7 can be reduced by using the embodiment of the present invention shown in FIG.

Next, a feature of the present invention in which the fluctuation of the anode voltage can be reduced will be described. In the display device of the present invention, the variation of the anode voltage supplied to the cathode ray tube 9 in FIG. 1 is reduced by using the embodiment of the present invention shown in FIG. Hereinafter, this principle will be described with reference to FIGS. In the circuit shown in FIG. 4, the anode voltage EHV of the cathode ray tube is formed by rectifying the high voltage pulse VHP generated in the secondary winding 17B of the flyback transformer 17 by the diode 36.

In the circuit shown in FIG.
The pulse width of P (corresponding to the horizontal retrace period) substantially matches the flyback pulse Vcp. As a result, the display device of the present invention can increase the pulse width of the high-voltage pulse VHP as compared with the conventional display device. Therefore, the period during which the diode 36 is turned on by the high voltage pulse VHP is longer in the display device of the present invention than in the conventional display device. Therefore, the capacity of the high-voltage capacitor 91 via the diode 36 in one horizontal period,
The amount of charge stored in the capacitance between the anode terminal 22 of the cathode ray tube 9 and the ground is larger in the display device of the present invention than in the conventional display device. For this reason, the shortage of electric charge caused by the beam current Ib output from the anode voltage output terminal 22 can be supplemented. That is, the anode terminal 2 is connected via the diode 36.
2, the amount of charge supplied to the display device of the present invention is larger. Therefore, in the display device of the present invention, it is possible to suppress a decrease in anode voltage caused by an increase in the beam current Ib.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 9 is a block diagram showing a second embodiment of the display device according to the present invention. In FIG. 9, reference numeral 80 denotes a synchronization separation circuit, 16 denotes a power supply voltage control circuit,
EBI is a power supply voltage supplied to the power supply voltage control circuit 16. The circuit shown in FIG. 9 differs from the block diagram shown in FIG. 1 in that a synchronization separation circuit 80 and a power supply voltage control circuit 16 are provided.

In FIG. 9, a synchronization separation circuit 80 detects a horizontal synchronization signal HD and a vertical synchronization signal VD superimposed on the converted video signal Vbs output from the signal processing circuit 8, separates them, and separates them into horizontal deflection circuits. 7, the vertical deflection circuit 6. Therefore, the operating frequencies of the horizontal deflection circuit 7 and the vertical deflection circuit 6 are determined by the horizontal frequency and the vertical frequency of the converted video signal Vin output from the signal processing circuit 8 irrespective of the horizontal frequency and the vertical frequency of the input video signal Vin. Work by.

FIG. 10 shows a specific circuit example of the horizontal deflection output circuit 13, the horizontal size control circuit 55, and the power supply voltage control circuit 16 in FIG. FIG. 10 is a circuit diagram of a horizontal deflection output circuit, a horizontal size control circuit, and a power supply voltage control circuit.
In FIG. 10, reference numeral 24 denotes a power supply voltage input terminal, 25 denotes an anode voltage control signal input terminal, and the power supply voltage control circuit 1
Reference numeral 6 denotes transistors 44 and 45, a capacitor 46, a differential amplifier circuit 47, resistors 48, 49, 50, 51, 52, and 5
3, 54, and 60. Also, VCC
Is a power supply voltage, and Vref is an anode voltage control signal.

In FIG. 10, the power supply voltage control circuit 16 uses a differential amplifier circuit 47, a transistor 45, and a transistor 4 based on an anode voltage control signal Vref.
4 is operating. Therefore, the flyback transformer 1
The power supply voltage EB supplied to the horizontal deflection output circuit 13 via the primary winding 17A of the V.7 is the anode voltage control signal Vre.
f. By changing the anode voltage control signal Vref according to the horizontal frequency, the power supply voltage EB can be changed according to the horizontal frequency, and the anode voltage EHV can be kept stable.

In the circuit shown in FIG. 9, by providing the sync separation circuit 80 and the power supply voltage control circuit 16, the conversion output from the signal processing circuit 8 is independent of the horizontal frequency and the vertical frequency of the input video signal Vin. Video signal Vb
s horizontal deflection operation according to the horizontal frequency and vertical frequency of s,
A vertical deflection operation can be performed. Further, in the circuit shown in FIG. 9, the horizontal display period can be converted by the signal processing circuit 8 as in the first embodiment of the present invention shown in FIG. Period T
The ratio Tr / TH of the horizontal retrace period Tr to H can be increased as compared with the related art, and the power consumption by reducing the horizontal deflection current IDY can be reduced.

By using the second embodiment of the present invention shown in FIG. 9, in addition to the effects of the first embodiment of the present invention shown in FIG. Horizontal frequency and vertical frequency of the converted video signal Vb
There is an effect that it can be operated at the frequency of s. 9 and 10, the anode voltage EHV can be kept constant by keeping the horizontal retrace period Tr1 of video signals having different horizontal frequencies constant and changing the power supply voltage EB.

In the above embodiment, the NTSC television signal has been described as an input video signal. However, a PAL, SECAM television signal, an HDTV television signal, a video signal output from a computer, or the like may be used. , Is not limited by the input video signal.

These signals (NTSC, PAL, SEC)
AM and HDTV television signals and video signals output from a computer) have different horizontal blanking periods. By using the signal processing circuit 8 of the present invention, it is possible to set substantially equal horizontal blanking periods. Therefore, the ratio of the horizontal retrace period to the horizontal cycle in the horizontal deflection circuit 7 can be set to substantially the same value. Therefore, the same display device can cope with the various signal specifications described above.

A video signal output from an external output terminal of a liquid crystal notebook personal computer has a horizontal blanking period which is shorter than that of a desktop personal computer on the assumption that a cathode ray tube is used as a display device. May be short. By using the signal processing circuit of the present invention, an appropriate horizontal blanking period can be set. Therefore, the ratio of the horizontal retrace period to the horizontal cycle in the horizontal deflection circuit can be set to an appropriate value.

Next, a third embodiment of the display device according to the present invention will be described with reference to FIGS.
The third embodiment changes the power supply voltage EB and operates at an arbitrary horizontal frequency in the second embodiment, whereas the power supply voltage EB is constant and the flyback period Tr is changed to change the arbitrary horizontal frequency. This is an example of operating at a frequency.

FIG. 11 is a block diagram showing a third embodiment of the display device according to the present invention. In FIG. 11, reference numeral 80 denotes a synchronization separation circuit. Therefore, as in the second embodiment shown in FIG. 9, the operating frequencies of the horizontal deflection circuit 7 and the vertical deflection circuit 6 are output from the signal processing circuit 8 irrespective of the horizontal frequency and the vertical frequency of the input video signal Vin. It operates according to the horizontal frequency and vertical frequency of the converted video signal.

In the circuit shown in FIG. 11, the horizontal display period can be converted by the signal processing circuit 8 as in the first embodiment of the present invention. Ratio Tr / of flyback period Tr /
At the same time as increasing the TH as compared with the related art, the period of the horizontal display period is changed according to the horizontal frequency, and (TH−Tr) /
Tr can always be constant without depending on the horizontal frequency. When a plurality of video signals having different horizontal frequencies are received by the same display device, the values of the deflection coil 31 or the first resonance capacitor 29 are changed according to the horizontal frequency of the video signals, and these values are switched using, for example, a switch. Thus, the anode voltage EHV can be made constant using the same power supply voltage EB.

Hereinafter, referring to FIG. 12, even if the video signal has a different horizontal frequency, the anode voltage EHV
A display device which can use a common power supply for the horizontal deflection output circuit and the video circuit while maintaining the constant value will be described. FIG. 12 is a circuit diagram showing one embodiment of the horizontal size control circuit and the horizontal deflection output circuit of FIG. In FIG. 12, 37 is a capacitor, and 38 is a switch, which is connected in parallel with the first resonance capacitor. Switch 38
, The horizontal flyback period Tr is switched according to the horizontal frequency, and the power supply voltage can be made constant. Thus, even if the horizontal frequency changes, the anode voltage EHV can be kept stable, and the same effect as in the second embodiment can be obtained.

In a general display device, the power supply of the video circuit is about 200V. Although the power supply voltage EB of the horizontal deflection output circuit 13 is about 110 V to 140 V when the compression in the horizontal scanning period is not performed, the power supply voltage EB of the horizontal output circuit 13 increases when the compression in the horizontal scanning period is performed. For example, in the case of the NTSC signal, the horizontal retrace period is set to about 9
μs, and the power supply voltage EB required to obtain a constant anode voltage EHV is about 200 V. In the case of the HDTV signal, when the horizontal retrace period is set to about 9 μs, the power supply voltage about 205 V is required to obtain the same anode voltage EHV. It is. On the other hand, when the horizontal retrace period of the HDTV signal is set to 8 μs, the same anode voltage EHV can be obtained at a power supply voltage of 200V. Therefore, when the horizontal blanking periods of video signals having different horizontal frequencies are set to the same value, the power supply voltages necessary to obtain the same anode voltage EHV are different.

In this embodiment, a video signal having a low horizontal frequency (for example, NTSC signal: when the horizontal frequency is doubled to obtain a progressive video signal, the horizontal frequency is about 31.5 kHz) and a video signal having a high horizontal frequency In order to receive a signal (for example, HDTV signal: 33.75 kHz) and make the power supply voltage EB necessary to keep the anode voltage EHV constant in both video signals, as described above, the horizontal flyback period is used. Change (TH-Tr)
/ Tr needs to be constant. Therefore, in the illustrated embodiment, the switch is turned on when a video signal having a low horizontal frequency is received. In this case, the first
Is the sum of the capacitors 29 and 37. A power supply voltage of 200 V is used, and a design is made so that a required anode voltage EHV can be obtained by resonance of the capacitor and the deflection coil 31 connected in parallel.

When a video signal having a high horizontal frequency is received, the switch 38 is turned off. In this case, since a resonance circuit is formed by the first resonance capacitor 29 and the deflection coil 31, by appropriately setting the value of the first resonance capacitor 29, a video signal having a power supply voltage of 200 V and a low horizontal frequency is obtained. The same anode voltage EH as when receiving
V can be obtained. Further, regardless of which video signal is received, the power of the horizontal deflection output circuit 13 can be used as the power of the video circuit 5.

Hereinafter, this will be described in detail using equations. Assuming now that the horizontal cycle TH, the flyback period Tr, the power supply voltage EB, the anode voltage EHV, and the power supply voltage EB, the anode voltage EHV
Is represented by Equation 5. EHV∝EB × (TH−Tr) / Tr (Equation 5) According to Equation 5, when the horizontal frequency changes, that is, even when the horizontal period TH changes, the ratio of (TH−Tr) / Tr becomes constant. The power supply voltage E is changed by switching the line period Tr.
It can be seen that the anode voltage EHV can be kept stable with B constant.

In this embodiment, the case where the power supply voltage of the video circuit 5 is 200 V has been described as an example. However, even if the power supply voltage of the video circuit 5 changes, TH-Tr) / Tr so that the first resonance capacitor 29 or the deflection coil 31 is constant.
Is changed, the power supply of the horizontal deflection output circuit 13 and the power supply of the video circuit 5 can be shared.

In the horizontal deflection output circuit shown in FIG. 12, the horizontal flyback period Tr is switched in accordance with the horizontal frequency by turning on and off the switch 38, so that the horizontal deflection circuit 7 and the vertical deflection circuit 6 can be arbitrarily set. , The power consumption can be reduced by reducing the horizontal deflection current IDY, and the same effect as in the second embodiment can be obtained.

[0059]

As described above, according to the present invention, the ratio of the horizontal retrace period to the horizontal period can be set to be larger than in the prior art, so that the horizontal deflection current is reduced and the power consumption in the horizontal deflection circuit is reduced. be able to. Further, according to the present invention, the power supply to the horizontal deflection output circuit and the power supply to the video circuit can be shared.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a display device according to the present invention.

FIG. 2 is a block diagram showing one embodiment of a signal processing circuit of FIG. 1;

FIG. 3 is a block diagram showing another embodiment of the signal processing circuit of FIG. 1;

FIG. 4 is a circuit diagram showing one embodiment of a horizontal deflection output circuit and a horizontal size control circuit of FIG. 1;

FIG. 5 is a waveform chart of each part of the horizontal deflection output circuit of FIG. 1;

FIG. 6 is a characteristic diagram of a power supply voltage with respect to a ratio between a horizontal blanking period and a horizontal cycle.

FIG. 7 is a characteristic diagram of the inductance of the horizontal deflection coil with respect to the ratio between the horizontal retrace period and the horizontal cycle.

FIG. 8 is a characteristic diagram of a deflection current with respect to a ratio between a horizontal blanking period and a horizontal cycle.

FIG. 9 is a block diagram showing a second embodiment of the display device according to the present invention.

FIG. 10 shows a horizontal deflection output circuit and a horizontal size control circuit;
It is a circuit diagram of a power supply voltage control circuit.

FIG. 11 is a block diagram showing a third embodiment of the display device according to the present invention.

FIG. 12 is a circuit diagram showing one embodiment of a horizontal size control circuit and a horizontal deflection output circuit of FIG. 11;

[Explanation of symbols]

5 video circuit, 6 vertical deflection circuit, 7 horizontal deflection circuit, 8 signal processing circuit, 9 cathode ray tube, 10 deflection yoke, 11 horizontal oscillation circuit, 12 horizontal drive circuit, 1
3: horizontal deflection output circuit, 16: power supply voltage control circuit, 17
... Flyback transformer, 27 ... First resonance capacitor, 31 ... Horizontal deflection coil, 37 ... Capacitor, 38 ...
Switch, 55: horizontal size control circuit, 70: A / D converter, 71: memory, 72: time axis conversion circuit, 73
... CPU, 74 ... D / A converter, 76 ... Memory, 7
7 ... I / P conversion circuit, 80 ... Sync separation circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Junji Motojima 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi Image Information Systems Co., Ltd. (72) Takashi Hasegawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture (72) Inventor Kazuhiro Kaizaki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture, Ltd. Inside the AV Division of Hitachi, Ltd. (72) Inventor Makoto Onozawa Yoshida, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture No. 292, Hitachi, Ltd. Multimedia System Development Division, Hitachi, Ltd. (72) Inventor Masato Sugiyama 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref. F-term in Hitachi Multimedia Systems Development Division (Reference) 5C068 AA06 BA02 BA09 BA11 CA09 CB01 CC09 CC10 EA00 HA15 HA18 KA02 LA02 LA15 MA05

Claims (13)

[Claims] 1. A horizontal deflection circuit having a horizontal deflection output circuit for driving a horizontal deflection coil of a cathode ray tube, a vertical deflection circuit for driving a vertical deflection coil of the cathode ray tube, and a video circuit for driving a cathode electrode of the cathode ray tube. In the display device provided with, a signal processing circuit for converting a horizontal display period of an input video signal is provided at a stage preceding the video circuit, and when the horizontal frequency of the converted video signal output from the signal processing circuit is several, In the frequency, the ratio between the horizontal display period and the horizontal retrace period is set to be substantially constant, and at least one of the resonance capacitor and the horizontal deflection coil of the horizontal deflection circuit is changed to change the power supply of the horizontal deflection circuit. A display device characterized by: 2. The display device according to claim 1, wherein the horizontal frequency of the converted video signal output from the signal processing circuit is approximately 31.5 kHz and approximately 33.75 kHz, and the horizontal frequency is approximately 31.5 kHz when the horizontal frequency is approximately 31.5 kHz. The retrace period becomes approximately 9.1 μs, and the horizontal frequency is approximately 33.75 kHz.
At this time, the horizontal blanking period is set to approximately 8.5 μs, and the ratio between the horizontal display period and the horizontal blanking period is set to be substantially constant, and the power supply voltage of the horizontal deflection output circuit of the horizontal deflection circuit is set. A display device characterized by: 3. The display device according to claim 1, wherein a power supply voltage of said video circuit for driving a cathode electrode of said cathode ray tube is substantially equal to a power supply voltage of said horizontal deflection output circuit. Display device. 4. The display device according to claim 1, wherein a ratio of a horizontal blanking period to said horizontal period is approximately 20% or more. 5. The display device according to claim 1, wherein said signal processing circuit has a function of converting an interlaced video signal into a progressive video signal. 6. The display device according to claim 1, wherein the horizontal frequency of one of the converted video signals output from the signal processing circuit is approximately 31.5.
and a horizontal blanking period in the horizontal deflection output circuit is set to 6.3 μs or more. 7. The display device according to claim 6, wherein another horizontal frequency of the converted video signal output from the signal processing circuit is set to approximately 33.75 kHz, and a horizontal blanking period in the horizontal deflection output circuit is provided. 5.9 μs
A display device characterized by the above. 8. A horizontal deflection circuit having a horizontal deflection output circuit for driving a horizontal deflection coil of a cathode ray tube, a vertical deflection circuit for driving a vertical deflection coil of the cathode ray tube, and a video circuit for driving a cathode electrode of the cathode ray tube. In the display device provided with, a signal processing circuit for converting a horizontal display period of an input video signal is provided at a stage preceding the video circuit, and when the horizontal frequency of the converted video signal output from the signal processing circuit is several, A display apparatus wherein the horizontal retrace period is set to be substantially constant also at a frequency, and the power supply voltage of the horizontal deflection output circuit is changed to keep the anode voltage of the cathode ray tube substantially constant. 9. The display device according to claim 8, wherein at one of several horizontal frequencies,
A display device, wherein a power supply voltage of the video circuit for driving a cathode electrode of a cathode ray tube is equal to a power supply voltage of a horizontal deflection output circuit in a horizontal deflection circuit. 10. The display device according to claim 8, wherein a ratio of a horizontal retrace period to the horizontal period is approximately 20% or more. 11. The display device according to claim 8, wherein said signal processing circuit has a function of converting an interlaced video signal into a progressive video signal. 12. The display device according to claim 8, wherein one of the converted video signals output from the signal processing circuit has a horizontal frequency of about 31.5 kHz.
A horizontal blanking period in the horizontal deflection output circuit is set to 6.3 μs or more. 13. The display device according to claim 12, wherein another horizontal frequency of the converted video signal output from the signal processing circuit is approximately 33.75 kHz.
The horizontal retrace period in the horizontal deflection output circuit is 5.9 μm.
s or more.