JPH07162697A - Vertical deflection circuit - Google Patents

Abstract

PURPOSE:To provide a low-power-consumption small-sized vertical deflection circuit without providing complicated additional circuits such as a blanking circuit or the like. CONSTITUTION:The power supply voltage of a deflection coil driving means 20 driven by a vertical tooth-shaped wave generation circuit 10 is set at a low voltage VCC during a scanning period even during a fly-back period. A power source is supplied by using a selection circuit 22 for selecting the connection of a DC power source VCC and a pump-up circuit 21 and control is performed so as to directly connect the DC power source VCC without the pump-up circuit 22 at the time of an expansion mode. Further, the timing of vertical synchronizing signals is quickened, phase shifted synchronizing signals VSYNCB for which a phase is shifted are supplied to the tooth-shaped wave generation circuit 10 and the deflection coil driving means 20 is driven.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical deflection circuit for a color television receiver, and more particularly to a vertical deflection circuit for a 16: 9 wide aspect specification television receiver.

[0002]

2. Description of the Related Art At present, in Japan, NTSC system television broadcasting is being carried out, and further, high-definition television broadcasting with a large screen and high definition has been started. In high-definition television broadcasting, the aspect ratio of the screen is different from that of the NTSC system, and a picture tube having an aspect ratio (16: 9) wider than that of the current NTSC television receiver is adopted. Also, down conversion of high-definition television broadcasting to the current NTSC system
It may be possible to listen to high-definition television broadcasting by using a television receiver for the C system. Even in this case, a wide aspect picture tube having an aspect ratio of 16: 9 may be used in order not to lose image information in the entire screen.

In a television receiver having such an aspect ratio of 16: 9, when displaying an image having an aspect ratio of 4: 3, there are the following display modes.
The first display mode is a mode in which the horizontal time axis of the NTSC signal is compressed and a 4: 3 image is displayed in the central portion of the wide aspect picture tube. The second display mode is 4: 3.
In this mode, the horizontal time axis of the image is displayed without compression, and the vertical amplitude is expanded to be displayed in the entire wide aspect tube.

The second mode is suitable for displaying movie software. That is, as shown in FIG.
When a movie is displayed on three screens, it is displayed in a cinema size, so black blank regions are formed at the top and bottom, but when this is expanded and displayed on a 16: 9 wide aspect tube, it is shown in FIG. ), The black blank area is erased, and the image part can be enlarged and displayed.

FIG. 4 shows a circuit diagram of a conventional vertical deflection circuit for extending the vertical amplitude. In FIG. 4, 10
Is a vertical sawtooth generating circuit, 20 is a deflection coil driving means, Q1
Is a switching transistor for switching the display mode. Further, FIG. 5A shows vertical deflection currents in the extension mode V2 and the normal mode V0.
Vertical scanning corresponding to the vertical direction of the screen of (b) is performed. A signal from a control circuit unit (not shown) is supplied to the base of the transistor Q1, a low level signal is supplied in the mode for expanding the vertical amplitude, and a high level signal is supplied in the normal amplitude mode.

The vertical sawtooth generating circuit 10 includes a ramp (sawtooth wave) producing circuit 11 and an amplifying circuit 12. The ramp producing circuit 11 is supplied with a vertical synchronizing signal VSYNCA, and a voltage source V1 and a ramp producing circuit. A capacitor C1 for charging / discharging is connected between the capacitor 11 and 11.

The lamp producing circuit 11 synchronizes with the vertical synchronizing signal VSYNCA and charges the capacitor C1.
A sawtooth signal having an amplitude determined by the amount of discharge is generated. Further, the collector of the transistor Q1 is coupled to the ramp forming circuit 11 via the resistor R1, and the charging / discharging amount of the capacitor C1 changes according to the on / off state of the transistor Q1 to change the amplitude of the sawtooth signal. You can do it.

The output wave of the lamp producing circuit 11 is amplified by the amplitude circuit 12 at the next stage and supplied to the deflection coil driving means 20 for output. The deflection coil driving means 20 is
It is composed of a first-stage transistor Q2 and single-ended complementary pair transistors Q3 and Q4. The complementary pair transistors Q3 and Q4 in the subsequent stage are driven by the sawtooth wave input to the base of the transistor Q2, and vertical deflection current is supplied to the deflection coil L1 connected between the single-ended complementary pair transistors Q3 and Q4. ing.

Further, the pump-up circuit 21 serves to save power by increasing the power supply voltage of the transistors Q3 and Q4 in the vertical retrace period and in the scanning period. Further, the capacitors C2 and C3 and the resistors R5 to R7 connected between the deflection coil L1 and the amplifier circuit 12 form a negative feedback loop for DC and AC components.

By the way, in such a circuit, as shown in FIG. 5, in the extension mode, the amplitude-extended vertical deflection current V2 increases by about 30% as compared with that in the normal mode V0. In addition to increasing the power consumption of the output stage of the circuit, there is a drawback that the circuit scale is increased and the circuit is complicated by providing a blanking circuit as a measure against overscan.

[0011]

As described above, in the conventional apparatus, when the vertical amplitude is expanded, the power consumption of the output stage of the vertical deflection circuit is increased and the circuit scale is increased due to the blanking measures of the overscan section. There was a problem.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a vertical deflection circuit of low power consumption and small size without providing a complicated additional circuit such as a blanking circuit.

[0013]

A vertical deflection circuit according to the present invention according to claim 1 is a vertical synchronizing signal generating means for generating a first synchronizing signal of a vertical cycle and a phase shift signal obtained by shifting the synchronizing signal. And a sawtooth wave signal generating means for generating a sawtooth wave signal based on the first synchronization signal in the first mode, and an enlarged amplitude based on the phase shift signal in the second mode. A deflection coil including a first-stage transistor driven by the sawtooth-wave signal from the sawtooth-wave signal generating means and a single-ended complementary pair transistor which forms an output stage of the first-stage transistor and supplies a deflection current to the deflection coil. Drive means and in the first mode,
A power supply circuit for supplying the deflection coil driving means with a low power supply voltage during a scanning period and a blanking period with a high power supply voltage, and in the second mode for supplying the deflection coil driving means with the low power supply voltage. It is a feature.

[0014]

In the present invention, in the extension mode, the blanking period can be expanded without changing the inclination of the deflection current with respect to time, so that the vertical amplitude of the deflection current can be made equal to that in the normal mode.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a vertical deflection circuit according to the present invention. In FIG. 1, the same components as those of FIG. 4 are designated by the same reference numerals and described. In the present embodiment, description will be added using a television receiver that up-converts a video signal. The configurations of the transistor Q1, the sawtooth wave generation circuit 10, and the feedback circuit are the same as those in FIG. 4, and in the normal mode, a high level signal is supplied to the base of the transistor Q1 to turn it on and the capacitor C1 is turned on.
The amount of charge / discharge of the device becomes small and the vertical amplitude becomes a normal level. In the vertical amplitude expansion mode, a low-level signal is supplied to the base of the transistor Q1 to turn it off, and the amount of charging / discharging of the capacitor C1 increases to increase the vertical amplitude.

Further, the video signal is supplied to the vertical synchronizing signal generating means 30 to generate a vertical synchronizing signal VSYNCA and a phase shift synchronizing signal VSYNCB whose timing is different from that of the vertical synchronizing signal, that is, the phase is different. This phase shift signal VSYNC
B is supplied to the sawtooth wave generation circuit 10, and drives the deflection coil drive means 20 in the subsequent stage at a timing earlier than the conventional drive timing. It is assumed that a frequency-converted signal of the composite video signal and a signal before conversion are supplied to the vertical synchronizing signal generating means 30 by using an up converter (not shown).

The deflection drive means 20 is provided with a selection circuit 22 for selecting the power supply voltage supplied from the DC power supply Vcc to the single-ended complementary pair transistors Q3 and Q4. The selection circuit 22 uses the collector of the transistor Q3 and the DC power supply Vcc (contact S1) or the scanning period Ts.
Connection of the pump-up circuit 21 (contact S2) for switching the power supply voltage of the
The power supply voltage supplied to the deflection coil drive means 20 is controlled.

The selection of the power supply voltage described above is performed by the switching signal in the expansion mode or the normal mode. The pump-up circuit 21 receives the DC power supply voltage V during the scanning period Ts.
The power of CC is supplied, and during the retrace line period Tr, the power supply voltage 2Vcc that is twice the DC power supply voltage is supplied.

Next, the operation of FIG. 1 will be described with reference to FIG. FIG. 2A shows a waveform of the composite video signal (cycle 2
T) and (b) are video signals (cycle T) converted to double the frequency by the up converter. Figure 2 (c)
Shows the amplitude of the vertical sawtooth in the normal mode and the stretch mode, the waveform V0 is the normal mode, and the waveform V2 is the stretch mode amplitude. Switching of these amplitudes is performed by the transistor Q.
1 by switching the control signal to the base. FIG. 2D shows a voltage waveform at a middle point (point E) when the pump-up circuit 21 in the output portion of the complementary pair transistor is operated. FIG. 2E shows the vertical deflection current when the operation of the pump-up circuit 21 is stopped. FIG. 2F shows the phase shift signal VSYNCB generated by the vertical synchronizing signal generating means 30.
Is. FIG. 2G is a midpoint voltage waveform when the operation of the pump-up circuit 21 is stopped.

The up-converted composite video signal and the video signal before conversion are supplied to the vertical synchronizing signal generating means 30 to generate a synchronizing signal VSYNCB having a different phase. Normally, the sync signal V from the up-converted video signal
SYNCA is supplied to the sawtooth wave generating means 10, and in the expansion mode, the deflection current V2 of FIG. 2C is supplied to the deflection coil L1.

The pump-up circuit 21 applies to the output stage of the deflection coil driving means 20 a voltage 2VCC that is twice the power supply voltage VCC of Ts during the scanning period during the blanking period Tr, as shown in FIG. ) Midpoint voltage (see point E in FIG. 1) is generated. Here, by stopping the operation of the pump-up circuit 21 using the selection circuit 22, the blanking period Tr
Is set to supply the power supply voltage Vcc of Ts during the scanning period. By setting in this way, the blanking period Tr
Is enlarged, and the midpoint voltage of FIG. 2 (g) is obtained. This setting is performed based on the switching signals in the expansion mode and the normal mode.

The operating voltage of the deflection coil driving means 20 is set to the low voltage VCC of the power supply voltage in the scanning period Ts, and the deflection coil driving means 20 is operated at the low voltage VCC, so that the blanking period Tr is expanded. The deflection coil L1 is reset or the operating range of the transistors Q3 and Q4 changes with the power supply voltage, the midpoint voltage (point E) becomes as shown in FIG. 2G, and the blanking period Tr is extended. The amplitude of this sawtooth wave (VP-P
) Has an amplitude value equivalent to that in the normal mode, but since a synchronization shift with the blanking period Tr occurs, the vertical synchronization signal generation means 30 generates a phase shift signal VSYNCB having a phase shift from the video signal before frequency conversion. Then, the synchronizing signal VSYNCB is supplied to the sawtooth wave generating circuit 10 (see FIG. 2F). The synchronization signal VSYNCB accelerates the drive timing of the deflection coil drive means 20. Further, the vertical synchronizing signal generating means 30 is provided with an adjusting mechanism for changing the phase, such as a phase shifter, so that the drive timing of the vertical deflection circuit can be adjusted.

The vertical deflection current in the expansion mode (the voltage waveform of the dotted line waveform of FIG. 2E) operating at the timing from the sawtooth wave generation circuit 30 is converted into the amplitude value of the voltage in the normal mode (VP-
It is possible to operate with P). In the present embodiment, the selection circuit 22 is provided to supply the power supply voltage Vcc during the scanning period Ts.
However, the present invention is not limited to this.
Other power supply voltages may be used. It should be noted that the sawtooth wave generation circuit 10 can also set the time constants of the blanking period Tr of the sawtooth wave and the scanning period Ts. Although the television receiver that up-converts the video signal has been described in the present embodiment, the present invention is not limited to this as long as it is a vertical deflection circuit capable of controlling the vertical synchronizing signal.

[0024]

As described above, according to the present invention, without providing a complicated additional circuit such as a blanking circuit,
Providing a small vertical deflection circuit with low power consumption Since the amplitude of the vertical deflection current in the expansion mode can be made equal to the amplitude in the normal mode, it is possible to realize an expansion mode that does not increase the circuit power consumption and the circuit scale. It is possible to prevent the blanking circuit and the like from becoming complicated with respect to overscan.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a vertical deflection circuit according to the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG.

FIG. 3 is an explanatory diagram for explaining a display when an image having an aspect ratio of 4: 3 is displayed on a wide aspect picture tube having an aspect ratio of 16: 9.

FIG. 4 is a circuit diagram showing a conventional vertical deflection circuit.

FIG. 5 is a diagram illustrating a correspondence between a waveform diagram showing an operation waveform of a conventional vertical deflection circuit and a screen of a television receiver.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Sawtooth wave generation circuit 20 ... Deflection coil drive means 21 ... Pump-up circuit 22 ... Selection circuit 30 ... Vertical synchronization signal generation means Q1 to Q4 ... Transistors C1 to C3 ... Capacitors

Claims (1)

[Claims] 1. A first synchronizing signal of a vertical cycle, a vertical synchronizing signal generating means for generating a phase shift signal which is a phase shift of the synchronizing signal, and in a first mode, based on the first synchronizing signal. A sawtooth wave signal is generated, and in the second mode, it is driven by a sawtooth wave signal generating means whose amplitude is expanded based on the phase shift signal, and a sawtooth wave signal from the sawtooth wave signal generating means. A first-stage transistor and a deflection-coil driving means that includes a single-ended complementary pair transistor that forms an output stage of the first-stage transistor and supplies a deflection current to the deflection coil; and in the first mode, the deflection-coil driving means includes: A power supply circuit which supplies a low power supply voltage to the deflection coil driving means in the second mode while supplying a high power supply voltage during the scanning period and a high flyback period. A vertical deflection circuit, characterized in that.