JP2002319831A - Differential voltage/current conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a differential voltage/current conversion circuit incorporating a 1st stage amplifier so as to realize low distortion of the entire amplifier while decreasing a negative feedback to the entire amplifier. SOLUTION: The differential voltage/current conversion circuit adopts a characteristic configuration such that the circuit comprises a positive dual FETs 10 consisting of two FETs (FET QA1, FET QA2) whose characteristics are the same and a negative dual FETs 20 consisting of two FETs (FET QB1, FET QB2) whose characteristics are the same. Connecting gates of the FET QA1 and FET QB1 form an input A terminal and connecting gates of the FET QA2 and FET QB2 form an input B terminal. The FET QA1 and the FET QB2 are connected in series via a variable resistor VR1, and the FET QA2 and the FET QB1 are connected in series via a variable resistor VR2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential voltage / current conversion circuit used as a first stage circuit of an amplifier, and more particularly to a first stage circuit such as a total low NFB amplifier having a low negative feedback ratio as a whole. The present invention relates to a differential voltage / current conversion circuit that is suitable and is suitable for an audio preamplifier.

[0002]

2. Description of the Related Art Conventionally, in audio amplifiers,
In the second stage, a complementary push-pull circuit is generally used as a circuit constituting the voltage amplifier. The complementary push-pull circuit is superior in that the plus and minus drive impedances are equal and that even-order distortion is canceled.

As a circuit for driving a complementary push-pull circuit, that is, a first stage circuit of a conventional audio amplifier, a differential type voltage / current conversion circuit is generally used. A differential circuit is a circuit that outputs a value proportional to the difference between two input signals.It is difficult to saturate, can reduce drift, is not easily affected by temperature and power supply fluctuation, and can remove common-mode noise. There are such features.

FIG. 8 is a circuit diagram showing an example of a conventional differential voltage / current conversion circuit. This conventional differential voltage-current converter circuit has two input terminals, input A and input B, and two pairs of four output terminals, output 1, output 2, output 3, and output 4. Have. Then, the complementary push-pull circuit is directly driven by the output terminal.

[0005]

However, in the conventional differential circuit as shown in FIG. 8, the DC current output as the next-stage bias is almost determined by the accuracy of the constant current circuits 71 and 72. Since the current circuits 71 and 72 are separate solid-state circuits, the drift amounts with respect to temperature changes are different from each other, and it is not easy to increase the accuracy of the constant current circuits 71 and 72 to make them uniform.

[0006] Also, regarding the differential gain, the gm of the plus side dual FET 10 and the minus side dual FET
If gm of 20 is not uniform, it is difficult to adjust the symmetry and similarity of gain to a high degree. That is, in the conventional differential voltage-to-current conversion circuit, the plus side output (output 1, output 2) and the minus side output (output 3, output 3,
It was difficult to adjust the deviation of the gain from the output 4) and the sameness.

On the other hand, in the prior art, a method of increasing the negative feedback ratio in the whole amplifier including the first and second stages and a method of using a DC servo must improve the amplification characteristics comprehensively. did not become. Therefore, in order to create a circuit for accurately amplifying an input signal particularly in a high frequency range, a complicated circuit and a great deal of labor are required.

Therefore, in a conventional audio amplifier,
In order to comprehensively improve the amplification characteristics, the circuit configuration becomes complicated, and a great deal of labor is required for circuit adjustment to increase drift and gain symmetry and similarity with respect to temperature changes. There was a problem that high cost was required.

The main objects to be solved by the present invention are as follows. That is, a first object of the present invention is to provide a differential voltage / current conversion circuit which can directly drive a complementary push-pull circuit and can reduce distortion compared to the conventional one. Things.

A second object of the present invention is to provide a first stage circuit of an amplifier, and to reduce the distortion of the entire amplifier while suppressing the negative feedback ratio of the entire amplifier low. A current conversion circuit is not provided.

A third object of the present invention is to provide a differential voltage / current circuit capable of reducing the trouble of adjusting the circuit for temperature drift and gain symmetry and similarity with a relatively simple circuit configuration. No conversion circuit is provided.

Other objects of the present invention will become apparent from the description of the specification, the drawings, and particularly the description of each claim in the claims.

[0013]

In order to solve the above-mentioned problems, the device of the present invention comprises two transistors, the first transistor (QA1) and the second transistor (QA2) having the same characteristics. The positive dual transistor housed in one package and the negative first transistor, two transistors with the same characteristics
A negative dual transistor in which the transistor (QB1) and the negative second transistor (QB2) are housed in one package; a positive first transistor (QA1) and a negative second transistor (QB2) Are connected in cascade via a first variable resistor (VR1), and the positive second transistor (QA2) and the negative first transistor (QB1) are connected to a second variable resistor (VR).
It is characterized in that it is connected in cascade through 2) to provide a configuration means for forming a differential circuit.

More specifically, to solve the above-mentioned problems, the present invention achieves the above object by adopting a novel characteristic configuration means or technique ranging from a superordinate concept to a subordinate concept as listed below. It is done as follows.

That is, a first feature of the device of the present invention is that two transistors having the same characteristics, that is, a plus first transistor (QA1) and a plus second transistor (QA2) are housed in one package. The positive side dual transistor and the negative side first transistor (QB
1) and the negative second transistor (QB2)
And a negative side dual transistor housed in one package.
Substantially all of the current flowing through the plus-side first transistor (QA1) is supplied to the minus-side second transistor (QA1).
B2), the plus-side first transistor (QA1) and the minus-side second transistor (QB2) are connected in cascade so as to flow through the plus-side second transistor (QA2). The plus-side second transistor (QA2) and the minus-side first transistor (QB1) are connected in cascade so that the whole flows through the minus-side first transistor (QB1),
An operation control terminal of the positive-side first transistor (QA1) is connected to an operation control terminal of the negative-side first transistor (QB1) to form an input A terminal, and an operation control of the positive-side second transistor (QA2) is performed. An input B terminal is formed by connecting an end of the positive-side first transistor (QA2) to an operation control end of the negative-side second transistor (QB2).
1) and a plus output terminal connected to at least one of the current inflow ends of the plus second transistor (QA2), and at least one of the minus first transistor (QB1) and the minus second transistor (QB2). A differential voltage / current conversion circuit having a negative output terminal connected to one of the current inflow ends is employed.

According to a second feature of the device of the present invention, the differential voltage / current conversion circuit according to the first feature of the device of the present invention is characterized in that the differential voltage / current conversion circuit includes the plus first transistor (QA1) and the minus second transistor (QA1). A first variable resistor (VR1) that limits the amount of current flowing through the first transistor QB2) and a second variable resistor (VR1) that limits the amount of current flowing through the second transistor (QA2) and the first transistor (QB1). And a variable resistor (VR2).

A third feature of the device of the present invention is that the plus first transistor (QA1) and the plus second transistor (QA1) in the second feature of the above device of the present invention.
2) are n-channel junction FETs, respectively.
The minus first transistor (QB1) and the minus second transistor (QB2) are respectively
Channel junction type FET, and the first variable resistor (V
R1) is the source terminal of the first transistor on the positive side (QA1) and the second transistor on the negative side (QB2).
Of the second variable resistor (VR)
2) lies in the configuration adoption of a differential voltage / current conversion circuit arranged between the source terminal of the positive second transistor (QA2) and the source terminal of the negative first transistor (QB1).

According to a fourth feature of the device of the present invention, the drain terminal of the first transistor on the positive side (QA1) in the third feature of the device of the present invention is an n-channel junction type FET.
Is connected in cascade, and a drain terminal of the third junction FET (Q3) has an output 1 terminal forming one of the plus side output terminals,
One end of the first resistor (R1) is connected, the other end of the first resistor (R1) is connected to a plus power supply, and the drain of the plus second transistor (QA2) is connected to , A fourth junction type FET (Q4), which is an n-channel junction type FET, is cascaded.
A drain terminal of the junction type FET (Q4) has two output terminals, one of the positive side output terminals, and a second resistor (R2).
Is connected to the other end of the second resistor (R2), and the plus-side power supply is connected to the third junction FET (Q3) and the fourth junction FET (Q4).
A positive bias circuit for supplying a constant positive voltage is connected to the gate terminal of the transistor, and a drain terminal of the first transistor (QB1) on the negative side is connected to a fifth junction type FET which is a p-channel junction type FET. The FET (Q5) is cascade-connected, and the drain terminal of the fifth junction type FET (Q5) has three output terminals, one of the negative output terminals, and one end of a third resistor (R3). Connected
The other end of the third resistor (R3) is connected to a negative power supply, and the negative second transistor (QB
A sixth junction FET (Q6), which is a p-channel junction FET, is cascaded to the drain end of 2), and a drain end of the sixth junction FET (Q6) is
Four output terminals forming one of the minus side output terminals are connected to one end of a fourth resistor (R4), and the other end of the fourth resistor (R4) is connected to the minus power source. A differential voltage / current conversion circuit in which a gate terminal of the fifth junction type FET (Q5) and the sixth junction type FET (Q6) is connected to a negative bias circuit for supplying a constant negative voltage. Configuration adoption.

A fifth feature of the device of the present invention is that the differential voltage / current conversion circuit according to the fourth feature of the device of the present invention functions as a circuit for driving a complementary push-pull circuit. A positive input terminal of the complementary push-pull circuit is connected to one of the output 1 terminal and the output 2 terminal, and the complementary push-pull circuit is connected to one of the output 3 terminal and the output 4 terminal. Of the differential voltage / current conversion circuit to which the negative input terminal of the above is connected.

[0020]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
An embodiment of the present invention will be described with respect to an example of an apparatus and an example of an operation.

According to the present invention, a differential circuit is constituted by using two dual-type FETs each having two built-in FETs.
By adjusting the variable resistance, the symmetry and the similarity of the DC output and the differential gain can be easily and accurately matched to each other, which is suitable for the first stage circuit of an audio amplifier.

In the present embodiment, an example will be described in which the present invention is applied to a circuit for driving a complementary push-pull circuit. However, the present invention is not limited to this, and amplification of a signal detected by a sensor is performed. The present invention can be applied to various signal amplifier circuits such as a circuit and a buffer circuit.

(Example of Apparatus) FIGS. 1A and 1B are circuit diagrams showing an example of the apparatus of the present invention. FIG. 1A shows a differential voltage / current conversion circuit according to an embodiment of the present invention, and FIG. It is a driven complementary push-pull circuit.

In the drawing, reference numeral 10 denotes a positive dual FET, 2
0 is a negative dual FET, VR1 is a variable resistor for adjustment (first variable resistor), VR2 is a variable resistor for adjustment (second variable resistor), and Q3 and Q4 are junction type n-channel FEs.
T, Q5 and Q6 are junction type p-channel FETs.
R1, R2, R3, R4, R5 and R6 are resistors,
D1 and D2 are Zener diodes, and C1 and C2 are capacitors.

Further, 1 is one output of the positive output terminal, 2 is the other output of the positive output terminal, 3 is one output of the negative output terminal, and 4 is the other output of the negative output terminal. . A is an input at the input A terminal, and B is an input at the input B terminal.

The complementary push-pull circuit comprises a pnp type bipolar transistor TR1, n
It comprises a pn bipolar transistor TR2, a resistor R7 and a resistor R8.

The plus-side dual FET 10 is a plus-side dual transistor in which two FETs having the same characteristics and thermally coupled are accommodated in one package, and each of which is a junction type n-channel FET FET QA1 (plus-side first transistor). ) And FET QA2 (plus-side second transistor).

The negative dual FET 20 is also a negative dual transistor in which two FETs having the same characteristics and thermally coupled are accommodated in one package, and is a junction type p-channel FET FET QB1 (negative first transistor). ) And FET QB2 (negative side second transistor).

Here, the characteristics of the plus side dual FET 10 and the minus side dual FET 20 are not uniform.
In other words, (FET QA1, FET QA2) and (FET QA1, FET QA2)
QB1 and FET QB2) have different signal transmission characteristics.
The signal transfer characteristics refer to temperature drift such as gain, and symmetry and similarity of gain. This is due to difficulties in manufacturing the transistor and limitations in terms of manufacturing cost.

The source of the FET QA1 and the source of the FET QB2 are connected via a variable resistor VR1. The source of the FET QA2 and the source of the FET QB1 are connected via a variable resistor VR2.

Further, the gate of the FET QA1 and the FET QB
One gate is connected to form an input A terminal. The gate of the FET QA2 and the gate of the FET QB2 are connected to form an input B terminal.

The source of the FET Q3 is connected to the drain of the FET QA1, and the FET QA1 and the FET Q3 form a cascade circuit. The drain of the FET Q3 is connected to an output 1 terminal, which is one of the positive side output terminals, and a resistor R1 is further connected to the output 1 terminal. The other end of the resistor R1 is connected to a positive power supply.

The drain of the FET QA2 is connected to the source of the FET Q4, and the FET QA2 and the FET Q4 form a cascade circuit. The drain of the FET Q4 is connected to the output 2 terminal, which is one of the positive-side output terminals, and the resistor R2 is further connected to the output 2 terminal. The other end of the resistor R2 is connected to a positive power supply.

The drain of the FET QB1 is connected to the source of the FET Q5, and the FET QB1 and the FET Q5 form a cascade circuit. The drain of the FET Q5 is connected to the output 3 terminal, which is one of the minus-side output terminals, and a resistor R3 is further connected to the output 3 terminal. The other end of the resistor R3 is connected to a negative power supply.

The drain of the FET QB2 is connected to the source of the FET Q6, and the FET QB2 and the FET Q6 form a cascade circuit. The drain of the FET Q6 is connected to the output 4 terminal which is one of the minus side output terminals, and further connected to the resistor R4. The other end of the resistor R4 is connected to a minus power supply.

The gate of the FET Q3 and the gate of the FET Q4 are connected to each other, and further connected to a positive bias circuit including a resistor R5, a Zener diode D1, and a capacitor C1. Gate of FET Q5 and FET Q6
And a negative bias circuit including a resistor R6, a Zener diode D2, and a capacitor C2.

Thus, as a whole circuit, the plus side and the minus side exhibit a symmetrical connection form, and a current corresponding to the difference between the signal applied to the input A terminal and the signal applied to the input B terminal is output to one output terminal. , An output 2 terminal, an output 3 terminal, and an output 4 terminal.

The variable resistor VR1 or the variable resistor VR
By adjusting 2, output 1 terminal, output 2 terminal, output 3
With respect to the output of the terminal and the output of each of the four terminals, the DC output by the idling current and the symmetry and similarity of the differential gain can be matched with high accuracy and easily. It should be noted that the DC output by the idling current becomes the next stage bias voltage in the case of the direct connection amplifier.

The connection between the differential voltage / current conversion circuit shown in FIG. 1A and the complementary push-pull circuit shown in FIG. 1B is made, for example, by connecting two output terminals to the base of the bipolar transistor TR1. , And four output terminals are connected to the base of the bipolar transistor TR2.

(Operation Example) An operation example of the above-described apparatus example will be described with reference to the drawings. First, an outline of the operation will be described with reference to FIG.

Since the present differential voltage / current conversion circuit uses a self-bias, the idling current is set by the variable resistors VR1 and VR2. Here, the gate leakage current of the junction type FET changes with the fluctuation of the temperature and the voltage between the drain and the source. However, the change value of the leakage current is sufficiently smaller than the value of the idling current. FE
Since the difference between the leakage currents of T is smaller, such leakage current can be eliminated.

From this, in FIG. 1, current I1 = current I4 current I2 = current I3.

The variable resistor VR1 or the variable resistor VR
By finely adjusting 2, current I1 = current I2 = current I3 = current I4.

As a result, the bias voltage of each input of the next stage (complementary push-pull circuit) is determined by the resistances R1 and R2 connected to the output 1 terminal, output 2 terminal, output 3 terminal and output 4 terminal, respectively. , And the values of the resistors R3 and R4 are identical.

The values of the currents flowing through the FETs are the same, and the FETs QA1, FETA2,
1 and the FET QB2 are each thermally coupled, so that the similarity of the temperature drift of each output is also good. As described above, when the similarity of the temperature drift of each output is high, the junction type FET has a negative region / 0 with respect to the temperature characteristic.
Since the differential voltage / current conversion circuit has a point / positive region, the present differential voltage / current conversion circuit can contribute to guaranteeing the temperature of the next stage circuit.

Further, since current I1 = current I4, the transfer characteristic of one differential circuit in the present differential voltage / current conversion circuit is a combined characteristic of the transfer characteristics of FET QA1 and FET QB2. However, the drain cutoff current (IDSS) is limited by the FET of the lower FET, and the limiting pinch-off voltage is also limited by the FET of the smaller absolute value.

Next, details of the operation of the above-described apparatus will be described. Now, it is assumed that the input B terminal is grounded to the ground. The operation when the "plus" signal is input to the input A terminal is as follows.

First, the gate potential of the FET QA1 becomes higher, which increases the current I1 and the current I4.
The output 1 terminal is displaced to the minus side, and the output 4 terminal is displaced to the plus side. Here, since current I1 = current I4, the displacement at the output 1 terminal and the displacement at the output 4 terminal have the same value, which means that there is symmetry.

Conversely, the gate potentials of the FETs QA2 and QB2 become lower than the gate potentials of the FETs QA1 and QB1 and the currents I2 and I3 decrease, so that the output 2 terminal is displaced to the positive side and the output 3 terminal is displaced to the negative side. Is displaced. Here, since the current I2 = current I3, the displacement at the output 2 terminal and the displacement at the output 3 terminal have the same value, which means that there is symmetry.

When a "minus" signal is input to the input A terminal, the operation is reversed for the output 1 terminal and the output 4 terminal and for the output 2 terminal and the output 3 terminal. Is the same as when the "plus" signal is input.

As a result, the potentials of the output 1 terminal, the output 2 terminal, the output 3 terminal and the output 4 terminal respectively change in accordance with the potential difference between the input A terminal and the input B terminal, and operate as a differential circuit. You can see that there is.

The positive output (output 1 terminal, output 2 terminal) and the negative output (output 3 terminal, output 4 terminal) in the differential voltage / current conversion circuit are connected to a positive dual junction type FET 10 (FET QA1, FET QA2)
And the negative side dual junction type FET 20 (FET QB
1, FET QB2) is formed by a composite circuit connected in a cascade manner.

Therefore, when the same signal of the same phase is input to the input A terminal and the input B terminal, the FET QA1 and the FET Q
A2, there is no potential difference between any of the gate potentials of the FET QB1 and the FET QB2.
The potential of any of the terminal, the output 3 terminal and the output 4 terminal does not change.

Since the dual junction type FET has two FETs having the same characteristics accommodated in one package, the characteristics of the FETs QA1 and QA2 are very similar, and the characteristics of the FETs QB1 and QB2 are also very similar. I have. Further, since the plus side dual FET 10 and the minus side dual FET 20 are cross-connected in cascade and combined, the plus side output (output 1 terminal, output 2
The displacement characteristics of the negative output (terminal 3) and the negative output (output 4 terminal) are also approximated.

Therefore, the variable resistor VR1 or the variable resistor VR
2 can be easily adjusted so that current I1 = current I2 = current I3 = current I4 when an in-phase signal is input, and output 1 terminal, output 2 terminal, output The similarity and symmetry of each of the three terminals and the four terminals can be matched with high accuracy.

That is, the variable resistor VR1 or the variable resistor V
By finely adjusting either of R2, FET QA1, F
The same circuit as that in which the characteristics of the ETQA2, the FET QB1, and the FET QB2 are matched with extremely high precision, and the values of the resistors R1, R2, R3, and R4 that directly affect the output voltage are matched with very high precision. Becomes

Therefore, when the in-phase signal enters the input terminal A and the input terminal B, not only the AC component but also the DC component is not output from the output terminals 1 to 4, and the operating point of the next stage circuit fluctuates. Instead, it is possible to improve the amplification accuracy of the entire amplifier, reduce the manufacturing cost, and improve the ease of circuit design.

Next, the differential gain of the present differential voltage / current conversion circuit will be described with reference to FIGS. FIG.
FIG. 2 is a circuit diagram in which a differential circuit on one side is extracted from the differential voltage / current conversion circuit of FIG. The resistors VR1 ′ and VR1 ″ are obtained by virtually dividing the variable resistor VR1 in FIG. 1 into two. FIG. 3 shows an equivalent circuit obtained by further simplifying the differential circuit shown in FIG. It is a circuit diagram.

In FIG. 2, for simplicity of explanation, F
It is assumed that the transfer characteristic of ETQA1 is the same as that of FET QB2. Assume that a signal of +1 displacement is input to the input A terminal and a signal of -1 displacement is input to the input B terminal. Since this circuit is a differential circuit, (potential of input A terminal) − (potential of input B terminal) = 1−
A value corresponding to the displacement of (-1) = 2 is generated at each output terminal.

At this time, the resistor R1, FET Q3, FET
Since the plus side circuit consisting of QA1 and the resistor VR1 'and the minus side circuit consisting of the resistor R4, the FET Q6, the FET QB2 and the resistor VR1 "are symmetrical and the potentials of the output 1 terminal and the output 4 terminal are the same. The potential does not fluctuate when looking at the point C in Fig. 2. Therefore, when the circuit shown in Fig. 2 is simplified, the circuit shown in Fig. 3 is obtained.

The point C can be regarded as a virtual ground since the potential does not change. Therefore, since the FET QA1 in FIG. 3 is a common source circuit, its voltage amplification Av (output voltage / input voltage) is represented by the following equation (1). Note that gm1 is a mutual conductance of the FET QA1.

(Equation 1)

The above equation (1) indicates the voltage amplification in the state where the displacement of “2” occurs between the input terminals as described above. That is, since the above equation 1 indicates the voltage amplification degree of the circuit above the broken line (the circuit on the plus power supply side) in FIG. Is also halved. In other words, it shows the gain with respect to the input displacement from the point C. Since it is assumed that the circuit shown in FIG. 2 has an input signal of “input A−input B = 2”, the overall voltage amplification Av ′ of the differential circuit shown in FIG. Becomes half of the voltage amplification Av. Accordingly, the overall voltage amplification Av ′ of the differential circuit shown in FIG.

(Equation 2)

The voltage amplification Av ′ shown in the above equation (2) has four outputs (output 1, output 2, output 3, and output 4) of the differential circuit shown in FIG.
Output 4) Each gain becomes. In addition, FET QA1
When the transconductance gm1 of the FET QB2 is different from the transconductance gm1 of the FET QB2,
The characteristics of QA1 and FET QB2 are combined, and the transconductance gm is the slope of the transfer characteristic of the junction FET, so the transconductance gm of FET QA1 and FET QB2 is expressed by the following equation (3). [Equation 3] gm = (gm1 + gm2) ÷ 2

Next, a description will be given of the result of actually producing the present differential voltage / current conversion circuit and the conventional differential voltage / current conversion circuit and measuring the operations thereof. FIG. 4 is a circuit diagram showing a conventional differential voltage / current conversion circuit and measured values of respective parts thereof. FIG. 5 is a circuit diagram showing a differential voltage / current conversion circuit according to the present invention and measured values of respective parts thereof.

FIGS. 4 and 5 also show the type of each component of the circuit. Specifically, resistors R1, R2,
As R3, R4, R5, and R6, each having 1.6 [K ohm] error of 1% is used. Also, “2SK386” is used as the positive dual FET 10, and “2SJ1” is used as the negative dual FET 20.
09 ”is used. Further, the conventional differential voltage / current conversion circuit shown in FIG. 4 has a configuration slightly different from that of the conventional differential voltage / current conversion circuit shown in FIG.

In the circuit shown in FIG. 4 and the circuit shown in FIG. 5, the components denoted by the same reference numerals use the same components. This clarifies the difference in performance between the present differential voltage / current conversion circuit and the conventional differential voltage / current conversion circuit.

In the conventional differential voltage / current conversion circuit shown in FIG. 4, the source of the FET QA1 and the source of the FET QA2 are short-circuited, and the source of the FET QB1 and the FET QB2
Between the sources of the FETs QA1 and QA1
All of the source currents of the FETs QB1 and QB2
Of the source current. Thus, the idling current value of the entire conventional differential voltage / current conversion circuit shown in FIG. 4 becomes the same as the idling current value of the entire differential voltage / current conversion circuit shown in FIG.

Here, the conventional differential voltage / current conversion circuit shown in FIG. 4 and the present differential voltage / current conversion circuit shown in FIG.
It should be noted that the gain is different. This differential voltage /
Each output terminal (output 1 terminal, output 2 terminal, output 3 terminal, output 4 terminal) corresponds to the gain being compressed in the current conversion circuit.
The error between the terminals is also compressed. However, it is necessary to consider whether the comparison is performed with the plus side output (output 1 terminal, output 2 terminal) or the minus side output (output 3 terminal, output 4 terminal).

On the other hand, the drain cutoff current (IDSS) of the FET QA1 is 10.77 mA, the drain cutoff current (IDSS) of the FET QA2 is 10.93 mA, and the FET QB
1 has a drain cutoff current (IDSS) of 5.63 mA, F
The drain interruption current (IDSS) of ETQB2 is 5.44.
mA.

That is, the FET QA1 and the FET QB2
Compared with the pair of FETs QA2 and QB1, the pair of FETs QA1 and QB2 has a larger drain cutoff current (IDSS). Therefore, FIG.
For the differential voltage / current conversion circuit shown in FIG.
The combination of A1, FET QA2, FET QB1 and FET QB2 is the worst combination.

FIG. 6 is a diagram comparing output errors of the conventional circuit shown in FIG. 4 and the circuit according to the present invention shown in FIG. In this table, the column of “average value” indicates the average value of output 1, output 2, output 3 and output 4. The column of “output error” indicates a value obtained by subtracting each output value from the maximum value of outputs 1 to 4.

The column of "correction value of output error of circuit of the present invention" indicates a correction value obtained by multiplying the value of column of "output error of circuit of the present invention" by 3.63. Here, the reason for the 3.63 multiplication is that while the output value of the circuit of the present invention of FIG. 5 of the conventional circuit of FIG. .63).

In each of the differential voltage / current conversion circuits shown in FIGS. 4 and 5, the current I1 + current I2 is obtained up to the error of the resistors (resistor 1, resistor 2, resistor 3, and resistor 4) connected to each output terminal. = Current I3 + current I4.

However, as shown in the table of FIG. 6, the circuit according to the present invention has a smaller output error. In particular, regarding the differential gain, when comparing the plus side gain (output 1 or output 2) with the minus side gain (output 3 or output 4), it is considered that the magnitude of the gain is smaller in the circuit of FIG. However, the error of the circuit according to the present invention of FIG. 5 is smaller than that of the circuit of FIG. That is, the circuit according to the present invention shown in FIG. 5 has greatly improved symmetry with respect to the differential gain as compared with the conventional circuit shown in FIG.

Incidentally, as shown by the double underlined data in the table of FIG. 6, the correction value of the output error of the circuit of the present invention is:
Compared with the output error of the conventional circuit, the DC component is about 1/10,
The AC component is about 1/5, which indicates that the symmetry of the differential gain of the circuit of the present invention is greatly improved.

The reason why the symmetry of the differential gain has been improved is that the FET QA1 and the FET QB2 are connected in cascade in the differential voltage / current conversion circuit according to the present invention in FIG. FET QA2 and FET
This is because the QB1s are connected in cascade and their characteristics are combined.

On the other hand, in the conventional differential voltage / current conversion circuit of FIG. 4, the FET QA1 or the FET QA2 and the FE
The characteristics are not combined with TQB1 or FET QB2,
Differential synthesis of ETQA1 and FET QA2 and FET QB1
And the FET QB2 only operate differentially, so that the symmetry of the differential gain is inferior to the circuit of the present invention.

Therefore, at the next stage of the circuit according to the present invention,
When constructing a symmetrical circuit such as a complementary push-pull circuit, the error between the plus side gain and the minus side gain is not affected by the pairing property of the junction type FET, and the plus side gain and the minus side gain can be matched by simple adjustment. This is a feature of the circuit according to the present invention.

FIG. 7 is a circuit diagram showing another conventional differential voltage / current conversion circuit and another measurement result of each part thereof. FIG.
In the circuit shown in FIG. 5, the same reference numerals are used for the same components as those of the circuit according to the present invention shown in FIG.

The circuit shown in FIG. 7 has a smaller gain as a whole than the conventional circuit shown in FIG.
The output error of each output (output 1, output 2, output 3 and output 4) is substantially the same as that of the conventional circuit shown in FIG. That is, it is shown that the circuit according to the present invention of FIG. 5 has greatly improved symmetry with respect to the differential gain as compared with the conventional circuit shown in FIG.

Although the embodiments of the present invention have been described above, the present invention is not necessarily limited to the above-mentioned items, and can be appropriately modified and implemented within the scope of achieving the objects of the present invention and achieving the following effects. It is.

For example, in the above-described embodiment, a junction FET is used as an amplifying element, but a MOS FET, a bipolar transistor, or a vacuum tube may be used instead of the junction FET. In addition, the variable resistors VR1 for adjustment,
VR2 is composed of FET QA1 and FET QB as shown in FIG.
2 or between the FET QA2 and the FET QB1. In this case, the resistor R1,
The values of R2, R3, and R4 are also appropriately changed.

[0083]

As described above, according to the present invention,
The plus dual-type FET composed of two FETs with the same characteristics and the negative dual FET composed of two FETs with the same characteristics are cross-linked so that the characteristics of the two dual-type FETs are combined. Since the differential voltage / current conversion circuit is constructed by cascade connection, the DC output by idling current and the symmetry and similarity of the differential gain can be controlled with a simple circuit adjustment and high accuracy while suppressing temperature drift. Can be matched.

The differential voltage / current conversion circuit according to the present invention has two input terminals, two positive output terminals,
Since it has two minus side output terminals, it is possible to directly drive the complementary push-pull circuit, and it is possible to reduce distortion compared to the conventional one.

Therefore, the circuit becomes the first-stage circuit of the amplifier, and the distortion of the whole amplifier can be reduced while the negative feedback ratio of the whole amplifier is kept low.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
A differential voltage / current conversion circuit according to the present invention is shown, and (b) is a complementary push-pull circuit driven by (a).

FIG. 2 is a circuit diagram showing a differential circuit on one side in the circuit of FIG.

FIG. 3 is a circuit diagram showing an equivalent circuit obtained by further simplifying the differential circuit shown in FIG. 2;

FIG. 4 is a circuit diagram showing a conventional differential voltage / current conversion circuit and measured values of each part thereof.

FIG. 5 is a circuit diagram showing the differential voltage / current conversion circuit shown in FIG.

6 is a diagram comparing output errors of the conventional circuit shown in FIG. 4 and the circuit according to the present invention shown in FIG. 5;

FIG. 7 is a circuit diagram showing another conventional differential voltage / current conversion circuit and another measurement result of each part thereof.

FIG. 8 is a circuit diagram showing an example of a conventional differential voltage / current conversion circuit.

[Explanation of symbols]

1, 2, 3, 4 ... output 10 ... plus side dual FET (plus side dual transistor) 20 ... minus side dual FET (minus side dual transistor) 71, 72 ... constant current circuit A, B ... input C1, C2 ... capacitor D1, D2: Zener diode I1, I2, I3, I4: Current Q3, Q4: n-channel FET Q5, Q6: p-channel FET QA1: n-channel FET (positive first transistor) QA2: n-channel FET (positive-side FET) Q2: p-channel FET (minus-side first transistor) QB2: p-channel FET (minus-side second transistor) R1, R2, R3, R4, R5, R6, R7, R8: resistance C: point TR1, TR2 ... Bipolar transistors VR1, VR2, VR3 ... Variable resistors

Continued on the front page F term (reference) 5J066 AA02 AA12 CA02 CA11 CA21 FA16 FA20 HA08 HA09 HA10 HA17 HA18 HA20 HA25 HA26 HA29 KA05 KA12 MA17 MA24 ND05 ND11 ND21 PD02 SA05 5J069 AA02 AA12 CA02 CA11 CA21 FA16 FA20 HA18 HA10 HA10 HA10 HA10 HA10 HA10 HA10 HA10 HA10 HA10 HA20 HA26 HA29 KA05 KA12 MA17 MA24 SA05 5J091 AA02 AA12 CA02 CA11 CA21 FA16 FA20 HA08 HA09 HA10 HA17 HA18 HA20 HA25 HA26 HA29 KA05 KA12 MA17 MA24 SA05

Claims (5)

[Claims] 1. A plus dual transistor in which a plus first transistor (QA1) and a plus second transistor (QA2), which are two transistors having the same characteristics, are housed in one package. A differential voltage / current conversion circuit comprising: a negative dual transistor in which two aligned transistors, that is, a negative first transistor (QB1) and a negative second transistor (QB2) are housed in one package. And substantially all of the current flowing through the plus-side first transistor (QA1) is substantially equal to the minus-side second transistor (QA1).
B2), the plus-side first transistor (QA1) and the minus-side second transistor (QB2) are connected in cascade so that the current flows through the plus-side second transistor (QA2). The whole is the negative side first transistor (Q
B1), the plus-side second transistor (QA2) and the minus-side first transistor (QB1) are connected in cascade so as to flow through the operation control terminal of the plus-side first transistor (QA1) and the minus side. An operation control end of the first side transistor (QB1) is connected to form an input A terminal, and an operation control end of the second side transistor (QA2) and an operation control end of the second side transistor (QB2) are connected. Connected to form an input B terminal; a positive output terminal is connected to at least one of the current inflow ends of the positive first transistor (QA1) and the positive second transistor (QA2); A negative output terminal is connected to at least one of the current inflow ends of one transistor (QB1) and the negative second transistor (QB2). A differential voltage / current conversion circuit characterized by the following. 2. A differential voltage / current conversion circuit comprising: a first variable resistor (VR1) for limiting an amount of current flowing through the plus first transistor (QA1) and the minus second transistor (QB2). And a second variable resistor (VR2) for limiting the amount of current flowing through the plus-side second transistor (QA2) and the minus-side first transistor (QB1). The differential voltage / current conversion circuit according to claim 1. 3. The positive side first transistor (QA1).
And the plus-side second transistor (QA2) is an n-channel junction FET, and the minus-side first transistor (QB1) and the minus-side second transistor (QB2) are each a p-channel junction. The first variable resistor (VR1) is disposed between the source terminal of the positive first transistor (QA1) and the source terminal of the negative second transistor (QB2); The resistor (VR2) is arranged between the source end of the plus-side second transistor (QA2) and the source end of the minus-side first transistor (QB1). Differential voltage / current conversion circuit. 4. The positive side first transistor (QA1).
Is connected to a third junction type FET (Q
3) are connected in cascade, and a drain terminal of the third junction type FET (Q3) has an output 1 terminal forming one of the plus side output terminals and a first output terminal.
One end of the resistor (R1) is connected, the other end of the first resistor (R1) is connected to a plus power supply, and the drain end of the plus second transistor (QA2) is n The fourth junction type FET (Q
4) are cascaded, and a drain terminal of the fourth junction type FET (Q4) has two output terminals, one of the positive side output terminals, and a second output terminal.
One end of a resistor (R2) is connected, and the other end of the second resistor (R2) is connected to the plus side power supply. The third junction type FET (Q3) and the fourth junction type FE
A positive bias circuit for supplying a constant positive voltage is connected to the gate terminal of T (Q4), and a p-channel junction FET is connected to the drain terminal of the negative first transistor (QB1). Fifth junction FET (Q
5) are connected in cascade, and a drain terminal of the fifth junction type FET (Q5) is connected to three output terminals forming one of the minus side output terminals and one end of a third resistor (R3). The other end of the third resistor (R3) is connected to a negative power supply, and the drain end of the negative second transistor (QB2) is connected to a sixth p-channel junction FET. Junction FET (Q
6) are connected in cascade, and a drain terminal of the sixth junction type FET (Q6) is connected to four output terminals forming one of the minus side output terminals and one end of a fourth resistor (R4). The other end of the fourth resistor (R4) is connected to the minus power supply, and the fifth junction type FET (Q5) and the sixth junction type FE
The differential voltage / current conversion circuit according to claim 3, wherein a negative bias circuit for supplying a negative constant voltage is connected to a gate terminal of T (Q6). 5. The differential voltage / current conversion circuit functions as a circuit for driving a complementary push-pull circuit, and one of the output 1 terminal and the output 2 terminal is provided with the complementary push-pull circuit. The positive input terminal of the pull circuit is connected, and the negative input terminal of the complementary push-pull circuit is connected to one of the output 3 terminal and the output 4 terminal. 5. The differential voltage / current conversion circuit according to 4.