JP2002319759A - Method for producing flexible printed circuit board - Google Patents
Method for producing flexible printed circuit boardInfo
- Publication number
- JP2002319759A JP2002319759A JP2001122781A JP2001122781A JP2002319759A JP 2002319759 A JP2002319759 A JP 2002319759A JP 2001122781 A JP2001122781 A JP 2001122781A JP 2001122781 A JP2001122781 A JP 2001122781A JP 2002319759 A JP2002319759 A JP 2002319759A
- Authority
- JP
- Japan
- Prior art keywords
- conductive portion
- base film
- insulating base
- conductive
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＣＳＰ（Chip Siz
e Package）やＢＧＡ（Ball Grid Array）やＬＧＡ（La
nd Grid Array）などの例えばＬＳＩを実装するパッケ
ージのための片面フレキシブル回路基板として使用され
るフレキシブルプリント回路基板の製造方法に関する。The present invention relates to a CSP (Chip Siz
e Package), BGA (Ball Grid Array), LGA (La
The present invention relates to a method of manufacturing a flexible printed circuit board used as a single-sided flexible circuit board for a package on which an LSI is mounted, such as an nd grid array.
【０００２】[0002]
【従来の技術】ＬＳＩの小型・高性能化と多層プリント
回路基板の高精密化に伴い、そのインターポーザとして
のパッケージも超小型化傾向にある。片面フレキシブル
回路基板を使用してのＣＳＰ、ＢＧＡ、ＬＧＡパッケー
ジなどでは、片面フレキシブル回路基板の絶縁ベースフ
ィルムに設けられた多数のスルホール内に金属メッキ処
理にて導電部を充填形成し、絶縁ベースフィルムの表側
の回路パターンと裏側の半田ボール等とをスルホール内
の導電部を介して電気接続している。2. Description of the Related Art With the miniaturization and high performance of LSIs and the high precision of multilayer printed circuit boards, packages as interposers are also becoming ultra-miniaturized. For CSP, BGA, LGA packages, etc. using a single-sided flexible circuit board, the conductive parts are filled and formed by metal plating in many through holes provided in the insulating base film of the single-sided flexible circuit board. The circuit pattern on the front side and the solder balls and the like on the back side are electrically connected via a conductive portion in the through hole.
【０００３】多数のスルホール内に金属メッキ処理にて
導電部を充填形成する場合、従来は次のようにして行っ
ていた。図１０および図１１に示すように、多数のスル
ホール５１およびパーホレーション５２を設けたポリイ
ミドによるテープ状絶縁ベースフィルム５３の表側に、
回路パターンを形成することになる銅箔５４を接着剤５
５にて接着した後、スルホール５１から離れたところを
給電部として給電し、銅箔５４を通じてメッキ個所であ
るスルホール５１へ電気が通ずることで、スルホール５
１内に銅メッキによる導電部５６を充填形成する。Conventionally, when a conductive portion is filled and formed in a large number of through holes by metal plating, it has been performed as follows. As shown in FIGS. 10 and 11, on the front side of a tape-shaped insulating base film 53 made of polyimide provided with a large number of through holes 51 and perforations 52,
The copper foil 54 for forming the circuit pattern is bonded to the adhesive 5
After bonding at 5, power is supplied as a power supply portion away from the through hole 51, and electricity passes through the copper foil 54 to the through hole 51, which is a plating location, so that the through hole 5
1 is filled with a conductive portion 56 formed by copper plating.
【０００４】この場合、多数のスルホール５１は碁盤目
状に明けられているので、両側のスルホール５１ほど電
流密度が高く、内側のスルホール５１ほど電流密度が低
くなるため、両側のスルホール５１ほど導電部５６の厚
さが厚く、内側のスルホール５１ほど導電部５６の厚さ
が薄くなるバラツキを生ずる。In this case, since a large number of through holes 51 are cut in a grid pattern, the through holes 51 on both sides have a higher current density and the inner through holes 51 have a lower current density. The thickness of the conductive portion 56 is varied such that the thickness of the conductive portion 56 decreases as the through hole 51 on the inner side increases.
【０００５】このバラツキは避けられないため、従来
は、半田ボールでの信頼性確保の観点から、全ての導電
部５６が絶縁ベースフィルム５３の裏面から突出しない
ような条件にして、金属メッキ処理によりスルホール５
１への穴埋めメッキを行っていた。[0005] Since this variation is unavoidable, conventionally, from the viewpoint of ensuring the reliability of the solder balls, metal plating is performed under the condition that all the conductive portions 56 do not protrude from the back surface of the insulating base film 53. Surhole 5
No. 1 was filled with plating.
【０００６】[0006]
【発明が解決しようとする課題】しかし、このように少
な目に穴埋めメッキすると、内側のスルホール５１内の
導電部５６の厚さが、絶縁ベースフィルム５３の裏面か
ら見て寸法足らずになって許容範囲を満たさなくなって
しまい、図１２に示すように、絶縁ベースフィルム５３
の表側で銅箔５４による回路パターンにＬＳＩ５７を接
続して封止樹脂５８で封止し、絶縁ベースフィルム５３
の裏側で導電部５６に半田ボール５９を接続し、これを
マザーボード６０上の被覆メッキ６１が施された銅箔６
２に溶着させたパッケージ完成状態において、導電部５
６の厚さが許容範囲を満たしていないスルホール５１ａ
において、半田ボール５９との接続不良が生ずる恐れが
あった。However, if plating is carried out to a small extent in this way, the thickness of the conductive portion 56 in the inner through-hole 51 becomes smaller than the dimension as viewed from the back surface of the insulating base film 53, and thus the allowable range is reduced. Are not satisfied, and as shown in FIG.
The LSI 57 is connected to the circuit pattern formed by the copper foil 54 on the front side of the circuit board and sealed with the sealing resin 58.
The solder balls 59 are connected to the conductive portions 56 on the back side of the copper foil 6 on the mother board 60 on which the coating plating 61 is applied.
In the completed state of the package welded to
6. The through hole 51a whose thickness does not satisfy the allowable range.
In this case, there is a possibility that a connection failure with the solder ball 59 may occur.
【０００７】本発明の目的は、スルホール内の導電部の
厚さのバラツキを極力少なくでき、その厚さが許容範囲
を満たしていないことによる半田ボールとの接続不良を
無くして、半田ボールの接続信頼性を向上させることに
ある。SUMMARY OF THE INVENTION It is an object of the present invention to minimize the variation in the thickness of the conductive portion in the through hole and eliminate the connection failure with the solder ball due to the thickness not satisfying the allowable range. The purpose is to improve reliability.
【０００８】[0008]
【課題を解決するための手段】本発明は、絶縁ベースフ
ィルムに設けられた多数のスルホール内に金属メッキ処
理にて導電部を充填形成し、絶縁ベースフィルムの表側
の回路パターンと裏側の半田ボール等とをスルホール内
の導電部を介して電気接続するフレキシブルプリント回
路基板の製造方法において、金属メッキ処理は、少なく
とも一部のスルホールにおいて導電部が絶縁ベースフィ
ルムの裏面から突出する程度とし、その突出した導電部
については突出部分を一様に平滑にすることを特徴とす
る。もちろん、全てのスルホールにおいて、導電部が絶
縁ベースフィルムの裏面から突出するようにしても構わ
ない。SUMMARY OF THE INVENTION According to the present invention, a plurality of through holes provided in an insulating base film are filled with conductive portions by metal plating to form a circuit pattern on the front side of the insulating base film and solder balls on the back side. In a method of manufacturing a flexible printed circuit board for electrically connecting a conductive part and the like via a conductive part in a through hole, the metal plating treatment is performed such that the conductive part protrudes from the back surface of the insulating base film in at least a part of the through hole. The conductive portion is characterized in that the protruding portion is uniformly smoothed. Of course, in all the through holes, the conductive portion may project from the back surface of the insulating base film.
【０００９】導電部の突出部分を平滑にすることは、切
削、研磨、圧潰、又はエッチングのいずれによる方法、
あるいはそれらの方法を複数組み合わせることでも行え
る。[0009] The smoothing of the protruding portion of the conductive portion can be performed by any of cutting, polishing, crushing, or etching.
Alternatively, it can be performed by combining a plurality of these methods.
【００１０】突出した導電部について突出部分を平滑に
した後の各導電部の厚さは、絶縁ベースフィルムの厚さ
に対して−３０μｍ〜＋３０μｍとすることが好まし
い。It is preferable that the thickness of each conductive portion after smoothing the protruding portion is -30 μm to +30 μm with respect to the thickness of the insulating base film.
【００１１】[0011]
【発明の実施の形態】次に、本発明の実施の形態を図面
に従って詳細に説明する。Next, embodiments of the present invention will be described in detail with reference to the drawings.
【００１２】先ず、図１に示すように、厚さが例えば５
０μｍのポリイミドのテープ状絶縁ベースフィルム１の
表側に、厚さが１２μｍの熱硬化性の接着剤２で保護フ
ィルム３を接着しておき、図２に示すように、０．１５
〜０．２５φの大きさの多数のスルホール４を碁盤目状
に明けるとともに、絶縁ベースフィルム１の両側縁に沿
ってパーホレーション５を明ける。First, as shown in FIG.
A protective film 3 is bonded to the front side of a 0 μm polyimide tape-like insulating base film 1 with a thermosetting adhesive 2 having a thickness of 12 μm, and as shown in FIG.
A large number of through holes 4 having a size of about 0.25φ are formed in a grid pattern, and perforations 5 are formed along both side edges of the insulating base film 1.
【００１３】次に、図３に示すように、保護フィルム３
を剥がしてから接着剤２上に銅箔６を熱圧着した後、図
４に示すように、絶縁ベースフィルム１の裏側におい
て、多数のスルホール４内に金属メッキ処理、例えば銅
メッキ処理にて導電部７を充填形成する。その銅メッキ
処理は、バラツキを見越して、少なくとも一部のスルホ
ール４（両側のスルホール４）において導電部７が絶縁
ベースフィルム１の裏側の面から突出する程度に行う。
これにより、導電部７が絶縁ベースフィルム１の裏側の
面から突出するスルホール４ａと、絶縁ベースフィルム
１の裏側の面に一致するスルホール４ｂと、僅かに満た
ないスルホール４ｃが生ずる。もちろん、全てのスルホ
ール４において、導電部７が絶縁ベースフィルム１の裏
側の面から突出するようにしても構わない。Next, as shown in FIG.
After the copper foil 6 is thermocompression-bonded on the adhesive 2, as shown in FIG. 4, on the back side of the insulating base film 1, a large number of through holes 4 are subjected to metal plating treatment, for example, copper plating treatment. The part 7 is formed by filling. The copper plating process is performed so that the conductive portion 7 protrudes from the back surface of the insulating base film 1 in at least some of the through holes 4 (the through holes 4 on both sides) in anticipation of variation.
Thereby, a through hole 4a in which the conductive portion 7 protrudes from the back surface of the insulating base film 1, a through hole 4b corresponding to the back surface of the insulating base film 1, and a slightly less through hole 4c are generated. Of course, in all the through holes 4, the conductive portion 7 may protrude from the surface on the back side of the insulating base film 1.
【００１４】次いで、絶縁ベースフィルム１の裏側の面
から突出している導電部７ａについて、その突出部分を
切削、研磨、圧潰、又はエッチング、あるいはそれらの
組合せにより突出部分を平滑にして、図５に示すよう
に、絶縁ベースフィルム１の裏側の面と面一（絶縁ベー
スフィルム１と同じ厚さ）、又はわずかに凹んだ状態、
あるいはわずかに突出した状態にする。Next, with respect to the conductive portion 7a protruding from the back surface of the insulating base film 1, the protruding portion is smoothed by cutting, polishing, crushing, or etching, or a combination thereof, and FIG. As shown, flush with the surface on the back side of the insulating base film 1 (the same thickness as the insulating base film 1), or in a slightly concave state,
Alternatively, it is set in a slightly protruding state.
【００１５】切削は、フライスやエンドミルなどで行
い、研磨は、砥石や砥粒入りブラシなどで行い、圧潰
（フラットニング）は、プレス機や金型にて押し潰し、
エッチングは塩化第ニ鉄などのエッチング液で平にす
る。突出している導電部７ａを平滑にすることにより、
各導電部７を絶縁ベースフィルム１の厚さに対して−３
０μｍ〜＋３０μｍの範囲内に収める。The cutting is performed by a milling machine or an end mill, the polishing is performed by a grindstone or a brush containing abrasive grains, and the crushing (flattening) is crushed by a press machine or a mold.
The etching is made flat with an etching solution such as ferric chloride. By smoothing the protruding conductive portion 7a,
Each conductive portion 7 is -3 with respect to the thickness of the insulating base film 1.
Within the range of 0 μm to +30 μm.
【００１６】次に、図６示すように、絶縁ベースフィル
ム１の裏側を樹脂コート８にて保護し、絶縁ベースフィ
ルム１の表側において銅箔６上にフォトレジスト９を施
し、エッチングおよび剥離により回路パターンを形成す
る。この後、図７に示すように、絶縁ベースフィルム１
の表裏両側において被覆メッキ処理して、回路パターン
を形成する銅箔６上と導電部７に仕上げメッキ１０・１
１を施す。Next, as shown in FIG. 6, the back side of the insulating base film 1 is protected by a resin coat 8, a photoresist 9 is applied on the copper foil 6 on the front side of the insulating base film 1, and the circuit is etched and peeled off. Form a pattern. Thereafter, as shown in FIG.
Of the front and back surfaces of the copper foil 6 for forming a circuit pattern and the conductive portion 7 by finish plating 10.1
Apply 1.
【００１７】次に、図８に示すように、回路パターン上
にＬＳＩ１２を実装して封止樹脂１３で保護するととも
に、導電部７の仕上げメッキ１１に半田ボール１４を添
付してモジュールとなす。そして、このようにテープ上
に複数形成したモジュールをテープから金型で打ち抜
き、個々のモジュールに分ける。Next, as shown in FIG. 8, an LSI 12 is mounted on the circuit pattern and protected by a sealing resin 13, and a solder ball 14 is attached to the finish plating 11 of the conductive portion 7 to form a module. Then, a plurality of modules formed on the tape in this manner are punched out of the tape with a mold and divided into individual modules.
【００１８】最後に、図９に示すように、このモジュー
ルの半田ボール１４をマザーボード１５上の銅箔１６の
被覆メッキ１７に溶着して、このモジュールをマザーボ
ード１５上に実装し、完成状態とする。なお、半田ボー
ル１４に代えて半田ペーストでもよい。Finally, as shown in FIG. 9, the solder balls 14 of the module are welded to the plating 17 of the copper foil 16 on the motherboard 15, and the module is mounted on the motherboard 15 to complete the module. . Note that solder paste may be used instead of the solder ball 14.
【００１９】[0019]
【発明の効果】本発明によれば、絶縁ベースフィルムに
設けられた多数のスルホール内に金属メッキ処理にて導
電部を充填形成する場合、少なくとも一部のスルホール
において導電部が絶縁ベースフィルムの裏面から突出す
る程度に金属メッキ処理し、その突出した導電部につい
ては突出部分を一様に平滑にするので、スルホール内の
導電部の厚さのバラツキを極力少なくできる。したがっ
て、その厚さが許容範囲を満たしていないことによる半
田ボールとの接続不良を無くして、半田ボールの接続信
頼性を向上させることができる。According to the present invention, when a conductive portion is filled and formed in a large number of through holes provided in an insulating base film by metal plating, the conductive portion is formed on at least a part of the through holes on the back surface of the insulating base film. Since the metal plating is performed to such an extent that the conductive portion protrudes from the conductive portion and the protruding portion of the protruding portion is uniformly smoothed, the thickness variation of the conductive portion in the through hole can be minimized. Therefore, connection failure with the solder ball due to the thickness not satisfying the allowable range can be eliminated, and the connection reliability of the solder ball can be improved.
【図１】本発明による製造方法において、絶縁ベースフ
ィルム上に接着剤にて保護フィルムを接着する工程の断
面図である。FIG. 1 is a cross-sectional view of a step of bonding a protective film on an insulating base film with an adhesive in a manufacturing method according to the present invention.
【図２】同じく、絶縁ベースフィルムにスルホールおよ
びパーホレーションを明ける工程の断面図である。FIG. 2 is also a cross-sectional view showing a step of forming through holes and perforations in an insulating base film.
【図３】同じく、絶縁ベースフィルム上に銅箔を熱圧着
する工程の断面図である。FIG. 3 is a cross-sectional view of a step of thermocompression bonding a copper foil on an insulating base film.
【図４】同じく、スルホール内に銅メッキ処理にて導電
部を充填形成する工程の断面図である。FIG. 4 is also a cross-sectional view of a step of filling and forming a conductive portion in a through hole by copper plating.
【図５】同じく、導電部の突出部分を平滑にする工程の
断面図である。FIG. 5 is also a cross-sectional view showing a step of smoothing a protruding portion of a conductive portion.
【図６】同じく、銅箔上にフォトレジストを形成する工
程の断面図である。FIG. 6 is a sectional view of a step of forming a photoresist on a copper foil.
【図７】同じく、回路パターンを形成する銅箔およびス
ルホールに充填形成した導電部に仕上げメッキを施す工
程の断面図である。FIG. 7 is also a cross-sectional view showing a step of subjecting a copper foil forming a circuit pattern and a conductive portion filled in a through hole to finish plating.
【図８】同じく、回路パターン上にＬＳＩを実装し、ス
ルホールに充填形成した導電部に半田ボールを添付する
工程の断面図である。FIG. 8 is a cross-sectional view of a process of mounting an LSI on a circuit pattern and attaching a solder ball to a conductive portion filled in a through hole.
【図９】同じく、図８の状態から打ち抜いたモジュール
をマザーボード上に実装する工程の断面図である。9 is a sectional view of a step of mounting a module punched from the state of FIG. 8 on a motherboard, similarly.
【図１０】従来の製造方法において、スルホール内の導
電部を形成する工程の断面図である。FIG. 10 is a cross-sectional view of a step of forming a conductive portion in a through hole in a conventional manufacturing method.
【図１１】同上の裏面図である。FIG. 11 is a rear view of the above.
【図１２】従来の製造方法において、モジュールをマザ
ーボード上に実装する工程の断面図である。FIG. 12 is a cross-sectional view of a step of mounting a module on a motherboard in a conventional manufacturing method.
１ 絶縁ベースフィルム ２ 接着剤 ３ 保護フィルム ４ スルホール ５ パーホレーション ６ 銅箔 ７ 導電部 ７ａ 突出した導電部 ８ 樹脂コート ９ フォトレジスト １０・１１ 仕上げメッキ １２ ＬＳＩ １３ 封止樹脂 １４ 半田ボール １５ マザーボード １６ 銅箔 １７ 被覆メッキ DESCRIPTION OF SYMBOLS 1 Insulation base film 2 Adhesive 3 Protective film 4 Through hole 5 Perforation 6 Copper foil 7 Conductive part 7a Protruding conductive part 8 Resin coat 9 Photoresist 10.11 Finish plating 12 LSI 13 Sealing resin 14 Solder ball 15 Motherboard 16 Copper foil 17 Coating plating
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5E317 AA24 AA27 BB01 CC31 CC52 CD01 CD25 CD27 GG01 GG07 5E319 AA03 AA08 AB05 AC03 AC11 BB04 CC22 CD02 GG03 5E343 AA02 AA07 AA12 AA33 BB09 BB24 BB61 BB71 DD43 EE42 EE43 EE52 EE58 GG06 GG18 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 5E317 AA24 AA27 BB01 CC31 CC52 CD01 CD25 CD27 GG01 GG07 5E319 AA03 AA08 AB05 AC03 AC11 BB04 CC22 CD02 GG03 5E343 AA02 AA07 AA12 AA33 BB09 BB24 BB61 BB71 EE EE EE EE EE
Claims (7)
スルホール内に金属メッキ処理にて導電部を充填形成
し、絶縁ベースフィルムの表側の回路パターンと裏側の
半田ボール等とをスルホール内の導電部を介して電気接
続するフレキシブルプリント回路基板の製造方法におい
て、前記金属メッキ処理は、少なくとも一部のスルホー
ルにおいて前記導電部が前記絶縁ベースフィルムの裏面
から突出する程度とし、その突出した導電部については
突出部分を一様に平滑にすることを特徴とする、フレキ
シブルプリント回路基板の製造方法。A conductive portion is filled and formed by metal plating in a large number of through holes provided in an insulating base film, and a circuit pattern on a front side of the insulating base film and a solder ball or the like on a back side are connected to the conductive portion in the through hole. In the method for manufacturing a flexible printed circuit board that is electrically connected via, the metal plating treatment is such that the conductive portion protrudes from the back surface of the insulating base film in at least a part of the through hole, and the protruding conductive portion is A method for manufacturing a flexible printed circuit board, wherein a protruding portion is uniformly smoothed.
は、切削にて行うことを特徴とする、請求項１に記載の
フレキシブルプリント回路基板の製造方法。2. The method according to claim 1, wherein the smoothing of the protruding portion of the conductive portion is performed by cutting.
は、研磨にて行うことを特徴とする、請求項１に記載の
フレキシブルプリント回路基板の製造方法。3. The method according to claim 1, wherein the smoothing of the protruding portion of the conductive portion is performed by polishing.
は、圧潰にて行うことを特徴とする、請求項１に記載の
フレキシブルプリント回路基板の製造方法。4. The method according to claim 1, wherein the smoothing of the projecting portion of the conductive portion is performed by crushing.
は、エッチングにて行うことを特徴とする、請求項１に
記載のフレキシブルプリント回路基板の製造方法。5. The method according to claim 1, wherein the smoothing of the protruding portion of the conductive portion is performed by etching.
は、切削、研磨、圧潰、又はエッチングのいずれか２つ
以上を組み合わせて行うことを特徴とする、請求項１に
記載のフレキシブルプリント回路基板の製造方法。6. The flexible print according to claim 1, wherein the smoothing of the projecting portion of the conductive portion is performed by a combination of two or more of cutting, polishing, crushing, and etching. A method for manufacturing a circuit board.
にした後の各導電部の厚さを、前記絶縁ベースフィルム
の厚さに対して−３０μｍ〜＋３０μｍとすることを特
徴とする、請求項１、２、３、４、５又は６に記載のフ
レキシブルプリント回路基板の製造方法。7. The thickness of each conductive part after smoothing the protruding part of the protruding conductive part is -30 μm to +30 μm with respect to the thickness of the insulating base film. 7. The method for manufacturing a flexible printed circuit board according to 1, 2, 3, 4, 5, or 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001122781A JP2002319759A (en) | 2001-04-20 | 2001-04-20 | Method for producing flexible printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001122781A JP2002319759A (en) | 2001-04-20 | 2001-04-20 | Method for producing flexible printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002319759A true JP2002319759A (en) | 2002-10-31 |
Family
ID=18972440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001122781A Pending JP2002319759A (en) | 2001-04-20 | 2001-04-20 | Method for producing flexible printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002319759A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004273495A (en) * | 2003-03-05 | 2004-09-30 | Tdk Corp | Electronic component and method of manufacturing the same |
| CN102006723A (en) * | 2009-08-31 | 2011-04-06 | 三星电机株式会社 | A printed circuit board having a bump and a method of manufacturing the same |
| JP2014082441A (en) * | 2012-10-15 | 2014-05-08 | Samsung Electro-Mechanics Co Ltd | Multi-layer type coreless substrate and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06334344A (en) * | 1993-05-19 | 1994-12-02 | Kyocera Corp | Manufacture of ceramic wiring board |
| JPH0917828A (en) * | 1995-04-28 | 1997-01-17 | Asahi Denka Kenkyusho:Kk | Circuit board |
| JPH1154926A (en) * | 1997-06-06 | 1999-02-26 | Ibiden Co Ltd | One-sided circuit board and its manufacture |
| JP2002084064A (en) * | 2000-09-08 | 2002-03-22 | Ibiden Co Ltd | Manufacturing method of printed board |
| JP2002111200A (en) * | 2000-09-26 | 2002-04-12 | Ibiden Co Ltd | Method for manufacturing printed board |
-
2001
- 2001-04-20 JP JP2001122781A patent/JP2002319759A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06334344A (en) * | 1993-05-19 | 1994-12-02 | Kyocera Corp | Manufacture of ceramic wiring board |
| JPH0917828A (en) * | 1995-04-28 | 1997-01-17 | Asahi Denka Kenkyusho:Kk | Circuit board |
| JPH1154926A (en) * | 1997-06-06 | 1999-02-26 | Ibiden Co Ltd | One-sided circuit board and its manufacture |
| JP2002084064A (en) * | 2000-09-08 | 2002-03-22 | Ibiden Co Ltd | Manufacturing method of printed board |
| JP2002111200A (en) * | 2000-09-26 | 2002-04-12 | Ibiden Co Ltd | Method for manufacturing printed board |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004273495A (en) * | 2003-03-05 | 2004-09-30 | Tdk Corp | Electronic component and method of manufacturing the same |
| CN102006723A (en) * | 2009-08-31 | 2011-04-06 | 三星电机株式会社 | A printed circuit board having a bump and a method of manufacturing the same |
| JP2014082441A (en) * | 2012-10-15 | 2014-05-08 | Samsung Electro-Mechanics Co Ltd | Multi-layer type coreless substrate and method of manufacturing the same |
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