JP2002319649A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, capable of being miniaturized and lowering a price by mounting an LSI on a single layer wiring board, and to provide manufacturing a package. SOLUTION: The semiconductor device is provided with a resin substrate 200, provided with a first surface and a second surface on the opposite side of the first surface and provided with a through-hole passing through the first surface and the second surface, metal wirings 204 and 208 formed on the first surface of the resin substrate 200 so as to cover the through-hole at a part; an insulation sheet 231 provided on an area corresponding to the through-hole of the metal wiring 204 and 208; a semiconductor chip 240 loaded on the area corresponding to the through-hole of the insulation sheet 231 and provided with a plurality of electrodes electrically connected to the part exposed from the insulation sheet 231 of the metal wirings 204 and 208; and solder balls 234 and 238 formed on the second surface side of the resin substrate 200 and connected to the metal wiring 204 and 208 exposed inside the through-hole.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI package, and more particularly, to a semiconductor device having substantially the same size as an LSI chip.

[0002]

2. Description of the Related Art Conventionally, this type of package has a μ-BG
A, chip size package, CSP, etc. are called by various names, and various types of chip size packages have been developed.

Such a second chip size package is described in, for example, a practical lecture “VLSI Packaging Technology (Lower)”, published by Nikkei BP, May 3, 1993.
There were those described on page 174 a day.

FIG. 11 is an overall sectional view showing such a conventional chip size package mounted on a ceramic substrate.
FIG. 12 is an enlarged sectional view of a portion A in FIG. 11.

As shown in these figures, an LSI chip 1
A stud bump 3 made of Au is formed on the aluminum electrode 2 of this embodiment, and this is flip-chip bonded to a ceramic substrate 5 having a two-layer wiring.

The upper wiring layer 7 and the lower wiring layer 8 of the ceramic substrate 5 are connected by a via hole 6. The ceramic substrate 5 and the stud bumps 3 are made of an AgPd paste 4
The AgPd paste 4 is electrically connected to the via hole 6 of the ceramic substrate 5. The LSI chip 1 and the ceramic substrate 5 are fixed by a sealing resin 9 injected between them. A land 8A is formed on the back surface of the ceramic substrate 5 and is electrically connected to the via hole 6, and the land 8A is connected to an external wiring.

Further, after wire bonding the LSI to the two-layer printed circuit board, the side on which the LSI is mounted is molded, and an area-shaped solder bump is formed on the back surface of the package. ).

[0008]

However, in the above-described conventional structure, the mounting of the LSI on the wiring board requires two steps.
The use of a multilayer ceramic substrate results in a high price. Further, in order to eliminate the influence of the expansion coefficient of the ceramic and the like, the thickness of the ceramic needs to be 0.4 mm or less, which is too thin for a stable operation.

There are also the following problems.

(1) The adhesion between the printed circuit board (epoxy resin in the above document) and the mold resin is poor, and peeling often occurs from the joint surface between the two.

(2) Due to the difference in the coefficient of thermal expansion between the printed circuit board and the mold material, the package is warped during reflow, making reliable mounting impossible.

(3) Since the two-layer printed circuit board is mounted on the wiring board, the price is relatively high.

(4) A mold is required for the mold, and a mold release agent must be added to the mold material (the adhesion between the mold resin and the substrate, wiring metal, etc. becomes poor).

(5) Heat radiation is not good.

(6) Since a printed circuit board (epoxy resin in the literature) is used, it cannot be used for applications exceeding the heat resistance of the printed circuit board.

[0016] There are a number of problems such as this, and although it is called a technology that follows the field of fine pitch QFP that has not been achieved, its general practical application is still in danger.

An object of the present invention is to provide a semiconductor device which eliminates the above problems, uses a single-layer wiring board, has a simplified structure, and can be kept at a low price.

[0018]

According to the present invention, there is provided a semiconductor device having a first surface and a second surface opposite to the first surface. A resin substrate provided with a through-hole penetrating the first surface and the second surface; and a resin substrate formed on the first surface of the resin substrate so as to partially cover the through-hole. A metal wiring, an insulating sheet provided on a region of the metal wiring corresponding to the through hole, and mounted on a region of the insulating sheet corresponding to the through hole, and exposed from the insulating sheet of the metal wiring A semiconductor chip having a plurality of electrodes electrically connected to portions thereof, and a solder ball formed on the second surface side of the resin substrate and connected to the metal wiring exposed in the through hole. It is characterized by including.

[2] The semiconductor device according to [1], wherein the resin substrate is a single-layer substrate.

[3] The semiconductor device according to [1] or [2], wherein the resin substrate is a glass epoxy substrate.

[4] The semiconductor device according to the above [1] or [2], wherein the resin substrate is a polyimide film.

[5] Any one of the above [1] to [4]
Item 13. The semiconductor device according to Item 1, wherein the electrode of the semiconductor chip is connected to the metal wiring via a wire.

[6] In the semiconductor device, a through hole having a first surface and a second surface opposite to the first surface, penetrating the first surface and the second surface. And a metal wiring formed on the first surface of the resin substrate so as to partially cover the through-hole, and a plurality of bump electrodes connected to the metal wiring. A semiconductor chip mounted on the first surface corresponding to the through hole of the resin substrate, and an insulating sheet covering the metal wiring excluding a region connected to the bump electrode;
A solder ball formed on the second surface side of the resin substrate and connected to the metal wiring exposed in the through hole.

[7] In the semiconductor device according to the above [6], a portion of the metal wiring corresponding to the through hole is located in a region of the resin substrate where the semiconductor chip is mounted.

[8] In the semiconductor device according to the above [6], a portion of the metal wiring connected to the bump electrode is arranged near a periphery of the resin substrate.

[0026]

[9] The semiconductor device according to [6], wherein the resin substrate has substantially the same shape as the semiconductor chip.

[10] In the semiconductor device, the first surface, the second surface opposite to the first surface, and the first surface.
A resin substrate having a through-hole penetrating from the surface of the second surface to the second surface, a first end and a second end disposed inside the first end, A metal wiring formed on the first surface side of the resin substrate such that an end covers the through hole, an insulating resin that covers the metal wiring such that the first end of the metal wiring is exposed, The first surface of the metal wiring is mounted on the first surface side of the resin substrate.
And a solder ball provided in the through-hole and connected to the second end of the metal wiring exposed from the through-hole. Characteristic semiconductor device.

[11] The semiconductor device according to the above [10], wherein the second end of the metal wiring is covered with the insulating resin.

[12] In a semiconductor device, a through hole having a first surface and a second surface opposite to the first surface, penetrating the first surface and the second surface. And a metal wiring formed on the first surface of the resin substrate and partially projecting toward the second surface through the through hole; and A plurality of bump electrodes connected to the metal wiring, and a semiconductor chip mounted on the first surface side of the resin substrate.

[13] In the semiconductor device according to the above [12], a portion of the metal wiring corresponding to the through hole is located in a region of the resin substrate where the semiconductor chip is mounted.

[14] In the semiconductor device according to the above [13], a portion of the metal wiring connected to the bump electrode is arranged near a periphery of the resin substrate.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view of a single-layer resin substrate for mounting an LSI according to a first embodiment of the present invention, FIG. 2 is a sectional view taken along line AA 'of FIG. 1, and FIG. It is sectional drawing of the small package which has.

Here, in order to mount the LSI, for example, a single-layer resin substrate is used. Although not necessarily limited to resin, resin substrates are currently inexpensive and desirable.

In FIG. 1, reference numeral 100 denotes a resin substrate for supporting a wiring layer, and a polyimide film or a glass epoxy substrate is used. 50 μm for polyimide film
The thickness before and after is common. In the case of a glass epoxy board, an ordinary printed board can be used.

.., 108 are:
A copper wiring board electrically connected to each electrode of the LSI by wire bonding (not necessarily copper), and a thickness of about 35 μm is often used. 101 is connected to a land 111, 102 is connected to a land 112, and 103 is connected to a land 113. Others are the same.

The dashed line 121 in the land 111
Are holes formed in the resin portion of the resin substrate 100 (therefore, the copper lands 111 are exposed on the back surface of the resin substrate 100).

Similarly, the holes 122, 123,..., 128 are exposed on the back surface of the resin substrate 100. 130 corresponds to a die pad in the lead frame. Thus, the copper wiring boards 101, 102, 10
3, ..., 108, lands 111,112,113, ...,
118, die pad 130, and die pad 130
Are formed with openings 131 and the like.

In order to better understand the resin substrate used in this embodiment, as shown in FIG. 2, the resin is also removed immediately below a die pad (metal plate, for example, a copper plate) 130 to form an opening 131. The formation of the hole 131 is not always necessary in the present invention.

As shown in FIG. 3, an LSI 140 is mounted on the die pad 130 of the resin substrate 100 thus prepared.
, And wire bonding from the electrodes of the LSI 140 to the copper wiring boards 101, 102, 103,... Next, molding is performed with a molding resin 143 to protect the LSI 140, the wires 141, 142 and the like.

Finally, the solder ball 1 is formed by a very ordinary method.
52, 153 with holes 121, 122, 123, 124,
, 128 to form a single package. If the LSI particularly requires heat radiation, a die pad (metal) 15 such as solder is also provided on the back surface of the die pad 130.
1 can be installed and thermally connected to the wiring board to improve the heat radiation effect.

In FIG. 3, the molding is performed using the molding resin 143. In this case, the entire surface may be molded. A so-called potting agent may be simply potted. 141 is a wire bonded from the electrode of the LSI 140 to the copper wiring board 104, and 142 is a wire bonded from the electrode of the LSI 140 to the copper wiring board 108.

The solder balls 152 are connected to the lands 114.
The solder balls 153 are connected to the lands 118.

FIG. 4 is a plan view of a single-layer resin substrate for mounting an LSI according to a second embodiment of the present invention, and FIG. 5 is a sectional view of a small package (FIG. 4) in which the LSI is mounted on the resin substrate.
(Sectional view corresponding to line BB 'of FIG. 3). Hereinafter, description of the same parts as in the first embodiment will be omitted.

In the first embodiment, the solder balls 152 and 153 for connecting to the wiring board exist around the LSI 140. However, in order to further reduce the size of the package, in the second embodiment, most of the solder balls are L
Install immediately below SI.

As shown in these figures, copper wiring board 201
Lands 211, 214, and 218 at the tip of
It exists directly below 40. Reference numerals 221, 224, and 228 denote holes formed in the resin on the lands 211 (the same as in the first embodiment). In this embodiment, the copper wiring board 202 is L
It is not directly below SI240. The land 214 connected to the copper wiring board 204 exists immediately below. The same applies hereinafter. 4 indicate the copper wiring boards 201, 203, 204, and 2.
05, 207 and 208 are insulating sheets applied.

The LSI 24 is provided on the insulating sheet 231 of this substrate.
After the die bonding of No. 0 is performed, and then the wire bonding and the molding resin 243 are applied, the solder balls 238 and 234 are arranged in the holes 228 and 224 from the resin side (the back surface in the present invention) of the resin substrate 200. In FIG. 5, 2
41 and 242 are wires.

FIG. 6 is a plan view of a single-layer resin substrate for mounting an LSI according to a third embodiment of the present invention, and FIG. 7 is a cross-sectional view of a small package having the LSI mounted on the resin substrate (FIG. 6).
(C-C 'line section) of FIG.

In this embodiment, bumps are formed on an LSI to be mounted, mounted temporarily on a substrate by a flip chip method to form a chip size package, and then mounted on the circuit board.

In FIG. 6, as described above, reference numeral 300 denotes a resin substrate, which is formed, for example, by attaching a metal plate to an insulating layer and processing the metal plate into a desired shape by etching or the like. The LSI 350 is mounted on a portion surrounded by a dotted line. 308 are metal wiring boards made of processed copper or the like, and L
A wire is bonded from each electrode of SI350.

311, 312, 313, 314,... 31
8 is a metal wiring board 301, 302, 303, 3 respectively
The lands are electrically connected to the lands 04,... 308, and are installed inside the dotted line 350. 321,322,32
3,324, ... 328 are lands 311,312,31
318 are holes formed only in the insulating layer, and the copper plate is exposed on the side where the LSI is not mounted.

A dashed line 341 is an insulating sheet adhered to the substrate, and the lands 311, 312, 313, 31
4, ... 318 are installed inside.

FIG. 7 shows a state in which the LSI 350 is flip-chip mounted on such a substrate.
It is sectional drawing which follows the C 'line. In the figure, 344, 34
Reference numeral 8 denotes a solder ball formed on the LSI 350;
Solder balls 334 and 338 are provided at portions 24 and 328, respectively. Resin mold if necessary.

Next, a fourth embodiment of the present invention will be described.

In the fourth embodiment, a method of processing a part of a wiring board of a package to form connection terminals without using solder balls or the like for electrical connection between a chip size package and an external circuit will be described.

FIG. 8 is a plan view of a single-layer resin substrate for mounting an LSI according to a fourth embodiment of the present invention, FIG. 9 is a sectional view taken along the line DD 'of FIG. 8, and FIG. It is sectional drawing of the small package which has.

As shown in these figures, reference numeral 400 denotes an insulating substrate for supporting a wiring board, and wiring boards 401, 402, 403,.
An LSI is connected to 408 or the like. 421, 422, 42
.. 428 are holes formed in the insulating plate.
411 is a terminal connected to the wiring board 401 and connected to an external circuit. 414 is a terminal connected to the wiring board 404 and connected to an external substrate. Similarly, 418 is a terminal connected to the wiring board 408 and connected to an external circuit.

The terminal 411 is floating in the air at the hole 421. The terminal 414 is suspended at the hole 424.
Terminals 418 are suspended in holes 428. Others are the same. Such a structure can be easily manufactured by ordinary techniques. For example, a metal plate is stuck on an insulating substrate with holes formed in advance,
This may be etched from the surface.

Next, these terminals floating in the air are processed.
This processing can also be easily realized by ordinary means. Terminal 41
4,418 are deformed so as to be easily connected to an external circuit.

FIG. 10 shows a state in which the LSIs are connected, but the insulating sheet and the mold resin are not shown and are omitted to clarify the main parts.

Reference numerals 454 and 458 denote bumps formed on the LSI 450, which are connected to the wiring boards 404 and 408.

Further, the following utilization forms can be adopted.

(1) In the above embodiment, an example in which one LSI is mounted on a (resin) substrate has been described for ease of description. However, a plurality of LSIs can be mounted, and chip components and the like can be mounted simultaneously. It is also possible.

(2) After mounting a plurality of LSIs and chip components on a substrate, each of them may be cut off during the process or at the end.

(3) When the solder balls were provided, the solder resist was not described, but this was because the insulating layer portion of the substrate also served as the resist layer, so that the solder resist layer was applied again. You may.

(4) In the second embodiment, an insulating sheet was used. This insulating sheet can be replaced with an adhesive for die bonding the LSI.

(5) Although bumps are used in the third embodiment, the bumps may be made of gold, copper, or the like, or may be made of lead-tin solder. In addition, the insulation sheet has the role of a solder dam that prevents the bumps from melting and flowing out during connection,
When gold, copper, or the like was used, it was not particularly required.

(6) In the fourth embodiment, the LSI is flip-chip mounted. However, the present invention is not limited to this mounting method, and another mounting method such as wire bonding may be used. Further, the connection place with the external circuit does not always need to be directly below the LSI.

Further, the description has been given of the case where the tip of the wiring of the single-layer wiring board is processed to be a connection terminal. However, it is not always necessary to have the tip, and the middle part is floated on an opening (through hole). It may be processed.

Next, a fifth embodiment of the present invention will be described.

FIGS. 13 to 18 are configuration diagrams showing a fifth embodiment of the present invention, and FIG. 13 is a block diagram showing a fifth embodiment of the present invention.
FIG. 14 is a perspective view showing an SI mounting substrate, and FIG.
FIG. 15 is a plan view of the LSI mounting substrate, and FIG. 16 is a sectional view of a small package manufacturing process showing a fifth embodiment of the present invention.

In FIG. 13, reference numeral 500 denotes a metal substrate, for example, a Kovar plate or a copper plate, which has a thickness of 30 to 100 μm. LSIs 511, 512, 5
13, 514, 515, 516,... Are regularly die-bonded. For example, the interval L ₁ between the LSI 511 and the LSI 512 and the interval L ₂ between the LSI 511 and the LSI 514 are known. The angles of each other are also known. 501,50
.. Are reference holes for bonding. The positional relationship between the reference holes 501, 502,... And each LSI is known.

Also, 521, 522, 523,..., 53
Reference numerals 1536 denote wires extending from the respective pads (electrodes) of the LSI 511 to the metal substrate 500. These are due to ordinary wire bonds. Similarly, 541,
, 556 are wires connecting each pad of the LSI 512 and the metal substrate 500, and 561,.
, 571 are wires bonded from the LSI 514 to the metal substrate 500.

The circle 610 shown by the dotted line is the metal substrate 50.
0 indicates that the wire 52
1 is connected. Similarly, the wire 522 is connected to the circle 611, and the wire 523 is connected to the circle 612. The wire 563 is provided on the circular portion 631, and the wire 57 is provided on the circular portion 632.
1 is connected. Each circle has a known position.

As described above, the metal substrate 500
After die bonding and wire bonding, a resin (here, epoxy resin) was applied to the entire surface. In FIG. 14, reference numeral 650 denotes a resin, which was heated and cured while pressing the resin.

In this step, the metal substrate 500 was set in a hot press and pressed from its surface (this step is not shown because it is easy to understand).

Since no mold is used this time, the resin 650 and the metal substrate 500, and the resin 650 and the LSI
The coupling agent for improving the adhesion to 511, 512, 513,... Could be sufficiently utilized. No release agent was added to the resin 650.

The type of metal, especially its coefficient of thermal expansion, thickness,
Depending on the dimensions, stress may occur between the resin and the resin at a value higher than the allowable value, and an undesirable state may occur. A method of cutting the metal substrate 500 in advance and allowing the resin to shrink was also effective.

A thin epoxy sheet is inserted between the hot press and the resin 650 at the time of pressing, and the sheet is left as it is when the sheet is bonded to the resin 650.
No stripping operation was performed.

At the time of pressing, a spacer was inserted between the metal substrate 500 and the pressing plate, and the mixture was cured at a pressure of 15 kg / cm ² and a temperature of 80 ° C. for a pressing time of 1 hour. The thickness of the resin could be controlled by the size of the spacer, and the resin was cured by pressure, so that no irregularities on the surface due to the presence of LSI or the like were generated.

Next, an attempt was made to etch the metal substrate 500 into a desired shape. Since a normal metal is used for the metal substrate 500, an existing technique can be used for the etching. For example, a dry film is applied to the surface of the metal substrate 500, developed using a mask, and unnecessary portions are removed with an etchant. The positioning was performed using reference holes 501, 502, and so on. When the metal substrate 500 is made of copper, a good etching solution using iron chloride, tin chloride or the like has been developed. The same applies to other metals such as Kovar.

FIG. 15 shows the metal substrate after the etching is completed. Reference numeral 511A denotes a portion on the back surface on which the LSI 511 of FIG. 1 is mounted, which corresponds to a die pad of a lead frame. In FIG. The same applies to 512A, 513A,...

The wire 521 is provided on the back surface of the circular portion 610.
(See FIG. 13) are connected. A wire 522 (see FIG. 13) is connected to the back surface of the circular portion 611. The same applies to other circles.

FIG. 16 is a process sectional view after the etching of the metal substrate. That is, FIG. 14 is a cross-sectional view along the line AA ′ in FIG.

First, as shown in FIG.
511 and 514 are sealed with a resin 650.

Next, as shown in FIG. 16 (b), in order to connect the solder balls to all the above-mentioned circle portions, a portion other than the connection portions of these circle portions is coated with a solder resist 701.

Next, as shown in FIG. 16 (c), the solder balls 702, 70
After forming No. 3, cutting is performed along the dashed lines C1, C3,..., C2, C4, C6, C8,.

Next, in order to improve the heat radiation of the LSI, as shown in FIG.
It is also possible to apply solder or the like to A,... To improve the thermal contact with the substrate. Here, a situation in which the material 704 having good heat conductivity is provided together with the solder balls is shown.

FIG. 17 shows an LSI showing a sixth embodiment of the present invention.
FIG. 4 is a plan view of the mounting substrate of FIG.

In FIG. 17, reference numeral 1000 denotes a support, on which metal pieces (rectangular portions) 1210, 1220, 1212
30, 1240, 1250, 1260, and metal pieces (circular portions) 1010, 1020,... 1050,. As an example of the manufacturing method, reference numeral 1000 denotes a Kapton tape to which an adhesive as a support is applied, and after attaching a metal substrate to the Kapton tape, an arrangement of metal pieces as shown in FIG.

Next, the LSI is placed on the metal piece 1210 as shown in FIG.
Similarly, wire bonding is performed on metal pieces 1010, 1020,..., 1050. The same applies to the metal pieces 1220, 1230,...

Further, after the epoxy resin is sufficiently applied to the entire surface, the resin is cured while being pressed and heated by a hot press as already described in the first embodiment. Next, similarly, as shown in the fifth embodiment, the application of the solder resist and the installation of the solder balls are performed, and then, C shown by the dashed line in FIG.
, C2, C4, C6, C8, etc. are cut.

FIG. 18 shows an LSI showing a seventh embodiment of the present invention.
19 is a cross-sectional view taken along the line FF 'in FIG. Here, the description will be made with reference to FIG. 18, but the same applies to other small package regions. In this embodiment, the metal piece also serves as a wiring.

In this figure, the metal piece 4030 has LS
The wire from the pad of I is bonded,
No solder ball is set on the back surface of the “0”. Metal piece 403
0 reaches the metal piece 4032 via the wiring 4031 connected thereto. The wiring 4031 passes directly below the LSI. A solder ball for mounting is formed on the back surface of the metal piece 4032.

Also, a wire from the LSI pad is bonded to the metal piece 4060, but reaches the metal piece 4062 through the wiring 4061, and a solder ball is formed on the back surface of the metal piece 4062. Similarly, a wire is connected to the metal piece 4110, but no solder ball is formed on the back surface of the metal piece 4110, reaches the metal piece 4112 through the wiring 4111 connected thereto, and the solder ball is Is installed.

Here, the work of obtaining the shape of the metal piece is performed by an LSI.
Before mounting or after the resin is cured. L
In order to fix the SI, the width of the wirings 4111, 4031, etc. can be designed to be wide, and a metal piece that is not electrically connected is set in a place corresponding to the area of 4210 ', 4220',. (Not shown).

In the cross section of FIG. 19, 4100 is a solder resist, 4406 and 4416 are wires, and 4514 is L
SI, 4650 is a mold resin.

The epoxy resin mold, the application of the solder mask, the installation of the solder balls, the cutting of the resin, and the like are exactly the same as those in the fifth and sixth embodiments. FIG. 19 shows a cross section of a main part at a location corresponding to the line FF 'in FIG. In FIG. 19, reference numerals 4060 and 4061 denote solder balls.

20 to 22 are configuration diagrams showing an eighth embodiment of the present invention. FIG. 20 is a perspective view of a mounting board of the LSI, FIG. 21 is a rear view of FIG. 20, and FIG. G-
It is G 'line sectional drawing.

In this embodiment, a so-called multi-chip module system will be described.

The LSI 4020, the LSI 4030, and the chip component 4040 are mounted on the BGA.
500.

In the steps of this embodiment, the LSI 4020, the LSI 4030, and the chip
(The metal plate 4010 is the same as that in the fifth embodiment, and is not shown in the present embodiment). Die bonding is performed as shown in FIG. However, in this step, the substrate is 4010, and the wiring pattern as shown in the figure has not been formed yet. Perform mounting work as it is formed. The die bonding process can be performed by a completely ordinary connection technique.

Next, wire bonding is performed from the pads of the LSI 4020 and the LSI 4030 to the metal plate 4011 at predetermined positions. The procedure of this wire bond is the same as that of the fifth embodiment. Further, the multilayer wiring portion 4500 is formed by a bonding technique or the like.

The order of bonding of the LSI, the chip components, and the wires does not matter.

These LSI 4020 and LSI 4030,
A chip component 4040, a multilayer wiring 4500, and a group of a large number of bonded wires are regularly formed on a metal plate 4010 as shown in FIG.

Next, as in the fifth embodiment, an epoxy resin 4650 is applied to the entire surface and heated and pressed by a hot press to cure the epoxy resin. Further, the metal plate 4010
Is also etched from the exposed side in the same steps as in the fifth embodiment. FIG. 21 shows the state after the etching process.

In FIG. 21, LSIs 4020 and 4030 are connected to the surface opposite to the surfaces 4071 and 4072. Reference numeral 4040 denotes a chip component. Other substrate 4010
Is etched to form metal pieces 4401, 4402,
4403, 4404, 4405, 4406,...

In this BGA, connection solder balls are provided at both ends of the completed module. Based on this policy, a solder resist was applied by an existing method, and then solder balls were installed. Further, a dashed line C of FIG.
, C3, C5,..., C2, C4, C6, C8.

As shown in FIG. 22, solder balls 4031 and 4033,
A solder resist 4100 is formed.

FIG. 23 is an LSI showing a ninth embodiment of the present invention.
FIG. 24 is a cross-sectional view (cross section taken along line HH 'of FIG. 23) of a small package showing a ninth embodiment of the present invention.

In this embodiment, the BGA connection solder balls are arranged directly below the LSI.

As in the fifth embodiment, a plurality of LSIs are die-bonded to a metal substrate (not shown), but before the dice bonding, the insulating sheets 5210, 5220,.
It is glued to the place where SI is installed. (FIG. 23 is a view after the metal piece 1010 is etched.
The relationship between 1021 and the insulating sheet 5210 can be understood from this figure).

After the die bonding of the LSI, FIG.
Metal pieces 1010, 1020, 1030, 104 shown in FIG.
Wire bonding is performed from each pad of the LSI at each location of 0, 1050,... This step is almost the same as in the first embodiment. Further, an epoxy resin is applied (not shown), and the resin is cured by heating and pressing.

Next, the metal plate 4010 is etched as shown in FIG. In this figure, metal piece 1
020 (the wire is connected to the back surface)
1 and continues to the metal piece 1022 immediately below the LSI 1021. A solder ball is placed on the metal piece 1022 later. The same applies to the metal piece 1122.

After the solder balls are set, the dashed line C in FIG.
.., C2, C4, C6, C8,.

Further, the following utilization forms can be adopted.

In the fifth embodiment, the material of the metal substrate is made of copper or Kovar. However, the material is not limited to these metals, and a copper alloy or a completely different metal can be used. Nor does it specify.

The same applies to the other examples of the metal substrate. Also, the thickness is not limited.

In the embodiments of the present invention, the mounting of the LSI has been described by wire bonding, but it is needless to say that other methods such as a flip chip method can be used.

Also, an epoxy resin has been described as a molding material for molding an LSI or the like. Depending on the usage conditions, for example, in an atmosphere requiring heat resistance, a heat-resistant epoxy resin, a polyimide resin, or the like should be used.

In the fifth embodiment, the resin film is inserted between the hot press and the resin at the time of pressing, but this prevents adhesion between the resin to be cured and the press, and is the same in other embodiments. . Instead of a resin film, paper or the like may be used. Often unnecessary.

In the above embodiment, it has been described that the module is connected to the outside by solder balls. However, depending on the situation, lead wires and lead terminals can be connected instead of solder balls, and a mounting method similar to a so-called leadless package is also possible.

With the above-described configuration, it is possible to set the connection point by the solder ball at the most efficient place.

In the conventional method using a lead frame, L
Since the pads of the SI correspond to the pins of the package as they are, there is no freedom in design, and as a result, it is often necessary to largely route the wiring of the printed circuit board on which the LSI is mounted. Also, in the case of BGA, if the arrangement is changed inside the BGA, the total number of printed boards increases, which leads to an increase in price.

With the structure of the present invention, the arrangement of the connection points can be easily changed.

Further, it is possible to obtain an MCM (multi-chip module) that does not use a printed circuit board. In recent years, with the development of electronic devices, there are many demands for installing a low-cost MCM near, for example, an engine of an automobile. Conventional FR-
A module consisting of four substrates has a problem in heat resistance and the like, and cannot be mounted.

Further, the MCM according to the present invention can cope sufficiently.

Further, it is easier to manufacture than a normal BGA. Also, since a printed circuit board is not used, warpage does not easily occur during mounting, which is convenient for mounting.

Further, the present invention is not limited to the above-described embodiment, and various modifications are possible based on the gist of the present invention, and they are not excluded from the scope of the present invention.

[0130]

As described above, according to the present invention, the following effects can be obtained.

(1) A package can be manufactured without forming bumps on an LSI, and the cost can be reduced because a single-layer wiring board is used.

Further, since the LSI is mounted on the single-layer wiring board and the package is manufactured, the size can be reduced and the price can be reduced.

(2) Since the terminals are formed around the LSI, in addition to the configuration of the above (1), a sufficient interval between the terminals can be ensured and a reliable connection can be made.

(3) The bumps formed on the single-layer wiring board are
Since it is arranged within the area of the SI, in addition to the configuration of the above (1), the degree of integration can be increased and the size can be reduced.

(4) Since the LSI is mounted on a single-layer wiring board having a substantially LSI area to produce a package, the size can be reduced and the price can be reduced.

(5) Since the electrode portion protruding from the opening of the single-layer wiring board at the tip or in the middle of the metal wiring board is formed, it is possible to increase the degree of integration and obtain a low-priced chip size package. Can be.

Further, since no solder ball is used, the connection portion is hardly damaged. It is also convenient for device evaluation before mounting.

(6) Many small packages can be manufactured at low cost by simple steps.

(7) A small package (BGA) can be obtained without using a conventional printed circuit board.

(8) Since a printed board is not used, there is no fear of peeling off the epoxy resin from the board. Since a so-called mold is not used, there is no need to add a release agent to the epoxy resin, and a coupling agent that improves the adhesion between the metal and the epoxy resin can be sufficiently used.

Therefore, the connection between the resin and the metal and the connection between the resin and the LSI can be ensured, and a small package with high reliability can be obtained.

Signals passed through wires from the pads of the LSI reach the solder balls for direct connection, so that the connection distance can be shortened and a small package with good electrical characteristics can be obtained.

Since the number of processes and the materials are small, a low-cost package can be obtained.

Since no mold is required, initial investment is small.

Further, when the resin is cured, since a metal piece has already been formed, the generation of stress due to the difference in the coefficient of thermal expansion between the resin and the metal is extremely small.

[Brief description of the drawings]

FIG. 1 is a plan view of a single-layer resin substrate for mounting an LSI according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA ′ of FIG. 1;

FIG. 3 is a sectional view of a small package having a resin substrate according to the first embodiment of the present invention.

FIG. 4 is a plan view of a single-layer resin substrate for mounting an LSI according to a second embodiment of the present invention.

FIG. 5 is a cross-sectional view (cross-section corresponding to line BB ′ in FIG. 4) of a small package in which an LSI is mounted on a resin substrate according to a second embodiment of the present invention.

FIG. 6 is a plan view of a single-layer resin substrate for mounting an LSI according to a third embodiment of the present invention.

FIG. 7 is a cross-sectional view (a cross-section corresponding to line CC ′ in FIG. 6) of a small package in which an LSI is mounted on a resin substrate according to a third embodiment of the present invention.

FIG. 8 is a plan view of a single-layer resin substrate for mounting an LSI according to a fourth embodiment of the present invention.

FIG. 9 is a sectional view taken along the line DD ′ of FIG. 8;

FIG. 10 is a sectional view of a small package having a resin substrate according to a fourth embodiment of the present invention.

FIG. 11 is an overall sectional view showing a conventional chip size package mounted on a ceramic substrate.

FIG. 12 is an enlarged sectional view of a portion A in FIG. 11;

FIG. 13 is a perspective view showing an LSI mounting board according to a fifth embodiment of the present invention.

FIG. 14 is a sectional view taken along line EE ′ of FIG. 13;

FIG. 15 is a plan view of an LSI mounting board according to a fifth embodiment of the present invention.

FIG. 16 is a sectional view showing a manufacturing process of a small package according to a fifth embodiment of the present invention.

FIG. 17 is a plan view of an LSI mounting board according to a sixth embodiment of the present invention.

FIG. 18 is a plan view of an LSI mounting board according to a seventh embodiment of the present invention.

FIG. 19 is a sectional view taken along line FF ′ of FIG. 18;

FIG. 20 is a perspective view of an LSI mounting board according to an eighth embodiment of the present invention.

FIG. 21 is a rear view of FIG. 20;

FIG. 22 is a sectional view taken along line GG ′ of FIG. 20;

FIG. 23 is a plan view of an LSI mounting board according to a ninth embodiment of the present invention.

FIG. 24 is a cross-sectional view (cross-section corresponding to line HH ′ in FIG. 23) of a small package showing a ninth embodiment of the present invention.

[Explanation of symbols]

100, 200, 300 Resin substrate 101-108, 201-208 Copper wiring board 111-118, 211, 214, 218, 311-3
18 lands 121 to 128, 221, 224, 228, 321 to 3
28,421-428 holes 130,151,511A, 512A, 513A, ... 5
16A die pad 131 opening 140, 240, 350, 450, 511-516, 1
021, 4020, 4030, 4514 LSI 141, 142, 241, 242, 521, 522, 5
23, ... 531,536,541,542,543,
..., 556, 561, ... 563, ... 571, 4406,
4416 Wire 143, 243, 4650 Mold resin 152, 153, 234, 238, 334, 338, 7
02,703,4031,4033 Solder balls 231,341,5210,5220, ..., 5260
Insulating sheet 301-308 Metal wiring board 344, 348, 454, 458 Bump 400 Insulating substrate 401-408 Wiring board 411, 414, 418 Terminal 500 Metal substrate 501, 502 ... Reference hole 610, 611, 612, 614, 620, 621 , 6
31,632 Circular portion 650,4650 Resin 701,4100 Solder resist 704 Good thermal conductive material 1000 Kapton tape (support) 1010,1020,1022,1050,1160,
1210, 1220, 1230, 1240, 1250,
1260, 4030, 4032, 4060, 4062
4110, 4112, 4401, 4402,... 4406
Metal pieces 1031, 1061, 1111, 4031, 4061
4111 wiring 4011 metal plate 4040 chip component 4500 multilayer wiring

Claims (14)

[Claims] (A) a first surface having a first surface and a second surface opposite to the first surface, and a through-hole penetrating the first surface and the second surface; Resin substrate,
(B) a metal wiring formed on the first surface of the resin substrate so as to partially cover the through hole; and (c) a metal wiring provided on a region corresponding to the through hole of the metal wiring. An insulating sheet, and (d) a semiconductor chip mounted on a region corresponding to the through hole of the insulating sheet and having a plurality of electrodes electrically connected to a portion of the metal wiring exposed from the insulating sheet; (E) a solder ball formed on the second surface side of the resin substrate and connected to the metal wiring exposed in the through hole. 2. The semiconductor device according to claim 1, wherein said resin substrate is a single-layer substrate. 3. The semiconductor device according to claim 1, wherein said resin substrate is a glass epoxy substrate. 4. The semiconductor device according to claim 1, wherein said resin substrate is a polyimide film. 5. The semiconductor device according to claim 1, wherein said electrode of said semiconductor chip is:
A semiconductor device connected to the metal wiring via a wire. 6. A through hole having a first surface and a second surface opposite to the first surface, and penetrating the first surface and the second surface. Resin substrate,
(B) a metal wiring formed on the first surface of the resin substrate so as to partially cover the through hole, and (c) a plurality of bump electrodes connected to the metal wiring, and the resin A semiconductor chip mounted on the first surface corresponding to the through hole of the substrate; (d) an insulating sheet covering the metal wiring excluding a region connected to the bump electrode; and (e) the resin substrate. And a solder ball formed on the second surface side and connected to the metal wiring exposed in the through hole. 7. The semiconductor device according to claim 6, wherein a portion of said metal wiring corresponding to said through hole is located in a region of said resin substrate where said semiconductor chip is mounted. 8. The semiconductor device according to claim 6, wherein a portion of the metal wiring connected to the bump electrode is disposed near a periphery of the resin substrate. 9. The semiconductor device according to claim 6, wherein said resin substrate has substantially the same shape as said semiconductor chip. 10. A resin substrate having a first surface, a second surface opposite to the first surface, and a through-hole penetrating from the first surface to the second surface. And (b) a first end and a second end disposed inside the first end, wherein the second end of the resin substrate covers the through-hole so that the second end covers the through hole. A metal wiring formed on the surface side of 1;
(C) an insulating resin covering the metal wiring so that the first end of the metal wiring is exposed; and (d) an insulating resin mounted on the first surface side of the resin substrate, And (e) a solder ball provided in the through hole and connected to the second end of the metal wiring exposed from the through hole. A semiconductor device characterized by including: 11. The semiconductor device according to claim 10, wherein said second end of said metal wiring is covered with said insulating resin. (A) a first surface having a first surface and a second surface opposite to the first surface, wherein the first surface and the second surface are provided;
A resin substrate provided with a through-hole penetrating the surface of the
(B) a metal wiring formed on the first surface of the resin substrate, a part of which protrudes toward the second surface through the through hole; and (c) the metal wiring on the first surface. A semiconductor chip provided with a plurality of bump electrodes connected to metal wiring and mounted on the first surface side of the resin substrate. 13. The semiconductor device according to claim 12, wherein a portion of said metal wiring corresponding to said through hole is located in a region of said resin substrate on which said semiconductor chip is mounted. 14. The semiconductor device according to claim 13, wherein a portion of the metal wiring connected to the bump electrode is disposed near a periphery of the resin substrate.