JP2002314087A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is formed on an SOI substrate, exhibits less variation in reverse breakdown voltage, and is low in on- resistance. SOLUTION: The semiconductor device comprises a first semiconductor layer 3 of first conductivity type formed on a first insulating film 2 on a semiconductor substrate 1; a second semiconductor layer 9 of second conductivity type formed on the surface of the first semiconductor layer 3; a third semiconductor layer 11 of the first conductivity type formed on the surface of the first semiconductor layer 3; a fourth semiconductor layer 12 of the first conductivity type formed under the third semiconductor layer 11; and a fifth semiconductor layer 13 of the first conductivity type discretely formed between the second semiconductor layer 9 and the third semiconductor layer 11. When a positive high voltage is applied to the third semiconductor layer 11, a depletion layer extending from the first insulating film 2 toward the third semiconductor layer 11 and a depletion layer extending from the second semiconductor layer 9 toward the third semiconductor layer 11 are substantially matched with each other in the degree of extension, and stable reverse breakdown voltage characteristics are obtained at low on-resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device formed on an SOI substrate.

[0002]

2. Description of the Related Art A semiconductor device using dielectric isolation (including SOI) can fundamentally solve problems such as leakage current of a PN junction and malfunction of a parasitic transistor, which were problems in PN junction isolation. In particular, it is promising for application to high breakdown voltage semiconductor devices, semiconductor devices for analog switches, and the like.

Hereinafter, a conventional semiconductor device will be described with reference to the drawings. Conventional semiconductor devices, for example,
It is disclosed in Japanese Patent Publication No. 2896141.

FIG. 5 shows the structure of an n-type high voltage MOS transistor which is a conventional semiconductor device using dielectric isolation.

In FIG. 5, a semiconductor substrate 101 as a support substrate in an SOI substrate is interposed via a silicon oxide film 102 as a first insulating film, and n ⁻ as a first semiconductor layer serving as an active layer of the SOI substrate. ^The- type semiconductor layer 103 is formed by lamination. Embedded silicon oxide film 102
Is formed by etching, a silicon oxide film 105 as a second insulating film is formed on the side wall of the separation groove 104, and a polysilicon film 106 is buried. Membrane 1
05 separates the n ⁻ -type semiconductor layer 103 into an island-like dielectric. In the island-shaped n ⁻ -type semiconductor layer 103 thus formed, the gate oxide film 107 and the gate electrode 1 are formed.
08, a p-type semiconductor layer 109 as a second semiconductor layer for forming a channel region, a source electrode 115, and an n ⁺ -type semiconductor layer connected to the source electrode 115 and formed so as to be surrounded by the p-type semiconductor layer 109 110, drain electrode 1
16, an n ⁺ -type semiconductor layer 111 as a third semiconductor layer connected to the drain electrode 116 is provided to form an n-type high breakdown voltage MOS transistor.

In this n-type high breakdown voltage MOS transistor, a gate electrode 108 and a source electrode 115, that is, a p-type semiconductor layer 109 and an n ⁺ type semiconductor layer 110 for forming a channel region connected to the source electrode 115 are formed. , The potential of the same voltage A is applied, and the drain electrode 116,
That is, when the potential of the voltage B having a potential that is always higher than the potential of the voltage A applied to the p-type semiconductor layer 109 or the like is applied to the n ⁺ -type semiconductor layer 111 connected to the drain electrode 116, The pn junction between the p-type semiconductor layer 109 and the n ⁻ -type semiconductor layer 103 is in a reverse bias state, and a depletion layer extends from the interface. The potential distribution in the n-type high breakdown voltage MOS transistor and how the depletion layer spreads in this state will be described with reference to FIG. As shown in FIG. 6, the generated depletion layer is n
^When the potential of the voltage B is further increased by reaching the silicon oxide film 102 buried in the SOI substrate and reaching the silicon oxide film 102 buried in the SOI substrate, the drain electrode 116 The depletion layer extends toward the n ⁺ -type semiconductor layer 111 connected to the gate electrode, reaches the n ⁺ -type semiconductor layer 111, restricts the extension of the depletion layer, increases the electric field strength of the n ⁻ -type semiconductor layer 103, and increases the avalanche The reverse breakdown voltage characteristic is determined by the breakdown. Further, as shown in FIG. 6, the generated depletion layer is an n ⁻ type semiconductor layer 1.
03 also extends toward the n ⁺ -type semiconductor layer 111 connected to the drain electrode 116, reaches the n ⁺ -type semiconductor layer 111, limits the extension of the depletion layer, and reduces the electric field strength of the n ⁻ -type semiconductor layer 103. As a result, the reverse breakdown voltage characteristic is determined by the avalanche breakdown. The reverse breakdown voltage characteristic of the n-type high breakdown voltage MOS transistor is the lower reverse breakdown voltage characteristic determined by or.

As described above, the applied reverse bias voltage completely depletes the n ⁻ -type semiconductor layer 103, and the applied reverse bias voltage is applied to the expanded depletion layer and the buried silicon oxide film 102. The distribution alleviates the electric field in the n ⁻ -type semiconductor layer 103. As a result, n
^- reverse breakdown voltage characteristics of the n-type high voltage MOS transistor avalanche breakdown in -type semiconductor layer 103 dominates is remarkably improved.

[0008]

However, in the conventional semiconductor device, the silicon oxide film 102 buried in the SOI substrate is connected to the n-electrode connected to the drain electrode 116.
^The depletion layer toward the ⁺ type semiconductor layer 111 is the n ⁺ type semiconductor layer 11
1 or when the p-type semiconductor layer 109 and n ⁻
If the depletion layer extending from the interface of the type semiconductor layer 103 to the n ⁺ -type semiconductor layer 111 has reached n ⁺ -type semiconductor layer 111, the elongation of the depletion layer is restricted, n ^- the electric field strength type semiconductor layer 103 is increased Since the reverse breakdown voltage characteristic is determined by avalanche breakdown, when the n ⁻ -type semiconductor layer 103 has a low n-type concentration, the depletion layer easily expands and reaches the n ⁺ -type semiconductor layer 111 quickly. Decrease. When the n ⁻ -type semiconductor layer 103 has a high n-type concentration, the depletion layer becomes difficult to expand, and the electric field strength of the n ⁻ -type semiconductor layer 103 increases, so that the reverse breakdown voltage characteristic is reduced. Therefore, in the conventional semiconductor device, when the n-type concentration of the n ⁻ -type semiconductor layer 103 varies, the reverse breakdown voltage characteristic greatly varies.

To prevent this, the n ⁻ type semiconductor layer 10
3, the p-type semiconductor layer 109 and n-type
⁺ By releasing type semiconductor layer 111 sufficiently, p-type semiconductor layer 109 and the n ^- -type directed from the interface of the semiconductor layer 103 to the n ⁺ -type semiconductor layer 111 depletion layer hardly reaches the n ⁺ -type semiconductor layer 111 However, in this case, the reverse breakdown voltage is improved, but the ON resistance increases because the concentration of the n ⁻ -type semiconductor layer 103 is low.

On the other hand, in an analog switch or the like, the reverse breakdown voltage characteristics under an application condition where a positive voltage is applied to the drain and 0 V is applied to the source even under an application condition where 0 V is applied to the drain and a negative voltage is applied to the source. Characteristics are required.

In a conventional semiconductor device, a semiconductor substrate 101 as a support substrate in an SOI substrate generally has 0 V
Is applied, but the voltage A applied to the p-type semiconductor layer 109 and the like is
Is substantially the same as that of the semiconductor substrate 101 as a support substrate in the SOI substrate, the drain electrode 1
In the reverse bias state in which the potential of the voltage B having a large positive potential is applied to the n ⁺ -type semiconductor layer 111 connected to the n ⁺ -type semiconductor layer 109 and the n ⁺ -type semiconductor layer 111
Pn junction diode composed of the n ⁻ type semiconductor layer 103 sandwiched between
The depletion layer extends from the interface of the pn junction between the semiconductor layer 103 and the n ⁻ type semiconductor layer 103, and the depletion layer has a large positive potential of the voltage B applied to the n ⁺ type semiconductor layer 111 and the semiconductor substrate 10.
Due to 0 V applied to 1 and the potential of the voltage A applied to the p-type semiconductor layer 109 and the like, the depletion layer spreads uniformly inside the n ⁻ -type semiconductor layer 103, and the concentration of the internal electric field is reduced. , The n-type high-breakdown-voltage MOS transistor exhibits good reverse breakdown voltage characteristics. However, the p-type semiconductor layer 109
And so on, when the voltage A given to the above becomes a large negative value,
Semiconductor substrate 101 as support substrate in SOI substrate
Is applied to the n ⁺ type semiconductor layer 111 and the voltage B applied to the n ⁺ type semiconductor layer 111 becomes 0 V. In a reverse bias state or the like, the n ⁺ type semiconductor layer 111 and the semiconductor substrate 101 as a support substrate in the SOI substrate are applied. In each case, 0 V is applied, and there is no potential difference between them. In such a state, the depletion layer extending from the interface of the pn junction between the p-type semiconductor layer 109 and the n ⁻ -type semiconductor layer 103 is the n ⁺ -type semiconductor layer 1
11 cannot sufficiently extend to the n ⁻ -type semiconductor layer 103 in the lower region. That is, the n ⁺ type semiconductor layer 111
And semiconductor substrate 10 as support substrate in SOI substrate
Under the influence of a potential substantially equal to 1, the extension of the depletion layer is suppressed and the concentration of the internal electric field is not reduced, so that the reverse breakdown voltage characteristic of the n-type high breakdown voltage MOS transistor is greatly deteriorated. This state is shown in FIG. FIG. 8B shows that p
This is a case where a negative voltage A is applied to the type semiconductor layer 109 and the like, and the potential of the voltage A applied to the n ⁺ type semiconductor layer 111 and the like is substantially the same as the semiconductor substrate 101 as a support substrate in the SOI substrate. In this case, unlike the case of FIG. 6, the p-type semiconductor layer 1
The depletion layer extending from the interface of the pn junction between the semiconductor layer 09 and the n ⁻ -type semiconductor layer 103 is n ^{− in} the lower region of the n ⁺ -type semiconductor layer 111.
It cannot extend sufficiently to the mold semiconductor layer 103.
In other words, under the influence of substantially equal potentials of the n ⁺ type semiconductor layer 111 and the semiconductor substrate 101 as a support substrate in the SOI substrate, the extension of the depletion layer is suppressed and the concentration of the internal electric field is not reduced. The reverse breakdown voltage characteristic of the breakdown voltage MOS transistor is greatly deteriorated.

An object of the present invention is to provide a semiconductor device which solves such a conventional problem.

[0013]

According to a first aspect of the present invention, there is provided a semiconductor device having a first conductivity type first semiconductor layer on a semiconductor substrate with a first insulating film interposed therebetween. Wherein the first semiconductor layer includes a separation groove that reaches the first semiconductor layer up to the first insulation film, and a second insulation film formed on a side wall of the separation groove. A second conductivity type semiconductor layer formed on the surface of the first conductivity type; a third conductivity type semiconductor layer of the first conductivity type formed on the surface of the first semiconductor layer; In this configuration, a fourth semiconductor layer of the first conductivity type is provided below the semiconductor layer.
Accordingly, when a positive high voltage is applied to the third semiconductor layer, a depletion layer in the first semiconductor layer extending from the first insulating film hardly reaches the third semiconductor layer.

According to a second aspect of the present invention, there is provided a semiconductor device according to the first aspect, wherein a fifth of the first conductivity type is provided between the second semiconductor layer and the third semiconductor layer. This is a configuration in which semiconductor layers are provided discretely. Thereby, when a positive high voltage is applied to the third semiconductor layer, a depletion layer in the first semiconductor layer extending from the second semiconductor layer toward the third semiconductor layer is formed in the third semiconductor layer. Hardly reach the semiconductor layer.

With this configuration, when a positive high voltage is applied to the third semiconductor layer, the depletion layer in the first semiconductor layer extending from the first insulating film reaches the third semiconductor layer. Depletion in the first semiconductor layer extending from the second semiconductor layer toward the third semiconductor layer when a high positive voltage is applied to the third semiconductor layer. Since the layer can hardly reach the third semiconductor layer, stable reverse breakdown voltage characteristics can be obtained even when the concentration of the first semiconductor layer varies.
Further, by providing a fifth semiconductor layer having the same conductivity type as the first semiconductor layer in the first semiconductor layer, the fifth semiconductor layer has the same conductivity type as the first semiconductor layer between the second semiconductor layer and the third semiconductor layer. Since the amount of impurities of the conductivity type increases, the ON resistance can be reduced. Note that a fifth semiconductor layer having the same conductivity type as the first semiconductor layer provided between the second semiconductor layer and the third semiconductor layer is a second semiconductor layer and a first semiconductor layer. Is depleted when the pn junction becomes reverse biased,
It is provided discretely.

Further, in order to achieve the above object, a semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first aspect, wherein an interface between the first semiconductor layer and the first insulating film is provided. A sixth semiconductor layer of the second conductivity type is provided, and when a high negative voltage is applied to the third semiconductor layer, the sixth semiconductor layer is not completely depleted, and the first semiconductor layer is not completely depleted. It is characterized by promoting uniform expansion of the depletion layer in the layer.

According to a fourth aspect of the present invention, there is provided the semiconductor device according to the second aspect, wherein a sixth conductive type sixth semiconductor is provided at an interface between the first semiconductor layer and the first insulating film. When a negative high voltage is applied to the third semiconductor layer, the sixth semiconductor layer is not completely depleted, and a uniform depletion layer in the first semiconductor layer is provided. It is characterized by promoting rapid growth.

In this configuration, in a reverse bias state in which a higher voltage is applied to the third n-type semiconductor layer than to the second p-type semiconductor layer, when the depletion layer extends into the first semiconductor layer, While the fourth semiconductor layer is not completely depleted, while keeping the potential at the bottom of the first semiconductor layer almost constant,
The depletion layer also extends to the first semiconductor layer side from the pn junction formed by the fourth semiconductor layer and the first semiconductor layer.

As described above, by having the fourth semiconductor layer having a conductivity type different from that of the first semiconductor layer and not being completely depleted, depletion in the first semiconductor layer is achieved. Promotes uniform elongation of the layer. As a result, the potential of an arbitrary reverse bias state with respect to the semiconductor substrate is changed to the second p.
Even when the depletion layer is applied to the first semiconductor layer and the third n-type semiconductor layer, the depletion layer spreads uniformly inside the first semiconductor layer, the concentration of the internal electric field is reduced, and good reverse breakdown voltage characteristics are exhibited.

As described above, according to the present invention, a low ON-resistance semiconductor device having a stable reverse breakdown voltage characteristic even in an arbitrary reverse bias state with respect to a semiconductor substrate can be realized.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of an essential part of an n-type high withstand voltage MOS transistor which is a first embodiment of the semiconductor device according to the embodiment of the present invention. An n ⁻ type semiconductor layer 3 as a first semiconductor layer serving as an active layer of the SOI substrate is laminated on a semiconductor substrate 1 as a support substrate in the SOI substrate via a silicon oxide film 2 as a first insulating film. Is formed. The isolation trench 4 reaching the buried silicon oxide film 2 is formed by etching, a silicon oxide film 5 as a second insulating film is formed on the side wall of the isolation trench 4, and the polysilicon film 6 is buried. The silicon oxide film 2 and the silicon oxide film 5 separate the n ⁻ -type semiconductor layer 3 into an island shape dielectric. In the island-shaped n ⁻ -type semiconductor layer 3 thus formed, the gate oxide film 7, the gate electrode 8, and p as a second semiconductor layer for forming a channel region are formed.
-Type semiconductor layer 9, source electrode 15, n ⁺ -type semiconductor layer 10 connected to source electrode 15 and formed to be surrounded by p-type semiconductor layer 9, drain electrode 16, and third semiconductor connected to drain electrode 16 N ⁺ type semiconductor layer 11 as layer
Is provided. An n ⁻ type semiconductor layer 12 as a fourth semiconductor layer is formed below the n ⁺ type semiconductor layer 10.

FIG. 2 is a sectional view of a principal part of an n-type high-breakdown-voltage MOS transistor which is a second embodiment of the semiconductor device according to the present invention. In FIG. 2, a p-type semiconductor layer 9 and an n ⁺ -type semiconductor layer 1 as a second semiconductor layer for forming a channel region are further added to the n-type high withstand voltage MOS transistor of FIG.
The n ⁻ type semiconductor layers 13 are provided discretely between 0.

FIG. 3 is a sectional view of a principal part of an n-type high breakdown voltage MOS transistor which is a third embodiment of the semiconductor device according to the present invention. In FIG. 3, the semiconductor device of FIG. 2 has a discrete n ⁻ -type semiconductor layer between the p-type semiconductor layer 9 and the n ⁺ -type semiconductor layer 10 for forming a channel region. A semiconductor layer 13 is formed.

FIG. 3 is a cross-sectional view of a main part of an n-type high withstand voltage MOS transistor which is a third embodiment of the semiconductor device according to the embodiment of the present invention. 3, a p-type semiconductor layer 14 as a sixth semiconductor layer is formed at the interface between the bottom of the island-shaped n ⁻ -type semiconductor layer 3 and the buried silicon oxide film 2 of the semiconductor device of FIG. I have.

Next, a brief description will be given of a method of manufacturing the n-type high voltage MOS transistor of the present invention.

First, the n ⁻ type semiconductor layer 3 is formed on at least the surface.
Is prepared, a p-type semiconductor layer 14 is formed on the surface of the n ⁻ -type semiconductor layer 3 by an ion implantation method, a thermal diffusion method, or the like, and then the semiconductor substrate having the n ⁻ -type semiconductor layer 3 is formed. Is bonded to the surface of another semiconductor substrate 1 with the silicon oxide film 2 interposed therebetween, and is subjected to heat treatment or the like. The silicon oxide film 2 may be formed on one of the semiconductor substrate 1 and the n ⁻ type semiconductor layer 3 or on both of them.

The substrate on which the semiconductor substrate 1 and the n ⁻ -type semiconductor layer 3 are adhered so as to sandwich the silicon oxide film 2 is ground by a surface polishing method or the like, so that the n ⁻ -type semiconductor layer 3 has a desired thickness. Next, using a photoresist mask or a patterned silicon nitride film or silicon oxide film as a mask, a part of the n ⁻ -type semiconductor layer 3 is etched until reaching the silicon oxide film 2 to form an isolation groove 4. . Separation groove 4
The silicon oxide film 5 is formed on the side wall portion of the silicon oxide film 5 and the polysilicon film 6 is buried, so that the silicon oxide film 2 and the silicon oxide film 5 separate the n ⁻ -type semiconductor layer 3 into an island-like dielectric.

[0029] Then, like islets dielectric isolation n ^- type in the semiconductor layer 3, and a photoresist mask or patterned silicon oxide film as a mask, n as a fourth semiconductor layer ^- type semiconductor The layer 12 and the n ⁻ type semiconductor layer 13 as a fifth semiconductor layer are formed by performing ion implantation and heat treatment. Note that the n ⁻ -type semiconductor layer 12 as the fourth semiconductor layer and the n ⁻ -type semiconductor layer 13 as the fifth semiconductor layer can be simultaneously formed with the same mask by adjusting the amount of ion implantation. It is possible. Thereafter, after forming a gate oxide film 7 and a gate electrode 8, ion implantation and heat treatment are performed to form a p-type semiconductor layer 9, and the p-type semiconductor layer 9 is formed.
The type semiconductor layer 9 is used as a channel region.

Next, in the p-type semiconductor layer 9, n serving as a source
⁺ -Type semiconductor layer 10 and p-type semiconductor layer 9
The n ⁺ -type semiconductor layer 11 serving as a drain is formed on the surface of the n ⁻ -type semiconductor layer 3 which is appropriately spaced apart from the substrate. Finally, the source electrode 15 is connected to the p-type semiconductor layer 9 and the n ⁺ -type semiconductor layer 10.
Then, by connecting the drain electrode 16 to the n ⁺ -type semiconductor layer 11, the n-type high breakdown voltage MOS transistor of the present invention is manufactured.

Here, as a method of forming the p-type semiconductor layer 14, a semiconductor having the n ⁻ -type semiconductor layer 3 on at least the surface thereof before bonding the n ⁻ -type semiconductor layer 3 to the semiconductor substrate 1 is used. although the method of forming a p-type semiconductor layer 14 on the surface of the substrate, n ^- and a semiconductor substrate having a type semiconductor layer 3 so as to sandwich the silicon oxide film 2 stuck to the semiconductor substrate 1, n ^- -type semiconductor layer 3 -type semiconductor layer 3 ^- but n due surface polishing method to the desired thickness ^- n after shaved -type semiconductor layer 3, by using a high-energy ion implantation method
Ions are implanted from the surface of the p-type semiconductor layer 14 into n ⁻
It may be formed at the bottom of the mold semiconductor layer 3. Also, the semiconductor substrate 1 and n in a manner adhering to such heat treatment ^- showed how to form pasted by type semiconductor layer 3 so as to sandwich the silicon oxide film 2, n ^- -type semiconductor layer 3 at least that Oxygen ions may be implanted into the semiconductor substrate on the surface to form the silicon oxide film 2 on the bottom of the n ⁻ type semiconductor layer 3. Furthermore, in order to make the n ⁻ -type semiconductor layer 3 have a desired thickness, a method of shaving the n ⁻ -type semiconductor layer 3 by a surface polishing method or the like is shown here. The n ⁻ -type semiconductor layer 3 may be adjusted and processed to have a desired thickness by polishing the surface after applying a suitable heat treatment or an external force.

Next, the operation of the n-type high withstand voltage MOS transistor having such a configuration will be described.

By applying substantially the same voltage A to the gate electrode 8 and the n ⁺ -type semiconductor layer 10 and the p-type semiconductor layer 9 connected to the source electrode 15, the n-type high voltage MOS transistor is turned off. State. In this state, the potential of the voltage B having a potential always positively higher than the potential of the voltage A applied to the p-type semiconductor layer 9 and the like is applied to the n ⁺ -type semiconductor layer 11 connected to the drain electrode 16. And the p-type semiconductor layer 9
The pn junction diode composed of the n ⁺ -type semiconductor layer 3 and the n ⁻ -type semiconductor layer 3 sandwiched between the n ⁺ -type semiconductor layers 11 is reverse-biased, and the interface of the pn junction between the p-type semiconductor layer 9 and the n ⁻ -type semiconductor layer 3 Depletion layer extends into the n ⁻ -type semiconductor layer 3.

Next, the difference in operation between the n-type high-voltage MOS transistor of the second embodiment of the present invention and a conventional n-type high-voltage MOS transistor will be described in comparison.

FIG. 7A shows that a voltage A of 0 V is applied to the source electrode 15 and a voltage B of 400 V is applied to the drain electrode 16 of the n-type high breakdown voltage MOS transistor according to the second embodiment of the present invention. FIG. 7 (b) shows a simulation result of the potential distribution inside the n-type high breakdown voltage MOS transistor and the expansion of the depletion layer in the case of the present invention,
Shows a simulation result of the potential distribution inside the transistor and the spread of the depletion layer when 0 V is applied as the voltage A to the source electrode 15 and 350 V is applied as the voltage B to the drain electrode 16 of the conventional n-type high breakdown voltage MOS transistor. Is shown.

As can be seen from the simulation results, in the conventional n-type high breakdown voltage MOS transistor,
The depletion layer in the n ⁻ -type semiconductor layer 3 extending from the interface of the pn junction between the p-type semiconductor layer 9 and the n ⁻ -type semiconductor layer 3 toward the n ⁺ -type semiconductor layer 11 and the silicon oxide film 2 to the n ⁺ -type The depletion layer in the n ⁻ -type semiconductor layer 3 extending toward the semiconductor layer 11 easily reaches n ⁺ 11, whereas n in the second embodiment
In the high withstand voltage MOS transistor, a depletion layer in the n ⁻ -type semiconductor layer 3 extending from the interface of the pn junction between the p-type semiconductor layer 9 and the n ⁻ -type semiconductor layer 3 toward the n ⁺ -type semiconductor layer 11 is formed. N extending from silicon oxide film 2 toward n ⁺ 11
The depletion layer in the ⁻ type semiconductor layer 3 is formed by the n ⁻ type semiconductor layer 12 and n ⁻
Since it is limited by the type semiconductor layer 13 and does not easily reach the n ⁺ type semiconductor layer 11, the uniform electric field intensity does not increase in the n ⁻ type semiconductor layer 3 and a good reverse breakdown voltage characteristic is exhibited. You can see that.

By providing the n ⁻ -type semiconductor layer 12 and the n ⁻ -type semiconductor layer 13 of the same conductivity type in the n ⁻ -type semiconductor layer 3, the distance between the p-type semiconductor layer 9 and the n ⁺ -type semiconductor layer 11 is increased. of n ^-
Since the amount of impurities of the same conductivity type as the type semiconductor layer 3 increases,
ON resistance can be reduced.

[0038] In the second embodiment, the n ^- type resistance of the semiconductor layer is 10 [Omega · cm, the n ^- -type semiconductor layer 12 and the n ^- -type semiconductor layer density of 13 ^{3 × 10 12 / cm 2,} n - When the width and the interval of the type semiconductor layer 13 are 2 μm and 5 μm, respectively, the reverse breakdown voltage is improved by 50 V as compared with the case where the n ⁻ type semiconductor layer 12 and the n ⁻ type semiconductor layer 13 are not provided, and the ON resistance is n ⁻ type semiconductor layer. 12 and １ ／ of the case without the n ⁻ type semiconductor layer 13,
It is possible to improve the reverse breakdown voltage characteristics and reduce the ON resistance.

Next, a general 0 V is applied to the semiconductor substrate 1 to apply a gate electrode 8, a p-type semiconductor layer 9 for forming a channel region connected to the source electrode 15, and an n ⁺ -type semiconductor layer 10. , A large negative voltage A, and an n-type high breakdown voltage M
With the OS transistor turned off, the drain electrode 1
A case where a potential of substantially the same voltage B as that of the semiconductor substrate 1 is applied to the n ⁺ -type semiconductor layer 11 connected to 6 will be described.

FIG. 8A shows that a voltage of -400 V is applied to the source electrode 15 of the n-type high breakdown voltage MOS transistor according to the second embodiment of the present invention, and a voltage of B is applied to the drain electrode 16.
N-type high breakdown voltage M according to the present invention when 0 V is applied as
FIG. 8B shows a simulation result of the potential distribution inside the OS transistor and the spread of the depletion layer. FIG. 8B shows that the source electrode 15 of the conventional n-type high breakdown voltage MOS transistor is supplied with -260 V as the voltage A and the drain electrode 16 is provided. Shows a simulation result of the potential distribution inside the transistor and the expansion of the depletion layer when 0 V is applied as the voltage B to the transistor. As can be seen from the simulation results, in the case of the conventional n-type high withstand voltage MOS transistor, FIG.
Under the conditions shown in (1), since 0 V is applied to both the n ⁺ -type semiconductor layer 11 and the semiconductor substrate 1, the interface between the p-type semiconductor layer 9 and the n ⁻ -type semiconductor layer 3 at the pn junction The extending depletion layer cannot extend sufficiently to the n ⁻ -type semiconductor layer 3 in the lower region of the n ⁺ -type semiconductor layer 11, and the extension of the depletion layer is suppressed, and the concentration of the internal electric field is not reduced.
While the reverse breakdown voltage characteristic of the n-type high breakdown voltage MOS transistor is greatly deteriorated, in the n-type high breakdown voltage MOS transistor according to the third embodiment of the present invention, the inside of the n ⁻ -type semiconductor layer 3 is completely depleted. As a result, the potential distribution in the n ⁻ -type semiconductor layer 3 becomes very gentle, the concentration of the internal electric field is reduced, and the n ⁻ -type height in which the avalanche breakdown in the n ⁻ -type semiconductor layer 3 is dominant. It can be seen that the withstand voltage MOS transistor exhibits good reverse withstand voltage characteristics.

As described above, when the voltage A applied to the p-type semiconductor layer 9 and the like has a large negative value, a general 0 V is applied to the semiconductor substrate 1 as a support substrate in the SOI substrate, and the n ⁺ -type When the voltage B applied to the semiconductor layer 11 is 0
In a reverse bias state where V is V, the n ⁺ type semiconductor layer 1
0 V is applied to both the semiconductor substrate 1 and the semiconductor substrate 1, and there is no potential difference between them.
^- -type semiconductor layer 3 of the bottom p-type semiconductor layer is embedded in the portion 14
Is not completely depleted, the undepleted p-type semiconductor layer 14 functions to keep the potential at the bottom of the n ⁻ -type semiconductor layer 3 almost constant, and the p-type semiconductor layer 14 n ^- type by semiconductor layer 3 and the reverse bias applied to the pn junction formed by a p-type semiconductor layer 14 n ^- depletion layer from the pn junction formed by type semiconductor layer 3 n ^{- -} so that the extending type semiconductor layer 3 side. as a result,
The electric field strength in the n ⁻ -type semiconductor layer 3 is reduced, and the n-type high-breakdown-voltage MOS transistor exhibits excellent reverse breakdown voltage characteristics.

In this embodiment, the resistance of the n ⁻ -type semiconductor layer is 10 Ω · cm, and the concentration of the p-type semiconductor layer 14 is 3 × 1.
In the case of 0 ¹² / cm ² , the reverse breakdown voltage when a negative voltage is applied is improved by 140 V as compared with the case where the p-type semiconductor layer 14 is not provided. Even when a negative voltage is applied, it is the same as when a positive voltage is applied Can be realized.

FIG. 4 shows a lateral view according to a fourth embodiment of the present invention.
It is principal part sectional drawing of type | mold IGBT. N-type of the third embodiment
An island formed in the same way as a high voltage MOS transistor
N ^-A gate oxide film 7 and a gate electrode
Pole 8, a second semiconductor layer for forming a channel region;
P-type semiconductor layer 9, emitter electrode 19,
Formed so as to be connected to the pole 19 and surrounded by the p-type semiconductor layer 9
Done n⁺Type semiconductor layer 10, collector electrode 20, collector
P connected to the data electrode 20⁺Type semiconductor layer 17, collector
P connected to electrode 20⁺Around the semiconductor layer 17
The n-type semiconductor layer 18 formed as described above is provided. Ma
, P⁺Below the type semiconductor layer 17, n^-Type semiconductor layer 12,
As a second semiconductor layer for forming a channel region
p-type semiconductor layer 9 and n⁺N discretely between the semiconductor layers 10^-
A type semiconductor layer 13 is provided. Furthermore, the island-like n^-
Buried silicon oxide film at the bottom of the semiconductor layer 3
P-type semiconductor layer 14 as a sixth semiconductor layer at the interface with
Are formed. Also in this horizontal IGBT, the p-type
Semiconductor layer 9 and n^-Pn die composed of semiconductor layer 3
Since the basic configurations of the odes are the same, the n-type of the second embodiment
Effects similar to those obtained with high voltage MOS transistors
And a lateral IGBT exhibiting excellent reverse breakdown voltage characteristics
realizable.

In each of the embodiments of the present invention, the case where the n ⁻ type semiconductor layer is used as the first semiconductor layer has been described, but the p ⁻ type semiconductor layer is used as the first semiconductor layer. It goes without saying that the same effect can be obtained by using a layer. However, when a p ⁻ type semiconductor layer is used, an n type semiconductor layer is formed as a fourth semiconductor layer at the interface with the embedded first insulating film at the bottom of the island-shaped first semiconductor layer. Need to be done.

[0045]

As described above, according to the present invention, the fifth semiconductor layer is discretely provided between the second semiconductor layer and the third semiconductor layer, so that the third semiconductor layer When a high voltage is applied, the depletion layer extending from the first insulating film toward the third semiconductor layer and the depletion layer extending from the second semiconductor layer toward the third semiconductor layer have the same extent. Thus, stable reverse breakdown voltage characteristics can be obtained even if the concentration of the first semiconductor layer varies.

Further, by forming a fourth semiconductor layer containing many impurities in the first semiconductor layer on the interface side between the first semiconductor layer and the first insulating film, the first semiconductor layer is formed. While the potential at the bottom of the layer is kept substantially constant, the depletion layer of the pn junction formed by the fourth semiconductor layer and the first semiconductor layer can be extended to the first semiconductor layer side. Uniform elongation of the depletion layer in one semiconductor layer can be promoted, and good reverse breakdown voltage characteristics can be obtained.

Therefore, according to the present invention, a semiconductor device having a low ON resistance and having a stable reverse breakdown voltage characteristic even in an arbitrary reverse bias state with respect to the semiconductor substrate can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of an n-type high-voltage MOS transistor of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is an essential part cross-sectional view of an n-type high breakdown voltage MOS transistor of a semiconductor device according to a second embodiment of the present invention;

FIG. 3 is a sectional view of a main part of an n-type high-voltage MOS transistor of a semiconductor device according to a third embodiment of the present invention;

FIG. 4 is a sectional view of a main part of a lateral IGBT of a semiconductor device according to a fourth embodiment of the present invention;

FIG. 5 is a cross-sectional view of a main part of an n-type high withstand voltage MOS transistor which is a conventional semiconductor device.

FIG. 6 is a diagram showing a simulation result of the potential distribution inside the high breakdown voltage n-type MOS transistor and the expansion of the depletion layer when 0 V is applied to the source electrode of the conventional n-type high breakdown voltage MOS transistor.

7A is a diagram showing a simulation result of the potential distribution inside the n-type high breakdown voltage MOS transistor and the expansion of the depletion layer in the embodiment of the present invention when 400 V is applied to the drain electrode; FIG. Showing simulation results of the potential distribution inside the conventional n-type high breakdown voltage MOS transistor and the spread of the depletion layer when 350 V is applied to the transistor

8A is a diagram showing a simulation result of the potential distribution inside the n-type high breakdown voltage MOS transistor and the expansion of the depletion layer in the embodiment of the present invention when -400 V is applied to the source electrode; FIG. The figure which shows the simulation result of the electric potential distribution inside the conventional n-type high voltage | pressure MOS transistor, and expansion of a depletion layer when -260V is applied to an electrode.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate as support substrate in SOI substrate 2 silicon oxide film as first insulating film 3 n ⁻ type semiconductor layer as first semiconductor layer serving as active layer of SOI substrate 4 separation groove 5 second insulation n ⁺ -type semiconductor layer of a p-type semiconductor layer 10 n ⁺ -type semiconductor layer 11 a third semiconductor layer of a silicon oxide film 6 a polysilicon film 7 gate oxide film 8 the gate electrode 9 a second semiconductor layer of the film 12 first n as fourth semiconductor layer ^- -type semiconductor layer 13 n of the fifth semiconductor layer ^- -type semiconductor layer 14 a sixth p-type semiconductor layer 15 source electrode 16 drain electrode of the semiconductor layer 17 p ⁺ -type semiconductor layer 18 n Type semiconductor layer 19 Emitter electrode 20 Collector electrode 101 Semiconductor substrate as support substrate in SOI substrate 102 Silicon oxide film as first insulating film 103 SOI N ⁻ type semiconductor layer 104 serving as a first semiconductor layer serving as an active layer of a substrate 104 isolation trench 105 silicon oxide film serving as a second insulating film 106 polysilicon film 107 gate oxide film 108 gate electrode 109 second semiconductor layer p-type semiconductor layer 110 n ⁺ -type semiconductor layer 111 n ⁺ -type semiconductor layer 115 source electrode 116 drain electrode of a third semiconductor layer of a

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Claims (4)

[Claims] In a semiconductor device in which a first semiconductor layer of a first conductivity type is formed on a semiconductor substrate via a first insulating film, a separation reaching the first semiconductor layer to the first insulating film is provided. A trench, a second insulating film formed on a side wall of the isolation trench, a second conductivity type semiconductor layer of a second conductivity type formed on a surface of the first semiconductor layer; Comprising: a first conductivity type third conductivity type semiconductor layer formed on the surface of the first semiconductor type; and a first conductivity type fourth semiconductor layer provided below the third semiconductor layer. apparatus. 2. The semiconductor device according to claim 1, wherein a fifth semiconductor layer of a first conductivity type is discretely provided between said second semiconductor layer and said third semiconductor layer. Semiconductor device. 3. The semiconductor device according to claim 1, wherein a sixth semiconductor layer of a second conductivity type is provided in said first semiconductor layer on an interface side between said first semiconductor layer and said first insulating film. A semiconductor device comprising: 4. The semiconductor device according to claim 2, wherein a sixth semiconductor layer having a conductivity type different from that of the first semiconductor layer is provided at an interface between the first semiconductor layer and the first insulating film. A semiconductor device, comprising: