JP2002313674A - Lamination type capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a lamination type capacitor for reducing ESL without depending on the shape and eliminating noise surely. SOLUTION: The lamination type capacitor 1 comprises a laminate 2 where first and second dielectric layers are laminated alternately, an external electrode 3 for signals that is formed at both the ends of the laminates 2 in a laminating direction, an external electrode 4 for grounding that is formed on the side of the laminate 2, and a feedthrough conductor 5 that is electrically connected to the external electrode 3 for signals through the laminate 2. In the capacitor 1, an internal electrode 6 for signals that is electrically insulated from the external electrode 4 for grounding and is electrically connected to the feedthrough conductor 5 is formed at the first dielectric layer, and an inner electrode 7 for grounding that is drawn to the outer end of the second dielectric layer so that it is electrically connected to the external electrode 4 for grounding and is electrically insulated from the feedthrough conductor 5 is formed at the second dielectric layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer capacitor, and more particularly, to an equivalent series inductance (hereinafter referred to as ES).
L) and a multilayer capacitor for a noise filter having excellent high frequency characteristics.

[0002]

2. Description of the Related Art Heretofore, there have been the following multilayer capacitors for a noise filter. JP 2000
Japanese Patent Application No. 58376 discloses a multilayer capacitor as shown in FIGS. FIG. 24 is a cross-sectional view when the multilayer capacitor is cut along the laminating direction of the dielectric sheet. FIGS. 25 and 26 are cross-sectional views when cut perpendicular to the laminating direction of the dielectric sheet. FIG. The multilayer capacitor 51 includes a ceramic substrate 5
2, first and second terminal electrodes 53 a and 53 b, a third terminal electrode 54, and first and second internal electrodes 56 and 57. The first internal electrode 56 is connected to the first and second terminal electrodes 53a and 53b, and the second internal electrode 57 is connected to the third terminal electrode 54.

In this multilayer capacitor 51, the length of the first internal electrode 56 (the length of the ceramic base 52)
X ₀ , the width of the second internal electrode 57 (the ceramic substrate 52
When the width) was set to Y _0, is set to X ₀ / Y ₀ ≧ 4 can remove high-frequency noise reduces ESL by satisfying.

In Japanese Patent Application Laid-Open No. 6-20870,
A multilayer capacitor as shown in FIGS. 27 to 29 is disclosed. FIG. 27 is a cross-sectional view when the multilayer capacitor is cut along the stacking direction of the dielectric sheets. FIGS. 28 and 29 are cross-sectional views when cut perpendicular to the stacking direction of the dielectric sheets. FIG. The multilayer capacitor 61 includes a laminate formed by alternately laminating first and second ceramic dielectric sheets 63a and 63b having through holes 62, and external electrodes 64 formed at both ends of the laminate. Is provided. In the first ceramic dielectric sheet 63a, an internal conductor 65 is formed around the through hole 62, and a separation conductor 66 is formed at an interval from the internal conductor 65. In the second ceramic dielectric sheet 63b, a ground conductor 67 is formed at an interval from the through hole 62. A conductor layer 62a is formed on the hole wall of the through hole 62.

In this multilayer capacitor 61, the inner conductor 65 of the first ceramic dielectric sheet 63a and the second
Because capacitance is formed between the ground conductor 67 of the ceramic dielectric sheet 63 b, is set to the noise entering it can be removed through holes rod-shaped metal conductors L ₁ of the inserted signal line to 62, L _2, L _3.

[0006]

However, in the multilayer capacitor 51, the shape of the ceramic base 52 is elongated to satisfy X ₀ / Y ₀ ≧ 4, and the bending strength of the ceramic base 52 is reduced. There was a problem.

In the multilayer capacitor 61,
There is a problem that an inductance is generated at a connection point between the rod-shaped metal bodies L ₁ , L ₂ , L ₃ and the conductor layer 62a, and the ESL increases. Further, the rod-shaped metal bodies L ₁ , L ₂ ,
L ₃ and for the conductor layer to completely bonded in the through-hole 62a is difficult, it may be impossible to reliably remove noise.

[0008] The present invention provides an ESL that does not depend on the shape.
It is an object of the present invention to provide a multilayer capacitor capable of reducing noise and reliably removing noise.

[0009]

According to a first aspect of the present invention, there is provided a multilayer capacitor including a laminated body including a portion in which first dielectric layers and second dielectric layers are alternately laminated, and a laminated body in a laminating direction. A signal external electrode formed at both ends of the body, a grounding external electrode formed on the side surface of the laminate, and a signal external electrode are provided so as to penetrate the laminate along the lamination direction. The first dielectric layer is formed with a signal internal electrode which is electrically insulated from the grounding external electrode and is electrically connected to the penetrating conductor. In the dielectric layer, a grounding internal electrode which is drawn out to the outer edge of the second dielectric layer so as to be electrically connected to the grounding external electrode and is electrically insulated from the through conductor is formed. It is characterized by having.

With this configuration, the grounding internal electrode can be arbitrarily pulled out toward the outer edge of the dielectric layer and connected to the grounding external electrode. For example, when the dielectric layer has a quadrilateral shape, the connection points between the grounding internal electrode and the grounding external electrode can be taken on all four sides.

Further, since the signal internal electrode and the through conductor are securely connected, it is possible to prevent an excessive increase in ESL and to remove noise without leakage.

According to a second aspect of the present invention, there is provided a multilayer capacitor including a laminated body including a portion in which first dielectric layers and second dielectric layers are alternately laminated, and formed at both ends of the laminated body in the laminating direction. Signal external electrode, a grounding external electrode formed on the side surface of the laminate, and a through conductor that is provided so as to penetrate the laminate along the lamination direction and is electrically connected to the signal external electrode. The first dielectric layer includes a grounding internal electrode extended to the outer edge of the first dielectric layer so as to be electrically connected to the grounding external electrode, and an electrical connection between the grounding internal electrode and the grounding internal electrode. And a signal internal electrode electrically connected to the through conductor and formed in the second dielectric layer.
A grounding internal electrode which is drawn out to the outer edge of the second dielectric layer so as to be electrically connected to the grounding external electrode and is electrically insulated from the through conductor is formed. .

With such a configuration, the grounding internal electrode of the first dielectric layer and the signal internal electrode of the second dielectric layer overlap in the laminating direction to form a capacitance. And the second internal electrode for grounding of the dielectric layer and the second
The signal internal electrode of the dielectric layer opposes in the plane direction to form a capacitance. That is, since the first dielectric layer and the second dielectric layer can be in contact with the external ground electrode, ESL can be reduced.

According to a third aspect of the present invention, there is provided a multilayer capacitor in which dielectric layers are stacked, signal external electrodes formed at both ends of the multilayer body in the stacking direction, and side surfaces of the multilayer body. A grounding external electrode, and a penetrating conductor provided so as to penetrate the laminate along the laminating direction, and electrically connected to the signal external electrode. A grounding internal electrode extended to the outer edge of the dielectric layer so as to be electrically connected, and a signal internal electrode electrically connected to the through conductor and electrically insulated from the grounding internal electrode are formed. It is characterized by having.

With such a configuration, a planar capacitance is formed only between the grounding internal electrode and the signal internal electrode of the dielectric layer. For this reason, the capacitance is reduced, but the contact between the grounding internal electrode and the grounding external electrode can be increased, so that the ESL is also reduced. Therefore, the resonance frequency of the multilayer capacitor is increased, and the impedance at the high frequency portion is reduced, so that high frequency noise is easily removed.

According to a fourth aspect of the present invention, there is provided a multilayer capacitor including a laminated body including a portion in which first dielectric layers and second dielectric layers are alternately laminated, and formed at both ends of the laminated body in the laminating direction. Signal external electrode, a grounding external electrode formed on the side surface of the laminate, and a through conductor that is provided so as to penetrate the laminate along the lamination direction and is electrically connected to the signal external electrode. The first dielectric layer includes a grounding internal electrode extended to the outer edge of the first dielectric layer so as to be electrically connected to the grounding external electrode, and an electrical connection between the grounding internal electrode and the grounding internal electrode. And a signal internal electrode electrically connected to the through conductor and formed in the second dielectric layer,
A float electrode electrically insulated from both the grounding external electrode and the signal external electrode is formed.

With this configuration, the noise current flows to the grounding external electrode with the float electrode bypassed. Also, by changing the size of the float electrode,
The capacitance can be adjusted according to the application.

A multilayer capacitor according to a fifth aspect of the present invention is the multilayer capacitor according to the first aspect of the present invention, wherein a portion of the grounding internal electrode extending to the grounding external electrode is radially and so on. At intervals and at least 3
It is characterized by being present.

With such a configuration, the magnetic fields generated around the currents flowing through the respective lead portions cancel each other, so that the ESL can be reduced.

A multilayer capacitor according to a sixth aspect of the present invention is the multilayer capacitor according to any one of the first to fifth aspects, wherein the grounding external electrode is formed over the entire side surface of the multilayer body, and the grounding internal electrode is formed. Is drawn out over the entire outer periphery of the dielectric layer.

With this configuration, the area of the connection between the grounding internal electrode and the grounding external electrode is maximized per dielectric layer, and ESL can be reduced most.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 1 is a perspective view of a multilayer capacitor according to the present embodiment, FIG. 2 is a sectional view along the L ₁ -L ₁ line in FIG. The multilayer capacitor 1 includes a laminate 2, a signal external electrode 3, a ground external electrode 4, a through conductor 5, and a signal internal electrode 6.
And a grounding internal electrode 7.

FIG. 3 is an exploded perspective view showing a laminated state of the laminate 2. The laminated body 2 has a structure in which first dielectric layers 8a and second dielectric layers 8b are alternately laminated, and a third dielectric layer 8c is laminated on both sides of the laminated intermediate. As a material of the first to third dielectric layers 8a to 8c,
A dielectric ceramic material such as BaTiO ₃ can be used.

FIG. 4 is a top view showing the first dielectric layer 8a, and FIG. 5 is a cross-sectional view taken along line L ₂ -L ₂ in FIG. As shown in FIG. 4, a signal internal electrode 6 is formed on one main surface of the first dielectric layer 8a so as not to be drawn out to the outer edge. Ag, Pd, Ni, or the like can be used as the material of the signal internal electrode 6.

A via hole 9 is provided at the center of the first dielectric layer 8a. As shown in FIG. 5, the via hole 9 is filled with a conductor 5a forming a part of the through conductor 5, and the conductor 5a is electrically connected to the signal internal electrode 6. Note that the conductor 5a is extended on the other main surface of the first dielectric layer 8a to facilitate conduction with the conductor 5a formed on the adjacent dielectric layer.

[0026] FIG. 6 is a top sketch illustrating a second dielectric layer 8b, FIG. 7 is a sectional view along the L ₃ -L ₃ line in FIG. As shown in FIG. 6, a grounding internal electrode 7 is formed on one main surface of the second dielectric layer 8b so as to be drawn out to the outer edge. The grounding internal electrode 7 is
Is electrically connected to the grounding external electrode 4 at the outer edge of the dielectric layer 8b. The material of the grounding internal electrode 7 is A
g, Pd, Ni, or the like can be used.

A via hole 9 is provided at the center of the second dielectric layer 8b. As shown in FIG. 7, the via hole 9 is filled with a conductor 5a forming a part of the through conductor 5, and the conductor 5a is electrically insulated from the grounding internal electrode 7. Note that the conductor 5a is extended on the other main surface of the second dielectric layer 8b to facilitate conduction with the conductor 5a formed on the adjacent dielectric layer.

As shown in FIG. 8, in the grounding internal electrode 7, a portion 7 extending to the grounding external electrode is provided.
a are present at equal intervals and are radially drawn out from the center of the second dielectric layer 8b. Pull-out part 7a
Indicates a portion of the grounding internal electrode 7 excluding a portion where the signal internal electrode 6 and the grounding internal electrode 7 overlap (a portion forming a capacitance). Thereby, when the noise current flows to the grounding external electrode 4 through the four lead portions 7a, the magnetic fluxes generated around the respective noise currents cancel each other, and the ESL can be reduced.

As shown in FIG. 9, the grounding internal electrode 7 is preferably extended over the entire outer periphery of the second dielectric layer 8b. At this time, the number of connection points between the grounding internal electrode 7 and the grounding external electrode 4 is maximized, and the inductance component per second dielectric layer 8b is minimized, so that ESL can be reduced most effectively. Can be.

Further, as shown in FIGS. 10 and 11, a cutout may be formed in the internal electrode 7 for grounding. This increases the number of joints between the second dielectric layer 8b and the dielectric layer laminated thereon, thereby improving the joint state between the dielectric layers.

FIG. 12 is a cross-sectional view showing the third dielectric layer 8c. In the third dielectric layer 8c, a via hole 9 is provided at the center, and the via hole 9 is filled with a conductor 5a forming a part of the through conductor 5. Note that the conductor 5a is extended on both main surfaces of the third dielectric layer 8c to facilitate conduction with the conductor 5a formed on the adjacent dielectric layer.

The signal external electrodes 3 are formed on both ends of the laminate 2 in the laminating direction, and the ground external electrodes 4 are formed on the side surfaces of the laminate 2. Further, the through conductor 5 is formed by connecting the conductor layers 5a formed in the via holes 9 of the respective dielectric layers, and both ends of the through conductor 5 are connected to the signal external electrodes 3.
Is electrically connected to The material of the signal external electrode 3, the grounding external electrode 4, and the through conductor 5 may be Ag, Pd,
Ni or the like can be used. For example, the signal external electrode 3 and the ground external electrode 4 preferably have a layered structure in which Ni plating and Sn plating are sequentially applied on a thick film electrode made of Ag. (Embodiment 2) FIG. 13 is a sectional view showing a multilayer capacitor in this embodiment. This multilayer capacitor 1
1, the signal internal electrode 16 and the ground internal electrode 1
A capacitance is formed at a portion where the first and second electrodes 7 overlap in the stacking direction and at a portion where the first and second electrodes 7 face each other in the plane direction.

The laminate 12 has a structure in which first dielectric layers 18a and second dielectric layers 18b are alternately laminated, and further, a third dielectric layer 18c is laminated on both sides of the laminated intermediate. is there.

As shown in FIG. 14, the first dielectric layer 18
On one main surface of a, a grounding internal electrode 17 is formed so as to be drawn out to the outer edge, and a signal internal electrode 16 is formed at an interval from the grounding internal electrode 17. Further, a via hole 9 is provided at the center of the first dielectric layer 18a, and the via conductor 9 is provided in the via hole 9.
Is filled with a conductor 15a which forms a part of.

As shown in FIG. 15, the second dielectric layer 18
In FIG. 2B, a grounding internal electrode 7 is formed so as to be drawn out to the outer edge, and a via hole 9 is provided in the center. The via hole 9 is filled with a conductor 15a forming a part of the through conductor 15. I have. The grounding internal electrode 17 is
At the outer edge of the second dielectric layer 18b, the external ground electrode 1
4 and electrically insulated from the conductor 15a. The other configuration is the same as that of the first embodiment, and the description is omitted.

In the multilayer capacitor 11, a connection point between the grounding internal electrode 17 and the grounding external electrode 14 can be taken on both the first dielectric layer 18a and the second dielectric layer 18b. Therefore, ESL is greatly reduced. (Embodiment 3) FIG. 16 is a sectional view showing a multilayer capacitor in this embodiment. This multilayer capacitor 2
In 1, the capacitance is formed at a portion where the signal internal electrode 26 and the grounding internal electrode 27 face each other in the plane direction.

The laminated body 22 is the same as that of the second embodiment shown in FIG.
, A dielectric layer 28a (not shown) having the same configuration as the first dielectric layer 18a is laminated, and a dielectric layer 28c (not shown) on which no internal electrode is formed is laminated on both sides of the laminated intermediate. It is a thing. The other configuration is the same as that of the first embodiment, and the description is omitted.

In the multilayer capacitor 21, only the signal internal electrode 26 and the grounding internal electrode 27 face each other in the plane direction, and the capacitance is reduced. Also,
Since the connection point between the grounding internal electrode 27 and the grounding external electrode 24 can be taken in each dielectric layer, the ESL is reduced.

The resonance frequency f of the multilayer capacitor 21
₀ is derived from the equation shown in FIG. 17, and if C (capacitance) and L (ESL) decrease, f ₀ increases. Also, the resonance frequency f ₀ of the multilayer capacitor 21
The relationship between the impedance and the impedance Z is as shown in the graph of FIG. That is, as the resonance frequency f ₀ increases, the impedance Z in the high frequency portion decreases.

From the above, it can be understood that high frequency noise is efficiently removed in the multilayer capacitor 21 having a small capacitance and small ESL. (Embodiment 4) FIG. 19 is a sectional view showing a multilayer capacitor in this embodiment. This multilayer capacitor 3
1, a grounding external electrode 34 and a through conductor 35
A float electrode 30 electrically insulated from any of them is formed.

The laminated body 33 has a structure in which first dielectric layers 38a and second dielectric layers 38b are alternately laminated, and a third dielectric layer 38c is laminated above and below the first dielectric layers 38a and the second dielectric layers 38b.

As shown in FIG. 20, the second dielectric layer 38
A float electrode 30 is formed on one main surface of b so as not to be drawn out to the outer edge and at a fixed interval from a via hole 39 provided at the center. By changing the area of the float electrode 30, the capacitance of the multilayer capacitor 31 can be adjusted. Also,
The conductor 3 forming a part of the through conductor 35 is provided in the via hole 39.
5a is filled.

The first dielectric layer 38a has the same structure as the first dielectric layer 18a in the second embodiment shown in FIG. 14, and the third dielectric layer 38c is the same as that in the first embodiment. It has the same configuration as the third dielectric layer 8c. The other configuration is the same as that of the first embodiment, and the description is omitted. (Embodiment 5) FIG. 21 is a perspective view showing a multilayer capacitor in this embodiment, and FIGS.
FIG. 22 is a cross-sectional view of the multilayer capacitor cut along a line L ₄ -L ₄ in FIG. 21. This multilayer capacitor 41
Is a device in which the multilayer capacitors 1 of the first embodiment are arranged in an array and integrated. Multilayer capacitor 41
Is provided with a slit 40, and a grounding external electrode 44 is formed by extending the hole wall of the slit 40. Thus, the contact between the grounding internal electrode 47 and the grounding external electrode 47 can be secured without causing the adjacent grounding internal electrodes 47 to conduct. Note that the other configuration is the same as that of the first embodiment, and a description thereof will be omitted.

[0044]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
It was manufactured based on the following manufacturing method and its electrical characteristics were examined.

First, a ceramic slurry was prepared by mixing a dielectric material powder containing BaTiO ₃ as a main component and an organic binder in a solvent. Next, the obtained ceramic slurry was formed into a sheet to obtain a green sheet. Next, the green sheet is cut into a square of a predetermined size, a via hole 9 is provided at the center of each sheet, and a conductive paste made of Ag is filled to form a conductor 5a. (Corresponding to the third dielectric layer 8c). Next, a conductive paste made of Ag was applied on the third dielectric sheet to form the signal internal electrode 6, and a first dielectric sheet (corresponding to the first dielectric layer 8a) was obtained. . Similarly, the grounding internal electrode 7 is formed on the third dielectric sheet to form the second dielectric sheet (the second dielectric layer 8).
b). Next, a first dielectric sheet and a second dielectric sheet were alternately laminated, and a third dielectric sheet was laminated on the upper and lower sides of the dielectric sheets, followed by pressure bonding to obtain a laminate 2. Next, the laminate 2 is fired at about 1100 ° C., and 1.6 mm × 1.6 mm × 3.
A 2 mm sintered body was obtained. Next, electrodes made of Ag were baked on both ends and side surfaces of the obtained sintered body to form a signal external electrode 3 and a grounding external electrode 4.

The conventional multilayer capacitor 51 shown in FIG. 24 was used as a comparative example. In this comparative example, the same green sheet as that used in the example was cut into a rectangular shape having a predetermined size, and first and second internal electrodes 56 and 57 were formed on the obtained dielectric sheet. It is obtained by laminating, pressing, and firing dielectric sheets, and then forming first, second, and third terminal electrodes. In the comparative example, the chip size of the sintered body before forming the terminal electrode was 1.0 mm ×
1.0 mm × 4.5 mm, which satisfies the condition of X ₀ / Y ₀ ≧ 4.

The reference example has the same structure as that of the conventional multilayer capacitor 51, but satisfies X ₀ / Y ₀ <4. This reference example is manufactured by the same manufacturing method as that of the above comparative example, but the chip size of the sintered body before forming the terminal electrode is 1.6 mm × 1.6 mm × 3.2 mm. It is the same as

Next, in Examples, Comparative Examples and Reference Examples,
The capacitance between the signal external electrode and the ground external electrode and the resonance frequency were measured. Table 1 shows the results.

[0049]

[Table 1]

From Table 1, it can be seen that the embodiment has relatively high capacitance and resonance frequency. This means that the ESL of the example is the smallest as compared with the comparative example and the reference example from the mathematical formula of FIG. In addition, it can be seen from the measurement results of the resonance frequency that the embodiment is most excellent in the high frequency characteristics.

[0051]

In the multilayer capacitor according to the present invention, the noise current input from the external signal electrode reaches the internal signal electrode through the through conductor, and passes through the dielectric layer to the internal ground electrode. Flows to the grounding external electrode. At this time, since the grounding internal electrode can be arbitrarily pulled out toward the outer edge of the dielectric layer and connected to the grounding external electrode, the degree of freedom in designing the multilayer capacitor is increased.
Further, since the signal internal electrode and the through conductor are securely connected, it is possible to prevent an excessive increase in ESL and to remove noise without leakage.

Further, in the multilayer capacitor according to the present invention, the grounding internal electrode and the grounding external electrode are formed by forming the grounding internal electrode on the first dielectric layer and the second dielectric layer. Since the number of connection points increases, ESL can be greatly reduced.

Further, in the multilayer capacitor according to the present invention, a capacitance is formed planarly between the signal internal electrode and the grounding internal electrode formed on the same dielectric layer. At this time, the capacitance decreases, but the connection point between the grounding internal electrode and the grounding external electrode increases, so that the ESL also decreases. Therefore, the resonance frequency of the multilayer capacitor is increased, and the impedance at the high frequency portion is reduced, so that high frequency noise is easily removed.

Further, in the multilayer capacitor according to the present invention, the second dielectric layer is provided with a float electrode which is electrically insulated from both the grounding external electrode and the signal external electrode. It flows to the grounding external electrode with the float electrode as a bypass. At this time, by changing the size of the float electrode, the capacitance can be adjusted according to the application.

In the above multilayer capacitor,
The presence of three or more radially and equidistantly extending portions of the grounding internal electrode to the grounding external electrode cancels out magnetic fields generated around currents flowing through the respective drawing portions, and the ESL is generated. Can be reduced.

In the above multilayer capacitor,
The grounding external electrode is formed over the entire side surface of the laminate, and the grounding internal electrode is extended over the entire outer periphery of the dielectric layer. The area of the connection portion with the external electrode for grounding is maximized, and ESL can be reduced most.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a multilayer capacitor in a first embodiment.

FIG. 2 is a sectional view taken along line L ₁ -L _{1 in} FIG. ₁ ;

FIG. 3 is an exploded perspective view showing a laminated state of the laminated body according to the first embodiment.

FIG. 4 is a top view showing a first dielectric layer according to the first embodiment.

FIG. 5 is a sectional view taken along line L ₂ -L ₂ in FIG. 4;

FIG. 6 is a top view showing a second dielectric layer according to the first embodiment.

FIG. 7 is a sectional view taken along line L ₃ -L ₃ in FIG. 6;

FIG. 8 is an explanatory view showing a lead-out portion of a grounding internal electrode in the first embodiment.

FIG. 9 is a top view showing a modification of the second dielectric layer in the first embodiment.

FIG. 10 is a top view showing a modification of the second dielectric layer in the first embodiment.

FIG. 11 is a top view showing a modification of the second dielectric layer in the first embodiment.

FIG. 12 is a sectional view showing a third dielectric layer according to the first embodiment.

FIG. 13 is a sectional view showing the multilayer capacitor in the second embodiment.

FIG. 14 is a top view showing a first dielectric according to the second embodiment.

FIG. 15 is a top view showing a second dielectric according to the second embodiment.

FIG. 16 is a sectional view showing a multilayer capacitor in a third embodiment.

FIG. 17 is a mathematical expression showing a resonance frequency f ₀ [Hz]. L [H] ... Equivalent series inductance (ESL) C [F] ... Capacitance

FIG. 18 is a graph showing the relationship between the resonance frequency f ₀ and the impedance Z [Ω].

FIG. 19 is a sectional view showing a multilayer capacitor in a fourth embodiment.

FIG. 20 is a top view showing a second dielectric layer according to the fourth embodiment.

FIG. 21 is a perspective view showing a multilayer capacitor in a fifth embodiment.

FIG. 22 is a sectional view of the multilayer capacitor in the fifth embodiment cut along a line L ₄ -L _{4 in} FIG. 21;

FIG. 23 is a sectional view of the multilayer capacitor in the fifth embodiment cut along a line L ₄ -L _{4 in} FIG. 21;

FIG. 24 is a sectional view showing a conventional multilayer capacitor.

FIG. 25 is a sectional view showing a conventional multilayer capacitor.

FIG. 26 is a sectional view showing a conventional multilayer capacitor.

FIG. 27 is a sectional view showing a conventional multilayer capacitor.

FIG. 28 is a sectional view showing a conventional multilayer capacitor.

FIG. 29 is a sectional view showing a conventional multilayer capacitor.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 multilayer capacitor 2 laminate 3 external signal electrode 4 external electrode for grounding 5 through conductor 6 internal electrode for signal 7 internal electrode for grounding 8a first dielectric layer 8b second dielectric layer 9 via hole 30 float electrode 40 slit

Claims (6)

[Claims] 1. A laminate including a portion in which first dielectric layers and second dielectric layers are alternately laminated; signal external electrodes formed at both ends of the laminate in a lamination direction; A grounding external electrode formed on a side surface of the laminate, and a through conductor provided to penetrate the laminate along a laminating direction and electrically connected to the signal external electrode; The first dielectric layer includes a signal internal electrode that is electrically insulated from the ground external electrode and electrically connected to the through conductor. The second dielectric layer includes: A grounding internal electrode that is drawn out to the outer edge of the second dielectric layer so as to be electrically connected to the grounding external electrode and that is electrically insulated from the through conductor is formed. Characteristic multilayer capacitor. 2. A laminated body including a portion in which first dielectric layers and second dielectric layers are alternately laminated; signal external electrodes formed at both ends of the laminated body in a laminating direction; A grounding external electrode formed on a side surface of the laminate, and a through conductor provided to penetrate the laminate along a laminating direction and electrically connected to the signal external electrode; The first dielectric layer includes a grounding internal electrode extended to an outer edge of the first dielectric layer so as to be electrically connected to the grounding external electrode, and an electrical connection with the grounding internal electrode. A signal internal electrode that is insulated and electrically connected to the through conductor is formed, and the second dielectric layer is formed on the second dielectric layer so as to be electrically connected to the grounding external electrode. 2 is drawn out to the outer edge of the second dielectric layer and electrically connected to the through conductor. Multilayer capacitor wherein the insulated grounding inner electrodes are formed. 3. A laminate in which dielectric layers are laminated, a signal external electrode formed on both ends of the laminate in a laminating direction, and a ground external electrode formed on a side surface of the laminate. A through conductor that is provided to penetrate the laminate along the lamination direction and is electrically connected to the external signal electrode; and the dielectric layer is electrically connected to the external ground electrode. A grounding internal electrode extended to the outer edge of the dielectric layer, and a signal internal electrode electrically connected to the through conductor and electrically insulated from the grounding internal electrode. A multilayer capacitor. 4. A laminated body including a portion in which first dielectric layers and second dielectric layers are alternately laminated; signal external electrodes formed at both ends of the laminated body in a laminating direction; A grounding external electrode formed on a side surface of the laminate, and a through conductor provided to penetrate the laminate along a laminating direction and electrically connected to the signal external electrode; The first dielectric layer includes a grounding internal electrode extended to an outer edge of the first dielectric layer so as to be electrically connected to the grounding external electrode, and an electrical connection with the grounding internal electrode. A signal internal electrode that is insulated and electrically connected to the through conductor is formed, and the second dielectric layer is electrically connected to both the ground external electrode and the signal external electrode. That an insulated float electrode is formed Multilayer capacitor to. 5. The grounding internal electrode, wherein three or more lead-out portions to the grounding external electrode are present on the radiation and at equal intervals.
The multilayer capacitor according to any one of claims 1 to 4. 6. The grounding external electrode is formed over the entire periphery of the side surface of the laminate, and the grounding internal electrode is drawn out over the entire outer periphery of the dielectric layer. The multilayer capacitor according to any one of claims 1 to 5.