JP2002309396A - Plate-making plating method - Google Patents

Plate-making plating method

Info

Publication number
JP2002309396A
JP2002309396A JP2001112219A JP2001112219A JP2002309396A JP 2002309396 A JP2002309396 A JP 2002309396A JP 2001112219 A JP2001112219 A JP 2001112219A JP 2001112219 A JP2001112219 A JP 2001112219A JP 2002309396 A JP2002309396 A JP 2002309396A
Authority
JP
Japan
Prior art keywords
plating
resist
resist film
electrodeposition
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001112219A
Other languages
Japanese (ja)
Other versions
JP2002309396A5 (en
Inventor
Chikao Ikenaga
知加雄 池永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP2001112219A priority Critical patent/JP2002309396A/en
Publication of JP2002309396A publication Critical patent/JP2002309396A/en
Publication of JP2002309396A5 publication Critical patent/JP2002309396A5/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

PROBLEM TO BE SOLVED: To provide a plate-making plating method by which a uniform coating film of an electrodeposition photoresist is obtained and high quality plating is applied. SOLUTION: In the plate-making plating method which is performed by forming the resist film of the electrodeposition photoresist on the whole surface of a material to be plated, pattern exposing and successively developing, forming an opening part corresponding to a part to be plated on the resist film and stripping the resist film after the plating, the resist film of the electrodeposition photoresist is formed by using an electrodeposition vessel 10 in which an anode 11 is separated from a cathode 12 by a partition 15 passing an electrolyte, but not passing a resist aggregated material. Because the aggregated material of the electrodeposition photoresist is generated in the anode 11 side and does not exist in the cathode 12 side by the partition 15, the abnormality in the resist film, of the defects such as the remaining of the resist, uneven plating, or the chipping of plating is prevented.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、製版めっき方法の
技術分野に属し、特に、半導体パッケージを形成するた
めのリードフレームにワイヤーボンディングのために必
要なめっきを施す際に好適な製版めっき方法に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention belongs to the technical field of plate making and plating, and more particularly to a plate making and plating method suitable for applying a plating required for wire bonding to a lead frame for forming a semiconductor package. Things.

【0002】[0002]

【従来の技術】一般に、半導体パッケージのうちで最も
代表的な樹脂パッケージの骨組みとしていわゆる金属製
のリードフレームが使用されている。このリードフレー
ムは、半導体素子と外部とを電気的に結ぶための導電性
材料で、通常は厚さ0.1〜0.25mmの金属板が用
いられており、半導体素子とプリント基板との寸法上の
仲介役や、半導体素子で発生した熱を拡散するなどの役
割も果たしている。リードフレームの素材としては、鉄
合金系ならびに銅合金系が主流で、インナーリードの先
端にはワイヤーボンディングを行うために銀や金などの
接続用のめっきを施してある。
2. Description of the Related Art In general, a so-called metal lead frame is used as the most typical skeleton of a resin package among semiconductor packages. The lead frame is a conductive material for electrically connecting the semiconductor element to the outside. Usually, a metal plate having a thickness of 0.1 to 0.25 mm is used. It also plays the role of the mediator and diffuses the heat generated in the semiconductor device. As a material of the lead frame, an iron alloy type and a copper alloy type are mainly used, and the tip of the inner lead is plated with silver or gold for connection in order to perform wire bonding.

【0003】このような半導体パッケージでは、パッケ
ージラインに基材以外の金属が存在するとデントライト
(葉筋)が発生し、マイグレーションに至る。よって、
図1に示すQFN( Quad Flat Non-Leaded Package )
のように、パッケージ自体に外部端子が内蔵されている
背面実装型のパッケージは、リードが短いために、設計
上、前述の如くワイヤーボンディングエリアに銀や金の
金属めっきを±0.1mm以下の精度で施さなければな
らない。
In such a semiconductor package, if metal other than the base material is present in the package line, dentite (leaf streak) is generated, leading to migration. Therefore,
QFN (Quad Flat Non-Leaded Package) shown in Fig. 1
As shown in the figure, the back-mounted package in which external terminals are built into the package itself has short leads. Must be performed with precision.

【0004】なお、図1に示すQFNは、4隅にあるリ
ードフレーム1の吊りリードによりダイパッド2が支持
され、そのダイパッド2上にダイボンドペースト層3を
介して半導体素子4が搭載され、この半導体素子4の上
面の電極とリードフレーム1のリード5とがワイヤー6
により電気的に接続されており、リード5の一部を露出
させた状態でワイヤー6を含む半導体素子4の外囲領域
を封止樹脂7でモールドした形態をしている。
In the QFN shown in FIG. 1, a die pad 2 is supported by suspension leads of a lead frame 1 at four corners, and a semiconductor element 4 is mounted on the die pad 2 via a die bond paste layer 3. The electrode on the upper surface of the element 4 and the lead 5 of the lead frame 1
, And an area surrounding the semiconductor element 4 including the wire 6 is molded with a sealing resin 7 with a part of the lead 5 exposed.

【0005】上記のようにリードフレームのワイヤーボ
ンディングエリアにめっきを施す場合、従来の治具めっ
き方法は、治具自体の精度及び治具とリードフレームの
位置合わせ精度から、±0.15mmが限界であり、さ
らに側面へのめっき付着は防ぎようがなく、したがって
上記したQFNのような背面実装型パッケージ用のリー
ドフレームへは適用できなかった。
When plating the wire bonding area of the lead frame as described above, the conventional jig plating method has a limit of ± 0.15 mm due to the accuracy of the jig itself and the positioning accuracy of the jig and the lead frame. Further, it is not possible to prevent the plating from adhering to the side surface, and therefore, it cannot be applied to a lead frame for a back-mount package such as the above-mentioned QFN.

【0006】このようなことから、リードフレームのワ
イヤーボンディングエリアにめっきを施す手段として製
版めっき方法が採られている。すなわち、リードフレー
ム全体にフォトレジストを塗布し、治具孔をアライメン
トマークとしてフォトマスクとリードフレームを位置合
わせし、露光とそれに続く現像を行ってから、金属めっ
きを施し、次いでレジスト剥離し、さらに洗浄した後、
必要に応じて後処理を行う製版めっき方法を適用するこ
とによって量産化を図ることが行われている。
For this reason, a plate making plating method has been adopted as a means for plating a wire bonding area of a lead frame. That is, a photoresist is applied to the entire lead frame, the photomask and the lead frame are aligned using the jig hole as an alignment mark, exposure and subsequent development are performed, metal plating is performed, and then the resist is peeled off. After washing,
Mass production has been achieved by applying a plate-making plating method for performing post-processing as necessary.

【0007】[0007]

【発明が解決しようとする課題】従来の技術で述べた製
版めっき方法は、高い位置精度でめっきが行え、しかも
側面にめっきが付着しないという利点を有している。し
かしながら、電着槽内でめっき対象物であるリードフレ
ームの表面に電着フォトレジストのレジスト膜を形成す
る際に、均一な塗膜状態が得られないという問題点があ
る。すなわち、電着フォトレジストはその性質から酸性
領域で凝集、凝固することが分かっているが、電着フォ
トレジストのレジスト膜形成時に電着槽の陽極側は「2
2 O→4H+ +O2 」の反応が起こって酸性となるの
で、電着フォトレジストの凝集物質が発生する。そし
て、このように電着フォトレジストの凝集物質が生じる
と、レジスト槽内に異物として浮遊し、それがリードフ
レームに付着し、陰極側のリードフレームの塗膜状態が
不均一となり、レジスト残り、めっきムラ、めっき欠け
等の不良モードが発生する。
The plate-making plating method described in the prior art has the advantage that plating can be performed with high positional accuracy and that plating does not adhere to the side surfaces. However, when a resist film of an electrodeposition photoresist is formed on the surface of a lead frame to be plated in an electrodeposition bath, there is a problem that a uniform coating state cannot be obtained. That is, it is known that the electrodeposited photoresist coagulates and coagulates in an acidic region due to its properties, but the anode side of the electrodeposition bath is "2" when the resist film of the electrodeposited photoresist is formed.
A reaction of “H 2 O → 4H + + O 2 ” takes place and becomes acidic, so that an agglomerated substance of the electrodeposited photoresist is generated. Then, when the coagulated substance of the electrodeposited photoresist is generated as described above, it floats as a foreign substance in the resist tank, adheres to the lead frame, the coating state of the lead frame on the cathode side becomes uneven, the resist remains, Failure modes such as uneven plating and missing plating occur.

【0008】本発明は、このような問題点に鑑みてなさ
れたものであり、その目的とするところは、電着フォト
レジストの均一な塗膜が得られ、その結果、品質のよい
めっきを施すことができる製版めっき方法を提供するこ
とにある。
The present invention has been made in view of the above problems, and has as its object the purpose of obtaining a uniform coating film of an electrodeposited photoresist and, as a result, applying high quality plating. It is an object of the present invention to provide a plate-making plating method that can perform the plate-making.

【0009】[0009]

【課題を解決するための手段】上記の目的を達成するた
め、本発明の製版めっき方法は、めっき対象物の表面全
体に電着フォトレジストのレジスト膜を形成した後、パ
ターン露光とそれに続く現像を行って、めっきすべき部
分に対応する開口部をレジスト膜に形成し、めっきを行
った後でレジスト剥離を行う製版めっき方法において、
電解液は通すが陽極側で発生したレジスト凝集物質は通
さない隔壁により陽極と陰極の間を隔離した電着槽を使
用して電着フォトレジストのレジスト膜を形成すること
を特徴としている。
In order to achieve the above-mentioned object, a plate-making plating method according to the present invention comprises forming a resist film of an electrodeposited photoresist on the entire surface of an object to be plated, pattern exposure and subsequent development. In the plate-making plating method of forming an opening corresponding to a portion to be plated in a resist film and stripping the resist after plating,
It is characterized in that a resist film of an electrodeposited photoresist is formed using an electrodeposition tank in which an anode and a cathode are separated by a partition wall which allows an electrolyte to pass therethrough but does not allow a resist coagulation substance generated on the anode side.

【0010】[0010]

【発明の実施の形態】図2は本発明に係る製版めっき方
法を実施する装置の概略構成図であり、以下、この図2
を参照して本発明の実施の形態について述べる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a schematic structural view of an apparatus for performing a plate-making plating method according to the present invention.
An embodiment of the present invention will be described with reference to FIG.

【0011】図2において10は電着槽であり、その中
に陽極11と陰極12が懸架されており、両者ともに電
解液13に浸漬した状態になっている。陰極12はめっ
き対象物としてのリードフレームで、フック14により
電着槽10内に吊り下げられており、電着槽10内にお
いて全面に電着フォトレジストのレジスト膜を形成する
ようになっている。
In FIG. 2, reference numeral 10 denotes an electrodeposition tank in which an anode 11 and a cathode 12 are suspended and both are immersed in an electrolyte 13. The cathode 12 is a lead frame as an object to be plated, and is suspended in the electrodeposition bath 10 by a hook 14 so that a resist film of an electrodeposition photoresist is formed on the entire surface of the electrodeposition bath 10. .

【0012】電着槽10の中は、多孔質セラミックから
なる隔壁15により陽極11と陰極12が隔離されてい
る。この隔壁15は、電解液は通すが陽極側で発生した
レジスト凝集物質は通さない構成である。
In the electrodeposition tank 10, the anode 11 and the cathode 12 are separated by a partition wall 15 made of porous ceramic. The partition wall 15 is configured to allow the passage of the electrolytic solution but not the resist coagulated substance generated on the anode side.

【0013】20は電解液タンクであり、電着槽10の
電解液を入れ替えるため、電着槽10との間の配管によ
り電解液を循環させるようになっている。すなわち、電
解液タンク20からポンプ21によりフィルター22を
通して電着槽10に電解液を供給するとともに、電着槽
10から電解液を回収することで循環させている。
Reference numeral 20 denotes an electrolyte tank, which is arranged to circulate the electrolyte through a pipe between the electrodeposition tank 10 and the electrodeposition tank 10 in order to replace the electrolyte. That is, the electrolytic solution is supplied from the electrolytic solution tank 20 to the electrodeposition tank 10 through the filter 22 by the pump 21, and is circulated by collecting the electrolytic solution from the electrodeposition tank 10.

【0014】また、使用する電解液は、pHを一定に保
つため、緩衝溶液としてアンモニア水を入れるのが好ま
しい。このように緩衝溶液を加えることで、電着フォト
レジストの凝集物質が発生しにくくなる。
Further, it is preferable to use aqueous ammonia as a buffer solution in the electrolytic solution used in order to keep the pH constant. The addition of the buffer solution makes it difficult to generate agglomerated substances of the electrodeposited photoresist.

【0015】[0015]

【実施例】ここでは、リードフレームのワイヤーボンデ
ィングエリアにめっきを施す場合を例に挙げて説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Here, a case where plating is performed on a wire bonding area of a lead frame will be described as an example.

【0016】厚さ0.2mmの銅合金平板「EFTEC
64T」をエッチングしてなるマップタイプのQFN用
のリードフレームを準備し、このリードフレームに対し
て前処理を行った。具体的には、リードフレームの表面
に付いた油、汚れ等を脱脂液を用いて取り除いた後、酸
洗してから化学研磨を行った。
A 0.2 mm thick copper alloy flat plate "EFTEC"
A map type QFN lead frame prepared by etching “64T” was prepared, and the lead frame was pre-processed. Specifically, after removing oil, dirt, and the like attached to the surface of the lead frame using a degreasing solution, the surface was pickled and then chemically polished.

【0017】次いで、一般的なシアン浴にて全面にCu
ストライクめっきを厚さ0.3μmで施し、その上から
全面に電着フォトレジストのレジスト膜を形成した。具
体的には、多孔質セラミックの隔壁により陽極と陰極の
間を隔離した図2に示すタイプの装置を使用し、電着レ
ジスト材として「Eagle2100ED(SHIPL
EY社)」を用い、35℃の溶液中で80秒間、100
Vの電圧をかけて電着させた。
Next, the entire surface of Cu is exposed to Cu in a general cyan bath.
Strike plating was applied to a thickness of 0.3 μm, and a resist film of an electrodeposition photoresist was formed on the entire surface from above. Specifically, an apparatus of the type shown in FIG. 2 in which an anode and a cathode are separated by a porous ceramic partition is used, and “Eagle2100ED (SHIPL) is used as an electrodeposition resist material.
EY) in a solution at 35 ° C. for 80 seconds
A voltage of V was applied for electrodeposition.

【0018】この電着プロセス時において、陽極側では
開始してから24時間後に凝集物質が発生したが、この
凝集物質は隔壁を通過することはなく、したがって陰極
側に凝集物質は全く存在せず、リードフレームのレジス
ト膜への異常は見られなかった。
During the electrodeposition process, agglomerated substances were generated on the anode side 24 hours after the start, but the agglomerated substances did not pass through the partition walls, and thus no agglomerated substances were present on the cathode side. No abnormality was found in the resist film of the lead frame.

【0019】また、上記の電着プロセスとは別に、電解
液に緩衝溶液としてアンモニア水を加えた状態で同様の
電着を行ったところ、168時間後に凝集物質が発生し
た。すなわち、緩衝溶液を入れた電解液を使用すると、
電着フォトレジストのレジスト成分が変質して凝集する
タイミングが遅くなることが確認できた。
Separately from the above-mentioned electrodeposition process, the same electrodeposition was carried out in a state in which aqueous ammonia was added as a buffer solution to the electrolytic solution, and aggregated substances were generated after 168 hours. In other words, when using an electrolyte containing a buffer solution,
It was confirmed that the timing at which the resist components of the electrodeposited photoresist deteriorated and aggregated was delayed.

【0020】電着レジストが乾燥した後、まず始めに裏
面全体に対して超高圧水銀灯により露光を行い、裏面側
レジストのタック性を消失せしめた。次いで、フォトマ
スクをリードフレームの治具孔でアライメントした後、
表面側レジストに対してパターン露光を行った。続い
て、現像工程を行って、リード先端にレジスト膜の開口
部を形成した。現像液は「Eagle2005(SHI
PLEY社)」を使用し、40℃の現像液に60秒間浸
漬した。
After the electrodeposited resist was dried, the entire back surface was first exposed with an ultra-high pressure mercury lamp to eliminate the tackiness of the back side resist. Next, after aligning the photomask with the jig hole of the lead frame,
Pattern exposure was performed on the front side resist. Subsequently, a development step was performed to form an opening of the resist film at the tip of the lead. The developer is “Eagle2005 (SHI
(PLEY)) for 60 seconds in a developer at 40 ° C.

【0021】次いで、リード先端の開口部に銀めっきを
厚さ3〜10μmで施した。この銀めっきは一般的なシ
アン浴によるスパージャめっきで行った。その後、電着
レジストの剥離を行った。剥離液は「Eagle200
9(SHIPLEY社)」を使用し、50℃の剥離液に
30秒間浸漬した。そして、洗浄した後、最後に変色防
止処理を施してから乾燥させた。
Next, silver plating was applied to the opening at the tip of the lead to a thickness of 3 to 10 μm. This silver plating was performed by sparger plating using a general cyan bath. Thereafter, the electrodeposition resist was peeled off. The stripping solution is “Eagle200
9 (SHIPLEY) "for 30 seconds in a 50 ° C. stripper. Then, after the washing, a discoloration preventing treatment was finally performed, followed by drying.

【0022】その結果、レジスト残り、めっきムラ、め
っき欠け等が皆無のリードフレームが得られた。
As a result, there was obtained a lead frame free of any remaining resist, uneven plating, chipped plating, and the like.

【0023】上記のように加工したリードフレームに対
し、半導体素子をマウントした。具体的には、まずリー
ドフレームの裏面側の全面に粘着テープを貼り付けた。
次いで、ダイサイズが1.8mm角の半導体素子をAg
ペーストでダイボンディングし、180℃で1時間硬化
させた。次いで、200℃で1分間かけてワイヤーボン
ディングを行った後、エポキシ樹脂を用いて一括モール
ドを行い、180℃で5時間かけて硬化させた。この樹
脂モールドの後、粘着テープを剥離し、Snめっきを行
ってから、ダイシングにより個片化することでQFN型
の半導体パッケージが得られた。
A semiconductor element was mounted on the lead frame processed as described above. Specifically, first, an adhesive tape was attached to the entire back surface of the lead frame.
Next, a semiconductor element having a die size of 1.8 mm square was Ag.
The paste was die-bonded and cured at 180 ° C. for 1 hour. Next, after performing wire bonding at 200 ° C. for 1 minute, collective molding was performed using an epoxy resin, followed by curing at 180 ° C. for 5 hours. After this resin mold, the adhesive tape was peeled off, plated with Sn, and diced into individual pieces to obtain a QFN type semiconductor package.

【0024】[0024]

【発明の効果】本発明の製版めっき方法は、めっき対象
物の表面全体に電着フォトレジストのレジスト膜を形成
した後、パターン露光とそれに続く現像を行って、めっ
きすべき部分に対応する開口部をレジスト膜に形成し、
めっきを行った後でレジスト剥離を行う製版めっき方法
において、電解液は通すが陽極側で発生したレジスト凝
集物質は通さない隔壁により陽極と陰極の間を隔離した
電着槽を使用して電着フォトレジストのレジスト膜を形
成することを特徴としているので、陽極側で電着フォト
レジストの凝集物質が発生しても、隔壁によって陰極側
には凝集物質が存在せず、レジスト膜に異常が生じない
ことから、レジスト残り、めっきムラ、めっき欠け等の
不良の発生を防止することができる。
According to the plate-making plating method of the present invention, a resist film of an electrodeposited photoresist is formed on the entire surface of an object to be plated, followed by pattern exposure and subsequent development to form openings corresponding to portions to be plated. Part is formed on the resist film,
In the plate-making plating method in which the resist is stripped after plating, the electrodeposition is performed using an electrodeposition tank in which the anode and the cathode are separated by a partition wall that allows the passage of the electrolyte but does not allow the coagulation of the resist generated on the anode side. It is characterized by forming a photoresist resist film, so even if the electrodeposited photoresist coagulates on the anode side, no agglomerate exists on the cathode side due to the partition walls, causing an abnormality in the resist film Because of the absence, it is possible to prevent the occurrence of defects such as remaining resist, uneven plating, and missing chips.

【図面の簡単な説明】[Brief description of the drawings]

【図1】半導体パッケージの一つであるQFNを示す断
面図である。
FIG. 1 is a sectional view showing a QFN which is one of semiconductor packages.

【図2】本発明に係る製版めっき方法を実施する装置の
概略構成図である。
FIG. 2 is a schematic configuration diagram of an apparatus for performing a plate-making plating method according to the present invention.

【符号の説明】[Explanation of symbols]

1 リードフレーム 2 ダイパッド 3 ダイボンドペースト層 4 半導体素子 5 リード 6 ワイヤー 7 封止樹脂 10 電着槽 11 陽極 12 陰極 13 電解液 14 フック 15 隔壁 20 電解液タンク 21 ポンプ 22 フィルター DESCRIPTION OF SYMBOLS 1 Lead frame 2 Die pad 3 Die bond paste layer 4 Semiconductor element 5 Lead 6 Wire 7 Sealing resin 10 Electrodeposition tank 11 Anode 12 Cathode 13 Electrolyte 14 Hook 15 Partition wall 20 Electrolyte tank 21 Pump 22 Filter

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 めっき対象物の表面全体に電着フォトレ
ジストのレジスト膜を形成した後、パターン露光とそれ
に続く現像を行って、めっきすべき部分に対応する開口
部をレジスト膜に形成し、めっきを行った後でレジスト
剥離を行う製版めっき方法において、電解液は通すが陽
極側で発生したレジスト凝集物質は通さない隔壁により
陽極と陰極の間を隔離した電着槽を使用して電着フォト
レジストのレジスト膜を形成することを特徴とする製版
めっき方法。
1. After forming a resist film of an electrodeposited photoresist on the entire surface of an object to be plated, pattern exposure and subsequent development are performed to form openings in the resist film corresponding to portions to be plated. In the plate-making plating method in which the resist is stripped after plating, the electrodeposition is performed using an electrodeposition tank in which the anode and the cathode are separated by a partition wall that allows the passage of the electrolyte but does not allow the coagulation of the resist generated on the anode side. A plate-making plating method comprising forming a resist film of a photoresist.
JP2001112219A 2001-04-11 2001-04-11 Plate-making plating method Pending JP2002309396A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001112219A JP2002309396A (en) 2001-04-11 2001-04-11 Plate-making plating method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001112219A JP2002309396A (en) 2001-04-11 2001-04-11 Plate-making plating method

Publications (2)

Publication Number Publication Date
JP2002309396A true JP2002309396A (en) 2002-10-23
JP2002309396A5 JP2002309396A5 (en) 2010-01-21

Family

ID=18963673

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001112219A Pending JP2002309396A (en) 2001-04-11 2001-04-11 Plate-making plating method

Country Status (1)

Country Link
JP (1) JP2002309396A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006115267A1 (en) * 2005-04-26 2006-11-02 Dai Nippon Printing Co., Ltd. Circuit member, circuit member manufacturing method, semiconductor device and multilayer structure on circuit member surface

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5016376B1 (en) * 1969-12-24 1975-06-12
JPS6415398A (en) * 1987-07-09 1989-01-19 Kyushu Nippon Electric Rack jig for plating lead frame
JPH0270097A (en) * 1988-09-06 1990-03-08 Ibiden Co Ltd Electrodeposition coating apparatus
JPH06220695A (en) * 1993-01-26 1994-08-09 Shikino Mekki Kk Plating method and device therefor
JPH07238397A (en) * 1994-02-25 1995-09-12 Electroplating Eng Of Japan Co Dip plating device for sheet-like object
JPH0964264A (en) * 1995-08-28 1997-03-07 Dainippon Printing Co Ltd Partial plating method for lead frame
JP2000031366A (en) * 1998-07-14 2000-01-28 Dainippon Printing Co Ltd Resin sealed semiconductor device and circuit member used therefor, and manufacture thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5016376B1 (en) * 1969-12-24 1975-06-12
JPS6415398A (en) * 1987-07-09 1989-01-19 Kyushu Nippon Electric Rack jig for plating lead frame
JPH0270097A (en) * 1988-09-06 1990-03-08 Ibiden Co Ltd Electrodeposition coating apparatus
JPH06220695A (en) * 1993-01-26 1994-08-09 Shikino Mekki Kk Plating method and device therefor
JPH07238397A (en) * 1994-02-25 1995-09-12 Electroplating Eng Of Japan Co Dip plating device for sheet-like object
JPH0964264A (en) * 1995-08-28 1997-03-07 Dainippon Printing Co Ltd Partial plating method for lead frame
JP2000031366A (en) * 1998-07-14 2000-01-28 Dainippon Printing Co Ltd Resin sealed semiconductor device and circuit member used therefor, and manufacture thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006115267A1 (en) * 2005-04-26 2006-11-02 Dai Nippon Printing Co., Ltd. Circuit member, circuit member manufacturing method, semiconductor device and multilayer structure on circuit member surface
JP2006310397A (en) * 2005-04-26 2006-11-09 Dainippon Printing Co Ltd Circuit member, its manufacturing method, semiconductor device and multilayer structure of surface of circuit member
KR100928474B1 (en) * 2005-04-26 2009-11-25 다이니폰 인사츠 가부시키가이샤 Method of manufacturing a circuit member
US8739401B2 (en) 2005-04-26 2014-06-03 Dai Nippon Printing Co., Ltd. Circuit member, manufacturing method for circuit members, semiconductor device, and surface lamination structure for circuit member
US8742554B2 (en) 2005-04-26 2014-06-03 Dai Nippon Printing Co., Ltd. Circuit member, manufacturing method for circuit members, semiconductor device, and surface lamination structure for circuit member

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