JP2002305131A - Semiconductor integrated circuit device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the chip region in a semiconductor wafer so as to take as many semiconductor chips as possible. SOLUTION: Alignment marks M9 and MM1 and the like are formed in the area GA, which is located in the chip region and at the periphery of the chip region. On an upper interlayer dielectric TH1 on the alignment marks M9, a resist film to which the pattern on a photomask has been transferred by aligning the pattern of the alignment marks M9 with the patterns on the photomask being formed, and contact holes C1 are formed. As a result, there is no need for the alignment marks M9 and MM1 and the like to be formed in the scribe region, and thus the chip region can be ensured of enlargement.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technique which is effective when applied to alignment between a photomask and a semiconductor wafer.

[0002]

2. Description of the Related Art Elements, wirings and the like constituting a semiconductor integrated circuit are formed in a chip area on a semiconductor wafer. After the integrated circuit is formed, the semiconductor wafer is cut along scribe lines for dividing the chip area. Is singulated.

[0003]

On the other hand, by collecting as many semiconductor chips as possible from one semiconductor wafer, it is possible to reduce the product cost and improve the yield.

[0004] However, alignment marks (targets) are formed on the scribe lines for aligning the exposure apparatus used in the photolithography process (see, for example, JP-A-11-29776).
Therefore, a certain width is required and the chip area is limited.

An object of the present invention is to provide a technique capable of increasing a chip area in a semiconductor wafer.

It is another object of the present invention to collect as many semiconductor chips as possible from a semiconductor wafer.

The above objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) In a method of manufacturing a semiconductor integrated circuit device according to the present invention, a first pattern is formed in a chip area and at an outer peripheral portion of the chip area, and a first pattern is formed inside the first pattern formation position. After forming the second pattern, the first
And the first pattern on the second film on the second pattern.
Forming a resist film to which the pattern on the photomask is transferred by aligning the pattern on the photomask with the mark on the photomask, and patterning the second film.

(2) A semiconductor integrated circuit device according to the present invention has a pattern for aligning an exposure apparatus formed on a singulated semiconductor substrate at an outer peripheral portion of the semiconductor substrate.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

First, a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention will be described.

FIG. 1 is a plan view of a semiconductor wafer W on which a semiconductor integrated circuit is formed. As shown in FIG. 1, a chip area CA and a scribe area SA (about 20 μm in width) exist on the semiconductor wafer W. I do. In the chip area CA, a MISFET (Metal Insulato) constituting a semiconductor integrated circuit is provided.
r Semiconductor Field Effect Transistor), and a plurality of semiconductor chips C are formed by cutting (dicing) along the scribe area SA after forming the integrated circuit.

Hereinafter, a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention will be described.
Channel type MISFET Qn and p channel type MIS
An example in which the FET Qp is formed will be described. 2 to 1
1 is a cross-sectional view or a plan view of a main part of a substrate, showing an example of a method for manufacturing a semiconductor integrated circuit device having MISFETs Qn and Qp. In the cross-sectional views, the left side in the figure shows the vicinity of the scribe area SA of the semiconductor wafer W, and the right side shows the chip area CA.

First, as shown in FIG. 2, an element isolation 2 is formed on a semiconductor substrate 1 (semiconductor wafer W) made of p-type single crystal silicon. In order to form the element isolation 2, an element isolation groove is formed by etching the semiconductor substrate 1, and a thin silicon oxide film is formed on the inner wall of the groove by thermally oxidizing the substrate 1. Next, a silicon oxide film 7 is deposited on the substrate 1 including the inside of the groove by a CVD (Chemical Vapor deposition) method, and is subjected to chemical mechanical polishing (CMP).
The surface of the silicon oxide film 7 is flattened by polishing the silicon oxide film 7 above the groove by an ical mechanical polishing method.

Next, a p-type impurity and an n-type impurity are ion-implanted into the substrate 1 and the impurities are diffused by heat treatment to form a p-type well 3 and an n-type well 4, and then the p-type well is formed by thermal oxidation. A clean gate oxide film 8 is formed on each surface of the 3 and n-type wells 4.

Next, as shown in FIG. 3, the gate oxide film 8 is formed.
A low-resistance polycrystalline silicon film doped with phosphorus is
A thin WN film and a W film are deposited thereon by a sputtering method, and a CVD method is further formed thereon.
A silicon nitride film 10 is deposited by a method.

Next, the silicon nitride film 10 is dry-etched to leave the silicon nitride film 10 in the region where the gate electrode is to be formed and in the chip region CA and on the outer peripheral portion GA of the chip region CA. Membrane 1
By dry-etching the W film, the WN film and the polycrystalline silicon film using 0 as a mask, a gate electrode 9 and an alignment mark M9 made of these films are formed. Here, the outer peripheral portion GA of the chip region CA is a region (P) where a pad portion P to be described later is formed.
Design so as not to arrange semiconductor elements and wiring as much as possible. Therefore, such an area GA has many empty areas, and by forming the alignment mark M9 therein, the scribe area can be narrowed. FIG. 4 is a plan view of the vicinity of the chip area CA showing the positional relationship between the pad portion P and the alignment mark M9. As shown in FIG. 4, various shapes such as a square shape and a cross shape can be considered as the shape of the alignment mark. Note that the alignment mark M9 is not limited to a position directly below the pad portion P, and may be formed at another position as long as it is in the outer peripheral portion GA, for example, in a region having a width of about 100 μm from the end of the chip.

Next, the p-type wells 3 on both sides of the gate electrode 9 are formed.
An n ⁻ -type semiconductor region 11 is formed by ion-implanting an n-type impurity into the n-type well, and a p ⁻ -type semiconductor region 12 is formed by ion-implanting a p-type impurity into the n-type well 4.
To form

Next, as shown in FIG.
After depositing a silicon nitride film by the method D, the sidewall spacers 13 are formed on the side walls of the gate electrode 9 by anisotropically etching. At this time, the sidewall spacer 13 also remains on the side wall of the alignment mark M9.

Next, an n ⁺ -type semiconductor region 14 (source and drain) is formed by ion-implanting an n-type impurity into the p-type well 3, and a p-type impurity is ion-implanted into the n-type well 4. ⁺ Type semiconductor region 15
(Source, drain) are formed.

In the steps so far, LDD (Lightly Doped
N-channel type MISFET Qn and p-channel type MISFET Qp
Is formed.

Thereafter, as shown in FIG.
After a silicon oxide film having a thickness of about 700 nm to 800 nm is deposited on n and Qp by the CVD method, the silicon oxide film is
The interlayer insulating film TH1 is formed by polishing by the MP method and flattening the surface.

Next, a photoresist film R is formed on the interlayer insulating film TH1, and the mask pattern formed on the photomask is transferred (exposed / developed). At this time, by aligning the mask alignment mark formed on the photomask with the above-described alignment mark M9, a contact is formed on the n ⁺ -type semiconductor region 14 and the p ⁺ -type semiconductor region 15 (source and drain). Hole patterns can be superimposed. Next, the contact hole C1 is formed on the n ⁺ -type semiconductor region 14 and the p ⁺ -type semiconductor region 15 on the main surface of the semiconductor substrate 1 by etching the interlayer insulating film TH1 using the photoresist film R as a mask.

Next, the photoresist film R is removed, and a tungsten film is deposited by CVD on the interlayer insulating film TH1 including the inside of the contact hole C1, as shown in FIG. The plug P1 is formed in the contact hole C1 by polishing by a CMP method until the plug P1 is exposed.

Next, the interlayer insulating film TH1 and the plug P
A titanium nitride film (not shown), an aluminum film, and a titanium nitride film (not shown) are sequentially deposited on the substrate 1 by a sputtering method, and are patterned into a desired shape.
The layer wiring M1 is formed. When patterning the first layer wiring M1, the above-described alignment mark M9 may be used for alignment with a photomask. Thus, 1
One alignment mark can be used for forming a plurality of patterns (contact hole patterns and wiring patterns). However, if an alignment mark of a lower layer is used too much for the film to be patterned, the mark will be blurred or distorted, and the alignment accuracy will be poor. Therefore, it is necessary to appropriately form an alignment mark.

For example, at the time of forming the above-mentioned first layer wiring M1,
On the alignment mark M9, a titanium nitride film (not shown), an aluminum film, and a titanium nitride film (not shown)
Is formed in advance (see FIG. 7).

Next, as shown in FIG.
1, an interlayer insulating film TH2 similar to the interlayer insulating film TH1.
To form Thereafter, a contact hole C2 is formed in the interlayer insulating film TH2, and a plug P2 is formed in the contact hole C2. The contact hole C2 and the plug P2 correspond to the contact hole C1 and the plug P1.
It is formed in the same manner as described above. That is, a contact hole C2 is formed in the interlayer insulating film TH2 using the alignment mark MM1 for alignment, and a plug P2 is formed by embedding a tungsten film in the contact hole C2.

Further, the interlayer insulating film TH2 and the plug P
2, a second layer wiring M2 is formed in the same manner as the first layer wiring M1. When patterning the second layer wiring M2, the above-described alignment mark MM1 may be used for alignment. Further, at this time, an alignment mark MM2 may be formed (see FIG. 8), and may be used for alignment in the subsequent patterning of the contact hole C3 and the third-layer wiring M3.

Next, as shown in FIG.
2 as well as the interlayer insulating film TH1.
3 and then a contact hole C3 and a plug P3 are formed in the interlayer insulating film TH2. The contact hole C3 and the plug P3 are
1 and the plug P1.

Next, the interlayer insulating film TH3 and the plug P
A third layer wiring M3 is formed on the third layer 3 in the same manner as the first layer wiring M1. When patterning the third layer wiring M3, the above-described alignment mark MM2 may be used for alignment. The third layer wiring M3 is the uppermost layer wiring and extends to the outer peripheral portion GA of the above-described chip area CA.

Next, as shown in FIG. 10, a passivation film PV made of a silicon nitride film or the like is formed on the third layer wiring M3.

Further, a contact hole C4 is formed by selectively removing the passivation film PV located on the outer peripheral portion GA on the third layer wiring M3. At the bottom of the contact hole C, the surface (pad portion P) of the uppermost wiring is exposed.

Next, including the inside of the contact hole C4,
An underlying metal layer 27 made of Au (gold) or the like on the pad portion P
To form The base metal layer 27 is formed to improve solder wetting (adhesion of a solder paste described later).

Next, Sn (tin) and Pb are formed on the underlying metal layer 27 and on the passivation film PV in the vicinity thereof.
A solder paste made of an alloy of (lead) is formed by screen printing or the like, and is subjected to a heat treatment to form a bump electrode 2.
8 is formed.

Next, the wafer W shown in FIGS.
Is cut into individual chip areas CA to form a plurality of chips C.

As described above, according to the present embodiment, since the alignment marks used for patterning the contact holes and the wirings are formed in the outer peripheral portion GA of the chip area CA, the alignment marks are formed on the scribe area SA. The scribe area SA can be made small, for example, about 20 μm in width.

That is, as shown in FIG. 11, in order to form the alignment mark M in the scribe area SA, it is necessary to make the width of the scribe area SA larger than the size of the alignment mark M. Although it depends on the size of the alignment mark M, a width of about 90 μm is usually required.

On the other hand, in the present embodiment, a large chip area CA can be ensured, and the number of semiconductor chips obtained from one wafer can be increased. Further, the product yield can be increased.

According to the present embodiment, since it is not necessary to provide an alignment mark in the scribe area SA, only an insulating film such as a silicon oxide film can be left on the scribe area SA. The stress at the time can be reduced. As a result, generation of cracks that can occur during dicing can be reduced.

That is, in the above case, since the alignment marks (M9, MM1, etc.) are formed using a metal film such as a polycrystalline silicon film or an aluminum film, the alignment marks are formed in the scribe area SA as shown in FIG. (M
9, MM1), a metal film having hardness different from that of the insulating film remains in the insulating film such as the silicon oxide film. As a result, various films must be cut during dicing, and cracks are likely to occur.

On the other hand, in this embodiment, since only the insulating film such as the silicon oxide film can be left, the occurrence of cracks can be reduced.

Thereafter, the chip C is mounted on, for example, a lead frame or a mounting board. FIG. 13 is a diagram showing a case where the semiconductor device is mounted on a lead frame 30.
FIG. 4 is a view showing a case where the mounting is similar on the mounting board 41. Less than,
These mounting methods will be briefly described.

The lead frame 30 has a tab portion 32 on which a chip is mounted, and a lead portion 33 disposed around the tab portion 32. The lead portion 33 is connected to an outer frame portion. The tab portion 32 and the outer frame portion are connected via a tab suspension lead. A die bond material such as a silver paste is formed on the tab portion 32 of the lead frame 30,
By mounting the semiconductor chip C thereon, the semiconductor chip C is fixed on the tab portion 32.

Thereafter, bump electrodes (not shown) on the surface of the semiconductor chip C are connected to the lead portions 33 of the lead frame 30 using conductive wires 37 such as gold wires.

Next, the periphery of the semiconductor chip C is covered with a sealing resin 38 using a molding die or the like, and the ends of the tab suspension leads and the plurality of leads 33 are cut off.
The lead portion 33 protruding from 8 is shaped into a desired shape, for example, a J-shape.

A wiring 42 is printed on the mounting substrate 41 shown in FIG. 14 in advance, and the wiring 42 is aligned so that a part of the wiring 42 is in contact with the bump electrode 28 of the semiconductor chip C. Next, the chip C and the mounting board 41 are bonded by heating and reflowing the bump electrodes 28. The wiring 42 is, for example, a Cu wiring, and a solder resist 43 is formed around the wiring 42.

In the above-described case, the bump electrode is formed on the uppermost layer wiring M3. However, the rearrangement wiring 22 is formed on the surface (pad portion P) of the uppermost layer wiring M3. A bump electrode may be formed on 22.

For example, as shown in FIG. 15, a redistribution wiring 22 made of a Cu (copper) film is formed on the passivation film PV1 including the surface (pad portion P) of the uppermost wiring M3 by, for example, a plating method. Is patterned so as to extend from above the pad portion P to above the inside of the chip area CA. On the rearrangement wiring 22 and the passivation film PV,
Passivation film PV made of photosensitive polyimide film etc.
2, and a contact hole (opening) C5 is formed on the rearrangement wiring 22. This contact hole C5
A part of the surface of the rearrangement wiring 22 (the pad 2
6) is exposed.

Next, a base metal layer 27 made of Au (gold) or the like is formed on the pad portion 26, and Sn (tin) and Pb
A solder paste made of an alloy of (lead) is formed by screen printing, and then heat-treated to form a bump electrode 28.
To form In this way, the pad portion P is
By drawing out to the inside of the chip area CA, a large formation area of the bump electrodes 28 and a space between the bump electrodes can be secured, and short circuit can be prevented.

In the present embodiment, the alignment mark is formed by a metal film such as a polycrystalline silicon film or an aluminum film, but may be formed by an insulating film such as a silicon oxide film. Further, the mark shape may be not only a convex shape but also a concave shape. Further, an alignment mark may be formed below the alignment mark M9, or three or more layers of wiring may be formed.

In this embodiment, the MISFETs Qn and Qp are formed as semiconductor elements. However, the present invention is not limited to these MISFETs, and various semiconductor elements can be formed.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

[0054]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

In the chip area, a first pattern is formed at an outer peripheral portion of the chip area, a second pattern is formed inside the first pattern formation position, and then the first and second patterns are formed. Since the resist film to which the pattern on the photomask was transferred was formed by aligning the first pattern with the mark on the photomask on the upper second film, and the second film was patterned. There is no need to form the first pattern serving as an alignment mark in the scribe area, and a large chip area can be secured. Further, the number of semiconductor chips obtained from one wafer can be increased. Further, the product yield can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor wafer on which a semiconductor integrated circuit device according to an embodiment of the present invention is formed.

FIG. 2 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 4 is a plan view of a main part of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 11 is a plan view for explaining effects of the embodiment of the present invention.

FIG. 12 is a cross-sectional view for explaining effects of the embodiment of the present invention.

FIG. 13 is a fragmentary cross-sectional view of the substrate, illustrating the method for mounting the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the substrate, illustrating the method of mounting the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 element isolation 3 p-type well 4 n-type well 7 silicon oxide film 8 gate oxide film 9 gate electrode 10 silicon nitride film 11 n ^- type semiconductor region 12 p ^- type semiconductor region 13 sidewall spacer 14 n ⁺ type semiconductor Region 15 p ⁺ type semiconductor region 22 Relocation wiring 26 Pad portion 27 Base metal layer 28 Bump electrode 30 Lead frame 32 Tab portion 33 Lead portion 37 Conductive wire 38 Sealing resin 41 Mounting substrate 42 Wiring 43 Solder resist C Semiconductor chip C1 To C5 contact hole CA chip area GA outer peripheral area of chip area M alignment mark M1 first layer wiring M2 second layer wiring M3 third layer wiring (top layer wiring) M9 alignment mark MM1 alignment mark MM2 alignment mark P pad part P1 P3 Grayed PV passivation film PV1 passivation film PV2 passivation film Qn n-channel type MISFET Qp p-channel type MISFET R photoresist film SA scribe region TH1~TH3 interlayer insulating film W semiconductor wafer

Claims (5)

[Claims] (A) A semiconductor wafer having a plurality of chip regions divided in a substantially sectional shape by a scribe region is provided on a semiconductor wafer.
A step of forming a first film; and (b) a step of patterning the first film, wherein a first pattern is formed in an outer peripheral portion of the chip region in the chip region, (C) forming a second film above the first and second patterns; and (d) forming a second film above the first and second patterns. Forming a resist film on which a pattern on the photomask has been transferred by aligning the first pattern and a mark on the photomask on the film; and (e) forming the resist film using the resist film as a mask. Patterning a second film. 2. A method for manufacturing a semiconductor integrated circuit device, comprising: 2. The method for manufacturing a semiconductor integrated circuit device further comprises: (f) forming a wiring extending above an outer peripheral portion of the chip region, wherein the wiring is located on an outer peripheral portion of the chip region in the wiring. 2. The method according to claim 1, further comprising the step of exposing a surface of the portion. 3. A first pattern comprising a first film formed on an individualized semiconductor substrate and formed on an outer peripheral portion of the semiconductor substrate, and b. Located inside from the formation position,
And (c) the first pattern is a pattern for alignment of an exposure apparatus. 4. A semiconductor integrated circuit device having a pattern for aligning an exposure device on a singulated semiconductor substrate and on an outer peripheral portion of the semiconductor substrate. 5. A pattern for aligning an exposure apparatus, which is a part of a surface of a wiring on an uppermost layer among a plurality of wirings formed on a semiconductor chip and below a pad part serving as an external lead-out part. A semiconductor integrated circuit device characterized by the above-mentioned.