JP2002300141A - Device and method for controlling data capturing timing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically set timing to capture serial data from a terminal in a tracking way. SOLUTION: A multiphase clock generating section 3 generates a polyphase clock from a fast clock faster than a data rate of the terminal and synchronously with a network or the terminal. The data from the terminal are divided into a plurality of data depending on the timing of the multiphase clock, which a 1st data storage section 4 stores. A detection section 5 compares the stored data that are adjacent to each other and detects a change point of the data depending on the difference. A capture control section 6 selects proper data corresponding to the detected data change point and writes and stores the selected data to a 2nd data storage section 7 in a timing when there is no data change point of the multiphase clock corresponding to the selected data. A read control section 8 reads the data stored in the 2nd data storage section 7 according to a clock period synchronously with the network or the terminal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a terminal interface provided between a network to which a communication device is connected and a terminal device, and performs data communication between the communication device and the terminal device via the network. The present invention relates to a data fetch timing control device and method for controlling the timing of fetching data from a terminal device when performing the method.

[0002]

2. Description of the Related Art For example, when data communication is performed between a communication device and a terminal device via a public network or the like, a serial interface on the terminal side of the communication device transmits a transmission timing signal dependently synchronized with the network side to the communication device. To the terminal device. Then, the terminal device transmits data in synchronization with the transmission timing signal from the communication device, and the communication device determines the data at a timing less affected by the change point. In this case, under the condition that the transmission delay between the communication device and the terminal device is large with respect to the cycle of the transmission timing, the timing at which the communication device determines data from the terminal device cannot be uniquely determined.

Therefore, conventionally, the timing for determining data by calculating the transmission delay time from the internal delay between the communication device and the terminal device and the distance that the signal reciprocates in the cable between the communication device and the terminal-side interface has been designed. Was. Further, assuming that the internal delay of the terminal device and the delay due to the cable are larger than a design value, the terminal device has a function of reversing the timing of determining data, and the timing is reversed by operating a switch. At the actual installation location, the operator manually set the communication without any abnormality at either timing.

[0004]

However, in the above-mentioned conventional method, the data fetch timing is fixedly set. Therefore, when the data fetch timing is changed, the data fetch timing must be reset every time. There was a problem. In addition, if temperature fluctuation, jitter, wander, etc. occur after setting the data fetch timing, the data fetch timing may deviate from an appropriate timing due to the influence thereof. Then, when the set timing is shifted from the appropriate timing and comes to the data change point, data cannot be correctly taken in, so that there is a problem that a code error occurs.

Therefore, the present invention has been made in view of the above-mentioned problems, and the timing of fetching serial data from a terminal device is not a manual / fixed setting but an automatic timing.
It is an object of the present invention to provide a data capture timing control device and method that can be set to follow.

[0006]

According to one aspect of the present invention, there is provided a serial interface provided between a network to which a communication device is connected and a terminal device, the serial interface being provided via the network. When performing data communication between the communication device and the terminal device, in the data capture timing control device 1 for controlling the timing of capturing data from the terminal device, a clock synchronized with a network side or a terminal side is used. A multi-phase clock generating unit 3 for generating a multi-phase clock having the same phase as the data rate of the terminal device and shifted in phase from a clock faster than the data speed of the terminal device and synchronized with the network side; A first data holding unit for holding data from the terminal device by the multi-phase clock generated by the generating unit; and a data holding unit for holding data stored in the first data holding unit. A data change point detected by the detection unit 5 from among the data held in the first data holding unit, and a detection unit 5 that compares data adjacent to each other to detect a data change point. A capture control section for selecting and controlling capture by a clock synchronized with the network side or the terminal side; and a second data holding section for sequentially storing the data captured under the control of the capture control section. It is characterized by.

According to a second aspect of the present invention, in the data acquisition timing control device of the first aspect, the acquisition control section 6 determines that the number of detected change points of the data change point corresponding to the current data selection position exceeds a set value. In some cases, data corresponding to the data change point is selected, and the selected data is fetched and controlled by a clock synchronized with the network side or the terminal side without changing the data selection position.

According to a third aspect of the present invention, in the data acquisition timing control device of the first aspect, the acquisition control unit 6 is configured so that the number of detected change points of the data change point corresponding to the current data selection position does not exceed the set value. When the number of detected change points of the data change point exceeds a set value at a position beyond the center line of one cycle of a clock synchronized with the network side or the terminal side, the network side or the network side so that wander is absorbed. The number of bits for writing data to the second data holding unit 7 is controlled during a clock cycle synchronized with the terminal.

According to a fourth aspect of the present invention, when data communication is performed between the communication device and the terminal device via a network to which the communication device is connected, the timing for taking in data from the terminal device is controlled. A multiphase clock including a clock synchronized with the network side or the terminal side is generated from a clock synchronized with the network side at a speed higher than the data rate of the terminal device, and the generated multiphase clock is generated. Holding the data from the terminal device, and comparing adjacent data of the held data to detect a data change point, and among the held data, data corresponding to the detected data change point. Is selected and captured by a clock synchronized with the network side or the terminal side, and the captured data is sequentially held.

According to a fifth aspect of the present invention, in the data fetch timing control method of the fourth aspect, when the number of detected change points of the data change point corresponding to the current data selection position exceeds a set value, the data change point is controlled. Is selected, and the selected data is fetched and controlled by a clock synchronized with the network side or the terminal side without changing the data selection position.

According to a sixth aspect of the present invention, in the data fetch timing control method of the fourth aspect, the number of detected change points of the data change point corresponding to the current data selection position does not exceed the set value, and the clock of the network side becomes one. When the number of detected data change points exceeds the set value at a position beyond the center line of the cycle, the number of data write bits is controlled during the clock cycle on the network side so that wander is absorbed. It is characterized by doing.

In the present invention, for example, when the data rate of a terminal device is 6 MHz, a clock (multiple clocks) divided into six by combining the rise and fall of an 18 MHz fast clock (reference clock) faster than 6 MHz and synchronized with the network side. Hold_clk, m1ck to m5ck. Then, a clock hol having the same phase as the reference clock
d_clk is fixed to the latch or read timing, and the change point determination is performed using the remaining polyphase clocks of m1ck to m5ck. The data obtained by the polyphase clock is h
Since it is at least 1/6 phase shifted from old_clk, latching and reading can be performed. Also, hold_cl
Since k is synchronized with the network side (or the terminal side) and has the same phase, no error occurs.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The data acquisition timing control device of the present invention described below is a terminal-side serial interface provided between a network to which a communication device is connected and a terminal device. In this control device, when data communication is performed between the communication device and the terminal device via a network, the communication device controls the timing of receiving data from the terminal device when receiving data from the terminal device. I have.

FIG. 1 is a block diagram showing a schematic configuration of a data fetch timing control device according to the present invention.

As shown in FIG. 1, a data fetch timing control device (hereinafter abbreviated as a control device) 1 includes a setting unit 2, a multi-phase clock generation unit 3, a first data holding unit 4,
A detection unit 5, a capture control unit 6, a second data holding unit 7,
It is schematically configured with a read control unit 8.

The setting unit 2 sets the data rate (for example, 64 kHz to 6 M) of the terminal device input to the multi-phase clock generation unit 3.
Hz) and a fast clock synchronized with the network side or terminal side (a reference clock inside the device: for example, 12 MHz, 13
MHz, 15 MHz, and 18 MHz), the frequency dividing ratio of the high-speed clock when generating a plurality of multiphase clocks is set.

The multi-phase clock generation unit 3 divides a high-speed clock higher than the data speed of the terminal device synchronized with the network side or the terminal side according to the frequency division ratio set by the setting unit 2, and A plurality of multiphase clocks having the same speed but shifted in phase are generated. That is, the multi-phase clock generator 3
Is changed in accordance with the setting of the data rate of the terminal device.

The first data holding unit 4 divides serial data input from the terminal device in units of bits at a timing of each multi-phase clock by the plurality of multi-phase clocks generated by the multi-phase clock generation unit 3. Holding. Also,
The first data holding unit 4 latches the held data with a multi-phase clock generated by the multi-phase clock generation unit 3.

The detecting unit 5 compares bits of adjacent data in the data held and latched in the first data holding unit 4, and detects a data change point of data from the terminal device based on the difference. , And outputs the detection result to the control unit 6.

The fetch control unit 6 controls the fetch timing of the data held and latched in the first data holding unit 4 from the data change point detected by the detection unit 5.

The second data holding unit 7 temporarily holds the data taken in by the taking control unit 6 at the taking timing.

The read control unit 8 controls the reading of the data held in the second data holding unit 7 by a clock on the network side. Note that the reading control unit 8
In some cases, the reading of data held in the data holding unit 7 is controlled by a terminal clock.

In the control device 1 configured as described above,
When serial data is input from the terminal device, the data is divided for each multi-phase clock generated by the multi-phase clock generation unit 3 and held by the first data holding unit 4 and latched.

The detecting unit 5 compares the bits of adjacent data of the data latched in the first data holding unit 4, detects a data change point based on the difference, and fetches the detection result. Output to the control unit 6. The capture control unit 6 selects data considered to be optimal from the data held in the first data holding unit 4 according to the timing of the data change point detected by the detection unit 5, and transfers the selected data to the second data. The data is stored in the data storage unit 7. Then, the detection of the data change point and the selection of the optimum data automatically follow the temporal change of the data change point with the passage of time.

Thus, the data is fetched from the first data holding unit 4 and held in the second data holding unit 7 in a state where the temporal change in the fetch timing is absorbed.
Then, the data held in the second data holding unit 7 is
Under the control of the read control unit 8, the data is read at the timing of the clock on the network side (or the terminal side). At this time, the time series of the data is correctly output with respect to the read timing from the read control unit 8.

Next, FIG. 2 shows an example of a specific configuration of the control device 1. 3 and 4 are diagrams showing terms and signal names defined for explaining the operation of the control device 1. FIG.

In FIGS. 3 and 4, the phase relationship between the data from the terminal device and each of the multi-phase clocks is assumed, and it is not known what the actual phase relationship will be.
3 and 4, the data rate of the terminal device is set to 6 MHz and the speed clock synchronized with the network side is set to 18 MHz in order to make the description easy to understand, but the relationship is different at other speeds.

Hereinafter, a specific configuration of the control device 1 will be described with reference to FIG. In FIG. 2, components corresponding to those in FIG. 1 will be described with the same reference numerals.

The setting unit 2 in FIG. 2 generates a multi-phase clock at the same time as the data rate of the terminal device and generates and outputs from the multi-phase clock generation unit 3 six polyphase clocks. The division ratio is set.

The multi-phase clock generator 3 in FIG. 2 is a high-speed clock (eg, 12 MHz, 13 MHz, 15 MHz, 18 MHz) synchronized with the network side or the terminal side, which is faster than the data rate (eg, 64 kHz to 6 MHz) of the terminal device.
Is divided by the frequency division ratio set by the setting unit 2, and the six types of multiphase clocks m1ck, m2ck, m3ck, m4ck, and m5c which are the same as the data speed of the terminal device and are shifted in phase.
k, hold_clk are generated. Thereby, the circuit configuration other than the multi-phase clock generation unit 3 can be shared regardless of the speed.

In the example of FIG. 3, the hold clock h having the same cycle (6 MHz) as the clock cycle on the network side (or terminal side) is used.
old_clk is generated. Further, multi-phase clocks m1ck to m5ck whose phases are shifted by 1/6 cycle from the hold clock hold_clk are generated.

The first data holding unit 4 in FIG. 2 is a multi-phase clock generation unit 3 which outputs multi-phase clocks m1ck and m2c.
It is configured to include five flip-flop circuits (FFs) 4a to 4e to which k, m3ck, m4ck, and m5ck are input, and a latch unit 4f to which a hold clock hold_clk is input from the multi-phase clock generation unit 3.

In FIG. 2, a flip-flop circuit 4a
Receives the multiphase clock m1ck, the flip-flop circuit 4b receives the multiphase clock m2ck, the flip-flop circuit 4c receives the multiphase clock m3ck,
The multi-phase clock m4ck is input to the flip-flop circuit 4d, and the multi-phase clock m4ck is input to the flip-flop circuit 4e.
5ck is input.

Each of the flip-flop circuits 4a to 4e is supplied with the timing of a corresponding multi-phase clock.
The serial data input from the terminal device is held in bit units.

The latch section 4f has a multi-phase clock m1ck-
When data is held in each of the flip-flop circuits 4a to 4e by m5ck, the held data is transferred to a hold clock hold_cl having the same cycle as the network clock cycle.
latched at k.

The change point detecting section 5 in FIG. 2 corresponds to the detecting section in FIG. 1, and detects a data change point from the output of the latch section 4f. Specifically, the change point detection unit 5
In the example, the data (hold_
bit) and bit 2 and bit 2 and bit 3 of data)
As described above, adjacent data bits are compared, and a difference is detected as a data change point.

In FIG. 2, the capture control section 6 includes a counter section 6a, a capture position determination / control section 6b, a multiplexer section 6c, and a bit buffer write control section 6d.

The counter section 6a counts data change points detected by the change point detection section 5 for each change point detection window (predetermined section: windows 1 to 5). The counter 6a assumes that a valid data change point is detected when the count value of the data change point exceeds a preset value.

The counter section 6a can prevent erroneous detection of a change point due to noise or the like by increasing a preset value. On the other hand, if the set value is reduced, it is possible to follow a fast change of the change point.

The fetch position determination / control section 6b determines the data fetch position based on the information of the valid data change point from the counter section 6a, and based on the determined data fetch position, the multiplexer section 6c and the bit buffer write control. It controls the unit 6d.

The multiplexer section 6c, based on the control signal from the fetch position determining / control section 6b, converts the data determined to be optimum from the five data (hold_data) latched by the latch section 4f into the bit buffer section 7 (FIG. 1).
(Corresponding to a second data holding unit).

The bit buffer write control section 6d receives the control signal from the fetch position determination / control section 6b and sets the number of bits (0, 1, 2) to be written in the slot (network side cycle).
Is output to the bit buffer 7.

The bit buffer section 7 temporarily holds data from the multiplexer section 6c according to a control signal from the bit buffer write control section 6d.

In this example, when the data change point is the window 1, the data (hold) held in the flip-flop circuit 4c is held.
_Data [3]) is written and held in the bit buffer unit 7 as optimal data.

When the data change point is the window 2, the data (hold_da) held in the flip-flop circuit 4d
ta [4]) as the optimal data
Is written and held.

When the data change point is the window 3, the data (hold_da) held in the flip-flop circuit 4e
ta [5]) is determined as the optimum data by the bit buffer unit 7
Is written and held.

When the data change point is the window 4, the data (hold_da) held in the flip-flop circuit 4a is held.
ta [1]) is determined as the optimal data by the bit buffer unit 7.
Is written and held.

When the data change point is the window 5, the data (hold_da) held in the flip-flop circuit 4b is held.
ta [2]) is determined as the optimal data by the bit buffer unit 7
Is written and held.

When the data change point changes in a direction in which the data cycle becomes shorter than the center line, that is, when the data change point changes from the window 4 to the window 3, the data is held in the flip-flop circuits 4a and 4e. 2-bit data (hold_data [1], hold_data
a [5]) is written and held in the bit buffer unit 7.

On the other hand, when the data change point changes in the direction in which the data cycle becomes longer beyond the center line, that is, when the data change point changes from the window 3 to the window 4, the bit buffer 7 No data is written to.

The read control unit 8 shown in FIG. 2 outputs a control signal for reading out the data stored in the bit buffer unit 7 with the network clock to the bit buffer unit 7 and outputs the data stored in the bit buffer unit 7 to the network side. Output control.

Here, windows 1 to 5 shown in FIG. 2 to FIG.
This is a fixed break for detecting where the data change point (data change phase) is. For example, as shown in FIG. 3, when data is input from the terminal device, the data change point (data change phase) becomes window 1.

The windows 1 to 5 correspond to the multiphase clocks m1ck to
This corresponds to a section from the rise of the adjacent multiphase clock of m5ck to the rise. In the example of FIG.
Corresponds to a section from the rise of the multiphase clock m5ck to the rise of the multiphase clock m1ck. Window 2 corresponds to a section from the rise of clock m1ck to the rise of clock m2ck. Window 3 is clock m2c
This corresponds to a section from the rise of k to the rise of clock m3ck. The window 4 corresponds to a section from the rise of the clock m3ck to the rise of the clock m4ck. The window 5 corresponds to a section from the rise of the clock m4ck to the rise of the clock m5ck.

The multi-phase clocks m1ck to m5ck are:
This is a clock generated by the multi-phase clock generation unit 3 by using the rising and falling edges of a fast clock that is faster than the data rate of the terminal device and synchronized with the network or the terminal.

Data 1m to d in FIGS. 3 and 4
data5m is the corresponding multiphase clock m1ck to m5c
This is a signal obtained by taking in data from the terminal device at the timing of the rise of k. Also, hold_data [1] to hold_data [5] in FIG. 3 and FIG.
Holds data1m to data5m as the hold clock h
The data is held and aligned in old_clk.

The slot in FIG. 3 indicates a section from the rise of the signal of the hold clock hold_clk to the next rise. Therefore, when the clocks on the terminal device side and the network side are synchronized, it is considered that there is one data change point in one slot. The center line in FIG. 3 indicates the center of the slot (between the windows 3 and 4).

In this example, as shown in FIG. 4, when the change point window determined to have a data change phase is window 1, the corresponding data selection position is 3, the corresponding data is data3m, and the corresponding data is data3m. hold_data is ho
ld_data [3], corresponding polyphase clock is m3c
k.

If the change point window determined to have a data change phase is window 2, the corresponding data selection position is 4, the corresponding data is data 4m, and the corresponding hold
_Data is hold_data [4], and the corresponding multiphase clock is m4ck.

If the change point window determined to have a data change phase is window 3, the corresponding data selection position is 5, the corresponding data is data 5m, and the corresponding hold
_Data is hold_data [5], and the corresponding multiphase clock is m5ck.

If the change point window determined to have a data change phase is window 4, the corresponding data selection position is 1, the corresponding data is data1m, and the corresponding hold
_Data is hold_data [1], and the corresponding multiphase clock is m1ck.

If the change point window determined to have a data change phase is window 5, the corresponding data selection position is 2, the corresponding data is data2m, and the corresponding hold
_Data is hold_data [2], and the corresponding multiphase clock is m2ck.

If the valid data change point is, for example, window 1, the rising edge of the multiphase clock m3ck is determined as the data fetch position. That is, the rising timing of the multi-phase clock corresponding to the window of the effective data change point is determined as the data capturing position.

In the control device configured as described above, the serial data input from the terminal device is fetched by a multi-phase clock (m1ck to mc5ck), and the fetched data (data1m to data5m) is latched by the hold clock hold_clk ( hold_data
[1] to hold_data [5]).

Next, the latched data (hold_d
data), a data change point is detected, a bit considered to be optimal in hold_data is selected based on statistical information using a counter, and the data is written to the bit buffer unit 7. Then, the data written in the bit buffer unit 7 is read by the network clock.

Here, the jitter of the clocks on the network side and the terminal device side is absorbed by selecting bits when writing hold_data in the bit buffer unit 7. Also,
With respect to wander, writing of data to the bit buffer unit 7 during the period of the network clock is absorbed by processing of writing or not writing 2 bits instead of 1 bit.

FIG. 5 shows a processing operation of changing the data fetch position and the number of write bits by the controller 1.
This will be described in detail with reference to the flowchart of FIG.

First, after resetting the device, an initial (default) data selection position is determined (ST1). For example, it is assumed that the detection window 1 is a data selection 3 (data 3m).

Next, the number of detected changes in the windows 1 to 5 is set to a set value (for example, the count set value of the counter 6a is set to 1).
Is determined (ST2).

If it is determined that the number of detected changes in windows 1 to 5 does not exceed the set value, one bit of data is fetched in the slot (ST3) and the data selection position is not changed (ST4). , ST2.

When it is determined that the number of detected changes in the windows 1 to 5 exceeds the set value, it is determined whether the detected number of changes exceeds the set value in the window corresponding to the current data selection position ( ST5).

If it is determined that the number of detected changes does not exceed the set value in the window corresponding to the current data selection position, the operation shifts to ST3.

On the other hand, if it is determined that the change detection number exceeds the set value in the window corresponding to the current data selection position, the change detection number exceeds the set value in the window beyond the center line. It is determined whether or not (ST6).

If it is determined that the number of detected changes does not exceed the set value in the window beyond the center line, one bit of data is fetched in the slot (ST).
7) Change the data selection position (ST8), and return to the operation of ST2.

If it is determined that the number of detected changes has exceeded the set value in the window beyond the center line, and if the number of detected changes in the windows 2 and 3 has exceeded the set value (ST9), the window before the center line is set. It is determined that the change point has moved to (2), two bits of data are fetched in the slot (ST10), the data selection position is changed (ST8), and the operation returns to ST2.

It is determined that the number of detected changes exceeds the set value in the window beyond the center line, and
If the number of changes detected exceeds the set value (ST1
1) It is determined that the change point has moved after the center line, and no data is taken in the slot (ST1).
2) Change the data selection position (ST8) and return to the operation of ST2.

That is, in the above operation, after the reset (ST1) is released, the processing of ST2 → ST3 → ST4 is repeated until the number of detected data change points exceeds the set value.
When the data change point is fixed at a certain phase, S
Processing of T2 → ST3 → ST4 and ST2 → ST5 → ST
The process of 3 → ST4 is repeated. If the data change point moves within a range not exceeding the center line, ST
The processing of 2 → ST5 → ST6 → ST7 → ST8 → ST2 is repeated. Further, when the data change point moves in the direction of shortening the data cycle beyond the center line, ST2 → ST5 → ST6 → ST9 → ST10 → ST
8 → The process of ST2 is repeated. On the other hand, when the data change point moves in the direction of extending the data cycle beyond the center line, ST2 → ST5 → ST6 →
The processing of ST11 → ST12 → ST8 → ST2 is repeated.

Here, as an example of the above operation, FIG. 6 shows a timing chart in the case where the period of the data rate from the terminal device becomes shorter than the clock synchronized with the network side or the terminal side. In the example of FIG. 6, the data rate from the terminal device and the clock synchronized with the network side or the terminal side are 6 MHz,
The speed clock is set to 18 MHz, and the set value of the counter unit for counting the change point is set to 1 for easy understanding of the operation. Further, the initial settings are the detection window 1 and the data acquisition selection 3 (data 3m).

In the example shown in FIG. 6, first, the change point detection window, which is the first data change point, is window 1. Therefore, data d0 of hold_data [3] corresponding to this window 1 is at the rising edge of the multiphase clock m3ck. The data is written to the bit buffer unit 7.

Since the subsequent change point detection window remains the window 1, similarly, data d1 of hold_data [3] corresponding to the window 1 is written into the bit buffer unit 7 at the rising timing of the multiphase clock m3ck.

Subsequently, since the change point detection window changes from the window 1 to the window 5, hold_data corresponding to the window 5 is displayed.
The data d2 of [2] is written to the bit buffer unit 7 at the rising timing of the multiphase clock m2ck.

Since the subsequent change point detection window remains the window 5, the data d3 of hold_data [2] corresponding to the window 5 is similarly written into the bit buffer unit 7 at the rising timing of the multiphase clock m2ck.

Since the subsequent change point detection window remains the window 5, the data d4 of hold_data [2] corresponding to the window 5 is written to the bit buffer section 7 at the rising timing of the multiphase clock m2ck.

Subsequently, since the change point detection window changes from the window 5 to the window 4, hold_data corresponding to the window 4 is displayed.
The data d5 of [1] is written to the bit buffer unit 7 at the rising timing of the multiphase clock m1ck.

Since the subsequent change point detection window remains the window 4, similarly, the data d6 of hold_data [1] corresponding to the window 4 is written into the bit buffer unit 7 at the rising timing of the multiphase clock m1ck.

Since the succeeding change point detection window remains the window 4, the data d7 of hold_data [1] corresponding to the window 4 is written to the bit buffer unit 7 at the rising timing of the multiphase clock m1ck.

Subsequently, the change point detection window changes from window 4 to window 3. In this case, since the transition point moves in a direction in which the data period becomes shorter than the center line, the data d8 of hold_data [1] corresponding to the window 4 is stored in the bit buffer unit 7 at the rising timing of the multiphase clock m1ck. And corresponding to the window 3
The data d9 of old_data [5] is a multi-phase clock m
Bit buffer unit 7 at the rising timing of 5ck
Is written to.

Subsequently, since the change point detection window is the window 3, the data d1 of hold_data [5] corresponding to the window 3
0 is written to the bit buffer unit 7 at the timing of the rise of the multiphase clock m5ck.

Since the subsequent change point detection window remains the window 3, the data d11 of hold_data [5] corresponding to the window 3
Is written to the bit buffer unit 7 at the timing of the rise of the multiphase clock m5ck.

Hereinafter, as described above, the data corresponding to the change point detection window is selected, the number of data write bits to the bit buffer unit 7 is controlled, and the data write to the bit buffer unit 7 is performed sequentially. .

Next, FIG. 7 shows a timing chart when the cycle of the data rate from the terminal device becomes longer than the clock synchronized with the network side or the terminal side. In the example of FIG. 7, the data rate from the terminal device and the clock synchronized with the network side or the terminal side are 6 MHz, and the speed clock is 18 MHz.
In order to make the explanation of the operation easy to understand, the set value of the counter for counting the change points is set to 1. Further, the initial settings are the detection window 1 and the data acquisition selection 3 (data 3m).

In the example shown in FIG. 7, first, the change point detection window, which is the first data change point, is window 1. Therefore, data d0 of hold_data [3] corresponding to this window 1 is at the rising timing of the multiphase clock m3ck. The data is written to the bit buffer unit 7.

Since the subsequent change point detection window remains the window 1, similarly, data d1 of hold_data [3] corresponding to the window 1 is written to the bit buffer unit 7 at the rising timing of the multiphase clock m3ck.

Subsequently, since the change point detection window changes from window 1 to window 2, hold_data corresponding to window 2
The data d2 of [4] is written into the bit buffer unit 7 at the rising timing of the multiphase clock m4ck.

Since the subsequent change point detection window remains the window 2, similarly, the data d3 of hold_data [4] corresponding to the window 2 is written to the bit buffer unit 7 at the rising timing of the multiphase clock m4ck.

Subsequently, since the change point detection window changes from the window 2 to the window 3, hold_data corresponding to the window 3 is displayed.
The data d4 of [5] is written to the bit buffer unit 7 at the rising timing of the multiphase clock m5ck.

Since the subsequent change point detection window remains the window 3, similarly, data d5 of hold_data [5] corresponding to the window 3 is written to the bit buffer unit 7 at the rising timing of the multiphase clock m5ck.

Since the subsequent change point detection window remains the window 3, the data d6 of hold_data [5] corresponding to the window 3 is written into the bit buffer unit 7 at the rising timing of the multiphase clock m5ck.

Subsequently, the change point detection window changes from window 3 to window 4. In this case, since the transition point moves in a direction in which the data cycle becomes longer than the center line, data is not written in the bit buffer unit 7.

Subsequently, since the change point detection window is the window 4, the data d7 of hold_data [1] corresponding to the window 4
Is written to the bit buffer unit 7 at the timing of the rise of the multiphase clock m1ck.

Since the subsequent change point detection window remains the window 4, similarly, the data d8 of hold_data [1] corresponding to the window 4 is written into the bit buffer unit 7 at the rising timing of the multiphase clock m1ck.

Since the succeeding change point detection window remains the window 4, the data d9 of hold_data [1] corresponding to the window 4 is written into the bit buffer unit 7 at the rising timing of the multiphase clock m1ck.

Thereafter, as described above, the data corresponding to the change point detection window is selected, the number of data write bits to the bit buffer unit 7 is controlled, and the data write to the bit buffer unit 7 is performed sequentially. .

Next, FIG. 8 shows a timing chart when the changing point is fixed at a certain phase. In the example of FIG. 8, the data rate from the terminal device and the clock synchronized with the network side or the terminal side are set to 6 MHz, and the speed clock is set to 18 MHz. It is set to 4. Further, the initial settings are the detection window 1 and the data acquisition selection 3 (data 3m).

In the example of FIG. 8, the change point detection window as the data change point continues as the window 4, but until the number of change detections exceeds the set value 4, hold_d corresponding to the initially set window 1
The data of data [3] is written to the bit buffer unit 7 at the rising timing of the multi-phase clock m3ck. In the example of FIG. 8, hold_data corresponding to window 1
The data d0 to d3 of [3] are sequentially written in the bit buffer unit 7 at the rising timing of the multiphase clock m3ck.

When the number of detected changes in the change point detection window 4 exceeds the set value 4, hold_data corresponding to the window 4
The data d4 of [1] is written to the bit buffer unit 7 at the rising timing of the multiphase clock m1ck.
Thereafter, since the change detection window remains the window 4, the data d5 to d10 of hold_data [1] corresponding to the window 4 are sequentially written to the bit buffer unit 7 at the rising timing of the multiphase clock m3ck.

As described above, in the control device and the control method according to the present embodiment, the multi-phase clock generation unit 3 uses a speed clock that is faster than the data speed of the terminal device and is synchronized with the network (or the terminal side).
The data from the terminal device is divided into a plurality of data by the timing of the multi-phase clock generated by the first data holding unit 4.
Holding. Then, the adjacent data of the held data are compared by a detection unit (change point detection unit) 5 to detect a data change point. Thereafter, the capture control unit 6 selects appropriate data corresponding to the detected data change point, and writes and holds the selected data in the second data holding unit (bit buffer unit) 7. This makes it possible to automatically and follow-up fetch data from the terminal device at an appropriate timing and hold the data.

The detecting section (change point detecting section) 5 determines whether or not the number of detected changes in the windows 1 to 5 exceeds a set value, and determines the data change point in the window corresponding to the current data selection position. Selection of appropriate data and second data based on the determination as to whether or not the number of detected changes has exceeded the set value, and whether or not the number of detected changes has exceeded the set value in the window beyond the center line. The number of bits for writing data to the holding unit (bit buffer unit) 7 (the number of times of writing) is controlled. Thereby, the second data holding unit (bit buffer unit) 7 includes:
The data is held in a state where the temporal change of the change timing of the input data from the terminal device is absorbed. as a result,
Even when reading is performed at a fixed timing (a clock cycle synchronized with the network side or the terminal side) of the reading control unit 8, data can be correctly output in time series.

Therefore, according to the control device and the control method of the present embodiment, the timing of fetching data from the terminal device is controlled automatically and followingly without requiring the actual measurement and manual setting as in the related art. be able to. Moreover,
Even if the data capture timing is shifted due to the effects of temperature fluctuation, jitter, wander, etc., the data from the terminal device is not affected by the data change point due to these, nor does a code error occur as in the past. Can be captured accurately.

[0109]

As is apparent from the above description, according to the present invention, it is possible to control the data fetch timing automatically and followingly without the need for actual measurement and manual setting. Moreover, even if the data capture timing is deviated due to the effects of temperature fluctuation, jitter, wander, etc., the data from the terminal device is not affected by the data change point due to these and the code error does not occur. Can be captured accurately.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a control device according to the present invention.

FIG. 2 is a diagram showing a specific configuration example of the control device of FIG. 1;

FIG. 3 is a diagram showing terms and signal names defined for explaining the operation of the control device in FIG. 2;

FIG. 4 is a diagram showing terms and signal names defined for explaining the operation of the control device of FIG. 2;

5 is a flowchart showing a processing operation of the control device of FIG. 2 for changing a data fetch position and a write bit number.

FIG. 6 is a timing chart in the case where the period of the data rate from the terminal device becomes shorter than the clock synchronized with the network side or the terminal side in the control device of the present invention.

FIG. 7 is a timing chart in the case where the period of the data rate from the terminal device becomes longer than the clock synchronized with the network side or the terminal side in the control device of the present invention.

FIG. 8 is a timing chart in a case where a change point is fixed at a certain phase in the control device of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Control device, 2 ... Setting part, 3 ... Polyphase clock generation part,
4 a first data storage unit, 5 a detection unit (change point detection unit), 6 a capture control unit, 7 a second data storage unit (bit buffer unit), 8 a read control unit.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hideaki Takahashi 5-1027 Minamiazabu, Minato-ku, Tokyo Anritsu Corporation F-term (reference) 5B077 GG01 GG14 MM02 NN02 5K047 AA05 AA06 GG02 GG09 GG11 GG24 GG29 MM24

Claims (6)

[Claims] 1. A serial interface provided between a network to which a communication device is connected and a terminal device, wherein data communication is performed between the communication device and the terminal device via the network. A data capture timing control device (1) for controlling the timing of capturing data from the terminal device, comprising: Phase clock,
A multi-phase clock generator (3) that generates a clock higher than the data rate of the terminal device and is synchronized with a network or a terminal; and a multi-phase clock generated by the multi-phase clock generator generates a signal from the terminal device. A first data holding unit (4) for holding data, a detecting unit (5) for comparing adjacent data of the data held in the first data holding unit to detect a data change point, The data corresponding to the data change point detected by the detection unit from the data held in the first data holding unit,
A capture control unit (6) for selecting and controlling capture by a clock synchronized with the network side or terminal side, and a second data storage unit (7) for sequentially storing the data captured under the control of the capture control unit. A data acquisition timing control device comprising: 2. The data capture control section (6) selects data corresponding to the data change point when the number of detected change points of the data change point corresponding to the current data selection position exceeds a set value. 2. The data fetch timing control device according to claim 1, wherein the fetch control of the selected data is performed by a clock synchronized with the network side or the terminal side without changing the data selection position. 3. The capture control unit (6), wherein the number of detected change points of a data change point corresponding to a current data selection position does not exceed a set value, and one cycle of a clock synchronized with a network side or a terminal side. When the number of detected change points of the data change point exceeds a set value at a position beyond the center line, the second data is generated during a clock cycle synchronized with the network side or terminal side so that wander is absorbed. 2. The data fetch timing control device according to claim 1, wherein the number of bits for writing data to the holding unit is controlled. 4. A data fetch timing control for controlling a timing of fetching data from the terminal device when data communication is performed between the communication device and the terminal device via a network to which the communication device is connected. A method, comprising: synchronizing a multi-phase clock having the same data rate as the terminal device, including a clock synchronized with a network side or a terminal side, with a phase shift.
Generated from a clock that is faster than the data rate of the terminal device and synchronized with the network side or the terminal side, retains data from the terminal device by the generated multi-phase clock, and adjacent data of the retained data The data corresponding to the detected data change point is selected from the held data by using a clock synchronized with the network side or the terminal side, and the captured data is detected. Data acquisition timing control method, wherein the data is sequentially stored. 5. When the number of detected change points of a data change point corresponding to a current data selection position exceeds a set value, data corresponding to the data change point is selected, and the data selection position is not changed. 5. The data capture timing control method according to claim 4, further comprising: controlling the capture of the selected data with a clock synchronized with the network side or the terminal side. 6. The data at a position where the number of detected change points of a data change point corresponding to a current data selection position does not exceed a set value and exceeds a center line of one cycle of a clock synchronized with a network side or a terminal side. When the number of detected change points of the change point exceeds a set value, the number of write bits of the data is controlled during a clock cycle synchronized with the network side or the terminal side so that wander is absorbed. 5. The method according to claim 4, wherein the data acquisition timing is controlled.