JP2002299610A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control a work function of a gate electrode without causing the deterioration in characteristics of a gate insulation film, in a damascene type MIS transistor. SOLUTION: Indium ions are implanted into a TiN film 10 which is the gate electrode on the condition that they do not reach the gate insulation film 9, to form an In ion implanted layer 12 in the TiN film 10. Then, the indium ions in the In ion implanted layer 12 are diffused to form an In deposition layer 13 near an interface between the TiN film 10 and the gate insulation film 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device characterized by an electrode such as a gate electrode and a method of forming the same, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Recently, a damascene gate MIS transistor has attracted attention as one of the transistors advantageous for miniaturization. The reason is that after annealing for activating impurities in the source / drain regions is completed, a gate insulating film and a gate electrode can be formed, and a high dielectric film having low heat resistance is used as the gate insulating film. Because you can. Another reason is that a gate electrode mainly composed of metal (metal gate electrode) can be easily formed by a damascene process.

An n-channel damascene gate MIS transistor (hereinafter abbreviated as nMIS) and a p-channel damascene gate MIS transistor (hereinafter abbreviated as nMIS) are formed on the same substrate.
When forming pMIS, it is necessary to adjust the work function of the gate and control the threshold voltage (V _th ).

Usually, a metal gate electrode of the same material is used for nMIS and pMIS. Therefore, the work function of the metal gate electrode is fixed as it is, and nMIS
And pMIS cannot be made separately.

Therefore, by selectively implanting nitrogen ions into the nMIS metal gate electrode and adjusting the work function of the nMIS metal gate electrode, nMIS and pMIS are adjusted.
A method for separately producing MIS has been proposed. This method will be described with reference to FIGS.

Step 0-1 (FIG. 23) First, using a well-known STI (Shallow Trench Isolation) technique, an element isolation region 81 is formed on the surface of a silicon substrate 80.
To form Next, as a dummy gate to be removed in the future,
For example, a laminated film composed of a silicon oxide film 82 of about 6 nm, a polysilicon film 83 of about 150 nm or about 200, and a first silicon nitride film 84 of about 50 nm or about 40 nm is formed by oxidation, CVD, lithography and RIE. It is formed using. Next, an extension region (also referred to as an LDD region) 85 is formed by using an ion implantation technique and an annealing technique, and then a second silicon nitride film 86 having a width of about 40 nm as a gate side wall is formed by using a CVD technique and an RIE technique. It is formed by a so-called sidewall leaving technique.

Step 0-2 (FIG. 24) Next, after forming the source / drain region 87 having a higher impurity concentration and a deeper junction depth than the extension region 85 by using ion implantation technology and annealing technology,
Using a salicide process technique and using a dummy gate as a mask, a metal silicide film 88 such as a cobalt silicide film or a titanium silicide film of about 40 nm is formed only on the source / drain regions 87.

Step 0-3 (FIG. 25) Next, for example, a silicon oxide film 89 is formed as an interlayer insulating film by CV.
After the entire surface is deposited by the method D, the surface of the first silicon nitride film 84 which is the uppermost layer of the dummy gate and the surface of the second silicon nitride film 86 which is the gate side wall are exposed by planarization by the CMP technique. . Silicon oxide film 8
The film thickness of No. 9 is, for example, 300 nm.

Step 0-4 (FIG. 26) Next, the first silicon nitride film 84 which is the uppermost layer of the dummy gate is selectively removed from the silicon oxide film 89 which is an interlayer insulating film by, for example, hot phosphoric acid treatment. I do. At this time, the second silicon nitride film 86 which is the gate side wall is also etched to the height of the polysilicon film 83 which is the center layer of the dummy gate. Next, for example, CDE (Chemical
Using a dry etching technique, the polysilicon film 83 as the center layer of the dummy gate is replaced with a silicon oxide film 89 as an interlayer insulating film, and a second silicon nitride film 86 as a gate sidewall.
To be selectively removed.

Step 0-5 (FIG. 27) Next, the silicon oxide film 82, which is the lowermost layer of the dummy gate, is removed by dilute hydrofluoric acid treatment, and an opening for forming a gate in the silicon oxide film 89, which is an interlayer insulating film. (Gate groove) is formed. Next, a high dielectric material T
A gate insulating film 90 made of iO ₂ is formed on the entire surface, and then a Ti as a first gate electrode is formed on the gate insulating film 90.
An N film 91 is deposited to a thickness of about 10 nm by a CVD method. Ti
The N film 91 also plays a role of a barrier metal. Steps 0-1 to 0-5 so far are the same for both nMIS and pMIS.

Step 0-6 (FIG. 28) FIG. 28 shows both nMIS and pMIS. The left side of each figure shows an nMIS formation region, and the right side shows a pMIS formation region. In this step, a resist 92 having an opening only on the nMIS formation region is formed by using a lithography technique.

Step 0-7 (FIG. 29) Next, nitrogen ions are implanted using the resist 92 as a mask, and TiN having a high nitrogen concentration is formed near the interface between the TiN film 91 and the gate insulating film 90 in the nMIS formation region. The layer 93 is selectively formed. The condition of the acceleration voltage is set to, for example, about 3 keV. Under this condition, the distance from the surface of the TiN film 91 is 1
The nitrogen concentration peaks at a depth of 0 nm. Thereby, the TiN layer 93 having a high nitrogen concentration can be formed near the interface.

Here, if the nitrogen ion implantation direction is perpendicular to the surface of the silicon substrate 80, the TiN film 91 is formed on the side surface of the gate groove, so that the TiN film 91 is formed. It is difficult to implant nitrogen ions into the bottom of the gate groove. That is, it is difficult to implant nitrogen ions into the entire bottom surface of the TiN film 91.

In order to implant nitrogen ions into the entire bottom surface of the TiN film 91, the direction of implanting nitrogen ions is preferably set at a direction inclined several degrees from a direction perpendicular to the surface of the silicon substrate 80.

Step 0-8 (FIG. 30) Next, the resist 92 is removed. Next, after a tungsten (W) film 94 as a second gate electrode is formed on the entire surface so as to fill the gate groove by a CVD method or the like, the unnecessary W film 94, TiN film 91, etc. outside the gate groove are formed by a CMP technique. And the surface is planarized to bury the W film 94 in the gate groove. The gate electrode is made of TiN film 91 and W film 94
This is because the gate resistance cannot be sufficiently reduced even if the TiN film 91 is made thick.

By the above steps 0-1 to 0-8, nMI
Since the nitrogen concentration of the gate electrode in the S formation region can be higher than the nitrogen concentration of the gate electrode in the pMIS formation region,
The work function of the gate electrode in the S formation region can be lower than the work function of the gate electrode in the pMIS formation region. Specifically, it can be lowered by about 0.1 eV. This makes it possible to separately produce nMIS and pMIS.

However, this method has the following problems. The accelerating voltage of nitrogen ions in step 0-7 is Ti
It is desirable that the nitrogen concentration be set so as to peak near the interface between the N film 91 and the gate insulating film 90. The reason is that the lower the ion implantation concentration, the more efficiently the interface T
This is for changing the work function of the iN film 91.

FIG. 31 shows this state. FIG. 31 shows FIG.
9 is an enlarged cross-sectional view of a gate portion of an nMIS formation region of FIG.
As shown in FIG. 31, the TiN layer 93 having a high nitrogen concentration
The gate insulating film 90 is formed so as to be in contact with the region 95 into which nitrogen ions have been implanted.

Since the ion-implanted nitrogen has a concentration increase in the depth direction, the nitrogen ion-implantation is performed so that the nitrogen concentration peaks near the interface between the TiN film 91 and the gate insulating film 90. In this case, as shown in FIG. 31, nitrogen is ion-implanted into the gate insulating film 90. That is, the gate insulating film 90 is damaged by the ion implantation of nitrogen, and the insulating property and the reliability are deteriorated.

In order to efficiently change the work function, it is necessary to increase the nitrogen concentration near the interface between the TiN film 91 and the gate insulating film 90. Although it is desirable to perform ion implantation so as to have a peak, on the other hand, there is an essentially contradictory problem that it is not possible to selectively perform ion implantation near the interface in order to prevent deterioration of the gate insulating film.

Generally, a threshold voltage of 0.4 V or less is required for a MIS transistor for a high driving force.
Therefore, the work function of the gate electrode of the nMIS is 4.
It is desirable to be about 2 eV or less. However, since the change amount of the work function according to the above-described conventional technique is at most about 0.1 eV, it cannot be satisfied.

[0022]

As described above, as a method of controlling the threshold voltage of a damascene gate MIS transistor, nitrogen ions are implanted into a metal gate electrode to adjust the work function of the metal gate electrode. Had been proposed. However, this method has a problem that the work function of the metal gate electrode cannot be changed efficiently without lowering the insulation and reliability of the gate insulating film.

The present invention has been made in consideration of the above circumstances, and has as its object to change the work function of an electrode containing a metal without adversely affecting a region under the electrode. An object of the present invention is to provide an apparatus and a method of manufacturing the same.

[0024]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows. That is, in order to achieve the above object, a semiconductor device according to the present invention includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, and an electrode formed on the insulating film, wherein the electrode is A first region including a lower surface thereof and a second region formed on the first region, wherein the first region is formed of a predetermined substance, and the second region is formed of a metal or a metal. It is characterized by being formed from a metal compound containing nitrogen.

The semiconductor device according to the present invention can be manufactured by, for example, the following method for manufacturing another semiconductor device according to the present invention. In the method for manufacturing a semiconductor device according to the present invention, a step of forming an insulating film on a semiconductor substrate, and forming a metal-containing film made of a metal or a metal compound containing metal and nitrogen as an electrode on the insulating film A step of introducing the predetermined substance into the metal-containing film so as not to introduce a predetermined substance into the insulating film, and diffusing the predetermined substance by heat treatment to form the metal-containing and insulating film. Forming a region made of the predetermined substance in the metal-containing film on the interface and the region in contact with the interface.

In the above-described method for manufacturing a semiconductor device, a predetermined substance is formed on a metal-containing film so as not to introduce a predetermined substance into an insulating film. This predetermined substance can be deposited near the interface between the metal-containing film and the insulating film by thermal diffusion, whereby the work function of the metal-containing film can be adjusted.

Here, unlike the prior art, no metal ions (corresponding to the above-mentioned predetermined substance) are implanted into the gate insulating film (corresponding to the above-mentioned insulating film), so that the insulating film such as the gate insulating film or the like is not provided. It is possible to change the work function of an electrode such as a metal gate electrode without adversely affecting the performance.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a metal-containing film made of a metal or a metal compound containing metal and nitrogen on a semiconductor substrate; Forming a buffer layer thereon; and implanting ions into the buffer layer or implanting ions into the metal-containing film via the buffer layer.

In the present invention, the buffer layer is a film having an effect of slowing down the ions to be implanted, or a film having the ability to retain the ions and diffuse the ions by heat treatment.

According to the method of manufacturing a semiconductor device, even if the acceleration voltage of ions is increased, if the buffer layer is thickened,
The region where the ions are below the metal compound film (eg gate insulating film)
It can be prevented from being injected inside. That is, even if the acceleration voltage of ions is increased in order to prevent a decrease in throughput, damage to the region below the metal compound film can be avoided.

When ions are implanted into the buffer layer, heat treatment allows ions in the buffer layer to be introduced only into the metal compound film by thermal diffusion, thereby adjusting the work function of the metal compound film. become able to.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0033]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 1 to 7 show an nMIS and a pMIS (CM) according to a first embodiment of the present invention.
FIG. 9 is a cross-sectional view for describing the method for manufacturing the IS transistor.

Step 1-1 (FIG. 1) First, the steps up to step 01-05 are performed in the same manner as in the prior art, so that the element isolation region 2, the silicon oxide film 3 (the lowermost layer of the dummy gate) (Remaining insulating film), extension region 4, source / drain region 5, metal silicide film 6, first silicon nitride film (interlayer insulating film)
7, a second silicon nitride film (gate side wall) 8, a gate insulating film 9, and a TiN film (first gate electrode) 10 are formed. The process up to this point is the same for both nMIS and pMIS.

Here, the metal silicide film 6 may be a single layer film such as a cobalt silicide film or a titanium silicide film. Further, the gate insulating film 9, Ti0 may be a film of high dielectric material ₂ or the like, or may be a silicon oxide film formed by oxidizing the substrate surface which is exposed on the bottom of the gate trench.

Before the formation of the dummy gate, activation annealing is performed after ion implantation into the nMIS formation region and the pMIS formation region as necessary, respectively.
The impurity concentration of the channel region of the transistor may be adjusted.

In a normal MOS process, this type of channel ion implantation is performed before forming a source / drain or a gate. In a damascene gate process, even after a dummy gate is removed and a gate groove is formed. Since impurity ions can be implanted before the gate is formed, it is not always necessary to perform the process before the formation of the source / drain and the dummy gate.

However, in the case of the present invention, basically, metal ions are implanted into the gate electrode to control the threshold voltage. Therefore, it is not essential to adjust the impurity concentration of the channel region.

The method of forming the element isolation region 2 is, for example, as follows. First, a silicon nitride film serving as a mask is deposited on the silicon substrate 1 via a buffer oxide film. Next, a resist pattern having an opening in a region to be the element isolation region 2 is formed on the silicon nitride film, and the silicon nitride film is etched by RIE (Reactive Ion Etching) using the resist pattern as a mask. Then, the resist pattern is transferred to the silicon nitride film. Next, using the resist pattern and the silicon nitride film as a mask, the surface of the silicon substrate 1 in a region to be the element isolation region 2 is etched to form a shallow trench on the substrate surface. Next, after removing the resist pattern, an insulating film such as a silicon oxide film is deposited on the entire surface so as to fill the shallow trench. Next, the insulating film is polished by CMP (Chemical Mechanical Polishing), and is flattened to the upper surface of the silicon nitride film serving as a mask. Thereafter, by removing the silicon nitride film and the buffer oxide film, the element isolation region 2 shown in FIG.
Is completed.

Step 1-2 (FIG. 2) FIG. 2 shows both nMIS and pMIS. In the figure, the left side shows an nMIS formation region, and the right side shows a pMIS formation region. In this step, a resist 11 having an opening only on the nMIS formation region is formed by using a lithography technique.

Step 1-3 (FIG. 3) In the prior art, nitrogen ions are implanted here, but in the present invention, indium ions are implanted here. This ion implantation is performed using the resist 11 as a mask. The acceleration voltage at the time of ion implantation is set so that indium ions are implanted into the TiN film 10 but are not implanted into the gate insulating film 9 unlike the prior art. Thus, an indium ion implantation layer (In ion implantation layer) 12 is selectively formed in the TiN film 10 in the nMIS formation region.

FIG. 4 is an enlarged schematic diagram of a cross section of the gate insulating film 9, the TiN film 10, and the In ion implanted layer 12 in the nMIS formation region. Generally, the degree of spread of the ion implantation concentration in the depth direction can be approximated by a Gaussian distribution. Therefore, the concentration distribution in the depth direction of the In ion implanted layer 12 is approximated by a Gaussian distribution, and the peak position of the In concentration at that time is Rp, and the standard deviation is ΔRp, and is shown in FIG. In the figure, D denotes the gate insulating film 9 and the TiN film 10 from the peak position Rp of the In concentration of the In ion implanted layer 12.
It shows the distance to the interface with.

The distance D is desirably not less than ΔRp, and more desirably not less than three times ΔRp. For example, by setting the ion acceleration voltage for indium ion implantation to 1 keV, Rp becomes about 1 nm and ΔRp becomes about 0.3 nm. Since the thickness of the TiN film 10 is 10 nm, the distance D is 9
nm, which satisfies the above condition sufficiently.

The ion implantation concentration of indium is 5 ×
It is preferably at least 10 ¹⁴ / cm ² . This is because the TiN film 10
Is a dose necessary for depositing a sufficient amount of indium, assuming a film thickness of about 5 nm to 50 nm. Further, as described in the step 0-7 of the prior art, it is desirable that the ion implantation direction is inclined at a few degrees with respect to the direction perpendicular to the surface of the silicon substrate 1.

Step 1-4 (FIG. 5) Next, after removing the resist 11, a heat treatment at about 400 ° C. is performed. By this heat treatment, indium is implanted at the interface between the gate insulating film 9 and the TiN film 10 and at the crystal grain boundaries of the TiN film 10 in the formation of the nMIS formation region. As a result, the TiN film 10 has a precipitate layer (In precipitate layer) 13 in the region including the lower surface and in the crystal grain boundaries.

Here, the temperature of the heat treatment is set to about 400 ° C., but if it is 200 ° C. or more, the In precipitate layer 13 can be formed. In addition, when a substance other than indium is ion-implanted, a deposited layer can be generally formed at 200 ° C. or higher. Although there is no particular upper limit, 800 ° C. or lower is desirable in practice.

Since indium has a work function of about 4.1 eV, it has a desirable value as a gate electrode of nMIS. FIG. 6 is an enlarged view of the formation of the nMIS formation region in FIG. 5, in which an In precipitate layer 13 is formed at the interface between the TiN film 10 and the gate insulating film 9, and an In precipitate layer is also formed at the crystal grain boundary of the TiN film 10. 13 schematically shows a state in which 13 is formed.

Step 1-5 (FIG. 7) Next, as in the conventional step 0-8, in order to reduce the sheet resistance of the gate, the W film 14 (having a thickness of (For example, about 250 nm) is deposited on the entire surface so as to fill the gate groove. Then, unnecessary W film 14, TiN film 10, etc. outside the gate groove are removed by the CMP technique, and the surface is flattened to form the W film 14 into the gate groove. Embed in

As described above, the nMIS is composed of the In deposited layer 13 /
TiN film 10 / W film 14 and pMIS are TiN film 1
A CMIS transistor having the gate electrode structure of the 0 / W film 14 is completed. Since the work function of the In deposition layer 13 is about 4.1 eV and that of the TiN film 10 is about 4.6 eV, it is possible to use nMIS as a gate electrode having an optimum work function.

Thereafter, according to a well-known method, a step of depositing an interlayer insulating film over the entire surface, and contact holes for the gate and the source / drain are formed in the interlayer insulating film and the first silicon nitride film (interlayer insulating film) 7. A step of forming an opening by anisotropic etching, a step of depositing a metal film such as an Al film or a Cu film on the entire surface, a step of etching the metal film into a desired shape, and forming a wiring electrode and the like follow.

FIG. 8 shows the results of experiments conducted by the present inventors, and shows the CV characteristics of the present invention and the conventional MIS capacitor.

The method of forming the MOS capacitor of the present invention used in the experiment is as follows. First, a silicon oxide film having a thickness of 8 nm as a gate insulating film on a p-type silicon substrate,
A TiN film having a thickness of 50 nm was sequentially formed as a gate electrode. Next, the ion acceleration voltage is 5 keV and the dose is 5 ×.
After ion implantation of indium under the condition of about 10 ¹⁵ / cm ² , the silicon oxide film and the TiN film are gate-processed. Finally, a heat treatment of about 400 ° C. is performed.
The MOS capacitor of the present invention is completed.

The indium ion implantation was performed so that the peak of the indium concentration was about 5 nm from the surface of the TiN film. That is, the implanted indium ions were prevented from reaching the interface between the silicon oxide film and the TiN film.

FIG. 8 shows that the MOS capacitor of the present invention in which indium was ion-implanted changed the flat band voltage by about -0.5 V as compared with the conventional MOS capacitor in which indium was not implanted. This indicates that according to the present invention, the work function of the gate electrode of the MOS capacitor can be reduced by about 0.5 eV as compared with the related art.

The prior art has a problem that the gate insulating film is damaged by ion implantation of a metal for controlling a work function, but the present invention does not have this problem.
The reason is the dopant (metal) that changes the work function
This is because ion implantation is performed in the conventional technology as a method of introducing the ions directly above the gate insulating film, whereas in the present invention, they are deposited by heat treatment and introduced. Therefore, unlike the ion implantation, the dopant is not knocked into the gate insulating film.

Although ion implantation is also used in the present embodiment, in this embodiment, the ion implantation is performed shallowly so that the dopant is not introduced into the gate insulating film 9, so that the gate implantation as in the prior art is performed. There is no problem of damage to the insulating film.

In this embodiment, the acceleration voltage is set to 1 keV in order to implant indium ions shallowly. l
There is no problem even if it is lowered to about keV. Further, the accelerating voltage was reduced, and There is no problem even if indium is deposited on the surface of the TiN film 10 at an ion accelerating voltage of 1 keV or less. Since indium may be deposited on the surface of the TiN film 10, instead of ion implantation, the indium film is formed by using a vapor deposition method, a sputtering method, or the like.
Alternatively, the In deposition layer 13 may be formed by depositing on zero and subsequently performing a heat treatment.

In step 1-4, the resist 11
Although the heat treatment is performed after removing the resist 11, the resist 11 may be removed after forming the In deposition layer 13 by a heat treatment at about 300 ° C. before removing the resist 11. This is particularly effective in the above-described method of depositing indium. To describe this method specifically, after step 1-2,
An indium film is deposited, and subsequently, a heat treatment at 300 ° C. is performed to form an In deposition layer 13. Next, the indium film on the resist 11 is removed with a nitric acid solution. Nitric acid solution is T
Since the iN film 10 is not dissolved, the indium film can be selectively removed. After that, the resist 11 may be removed using an alkaline solution.

As described above, the method of precipitation is the gist of the present invention. In order to cause this precipitation phenomenon, first, a substance having a lower melting point than TiN which is a base of the first gate electrode, and which is less likely to react with TiN and hardly form a solid solution may be selected as the implanted ion species.

The melting point of indium is about 160 ° C.
It is much lower than the melting point of TiN of 3000 ° C. Therefore, in this embodiment, indium is used. However, gallium, thallium, tin, lead, antimony, bismuth, selenium, and tellurium may be ion-implanted or deposited, and may be deposited by heat treatment. Their melting points are 30 ° C. (gallium), 300 ° C. (thallium), 230 ° C. (tin), 3
Since the temperatures are 30 ° C (lead), 630 ° C (antimony), 270 ° C (bismuth), 220 ° C (selenium), and 450 ° C (tellurium), there is no problem.

The ion implantation conditions for these elements, that is,
The ion implantation acceleration voltage and the ion implantation dose are desirably set as described in Step 1-3 similarly to indium.

Here, the work functions of solids composed of these elements are 4.3 eV (gallium) and 3.8 eV, respectively.
V (thallium), 4.4 eV (tin), 4.3 eV
(Lead), 4.2 eV (antimony), 4.3 eV (bismuth), 5.9 eV (selenium), 5,0 eV (tellurium)
Therefore, a material that is equal to or higher than 4.6 eV, preferably close to 5.0 eV is a material suitable for the gate electrode of pMIS.
That is, selenium and tellurium are materials more suitable for pMIS.

When a deposition layer is to be formed in the gate electrode of pMIS, a resist having an opening only in the pMIS formation region is formed in step 1-2, and any of these elements is formed only in the pMIS formation region. By performing ion implantation, a pMIS having a gate electrode including a deposition layer of these elements can be formed.

Further, indium is ion-implanted into the nMIS formation region, while, for example, tellurium is ion-implanted into the pMIS formation region, and thereafter, a heat process is performed, so that nM is formed.
If an In deposited layer is formed in the IS forming region and a tellurium deposited layer (Te deposited layer) is formed in the pMIS forming region, n
A gate electrode having a work function suitable for each of the MIS and the pMIS can be formed. This forming method will be described below with reference to FIGS.

First, steps 1-1 to 1-3 are performed. Next, as shown in FIG.
Contrary to -2, a resist 15 having an opening only on the pMIS formation region is formed. Next, as shown in FIG. 10, tellurium ion implantation is performed to make the Te ion implanted layer 16 p-type.
It is formed only in the MIS formation region. Next, as shown in FIG. 11, after removing the resist 15, a heat treatment at about 400 ° C. is performed, and the In precipitation layer 13 and the pM
The Te deposition layer 17 is formed in each of the IS formation regions.
Thereafter, as shown in FIG. 12, Step 1-5 is performed.

As described above, the nMIS is composed of the In deposited layer 13 /
As for the TiN film 10 / W film 14 and the pMIS, a CMIS transistor having the gate electrode structure of the Te deposition layer 17 / TiN film 10 / W film 14 is completed.

Here, the heating step for precipitating indium and tellurium was performed once at 400 ° C., but may be performed separately. The melting point of tellurium is about 450 ° C., which is higher than the melting point of indium, 160 ° C. Therefore, precipitation is less likely to occur in tellurium having a higher melting point than in indium.

Therefore, first, tellurium is ion-implanted only in the pMIS formation region, and a heat treatment at, for example, about 500 ° C. is performed to form a Te deposition layer 17.
By ion-implanting only in the S formation region,
If the heat treatment is performed at a lower temperature than the heat treatment for forming No. 7 and the In precipitate layer 13 is formed, it is possible to set the heat treatment temperature suitable for precipitating each of tellurium and indium.

The TiN film 10 used in this embodiment is used as a base for depositing indium or the like.
The film used for the mother body does not need to be limited to the TiN film 10,
Desirably, a film made of a nitride of a refractory metal such as TiN is used. Alternatively, a film made of tungsten or molybdenum which is a high melting point metal may be used.

For example, in the TiN film 10, the reaction with indium hardly occurs, and the melting point of TiN is 3000 ° C. or more, which is much higher than the melting point of indium, 160 ° C. If the reactions are unlikely to occur and the melting points are significantly different in this way, it becomes possible to easily precipitate a material having a low melting point.

Here, among the base films such as the TiN film 10, a metal nitride film or a metal film having a work function higher than 4.6 eV is suitable for the gate electrode of the pMIS. Therefore, nMIS is performed by the method described in this embodiment.
By forming the In deposition layer 13 only in the formation region, nM
Both the IS and the pMIS can have a gate electrode with an optimal work function.

The same applies to the case where a metal nitride film or a metal film having a work function of 4.6 eV or less is used. In this case, the work function of the metal nitride film is suitable for the gate electrode of nMIS.
By forming the deposited layer, both the nMIS and the pMIS can have a gate electrode having an optimal work function.

In these methods, the In deposition layer 13 is formed in the nMIS formation region, and the Te deposition layer 17 is formed in the pMIS formation region.
There is an advantage in that the number of steps can be reduced as compared with the method of forming. That is, a single ion implantation can form a gate electrode having a work function suitable for each of the nMIS formation region and the pMIS formation region.

The thickness of the In deposition layer 13 and the Te deposition layer 17 formed at the interface between the gate insulating film 9 and the TiN film 10 is preferably 5 nm or less, more preferably about 1 nm or less, which is a few atomic layers. It is desirable to adjust the ion implantation concentration of indium, tellurium, etc., and the heat treatment temperature after ion implantation so that

The reason is that indium has a melting point of indium simple substance of 160 ° C., which is closer to room temperature than other elements. Therefore, when the thickness of the indium deposit layer 13 exceeds 5 nm, the indium precipitate layer 13 becomes insoluble This is because, because of its strong properties, indium may flow even at a low heat treatment temperature close to room temperature as compared with other elements.

However, by setting the film thickness to 5 nm or less,
Indium is used for the lower gate insulating film 9 and the upper TiN film 1.
Due to the bonding force with 0, the properties of indium alone gradually disappear, the melting point becomes higher, and the flow hardly occurs. If the thickness is further reduced to several atomic layers of 1 nm or less, it is possible to obtain a higher melting point that is completely different from the melting point of indium alone.

So far, a method of forming gate electrodes having two different work functions in two types of transistors, nMIS and pMIS, has been described. Here, gate electrodes having different work functions may be formed by using the method described in the present invention so that three or more types of gate electrodes having different work functions are formed on the same semiconductor substrate.

For example, since gallium has a work function of about 4.3 eV, the gallium deposition layer (G
By forming the (a deposition layer), a gate electrode having a work function of about 4.3 eV can be formed.

The threshold voltage of the nMIS using the gate electrode including the Ga deposition layer is 0.2 times lower than that of the nMIS using the gate electrode including the In deposition layer 13 described above.
It becomes higher by about eV. The use of these gate electrodes makes it possible to form MISFETs having different threshold voltages by about 0.2 eV on the same silicon substrate without changing the structure such as the impurity concentration of the channel of the MISFET.

That is, using the present invention, when four types of gate electrodes of an In deposition layer, a Ga deposition layer, a Te deposition layer, and a TiN film having no deposition layer are formed on the same silicon substrate, The work function of the gate electrode of 4. le
V, 4.3 eV, 5.0 eV, and 4.6 eV,
Four types of MIS transistors of nMIS having a low threshold voltage, nMIS having a high threshold voltage, pMIS having a low threshold voltage, and pMIS having a high threshold voltage can be formed.

At this time, one channel structure may be used for each of the nMIS and pMIS. In other words, in the conventional MISFET technology using n-type polysilicon and p-type polysilicon for the gate electrode, when forming two types of nMISs with threshold voltages, the impurity distribution in the channel region of each transistor changes. Thus, it was necessary to change the threshold voltage. However, according to the present invention, MISFETs having different threshold voltages can be formed without changing the impurity distribution in the channel region.

Further, when the precipitation layer is formed by an alloy in which two or more elements used for the above-mentioned precipitation layer are combined, the threshold voltage can be continuously changed. For example, if indium and thallium are ion-implanted to form a deposited layer made of an alloy of indium and thallium, a deposited layer having a work function intermediate between the work functions of the respective elements can be formed.

Here, the work function of the gate electrode can be continuously changed by adjusting the ion implantation amount of each element. Therefore, the threshold voltage of the MISFET can be continuously changed.
MISFETs having optimum threshold voltages for various circuits can be easily formed.

As described above, according to the present invention, since the work function of the gate electrode can be continuously changed, M
The threshold voltage of the ISFET can be changed continuously.

In the case where an SOI (Silicon On Insulator) substrate is used instead of a silicon substrate as a semiconductor substrate, the feature relating to the continuous change of the threshold voltage is a further advantage over the prior art.

For example, in an SO1 substrate in which the thickness of the silicon in the MISFET formation portion is about 50 nm or less,
In the MISFET operation, the operation is performed by completely depleting the silicon in the channel portion of the MISFET. This is because complete depletion has the advantage of increasing the thickness of the channel in the depth direction and improving the driving force of the MISFET.

While having such advantages, the threshold voltage can hardly be changed by the impurity concentration in the channel region. This is because there is an upper limit to the impurity concentration in the channel region in order to operate the MISFET with complete depletion of the channel, and the MISFET can be operated only at a lower concentration.

To change the threshold voltage,
It is necessary to change the work function of the gate electrode. Therefore, two types of conventional polysilicon gates of n-type and p-type can be used to form MIs having different threshold voltages on the same SOI substrate.
An SFET could not be formed.

However, according to the present invention, it is possible to arbitrarily change the work function of the gate electrode as described above, so that three or more MISFEs having different threshold voltages are used.
T can be formed.

Here, an example has been described in which an MISFET that operates in a fully depleted mode is realized using an SOI substrate. However, in other cases, as long as the MISFET operates in a fully depleted mode, the effect of the present invention can be obtained. It can be enjoyed as well.

For example, in the case of nMIS, the channel region is usually formed of a p-type semiconductor region, but by forming a slight n-type semiconductor region here appropriately, only the work function of the gate electrode as described above can be obtained. A MISFET that operates in a fully depleted mode whose threshold voltage is determined can be realized.

A double gate M having two gates
Similarly, the ISFET can be operated in a completely depleted type. This double-gate MISFET is a MISFET in which a channel region made of a semiconductor is formed, regardless of a pair of gate electrodes having the same potential that are formed facing each other. The gate electrode may be arranged horizontally so that a channel is formed in the substrate plane as usual, or may be arranged vertically so that a channel is formed perpendicular to the substrate.
Even in these cases, it is necessary to change the work function of the gate electrode in order to change the threshold voltage.

In this embodiment, in step 1-2, indium was selectively ion-implanted into the nMIS formation region using the resist 11 as a mask. Such ion implantation can be more easily performed by using a stencil mask ion implantation technique.

FIG. 13 schematically shows that the step of implanting indium only in the nMIS formation region in the step 1-2 and the step 1-3 is performed by using the stencil mask ion implantation technique. FIG.

When implanting indium ions, a stencil mask 18 made of, for example, silicon is
By disposing it only above the MIS formation region and performing indium ion implantation in this state, the T of the nMIS formation region is reduced.
Indium can be implanted only in the iN film 10. By using such a stencil mask ion implantation technique, it is possible to selectively perform ion implantation without using the resist 11.

Since the stencil mask 18 can be used a plurality of times, unlike the process using the resist 11 described above, it is not necessary to form the stencil mask every time the ion implantation is performed.
The ion implantation process using the resist 11 requires a series of exposure processes such as resist coating, exposure, development, ion implantation, resist removal, and cleaning, but the ion implantation using the stencil mask 18 of the present invention is performed separately. Can save labor in the above series of exposure processes, so that the process time can be greatly reduced.

Further, using the stencil mask ion implantation method in the present invention has the following new merits. In stencil mask ion implantation,
The dopant to be implanted is also implanted into the stencil mask 18.

Therefore, the stencil mask 18 usually needs to be subjected to a heat treatment or the like periodically to recover the damage caused by the ion implantation before use. In addition, stencils implanted with ions that cannot be recovered by heat treatment
The mask 18 needs to be discarded.

However, in the present invention, as described above, the dopant may be deposited by setting the acceleration voltage for ion implantation to an extremely low acceleration voltage of, for example, about 100 eV or less.
Therefore, in FIG. 13, when stencil mask ion implantation of indium is performed at an acceleration voltage of, for example, 100 eV or less, indium is deposited on the TiN film 10 in the nMIS formation region, and is deposited on the stencil mask 18 in the pMIS formation region. Deposited on

Here, since indium on the stencil mask 18 is only deposited, as in the prior art,
It is not necessary to perform heat treatment or the like to recover damage to the stencil mask. And stencil mask 18
Can be used as many times as necessary by periodically removing the deposited layer of indium by wet etching with, for example, a nitric acid solution.

Furthermore, using the stencil mask ion implantation method in the present invention has the following new merits. That is, for example, a silicon substrate is
By performing the stencil mask ion implantation shown in FIG. 13 in the state of being heated, the ion implantation of indium and the heat treatment can be performed simultaneously.

(Second Embodiment) FIGS. 14 to 21 are sectional views for explaining a method for manufacturing a semiconductor device according to a second embodiment of the present invention. Note that parts corresponding to FIGS. 1 to 7 are denoted by the same reference numerals as those in FIGS.

Step 2-1 (FIG. 14) First, similarly to the first embodiment, after performing the step 1-1 (FIG. 1), a thickness of about 40 nm as a buffer layer is formed on the TiN film 10. Of silicon oxide film 19 is formed.

Step 2-2 (FIG. 15) Next, a resist 11 is formed on the silicon oxide film 19, and indium ions are implanted using the resist 11 as a mask, thereby forming a silicon oxide film 19 in the nMIS formation region. Is selectively implanted with indium ions. The implanted indium ions are indicated by crosses in the figure.

It should be noted that, if the amount is small, even if indium ions are implanted into the TiN film 10, no significant problem occurs. In this step, indium may be ion-implanted under the condition for forming the In ion-implanted layer 12 as described in the first embodiment.

Further, instead of the indium ion, the first
It is possible to use the ions of the elements described in the embodiment. Further, N, B, P, and C ions can be used as other ions not described in the first embodiment.

Step 2-3 (FIG. 16) Next, the resist 11 is removed by asher processing and SH processing. In general, the SH treatment is often effective as a treatment for removing a resist. However, when a metal film such as a TiN film is exposed when the resist is removed, the metal film is also etched by the SH treatment. is there. However, in the case of the present invention, since the entire surface of the TiN film 10 is covered with the silicon oxide film 19, the TiN film 1 is
The problem that 0 is etched does not occur.

As one of the methods for removing the resist 11, an asher + choline treatment can be considered. However, in the case of this method, since the resist 11 is deteriorated by ion implantation of indium, as shown in FIG. 22, there is a problem that the resist 92 cannot be completely removed and a part remains. However, according to the present invention, the deteriorated resist 11 can be completely removed by the SH treatment without causing the etching of the TiN film 10.

Step 2-4 (FIG. 17) Next, a resist 15 is formed on the silicon oxide film 19, and tellurium ions are implanted using the resist 15 as a mask to select tellurium ions in the silicon oxide film 19. Injection. This implanted tellurium ion is indicated by a symbol in the figure.

Note that T as described in the first embodiment is used.
Tellurium ion implantation may be performed under the condition that the e-ion implantation layer 16 is formed.

Step 2-5 (FIG. 18) Next, the altered resist 15 is completely removed by the asher process and the SH process. Also at this time, since the TiN film 10 is covered with the silicon oxide film 19, there is no problem that the TiN film 10 is etched by the SH process.

Step 2-6 (FIG. 19) Next, by heat treatment at about 400 ° C., indium ions contained in the silicon oxide film 19 in the nMIS formation region diffuse into the TiN film 10, and in the pMIS formation region The tellurium ions contained in the silicon oxide film 19 diffuse into the TiN film 10.

At this time, in the steps 2-2 and 2-4, the In ion implantation layer 12 and the Te ion implantation
When 6 is formed, an In deposition layer 13 and a Te deposition layer 17 are formed as in the first embodiment.

Step 2-7 (FIG. 20) Next, the silicon oxide film 19 is removed by wet etching using a hydrofluoric acid-based chemical. At this time, since the TiN film 10 is hardly etched, the silicon oxide film 19 can be substantially selectively removed by etching with respect to the TiN film 10.

Step 2-8 (FIG. 21) Thereafter, similarly to step 1-5 (FIG. 7), a step of forming the W film 14 as a second gate electrode and the like are continued.

In this embodiment, indium ions are implanted into the silicon oxide film 19 in order to adjust the work function of the gate electrode of the nMIS, and then the indium ions in the silicon oxide film 19 are reduced by heat treatment to form the underlying TiN film. 1
Indium ions are introduced into the TiN film 10 by diffusing into the TiN film 10.

Therefore, when indium ions are implanted, there is no problem that the gate insulating film is damaged by indium ions being implanted into the gate insulating film 9.

Furthermore, even if the accelerating voltage of indium ions is increased to prevent a decrease in throughput, if the silicon oxide film 19 is made correspondingly thicker, the indium ions will be reduced in the TiN film 10 and the gate insulating film 9. Can be prevented from being injected.

As another method for preventing the gate insulating film 9 from being damaged by indium ions, the TiN film 1
It is conceivable to increase the thickness of 0 so that indium ions do not reach the gate insulating film 9, but there are the following problems.

That is, if the TiN film 10 is thickened and the entire inside of the gate groove is buried with the TiN film 10, the W film 14 having lower resistivity than the TiN film 10 cannot be buried in the gate groove, and There is a problem that sheet resistance increases.

Here, the entire TiN film 10 is formed in the gate groove.
It is conceivable to increase the thickness of the TiN film 10 within the range not embedded by the above method, but it is difficult to lower the sheet resistance of the gate because the ratio of the W film 14 occupying the gate groove is reduced.

As another method for preventing damage to the gate insulating film 9 due to indium ion implantation, it is conceivable to lower the acceleration voltage for ion implantation. However, lowering the acceleration voltage causes an increase in implantation time. This causes problems such as a decrease in throughput.

In contrast to the method of controlling the thickness of the TiN film 10 and the acceleration voltage for ion implantation, in the present embodiment, a silicon oxide film 19 having a thickness functioning as a buffer layer is provided on the TiN film 10. By adopting a method in which ion implantation is performed in a state where the TiN film 10 is formed in an inclined state, an increase in the sheet resistance of the gate due to an increase in the thickness of the TiN film 10 and a decrease in the throughput (work efficiency) due to a decrease in the acceleration voltage are prevented. Can damage the gate insulating film 9 due to the ion implantation and lower the insulation and reliability caused by the ion implantation.

In the present embodiment, a method is employed in which indium ions and tellurium ions are implanted into the silicon oxide film 19 as a buffer layer, and thereafter, the ions in the silicon oxide film 19 are diffused into the TiN film 11 by heat treatment. Although employed, the effect of decelerating the ions to be implanted in the buffer layer may be used. That is, indium ions and tellurium ions are implanted into the TiN film 11 through the silicon oxide film 19 as a buffer layer in an amount necessary for adjusting the threshold value. In this case, the silicon oxide film 1 is heat-treated.
It is not necessary to diffuse the ions in 9 into the TiN film 11, and the number of steps can be reduced.

The effects of the method for adjusting the work function of the gate electrode of the nMIS of the present embodiment described above also apply to the method of adjusting the work function of the gate electrode of the pMIS of the present embodiment.

In this embodiment, the silicon oxide film 19 is used as the buffer layer, but another insulating film such as a silicon nitride film can be used instead. When a silicon nitride film is used, its removal is preferably performed by hot phosphoric acid treatment.

The present invention is not limited to the above embodiment. For example, in the above-described embodiment, TiN is used as the material of the first gate electrode.
Metals such as W and Ta, and metal silicides such as WSi can be used.

In the above embodiment, In or T is used as the ion species to be implanted into the gate electrode for adjusting the work function.
e, but Ga, Tl, Sb, T
Low melting point metal elements such as e and Se, N, B, P, and C can be used.

In the above embodiment, the case where the metal silicide film 6 is formed on the source / drain region 5 in the step immediately after the formation of the second silicon nitride film (gate side wall) 8 (salicide technique) will be described. However, the process 1-
After 5 (FIG. 7), the metal silicide film 6 may be formed after opening the contact holes for the gate and the source / drain.

In the above embodiment, the case of the MIS transistor having the damascene gate structure has been described. However, the normal MI in which the gate electrode is formed by RIE processing is described.
It can also be applied to S-type transistors. Further, the present invention can be applied to other elements such as a MIS capacitor.

In the above embodiment, the case where the element is formed in a silicon region (silicon substrate, SOI substrate) has been described. Alternatively, it may be formed in a region formed of a plurality of semiconductor elements such as silicon germanium.

Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements described in the embodiment, if the problem described in the section of the problem to be solved by the invention can be solved, the constituent Can be extracted as an invention. In addition, various modifications can be made without departing from the scope of the present invention.

[0134]

As described above in detail, according to the present invention, it is possible to realize a semiconductor device and a method of manufacturing the same which can change the work function of an electrode containing a metal without adversely affecting a region under the electrode. become.

[Brief description of the drawings]

FIG. 1 is a sectional view for explaining a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view for explaining a manufacturing method following the manufacturing method following FIG. 1;

FIG. 3 is a cross-sectional view for explaining the manufacturing method of the manufacturing method following FIG. 2;

FIG. 4 is a cross-sectional view for explaining the manufacturing method of the manufacturing method following FIG. 3;

FIG. 5 is a cross-sectional view for explaining the manufacturing method of the manufacturing method following FIG. 4;

FIG. 6 is a sectional view for explaining a manufacturing method following the manufacturing method following FIG. 5;

FIG. 7 is a sectional view for explaining the manufacturing method of the manufacturing method following FIG. 6;

FIG. 8 shows the CV of the present invention and the conventional MIS capacitor.
Diagram showing characteristics

FIG. 9 is a cross-sectional view for explaining a modification of the first embodiment.

FIG. 10 is a sectional view for explaining a modified example following FIG. 9;

FIG. 11 is a sectional view for explaining a modification example following FIG. 10;

FIG. 12 is a sectional view for explaining a modified example following FIG. 11;

FIG. 13 is a sectional view for explaining another modification of the first embodiment;

FIG. 14 is a sectional view for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention;

FIG. 15 is a sectional view for explaining the manufacturing method of the manufacturing method following FIG. 14;

FIG. 16 is a sectional view for explaining the manufacturing method of the manufacturing method following FIG. 15;

FIG. 17 is a sectional view for explaining the manufacturing method of the manufacturing method following FIG. 16;

FIG. 18 is a cross-sectional view for explaining the manufacturing method of the manufacturing method following FIG. 17;

FIG. 19 is a sectional view for explaining the manufacturing method of the manufacturing method following FIG. 18;

FIG. 20 is a sectional view for illustrating the manufacturing method following FIG. 19;

FIG. 21 is a sectional view for explaining the manufacturing method of the manufacturing method following FIG. 20;

FIG. 22 is a cross-sectional view for explaining a problem of a method of removing a resist using an asher + choline treatment.

FIG. 23 shows a conventional nMIS and pMIS on the same substrate.
Sectional view for explaining a method of forming

FIG. 24 is a sectional view for explaining the same forming method following FIG. 23;

FIG. 25 is a sectional view for explaining the same forming method continued from FIG. 24;

FIG. 26 is a sectional view for explaining the same forming method continued from FIG. 25;

FIG. 27 is a sectional view for explaining the same forming method continued from FIG. 26;

FIG. 28 is a sectional view for explaining the same forming method following FIG. 27;

FIG. 29 is a sectional view for explaining the same forming method continued from FIG. 28;

FIG. 30 is a sectional view for explaining the same forming method continued from FIG. 29;

FIG. 31 is an enlarged cross-sectional view of a gate portion in an nMIS formation region in FIG. 29;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 silicon substrate 2 element isolation region 3 silicon oxide film 4 extension region 5 source / drain region 6 metal silicide film 7 first silicon nitride film (interlayer insulating film) 8 second silicon nitride film (Gate side wall) 9 ... Gate insulating film 10 ... TiN film (first gate electrode) 11 ... Resist 12 ... In ion implantation layer 13 ... In deposition layer 14 ... W film (second gate electrode) 15 ... Resist 16 Te ion-implanted layer 17 Te deposition layer 18 Stencil mask 19 Silicon oxide film (buffer layer)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/41 H01L 29/62 G 29/43 29/78 301P 21/336 617K 29/786 617M (72) Inventor Kyoichi Suguro 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture F-term in the Toshiba Yokohama office (reference) 4M104 AA01 AA02 AA03 AA09 BB02 BB04 BB05 BB16 BB17 BB18 BB20 BB25 BB28 BB29 BB30 DD08 DD37 DD43 DD63 DD75 DD78 DD82 DD84 EE03 EE05 EE14 EE16 EE17 FF13 GG19 HH16 HH20 5F048 AA01 BA16 BB01 BB04 BB08 BB09 BB10 BB11 BB13 BB14 BB15 BC06 BE03 BF06 BF16 BG13 DA02 5A30 EB15 EE03 EE48 FF01 FF02 HJ13 HJ23 HL02 HL03 NN03 NN24 QQ19 5F140 AA00 AA06 AA19 AB03 AC36 BA01 BA03 BA05 BC06 BC17 BD11 BE07 BE10 BF 05 BF15 BF17 BF18 BF20 BF21 BF27 BF37 BF38 BF40 BF45 BG03 BG04 BG05 BG08 BG14 BG28 BG30 BG31 BG32 BG33 BG36 BG40 BG52 BG53 BH14 BJ01 BJ08 BK02 BK05 CB13 CC03 CB13

Claims (20)

[Claims] A semiconductor substrate; an insulating film formed on the semiconductor substrate; and an electrode formed on the insulating film. The electrode includes a first region including a lower surface thereof, A second region formed on the first region, wherein the first region is formed of a predetermined material, and the second region is formed of a metal or a metal compound containing a metal and nitrogen. A semiconductor device characterized by the above-mentioned. 2. The method according to claim 1, wherein the predetermined substance is gallium, indium, thallium, tin, lead, antimony, bismuth, selenium, tellurium, or an alloy composed of at least two elements selected from these elements. The semiconductor device according to claim 1, wherein 3. The semiconductor device according to claim 1, wherein said metal compound is titanium nitride, zirconium nitride, hafnium nitride, niobium nitride, tantalum nitride, or tungsten nitride. 4. The semiconductor device according to claim 1, wherein said metal is molybdenum or tungsten. 5. The semiconductor device according to claim 1, wherein said first region has a thickness of 5 nm or less. 6. The insulating film and the electrode each include:
2. The semiconductor device according to claim 1, wherein the semiconductor device is a gate insulating film and a gate electrode of a MIS transistor. 7. The MIS transistor according to claim 6, wherein said MIS transistor has a damascene gate structure.
3. The semiconductor device according to claim 1. 8. A step of forming an insulating film on a semiconductor substrate; a step of forming a metal-containing film made of a metal or a metal compound containing metal and nitrogen as an electrode on the insulating film; Introducing the predetermined substance into the metal-containing film so as not to introduce the predetermined substance into the metal-containing film; and diffusing the predetermined substance by heat treatment to form an interface between the metal-containing film and the insulating film and the interface. Forming a region made of the predetermined substance in the metal-containing film on a region in contact with the semiconductor device. 9. The step of introducing the predetermined substance into the metal-containing film so as not to introduce the predetermined substance into a region below the metal-containing film, wherein the step of ion-implanting the predetermined substance is performed. The method for manufacturing a semiconductor device according to claim 8, wherein: 10. The method according to claim 8, wherein the metal-containing film is a gate electrode, and a region below the metal compound film is a gate insulating film. 11. The method according to claim 8, wherein the temperature of the heat treatment is 200 ° C. or higher. 12. A step of forming a metal-containing film made of metal or a metal compound containing metal and nitrogen as an electrode on a semiconductor substrate; a step of forming a buffer layer on the metal-containing film; Implanting ions into the layer, or implanting ions into the metal-containing film via the buffer layer. 13. A step of forming a metal-containing film made of metal or a metal compound containing metal and nitrogen as an electrode on a semiconductor substrate; a step of forming a buffer layer on the metal compound film; Covering a part of the layer with a resist; and implanting ions into the buffer layer in a region not covered with the resist, or including the metal-containing material through the buffer layer in a region not covered with the resist. A method for manufacturing a semiconductor device, comprising: a step of implanting ions into a film; and a step of selectively removing the resist from the buffer layer. 14. The semiconductor device according to claim 13, wherein the step of selectively removing the resist with respect to the buffer layer is performed using a chemical solution containing sulfuric acid and a hydrogen peroxide solution. Method. 15. The method according to claim 12, further comprising a step of, when ions are implanted into said buffer layer, diffusing said ions in said buffer layer into said metal-containing film by heat treatment. 2. The method for manufacturing a semiconductor device according to claim 1. 16. The method of manufacturing a semiconductor device according to claim 12, wherein said ions are metal ions. 17. The method according to claim 12, wherein said buffer layer is a silicon oxide film or a silicon nitride film. 18. The method according to claim 8, wherein the metal-containing film is a metal nitride film. 19. The method according to claim 19, wherein the metal nitride film is a titanium nitride film,
19. The method according to claim 18, wherein the film is a zirconium nitride film, a hafnium nitride film, a niobium nitride film, a tantalum nitride film, or a tungsten nitride film. 20. The method according to claim 8, wherein the metal-containing film is a tungsten film or a molybdenum film.