JP2002291992A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine by which the power supply start of the main control part is easily delayed and a defective operation is prevented or suppressed by detecting the delay. SOLUTION: A power source unit 420 outputs a power source voltage to the main control part for controlling a game and to a sub-control part to be operated in response to the main control part. The power source unit 420 is provided with a main board power source control part 870 for controlling the output of the power source voltage to the main control part based on a signal (an operation occurrence signal) from the sub-control part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine such as a so-called seven machine, a blade, a right object, a ball game machine such as an arrangement ball, and a coin machine such as a slot machine.

[0002]

2. Description of the Related Art In general, computer control is adopted in a game machine such as a pachinko machine, and a signal necessary for game control is generated in a CPU from power-on of a game machine to a normal game. The control of the gaming device is performed. The control unit including such a CPU includes:
In many cases, the main control unit is divided into two or more for efficiency of control and simplification of the configuration. It is configured.

Here, when power is supplied to the plurality of control units, if the sub control unit starts up after the main control unit starts up, for example, a control signal from the main control unit is received by the sub control unit side. Problems such as spillage may occur. Therefore, conventionally, a method has been adopted in which a delay circuit is provided on the main control unit side to delay the rise of the main control unit when the power is turned on.

[0004]

However, the method of delaying the rise of the main control unit in the above-described configuration is determined by the delay time of the timer. However, it is difficult to confirm the operation failure related to the delay. Therefore, no error can be detected,
The delay of the main control unit may be inaccurate, and the control signal from the main control unit may be missed by the sub control unit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a game in which the power-on of the main control unit can be easily delayed, and the delay can be detected to prevent or suppress the occurrence of malfunction. The machine.

[0006]

In order to solve the above-mentioned problems, a first aspect of the gaming machine according to the present invention has a main control section for controlling a game and operates according to the main control section. A sub-control unit, and a power supply voltage output unit for outputting a power supply voltage to these control units, wherein the power supply voltage output unit transmits to the main control unit based on a signal from the sub-control unit. An output control unit for controlling the output of the power supply voltage is provided.

According to such a gaming machine, since the power supply voltage for operating the main control unit is output based on the signal from the sub control unit, the sub control unit operates before the main control unit operates. Therefore, for example, a problem such as that the control signal from the main control unit after the main control unit is operated may be missed on the sub control unit side may be less likely to occur. Further, in the power supply voltage output section (output control means), when a signal from the sub-control section is not received at a predetermined timing, or when a signal different from the predetermined signal is received, it is possible to detect an error, so that it is more reliable. It may be possible to perform control at the time of power supply output (when power is turned on). It should be noted that a notifying means may be provided in the gaming machine, and when an error is detected, the notifying means may notify the error.

[0008] Next, the sub-controller is capable of outputting an operation occurrence signal indicating the rise of the operation to the output control means, and the output control means is configured to output the operation occurrence signal based on the input of the operation occurrence signal. Control for outputting the power supply voltage to the main control unit may be performed. As described above, if the output control means controls the output of the power supply voltage to the main control unit based on the input of the operation occurrence signal from the sub control unit, the operation of the main control unit is more reliably performed by the sub control unit. Therefore, a problem such as the control signal from the main control unit being missed by the sub control unit may be less likely to occur.

The power supply voltage output section includes a main control section power supply voltage output section for outputting the power supply voltage to the main control section, and the output control means outputs the power supply voltage to the main control section based on the input of the operation occurrence signal. An operation signal as an operation command may be output to the main control unit power supply voltage output unit. As described above, in the present invention, there is no need for a delay circuit or the like having a timer or the like for delaying the operation of the main control unit from that of the sub control unit. The operation of the main control unit can be delayed with respect to the sub-control unit only by providing the control unit, which is simple and economical. That is, when a signal from the sub control unit is received by the input / output circuit unit (which constitutes an output control unit), the input / output circuit unit outputs the power supply voltage to the main control unit. Signal (operation command signal)
May be able to easily realize the delay. Also, for example, in a conventional gaming machine in which a delay circuit or the like is provided in the main control unit, the design change of the timer or the like of the delay circuit may be inevitably performed in the main control unit in accordance with the design change of the sub control unit. In the gaming machine of the present invention, the rising of the main control unit is delayed based on the input of the signal (operation occurrence signal) from the sub control unit.
Even when there is a change in the design of the sub-control unit, the design change in the main control unit is not required (or the design change is minimal), which may lead to cost reduction.

Next, in order to solve the above-mentioned problem, a gaming machine according to a second aspect of the present invention comprises a main control unit for controlling a game, and a plurality of sub-control units operating according to the main control unit. A power supply voltage output unit for outputting a power supply voltage to these control units, wherein the sub control unit is capable of outputting an operation occurrence signal indicating a rise of the operation,
The power supply voltage output unit outputs the power supply voltage to the sub-control unit when the power supply voltage is turned on, and then outputs the power supply voltage to the main control unit when receiving an operation occurrence signal from each of the plurality of sub-control units. An output control unit for performing control for outputting to the control unit is provided.

With this configuration, for example, when the power supply voltage of the gaming machine is turned on, the power supply voltage is first supplied to the plurality of sub-controllers, and the sub-controllers operated by the supply of the power supply voltage cause the sub-controllers to operate. A signal is output to the output control means, and when the output control means receives the operation occurrence signal, the power supply voltage is output to the main control unit. Therefore, since the operation of the main control unit is started more reliably than the operation of the sub-control unit, problems such as the control signal from the main control unit being missed by the sub-control unit side may be further reduced. Also in this case, the power supply voltage output unit (output control means) can detect an error when the operation occurrence signal is not received at a predetermined timing, or when a signal different from the operation occurrence signal is received. The power supply voltage output unit may be provided with an input / output circuit unit that receives an operation occurrence signal and can output a signal for outputting a power supply voltage based on the input of the operation occurrence signal.

In any of the above embodiments, the output control means outputs the power supply voltage to the main control section based on, for example, an input signal (input of an operation occurrence signal) from the sub control section. It is composed of an input / output circuit unit including a logic circuit that outputs a signal (operation command signal), or outputs a power supply voltage to the main control unit based on an input signal (input of an operation occurrence signal) from a sub control unit. Signal (operation command signal)
It is also possible to include a CPU (one-chip type CPU) that outputs the same.

Hereinafter, a configuration that can be added to the gaming machine of the present invention will be described. An input unit for receiving voltage, a voltage converting unit for converting the receiving voltage into a plurality of different power supply voltages,
A power supply unit having the power supply voltage output unit that outputs the converted power supply voltage, and a voltage input unit that is provided separately from the power supply unit and receives a plurality of power supply voltages output from the power supply voltage output unit. In order to supply the power supply voltage to the electric operation units provided in various parts of the gaming machine, the power supply voltage is formed individually corresponding to the power supply voltage, and a plurality of output terminals are provided for at least one of the power supply voltages. And a power distribution unit having a distribution-side power supply voltage output unit distributed and formed.

According to this configuration, a plurality of power supply voltages required for the gaming machine are generated at a time by the voltage converter of the power supply unit, and the power supply side power supply of the power distribution board provided independently of the power supply unit. Each power supply voltage from the power supply unit is distributed from the voltage output unit to various parts of the gaming machine. It is only necessary to change the specifications of the substrate, and the design change of the power supply can be minimized. The power distribution board is desirably detachably mounted to a predetermined mounting target portion (for example, a back mechanism panel of a game machine) in consideration of ease of design change and convenience of component replacement.

[0015] The voltage converter of the power supply unit may convert the AC receiving voltage into a plurality of DC power supply voltages. The AC receiving voltage can be, for example, 24 VAC, and the converted DC power supply voltage can be, for example, 32 VDC (in the case of a ball-and-play game machine, it can be used as a solenoid drive voltage for an accessory, etc.), 24 VDC (also the torque for the firing device). Can be used as a drive voltage of a motor), 12 V DC (also can be used as a drive voltage of a motor for a prize ball payout device, or other analog control voltages), 5 V DC
(Which can be used as a drive voltage for digital control). Any of them can be generated as a rectified, smoothed, etc. power supply voltage, and further as a + or-unipolar or bipolar power supply voltage according to the purpose.

Next, a plurality of control boards (each control board as a main control section or a sub-control section) for directly or indirectly controlling the operation of the gaming machine are connected to the power supply side power supply voltage output section of the power distribution board. In order to do so, a board-side connector that combines output terminals of one or more power supply voltages used on each board is
A plurality can be provided corresponding to the number of substrates to be connected.
According to this configuration, instead of separately providing a power supply unit for generating a required power supply voltage on each board, various power supply voltages generated by one power supply unit are integrated into each board from the power distribution board. Therefore, the number of power supply units can be reduced. In addition, when a third party verifies a gaming machine, the power supply-related parts must be verified in the technical manual of the power distribution board (including drawings, etc.) and the identification characters (part model name and voltage value) displayed on the board. And the like, it is possible to determine at a glance what power supply voltage is required for each substrate. The board-side connector may be provided with an input terminal for a signal (an operation occurrence signal) from the sub-control unit, and may be integrally configured with an output terminal for a power supply voltage.

[0017] The power distribution board has an output current of a specific voltage supplied to the control board for at least one of the plurality of control boards connected thereto in order to protect the board components from overcurrent. A current cutoff mechanism that cuts off excess power can be provided. It is effective that the current interruption mechanism is provided on a control board to which a large current load is connected, for example, a control board to which a motor is connected. In this case, the current cutoff mechanism cuts off the output current of the motor driving voltage when it becomes excessive. As the current interrupting mechanism, a switch-type breaker mechanism can be used, but a current interrupting mechanism including a current interrupting fuse is advantageous in that it is simple and inexpensive.

[0018]

Embodiments of the present invention will be described below with reference to the embodiments shown in the drawings. Here, as a gaming machine, a first-type pachinko machine (ball game machine) of a type called a so-called seven machine is taken as an example, and the structure thereof will be described with reference to FIGS.

The front part of the pachinko machine 1 comprises a main body frame 2, a middle frame 3, a front frame 4, an upper plate 5, a lower plate 6, and a locking device 7. The main body frame 2 is formed by assembling and fixing a wooden plate-like body into a substantially rectangular frame shape. The middle frame 3 is entirely made of plastic, has a frame portion (not shown) and a lower plate portion (not shown), and is supported by the main body frame 2 so as to be openable and closable. A locking device 7 is provided at the center of the right end of the middle frame 3. The locking device 7 has a substantially rectangular shape with a keyhole when viewed from the front, and is used for locking when the front frame 4 is closed.

The frame portion is formed in a substantially rectangular frame shape from the upper end to about 2/3 of the entire middle frame 3 downward, and a substantially triangular frame decoration LED of the front frame 4 is provided at the upper end portion. The prize ball display LED (not shown) and the prize ball display LED board 4d (see FIG. 4) are on the left side, and the stop display LED (not shown) and the stop display LE are on the right side corresponding to the lenses 4c and 4e.
A D substrate 4f (see FIG. 4) is provided.

The lower plate portion occupies approximately one third of the entire inner frame 3 from the lower end to the upper side. Speaker 40 that generates sound effects and other sounds (voices) according to the
0a (see FIG. 4) is provided, and a supply device or the like that supplies the game balls stored in the upper plate portion 5 to a launch device unit 8 (see FIG. 3) that shoots game balls (approximately in the center). (Not shown)
Is provided.

Further, below the lower plate portion, there is provided a lower plate portion 6 provided with an ashtray, a ball-drawing lever, and the like. Outlet 6a is opened, and the firing device unit 8 is provided at the right end.
A launch handle 9 for operating (see FIG. 3) is provided. Further, a touch switch 9a for detecting that the player is touching is mounted on the firing handle 9,
A fire stop switch 9b for temporarily instructing a stop of the fire is provided in the vicinity thereof.

The front frame 4 is entirely made of plastic, and is used to visually recognize the game board 10 (see FIG. 2) from the front.
The upper side has a substantially circular arc shape corresponding to the shape of the game area 11 (see FIG. 2) formed on the game board 10, and has an opening 4a entirely opened in a substantially bullet shape. A substantially rectangular glass frame (not shown) in which a glass plate is fitted according to the opening 4a is mounted on the back surface. Also,
The front frame 4 occupies about ／ of the entire front surface of the pachinko machine 1 and is pivotally mounted on the left end of the middle frame 3 so as to be openable and closable. Further, a frame decoration lamp lens 4b is provided at the upper end, and an opening 4 is provided inside the lens 4b.
A frame decoration lamp substrate 4g (see FIG. 4) and a plurality of game effect lamps (not shown) are provided along the arc portion at the upper end of the frame a.

The upper plate 5 is pivotally attached to the left end of the middle frame 3 below the front frame 4 so as to be openable and closable. Dish outer edge 5
In b, a ball removal button, a game ball lending / returning button, and the like are provided. The upper plate 5 is provided with a discharge port 5c for discharging game balls from inside the pachinko machine 1. On the left end, a speaker surface 5 having a plurality of long holes
a is formed, and the volume switch board 12
(See FIG. 4). On the left end side of the pachinko machine 1, a prepaid card unit 13 is mounted.

Next, the surface structure of the game board 10 of this embodiment will be described with reference to FIG. The game board 10 is a substantially rectangular wooden plate-shaped body, held by the middle frame 3 (see FIG. 1), and the back side of which is covered by a back mechanism board 102 (see FIG. 3) described later. The game board 10 has an outer rail 14 and an inner rail 15 provided on the surface of the game board 10.
Thus, a substantially circular game area 11 is formed. In the game area 11, a special symbol display device 16, a first-type starting port (ordinary electric accessory) 17, a variable winning device 18, and a left winning port are provided. 19, right winning opening 20, lower left winning opening 21, lower right winning opening 2
2, a number of obstacle nails 23, a pair of lamp windmills 24, 2
5 and so on are provided.

The special symbol display device 16 is disposed substantially at the center of the game area 11 and has a center role 26 and a liquid crystal display panel 27. The image screen of the liquid crystal display panel 27 has a substantially rectangular shape, and one or a plurality of special symbols (identification information) are displayed on the display screen while sequentially changing in a predetermined direction, and then stopped and displayed. A symbol display area (identification information display area) is formed. That is, the left special symbol display area for displaying the left special symbol, the middle special symbol display area for displaying the middle special symbol, and the right special symbol display area for displaying the right special symbol are arranged in the arrangement direction set substantially in a horizontal line. They are formed side by side in this order (not shown). Each of the special symbol display areas has a direction substantially orthogonal to the arrangement direction of these display areas, in this case, a symbol change direction is set in a vertical direction, and a plurality of symbols as identification information ( Special symbols) are sequentially displayed.

Returning to FIG. 2, the liquid crystal display panel 27 is displayed in a display area (not shown) of the video screen when a game ball enters the first-type starting port (ordinary electric accessory) 17. In this case, each special symbol is fluctuated and stopped and displayed. Then, for example, when the symbols are stopped and displayed (fixed display) with the same three digits of the symbol “7, 7, 7”, a large winning prize port 311 of the large prize winning device 31 described later provided in the variable prize winning device 18 is opened. Be released. Also, the center role 26 is
It is mounted on the periphery of the front surface of the liquid crystal display panel 27 in a frame-like manner, and has a normal symbol display device 32 and a special symbol hold display LED.
16a.

The normal symbol display device 32 is a center accessory 2
6, a 7-segment display 32a
And a normal symbol hold display LED 32b. 7
The segment display 32a is for variably displaying odd numbers of 1 to 9 and includes left and right ordinary symbol operation gates 3 to be described later.
One of the odd numbers is stopped and displayed after a lapse of a predetermined time, which fluctuates as the game ball passes through one of 6, 37. Then, when the stop is displayed at, for example, “7”, the first-type start port (ordinary electric accessory) 17 is kept for a predetermined time (for example, 0.
5 seconds) released.

At the lower left and right of the center role 26, there are provided normal symbol operation gates 36 and 37, respectively.
Right normal symbol operation gate detection switches 36s and 37s (see FIG. 4) are provided. Then, the 7-segment display 32a of the normal symbol display device 32 is variably displayed when the game ball passes through the normal symbol operation gate passage detection switches 36s and 37s.

The normal symbol hold display LED 32b is composed of four round red LEDs, and is a seven-segment display 32.
a. In this method, the number of game balls that have passed through the left and right normal symbol operation gates 36 and 37 is held up to four, and each time they pass, they are sequentially lit and shifted and displayed. Each time the next variable display of the 7-segment display 32a starts, the number of unstarted times is exhausted, and one ordinary symbol hold display LED 32b is turned off.

The special symbol holding display LED 16a is arranged on the upper part of the center accessory 26 and is divided into two each on the left and right sides of the normal symbol display device 32, and is arranged in parallel. I have. In this system, the number of game balls that have entered the first-type starting port (ordinary electric accessory) 17 is held up to four, and each entry is sequentially lit and shifted for display. Each time the next change of the special symbol starts, the number of unstarted times is exhausted, and one special symbol hold display LED 16a is turned off.

The first-type starting port (ordinary electric accessory) 17 is integrated with a variable winning device 18 described later, and is arranged at a distance below the center position of the center accessory 26 in the special symbol display device 16. Has been established. The first-type starting port (ordinary electric accessory) 17 is a so-called tulip type, and a pair of left and right wing pieces are formed so as to open and close. Inside,
First-class starting port that detects the passage of a game ball (normally electric accessory)
A winning detection switch 17s (see FIG. 4) and a first-type starting port (ordinary electric accessory) solenoid 17c (see FIG. 4) for operating the wing piece are provided. When the pair of wing pieces open left and right, the game ball enters an open state in which the ball can enter, and when the pair of wing pieces close, the game ball enters a closed state in which it is difficult to enter the ball.

The variable winning device 18 is provided below the first type starting port (ordinary electric accessory) 17 and a large winning device 31 is mounted on a substrate 34 having a substantially inverted trapezoidal front surface.
And a lower left winning opening 21 and a lower right winning opening 22.
Here, the special winning device 31 is formed substantially in the center, and has a large winning opening 311 opened in a belt shape, an opening / closing plate 312 for opening and closing the large winning opening 311, and an opening / closing plate 312 for opening and closing the opening / closing plate 312. Large winning opening solenoid 313 (see FIG. 4),
A specific area (V winning opening and general winning opening / not shown) through which a game ball passes after winning the big winning opening 311, an interlocking rod (not shown), and a winning ball detection switch 318 for detecting a winning ball.
(See FIG. 4), a back box (not shown), and a special winning opening relay board (not shown).

The lower left winning opening 21 is disposed substantially to the left of the first type starting port (ordinary electric accessory) 17 and has a lower left winning opening passage detection switch 21s (see FIG. 4) provided therein. Have been. A plurality of lower left winning opening LEDs 223 to 225 are attached to the lower left winning opening LED board 21f (see FIG. 4) below the lower left winning opening 21 and are covered with a decorative lens. Furthermore, lower right winning opening 2
Reference numeral 2 denotes a right-side winning opening passage detection switch 2 which is disposed substantially right next to the first-type starting port (normally electric accessory) 17 and has a lower right inside thereof.
2s (see FIG. 4) is provided. A plurality of lower right winning opening LEDs 220 are located below the lower right winning opening 22.
To 222 are attached to the lower right winning opening LED board 22f (see FIG. 4) and covered with a decorative lens.

Next, an out port 48 is provided below the game board 10.
A back ball prevention member 58 is provided below the out opening 48 to prevent a game ball that has returned without reaching the game area 11 from returning to the firing position. On the other hand, the foul ball prevention member 59 is attached to the distal end of the inner rail 15, and the return rubber 60 is located on the right half side of the game board 10, substantially opposite to the position of the foul ball prevention member 59. , Are fitted along the outer rail 14.

A left winning port 19 and a right winning port 20 are provided diagonally above and below the variable winning device 18, respectively. In addition, a left winning opening passage detection switch 19s (see FIG. 4) and a right winning opening passage detection switch 20s (see FIG. 4) are provided therein. Further, a pair of lamp windmills 24 and 25 are respectively disposed diagonally above and below the special symbol display device 16. Further, a pair of side lamps 38, 3
9 are arranged in a vertically arcuate and symmetrical manner. In addition, a large number of obstacle nails 23 are provided in the game area 11 so as to be suitable for the pachinko game in consideration of the positional balance with each of the gaming machines described above.

Next, the back surface structure of the pachinko machine 1 of this embodiment will be described with reference to FIG. The front frame 4 (see FIG. 1) is in the middle frame 3 and is supported by a pair of hinges 101 provided at the upper and lower ends of the front frame 4 so as to be openable and closable. The back mechanism board 102 is in the middle frame 3 and the back mechanism board 10
The pair of hinges 103 provided at the upper and lower ends of the pair 2 are supported to be openable and closable. The game board 10 (see FIG. 2) is detachably attached to the front side of the middle frame 3. On the left side when viewed from the position of the hinge 101 at the upper end, a prize ball tank 105 having a tank ball out detection switch 104 at the tank bottom and a tank rail 106 connected to the prize ball tank 105 are attached. ing.
Also, on the right side of the tank rail 106, a ball release lever 1 is provided.
07, a supply ball out detection switch 108 is provided downstream thereof, and a prize ball payout device 109 is provided downstream thereof.

Subsequently, a game ball distribution unit 110 is provided downstream of the prize ball payout device 109. On the lower side of the tank rail 106, there is provided a back case 111 with a lid in which the liquid crystal display panel 27 (see FIG. 2) of the special symbol display device 16 is stored. Main control board case 112 storing main control board 340 (see FIG. 4) as control unit 140 (see FIG. 4)
Is provided. On the left side of the main control board case 112, a launcher control board case 113 storing the launcher control board 201 (see FIG. 4) as a launch control unit 201a (see FIG. 4) and a launch control collective relay board 116 are provided. ing. In the lower left portion of the back mechanism panel 102, the above-described firing device unit 8 is provided. In the lower right portion as well, a frame control unit (payout control unit) 150 (see FIG. 4) is provided. Button, main power supply voltage abnormality, firing stop, main control board communication abnormality, prize ball motor abnormality, etc.
A frame control board case (payout control board case) 118 storing a first peripheral control board (payout control board) 350 (see FIG. 4) provided with a frame status indicator 117 indicated by D is provided.

On the other hand, a fuse box 119, a power switch 120, a power terminal board 121 and a big hit, a firing device control, a ball out,
A terminal board 122 provided with an external connection terminal for a game machine frame for opening a door, winning a ball, lending a ball, or the like is provided. A power cable 123 for receiving power supply from outside is also provided below the terminal board 122. Frame control board case 11 storing first peripheral control board 350 (see FIG. 4)
From 8, a connection cable 124 extends upward and is connected to a prepaid card unit 13 having a power cable 125. A ball passage member 126 for a lower plate portion is provided substantially at the lower end of the center of the back mechanism panel 102.

Next, the payout mechanism of the game balls in the back mechanism board 102 of the pachinko machine 1 of the present embodiment will be described with reference to FIG. Above the back mechanism panel 102, a tank ball out detection switch 104 is provided.
And a tank rail 106 connected to the prize ball tank 105. Further, a supply ball out detection switch 108 is provided at an intermediate position of the tank rail 106, and a prize ball payout device 109 is provided downstream thereof. Subsequently, a game ball distribution unit 110 is provided downstream of the prize ball payout device 109. A lower plate full switch 127 is provided on the downstream side of the tank rail 106, and the guide rail 131 communicates with a ball passage member 126 for the lower plate provided at a substantially central lower end of the back mechanism panel 102. I have. An amplifier board 128 is attached to the lower right portion of the back mechanism board 102, and a reset switch 129 is provided outside the amplifier board 128.

Next, the electronic control unit 130 of the pachinko machine 1 of this embodiment will be described with reference to FIG. First,
The electronic control unit 130 is connected to the main control unit 140 by the main control unit 140 and the shared bus 500a that is a common signal transmission path.
A plurality of sub-control units connected to 40, for example, a frame control unit (payout control unit (prize ball payout control unit that mainly performs prize ball payout control)) 150, a special symbol control unit 160, and a lamp control unit 1
70 and a voice control unit 180. The main control unit 140 includes a main control board 340, and the main control unit 1
The above four control units 150, 160, 170 other than 40
180 denotes a frame control board 350 and a special symbol control board 36 as first to fourth peripheral control boards (sub-control boards), respectively.
0, a lamp control board 370 and an audio control board 380.

The main control board 340 includes a CPU 401 (FIG. 9).
), And an input / output circuit unit 500. As shown in FIG.
The control program stored in the ROM 1482 includes a core 1480, and controls the operation of the entire pachinko machine 1 (that is, the basic progress control of the game) using the RAM 1481 as a work area. In addition, the CPU 401 mainly performs the control of determining whether or not to perform the determination based on the determination program stored in the ROM 1482 (the determination unit).

Returning to FIG. 4, the above-mentioned shared bus 500a is connected to the input / output circuit
From the control unit 150, 16 to the shared bus 500a.
Command data as command signals for instructing the processing contents to 0, 170, and 180 are transmitted. Data is transmitted from the main control unit 140 to each of the control units 150, 160, 170, and 180 in a one-way format. In addition, each of the control units 140 to
180 includes a power receiving board 410 from the power supply unit 42
0, and furthermore, power is supplied via a power distribution board (relay board) 430, and a system reset signal at power-on, which will be described later, is transmitted to all control boards via the power distribution board (relay board) 430. You.

The winning board detection switches 318, 19s to 22s and the like are connected to the relay board 200.
Are connected to the input / output circuit unit 500 of the main control unit 140. In addition, the first-class starting port (ordinary electric accessory)
Winning detection switch 17s, normal symbol display device substrate 32
f, various solenoids 17c and 313, a right normal symbol operation gate passage detection switch 37s, and a left normal symbol operation gate passage detection switch 36s are connected to the input / output circuit unit 500 of the main control unit 140.

A touch switch 9a, a firing stop switch 9b, a volume switch 202, a tank ball out detecting switch 104, a replenishing ball out detecting switch 108, and the like are connected to the frame terminal board 200a.
0a is connected to the input / output circuit unit 70 of the frame control unit 150.
0 is connected.

The frame control unit (payout control unit) 150 includes a main circuit unit 600 and an input / output circuit unit 70 similar to the main control unit 140.
0, and is connected to the shared bus 500a in the input / output circuit unit 700. Also, the input / output circuit unit 7
In 00, the prize ball payout device 109 and the launch device control board 20
1 and so on are connected.

The special symbol control unit 160 includes a CPU 161, a RAM 162, a ROM 1
63, an input / output port 164, and a VDP (video display processor) 166. These arithmetic circuit components are mutually connected by a bus 165, and are connected to the shared bus 500a at the input / output port 164. . The liquid crystal display panel 27 is connected to the input / output port 164, and the CPU 161 controls the operation of the special symbol display device 16 (the liquid crystal display panel 27) using the RAM 162 as a work area by a control program stored in the ROM 163 (that is, the display device). Display control).

The lamp control section 170 is a special symbol control section 1
It is configured to include the same arithmetic circuit components 171 to 175 as the
a. The input / output port 174 includes a frame decoration lamp board 4g, various lamp boards 261f and 262f,
Various LED boards 4d, 4f, 21f, 22f and the like are connected. One or more lamps or LEDs are connected to each of these boards. These lamps or the like are turned on / off or flashed in accordance with the progress of the game.

The voice control unit 180 is a special symbol control unit 16
It is configured to include the same arithmetic circuit components 181 to 185 as the zero and a sound generator 203, and is connected to a shared bus 500 a at an input / output port 184. The sound generator 203 outputs various sounds corresponding to the progress of the game from a speaker 400a connected via the volume switch board 12 based on the stored sound data and the sound output module. Volume switch board 12 connected to input / output port 184
Is for setting the output sound volume in response to the operation of a sound volume switch (not shown).

Further, various lamps such as the frame decoration lamp substrate 4g and the sound generator 203 are provided with a special symbol change / stop display mode controlled by the special symbol control unit 160,
The mode is controlled in accordance with the presence or absence of the reach, the reach display mode (described later), the special game mode, and the game mode (probability fluctuation, time saving, etc.). The command signal of the control command is used as a command signal for setting the lamp control unit 170 or the voice control unit 180 as an operation command target, and is described above.
00a.

The special symbol control unit 160, the lamp control unit 170, and the voice control unit 180 are the main control unit 1
It may be configured by a circuit unit similar to 40 or the frame control unit 150. That is, it is assumed that the main circuit unit and the input / output circuit unit are included, and a ROM, a RAM
Can also be used.

Next, the prize ball operation is executed in the following order. The main control unit 140 determines that the game ball is the winning ball detection switch 3
When passing through 18, the prize ball number data is passed, after passing through the first-type start-up port (ordinary electric accessory) prize detection switch 17s, 6 prize ball number data is passed, otherwise, for example, left and right bottom winning Passage detection switch 21 for ports 21 and 22
When the passage of s and 22s is detected, 10
The prize ball number data is transmitted to the frame control unit 150 via the above-described shared bus 500a as a command signal for setting the frame control unit 150 as an operation command target in the order of detection.
(That is, the number of unique prize balls is 6, 10, or 15 here.) The frame control unit 150 is the main control unit 14.
The winning ball number data from 0 is received, and the winning ball payout device 109 is operated by transmitting a winning ball payout signal.

The main control unit 140 determines a game state based on the outputs of the various detection switches described above, determines whether or not the game is valid based on the game state, and displays a corresponding symbol according to the content of the determination. Data for performing image display control in an aspect is read. For example, the main control unit 140
First-class starter (ordinary electric accessory) winning detection switch 17
s, using the detection result of the prize ball detection switch 318 and the like, the acquired value of the special symbol success / failure determination random number, and the like, a state of waiting for a customer who is not playing a game, a state of playing a game but no starting prize (Fluctuating preparation state), start winning prize,
And a special game state. In addition, when a start winning is detected, a win / fail determination is performed based on a random number value to be described later, and based on the determination result, a special symbol change (including a reach display mode) or a display mode control such as confirmation is performed. The data is read. This data is transmitted via the above-described shared bus 500a as a command signal for setting the special symbol control unit 160 as an operation command target.

Next, a main job executed by the main control unit 140 will be described with reference to FIG. this is,
11 is an example of a job executed by the CPU 401 based on a program stored in the ROM 482 of the main control unit 140 shown in FIG. That is, the stack pointer is set to R
After setting to a predetermined address of AM481 (S10),
It is determined that the initialization is completed (S20). If the initialization has been completed (S20: YES), the LED job (S3
The jobs from 0) to the switch job (S70) are executed. If the initialization has not been completed (S20:
NO), an initialization job (S190) is executed.

In the LED job (S30), the display mode data of the normal symbol and the normal symbol unstarted number, the display mode data of the special symbol unstarted number, and the like are output. In the constant-speed random number job (S40), a special symbol hit / failure determination random number memory and a general-purpose count memory of the RAM 481 described later are updated. In the non-constant-speed random number job (S50), a missed ordinary symbol random number memory (not shown) is updated. Note that the general-purpose count memory (not shown) is used, for example, for creating values of “0” to “255” for each user reset, executing a command job, a decoration job, and the like.

In the voice job (S60), data relating to music and voice is read, and in the switch job (S70), various detection switches are read. That is, various signals such as the right and left winning opening passage detection signal are transmitted to the main control unit 140 via the relay board 200, and various signals such as the firing stop detection signal, the touch detection signal, and the volume detection signal are transmitted via the frame terminal board 200a. It is taken in by the frame control unit 150, respectively, and is a first-type starting opening winning detection signal from the first-type starting opening (normal electric accessory) winning detection switch 17s, a winning ball detection signal from the large winning device 31, and a normal symbol operation. The gate passage detection signal is taken into the main control unit 140.

Further, switches 318 such as a count detection switch, a count detection and a specific area passage detection switch, etc.
It is determined whether or not there is an abnormality (see FIG. 4) (S8).
0), if there is no abnormality (S80: YES), jobs from the special symbol main job (S90) to the voice job (S110) are executed. If there is an abnormality (ball clogging, disconnection, etc.) (S80: NO), an error job (S13
0) is executed.

In the special symbol main job (S90), a job relating to data necessary for the main controller 140 and the special symbol controller 160 to operate in cooperation is executed. In the normal symbol main job (S100),
The reading of the display pattern data of the normal symbol and the number of times the normal symbol has not been started is performed. In the voice job (S110), voice data corresponding to the game state is output.

Thereafter, the status of each flag is set in the backup memory (S140), and the award ball signal job (S15)
0), an information signal job (S160), a command job (S170), and a remaining time job (S180). In the prize ball signal job (S150), data related to prize ball payout is read and output, and in the information signal job (S160), data necessary for information output to another control unit is read. Further, in the command job (S170), a command for special symbol management is output, and in the remaining time job (S180), non-constant random numbers are called and a general-purpose random number memory is updated.

Next, with reference to FIG. 6, a success / failure determination job at the time of a start winning (winning to the first type starting port (ordinary electric accessory) 17) executed in a series of the main job will be described. Will be explained. The various memories used for these jobs are stored in the RAM 481 of the main control unit 140 shown in FIG.
FIG. 7 shows typical ones (481a to 481m).

First, in S200, it is checked whether or not there is a winning start. If YES, the reserved number (unstarted number) stored in the special symbol reserved number memory 481b (see FIG. 7) is incremented by one in S210. I do. If the number of suspensions (the number of unstarted times) exceeds a certain value ("4" in this embodiment), the winning start is invalidated,
Skip to S250. If the number of reservations is within a certain value (the number of unstarted times), in S230, a special symbol success / failure determination random number (hereinafter, also referred to as a success / failure random number or a determination random number).
(Either by generating a program or by using a predetermined random number generating circuit (a random number generating means for pass / fail)), and in S240,
It is stored in a special symbol hit / fail judgment random number memory 481a (see FIG. 7; hereinafter also referred to as a judgment random number memory). This memory stores the read determination random value in a shift memory format in a time series of the start winning.

Next, in step S250, the oldest first judgment random value stored in the judgment random number memory 481a (see FIG. 7) is read. Then, in S260, the big hit number (hit judgment value) is read from the big hit number memory 481g (see FIG. 7), and in S270, the big hit number is compared with the above judgment random value. If they do not match, it is determined to be off. In the case of a jackpot determination, the process proceeds to S280, in which a jackpot symbol determining random number (random number for identification information determination) is generated, read, and the determined random number value is stored in the jackpot symbol determining random number memory 481.
c (see FIG. 7) (S290). The big hit symbol determination random number is read at the same time as the winning random number at the time of the start winning, but may be read at the same time as the hit determination or after a predetermined time after the hit determination. In S300, the judgment result of "big hit"("1" in this embodiment) is stored in the judgment result memory 48.
1i (see FIG. 7). A reach mode determining random number is generated at the same time as the jackpot symbol determining random number, and is read and the determined random number value is stored in the reach mode determining random number memory 48.
1j (see FIG. 7) (S295).

The special symbol specified by the big hit symbol determining random number is stored in the ROM 163 (FIG. 4) of the special symbol control unit 160.
(See FIG. 2) based on the special symbol image data stored in the liquid crystal display panel 27 (see FIG. 2).
An arrangement of three digits of the same symbol "7, 7, 7"). The special symbol image data is associated with the jackpot symbol determining random number value and is used as a value for identification information determination by the RAM 4 of the main control unit 140.
81 (see FIG. 10), and the symbol to be stopped and displayed may be determined by comparing the read big hit symbol determination random number value with the identification information determination value.

Further, the reach display mode specified by the reach mode determination random value is stored in the ROM 1 of the special symbol control section 160.
Based on the reach display mode image data stored in 63 (see FIG. 4), the image is displayed in a predetermined reach mode on the liquid crystal display panel 27 (see FIG. 2) after a variable display state.
In this case as well, the reach display mode image data is associated with the reach mode determination random number value and used as a reach mode determination value, and the reach mode determination value memory 481k (see FIG. 10) of the RAM 481 of the main control unit 140 (see FIG. 10). 7), and the reach mode to be displayed may be determined by comparing the read reach mode determination random value with the reach mode determination value.

On the other hand, if it is determined that there is a deviation, S270
Then, the process proceeds to S310, and it is determined by a random number whether to perform the off-reach job. That is, in S310,
A reach mode determination random number is generated and read, and in S320, the reach number stored in the reach number memory 481h (see FIG. 7) is read in S320. S3
At 30, if both match, the job is a missed reach job, and if they do not match, the job is a normal missed job.

In the case of a missed reach job, the process proceeds to S340, and at least two special symbols (for example, 3
Among the special symbols of the type, the left symbol and the right symbol are determined using the outreach-reach symbol determining random number (or the random symbol of the left symbol may be referred to and the right symbol may be made to match) ( S340), miss reach symbol number memory 481l
(See FIG. 7) (S350). Also, S360
In the same manner, the symbol during the departure is similarly determined by random numbers,
The random number value determined in step 70 is out of the random symbol number memory 4.
81f (see FIG. 7). Further, in S380, the determination result of “out-of-reach” (“2” in the present embodiment) is stored in the determination result memory 481i (see FIG. 7). On the other hand, in the case of a non-normal job, the process proceeds to S390, and each special symbol (for example, a left symbol, a right symbol, and a middle symbol) is used.
Are determined by random numbers, and the determined random number values are respectively assigned to corresponding out-of-design symbol numbers memories 481d, 481e,
481f (S390-S440). Also, S
At 450, the determination result of “normal departure” (“3” in this embodiment) is stored in the determination result memory 481i (see FIG. 7).
To memorize.

Next, the general flow of the special symbol main job, which is executed in the sequence of the main job, will be described with reference to FIG. First, in S500, based on a prize of a game ball to the first-type starting port (ordinary electric accessory) 17, a variation display of each special symbol is displayed on the liquid crystal display panel 27 (see FIG. 2) of the special symbol display device 16. Let it start. For example, the left and right and middle symbols are scrolled from top to bottom and from bottom to top.

Next, in S510, the judgment result for each winning obtained in the success / failure judgment job shown in FIG. 6 is read from the judgment result memory 481i (see FIG. 7). Specifically, in the case of the jackpot determination ("1"), (S520: YE
S), the process proceeds to S580, and the reach mode determination value stored in the reach mode determination value memory 481k corresponding to the reach mode determination random number described above is read out, and further S60.
The process proceeds to 0, and the big hit number (identification information determining value) is read from the big hit number memory (determination value storage means) 481g (see FIG. 7). After passing through the predetermined reach display mode, the middle symbol is aligned with the left symbol and the right symbol in the same symbol, stopped and displayed, and fixed.

On the other hand, in the case of the out-of-reach reach determination ("2") (S530: YES), the flow proceeds to S570, in which the out-reach-reach symbol number and the out-of-out-reach symbol number from the out-reach reach symbol number memory 481l (see FIG. 7). The memory 481f (FIG. 7)
Read out the reference symbol number. And S5
At 71, the read-out reach symbol number and the read-out middle symbol number are compared, and a miss-reach mode is determined based on the difference between them (S572). Specifically, in S571, a difference between those numbers (that is, for example, a difference between the left symbol and the middle symbol) is calculated, and the outreach mode data is read from the outreach mode memory 481m based on the difference. For example, when the difference is “−1” (that is, for example, when the middle symbol is the symbol immediately preceding the left symbol), one type is selected from a plurality of types (for example, three types) of out-of-reach super reach ( For example, it can be selected by obtaining a predetermined random number), and is read. After that, for example, after the left symbol and the right symbol are aligned with the same symbol and a predetermined reach display mode is passed, the middle symbol is stopped and displayed with a symbol different from other symbols, and fixed.

In the case of the normal miss determination ("3") (S540), the process proceeds to S550, and each of the miss symbol numbers is stored in the miss number memory 481d, 481e, 481f (see FIG. 7).
, And proceeds to S560, where the special symbols (for example, the left symbol, the right symbol, and the middle symbol) are stopped and displayed at timings shifted from each other and fixed. In the case of the normal deviation determination, the display mode can be changed to various modes by “slip display” or the like. In this case, the display mode image data is normally deviated in association with the reach mode determination random value. As a display mode determination value, the main control unit 140
Normally, the random number value stored in the RAM 481 (see FIG. 10) is stored in a value memory (not shown) for determining the out-of-normal display mode, and the read reach mode determining random number value is compared with the out-of-normal-display mode determining value. The departure mode may be determined.

Next, the big hit is judged and the liquid crystal display panel 27
(See FIG. 2), a special symbol is fixedly displayed in a predetermined arrangement mode (for example, an arrangement mode of the same three-digit symbol of "7, 7, 7"), and then a special game is executed (special game state). Or big hit game state). In the special game state, first, the opening and closing plate 312 of the special winning device 31 (see FIG. 2) is in an open state, and the winning of the game ball to the special winning opening 311 is a game ball receiving state in which the player is superior.

In this special game state, the special winning device 31 continues the game ball receiving state until the end condition is satisfied. For example, the open state is maintained for a predetermined time t1 (for example, 30).
Seconds), or the winning ball detection switch 318
When a predetermined number n1 (for example, 10) winnings are detected in (see FIG. 4), the end condition is satisfied, the game ball receiving state is temporarily ended, the open / close plate 312 is closed, and one round is performed. finish. After a predetermined time t2 (for example, 0.5 seconds) elapses after the opening and closing plate 312 is closed, if a predetermined continuation condition (passing to a specific area (not shown)) is satisfied,
The opening and closing plate 312 is again in the open state, and the special winning device 31 is in the game ball receiving state. Note that such a game ball receiving state in which the end condition is set to one round is repeatedly continued up to a predetermined maximum continuous round number (16 rounds in this embodiment). If the continuation condition is not satisfied when the end condition is satisfied, the special game state ends (so-called puncture) in the round.

In the pachinko machine 1, the liquid crystal display panel 27 of the special symbol display device 16 (see FIG.
Probability changing means for changing (improving) the probability (big hit probability) of the success / failure determination until the next big hit after the end of the special game state based on the type of the special symbol stopped and displayed in (see). Specifically, the jackpot symbol determining random number value stored in advance is composed of a random number value for probability change and a random number value for non-probability change. The change symbol is stopped and displayed. If the symbol stopped and displayed is the symbol for changing the probability, the probability of the success / failure judgment (big hit probability) is improved to about four to five times the normal hit after the end of the special game state until the next big hit.

Hereinafter, the configuration of the main control unit 140 will be described. As shown in FIG. 4, the main control unit 140 includes a main control board 340, and the main control board 340 includes a main circuit unit 4 including a CPU 401 as shown in FIG.
00 and an input / output circuit section 500 are formed. Hereinafter, the main circuit unit 400 and the input / output circuit unit 500 will be described in order.

First, as shown in FIG. 9, the main circuit section 400 includes a CPU 401, an oscillation section 1410, and a reset circuit section 1.
450, an I / O decode circuit section 1420, a data bus stabilizing section 1411, and a first external input circuit section 1430. Hereinafter, the components of the main circuit unit 400 will be described.

As shown in FIG. 10, the CPU 401
PU core 1480, built-in RAM 1481, built-in ROM 1
482, memory control circuit 1483, clock generator 14
84, address decoder 1485, watchdog timer 1486, counter / timer 1487, parallel input / output port 1488, reset / interrupt controller 1
489, an external bus interface 1490, and an output control circuit 1491. The oscillation unit 1410 includes a crystal oscillation module 1404 as shown in FIG.

As shown in FIG. 11, the reset circuit section 1450 includes an initialization reset signal generation section (power-on initialization signal generation section) 1412 and a user reset signal generation section (stationary control initialization signal generation section). 1413. The initialization reset signal generation unit 1412 includes a general-purpose initialization reset signal generation unit (general-purpose initialization signal generation unit) 141.
8 and a CPU initialization reset signal generation unit (CPU initialization signal generation unit) 1414. The general-purpose initialization reset signal generation unit 1418 of the initialization reset signal generation unit 1412 includes a power input connector 1445, a reset input protection resistor 1451, Schmitt trigger inverter ICs 1452 and 1454, a filter circuit 1453, and an NA.
It comprises an ND gate 1455, a NOR gate IC 1458, and counter ICs 1456 and 1457. Also, a CPU initialization reset signal generation unit 1414
Is configured to include a flip-flop IC 1467, a Schmitt trigger inverter IC 1459, a counter IC 1460, and a NOR gate IC 1461. Further, the user reset signal generation unit 1413 includes a flip-flop circuit unit 1462, a counter IC 1463, Schmitt trigger inverter ICs 1464 and 1466, and a counter IC 1465.

The I / O decode circuit section 1420 has the structure shown in FIG.
As shown in (1), a device selection signal generator 1415 and a gate signal generator 1416 are provided. The device selection signal generation unit 1415 includes a NOR gate IC 1422, decoder ICs 1423 and 1424, and a resistance array 1421, 1
428. In addition, the gate signal generation unit 1416
NOR gate IC 1425, NAND gate IC 142
6, flip-flop IC 1427, resistor array 142
9 and a Schmitt trigger inverter IC 1405. Further, the data bus stabilizing unit 1411 has a resistor array 1403 and a buffer IC 1402.

As shown in FIG. 13, the first external input circuit section 1430 has an input connector section 1440, a switch driver 1432, a signal matching section 1433, a standardized signal stabilizing section 1434, and a resistor array 1431. The input connector portion 1440 includes a frame connector 1441 and a first special symbol start switch connector 1 which is a game board connector.
442, second special symbol start switch connector 1443
And a normal symbol start switch connector 1444. The standardized signal stabilizing unit 1434 includes a plurality of resistors, and the signal matching unit 1433 includes a plurality of resistors and a capacitor.

Next, the CPU 401 of the main circuit section 400, the oscillating section 1410, and the respective circuit sections 1411, 1420, 143
The functions such as 0, 1450 will be described. Each terminal of the CPU 401 shown in FIGS. 11 to 13 is classified as follows. (1) Address section A0 to A15: 16-bit address bus output terminals. (2) Data section D0 to D7: 8-bit bidirectional data bus terminals. (3) System control unit XM1: An output terminal for a signal indicating machine cycle 1. XMREQ: output terminal of a request signal to the memory space. XIORQ: an output terminal for an input / output request signal to the I / O space. XWR: an output terminal for a signal indicating that the data bus is in a write cycle. XRD: an output terminal for a signal indicating that the data bus is in a read cycle. XRFSH: refresh signal output terminal. (4) CPU control unit XHALT: Halt signal output terminal. XINT: Input terminal of a maskable interrupt request signal. XNMI: an input terminal for a non-maskable interrupt request signal. XSRST: Input terminal for system reset signal. XSRTO: output terminal for system reset signal. XURST: User reset signal input terminal. IEO / SCLKO: A shared output terminal for daisy chain signals and divided clocks. PRG: Input terminal for setting the CPU to PROM mode. MODE: an output terminal indicating the state of the operation mode of the CPU. (5) I / O section CLK / TRG2 / CLK / TRG3: external clock /
Input terminal for timer trigger signal. ZC / TO0 / ZC / TO1: Output terminal for built-in CTC signal. PA0 to PA7: 8-bit parallel I / O terminals. PB0 / XCSIO0 to PB3 / XCSIO3: 4-bit parallel I / O port, dual-purpose terminal for chip select of an external device. (6) Clock section EXTAL1 and EXTAL2: crystal oscillator connection terminals. CLKO: Output terminal of the system clock signal. EXTA
A 50% duty square wave obtained by dividing the input signal frequency of the L1 / EXTAL2 terminal by 1/2 is output. (7) Power supply section VDD1 / 2: Power supply (+ 5V) terminal. VSS1,2: Power supply (GND) terminals. VBB: Backup terminal of built-in RAM 1481. (8) Others NC: Non-connection terminal.

The CPU 401 has a built-in R shown in FIG.
The built-in RAM 1481 is used as a work area based on the program written in the OM 1482. Further, when the power is cut off, the CPU 401
It has a RAM backup function for holding the contents of 1481 by the voltage holding unit connected to the VBB terminal, and a fraud prevention function such as a program authentication function and a program execution prohibition function outside the designated area. What is the program authentication function?
When an initialization signal for initializing the CPU 401 is input when the power is turned on, it is checked whether the authentication code calculated based on the program is correct. If the authentication code is not correct, execution of the program is stopped. Function. The program execution prohibition function outside the designated area is a function for prohibiting execution of a program outside a predetermined address range.

In the CPU 401, an interruption reset is performed at a constant cycle to prevent runaway. Causes of runaway include excessive noise penetration and the like. Also,
In the CPU 401 of this embodiment, the I / O mapped I
The decoding of the / O system is performed, the XIORQ terminal is used, and the XMREQ terminal is not used. However, the memory mapped I / O method is adopted for decoding, and XMRE
It is also possible to use the Q terminal.

The crystal oscillation module 1404 of the oscillation section 1410 shown in FIG. 11 outputs an operation clock signal of the CPU 401. This operation clock signal is supplied to the CPU 40
1 EXTAL1 terminal. Note that a crystal oscillator is used in place of the crystal oscillation module 1404, and this crystal oscillator is connected between the EXTAL1 and EXTAL2 terminals and the CPU
It is also possible to generate an oscillation clock by the clock generator 1484 (see FIG. 10) at 401. However, in this embodiment, a crystal oscillation module 1404 is used and
Since it is connected to the EXTAL1 terminal 401, there is no need to match the crystal oscillator with the clock generation circuit.

In the reset circuit unit 1450 shown in FIG. 11, a general-purpose initialization reset signal generation unit 1418 generates a general-purpose initialization reset signal, and a user reset signal generation unit 1413 generates a user reset signal.

General-purpose initialization reset signal generator 1418
Generates a general-purpose initialization reset signal based on a system reset signal (hereinafter, also referred to as a power-on reset signal) externally input via a power input connector 1445.
It is output to the PU initialization reset signal generation unit 1414 and the input / output circuit unit 500 (see FIG. 9). The CPU initialization reset signal generation unit 1414 outputs a CPU initialization reset signal to the XSRST terminal of the CPU 401 based on a system reset signal input from outside via the external input connector 1445. The CPU initialization reset signal is a pulse signal that maintains the H level for a certain period of time when the power supply of the CPU 401 is stabilized, and then temporarily changes to the L level and then further changes to the H level. This C
By generating the PU initialization reset signal, the CPU
At 401, the initialization at power-on is reliably performed without being affected by the power signal.

The user reset signal generation unit 1413
A user reset signal is output to the XURST terminal of the CPU 401 based on the output signal of the XM1 terminal of the CPU 401 and the system reset signal. That is, the user reset signal generation unit 1413 performs a counting operation based on the output signal of the XM1 terminal of the CPU 401 being at the L level, and supplies the CPU 401 with a user reset signal that is a pulse signal of a fixed cycle.

The I / O decode circuit 142 shown in FIG.
0 decodes an address signal from the CPU 401, and outputs a device selection signal (CS0 to CS6) and a gate signal (G).
Are output to the input / output circuit unit 500 (see FIG. 9). The device selection signals (CS0 to CS6) are signals for selecting an external device, and the gate signal (G) is a signal for validating the device selection signal (CS6). The device selection signals (CS0 to CS6) include an output device selection signal (CS0 to CS5) and an input device selection signal (CS
6).

Output device selection signals (CS0 to CS
5) is a case where the CPU 401 is in a state of writing data to the input / output circuit unit 500 (see FIG. 9), and
The range address of the 0 / XCSIO0 terminal is specified and A0
When a predetermined address signal is output from the terminals A4 to A4, the signal is output from the decoder IC 1423 to the flip-flop ICs 1511 to 1561. That is, CP
When the data of the D0 to D7 terminals of U401 is output to the input / output circuit unit 500 (see FIG. 9) via the data bus, an output device selection signal (CS0 to CS5) is output to the output port 1390 (described later) shown in FIG. The data is input to the 1D to 8D terminals of the flip-flop ICs 1511 to 1561. Note that the address signal is output by the I / O decode circuit unit 1420 to a device selection signal for output (CS
0 to CS5), which is output port 1390
(See FIG. 18) and input to the clock terminal of the corresponding flip-flop IC.

The input device selection signal (CS6) is A
When there is an output of a predetermined address signal from the 0 to A4 terminals and an output from the PB1 / XCSIO1 terminal, the decoder IC 1424 sends the buffer IC 1571
(See FIG. 17). Further, in the gate signal generation unit 1416, a gate signal (G) is generated based on the oscillation clock output from the crystal oscillation module 1404 and the output signals of the XRD and XIORQ terminals of the CPU 401, which are also output to the buffer IC 1571. Is done. That is, when the input device selection signal (CS6) and the gate signal (G) are output to the buffer IC 1571 (see FIG. 17), the buffer IC 1571 (see FIG.
7) are input to the D0 to D7 terminals of the CPU 401 via the data bus. The address signal is decoded by the I / O decode circuit 1420 into an input device selection signal (CS6), which is input to the G1 terminal of the buffer IC 1571 (see FIG. 17).

In this embodiment, as shown in FIG. 12, the impedance at the input terminal side is reduced by the resistor arrays 1421, 1428, and 1429, and the output selection signal and the input selection signal generated by the device selection signal generator are respectively provided. In addition, the influence of external noise and the like on the gate signal generated by the gate signal generation unit 1416 is suppressed. In this embodiment, the data buses (OD, D) are divided into two paths. This is due to the load capacitance between the CPU 401 and the flip-flop ICs 1511 to 1561 shown in FIG. 18, and may be a circuit configuration that does not need to be divided into two paths.

Data bus stabilizing section 1411 shown in FIG.
Stabilizes a signal on a data bus connecting the CPU 401 and the input / output circuit unit 500 (see FIG. 3). Resistance array 14
03 reduces the noise entering the bus by reducing the impedance, and the buffer 1402 uses the command output circuit units 1510 to 1540 for the prize ball, the lamp, the display, and the voice in the data bus divided into two paths (see FIG. 3). ) Are amplified from the bus (OD) output signals (OD0 to OD7).

Here, in the first external input circuit section 1430 shown in FIG. 13, the signals of the ball detection switches requested from the CPU 401 are transmitted to the CPU 401. That is, various switch groups are connected to the first external input circuit section 1430 via the input connector section 1440, and C
When the PU 401 reads the switch state, the state of each switch is sent to the CPU 401 from the O1 to O5 terminals and the VO terminal of the switch driver 1432. In this embodiment, the six output terminals (O) of the switch driver 1432 are adjusted according to the number of ball detection switches associated therewith.
1 to O5 terminals and VO terminals). These 6
One terminal corresponds to each of the six ports (PA0 to PA5) assigned by the CPU 401. Further, in this embodiment, PA0 to PA
The impedance of the five terminals is reduced, and the influence of external noise and the like is suppressed.

In FIG. 13, the signal from the input connector section 1440 is subjected to noise removal by a combination of the standardized signal stabilizing section 1434 or the signal matching section 1433 and the internal circuit of the switch driver 1432. Further, in the signal matching section 1433, voltage adjustment is also performed. This is based on the fact that some of the switches connected to the input connector unit 1440 have a branching destination, and that a detection signal is sent to other than the main control board 340. That is, since the load of the circuit system related to the switch is larger than that of the other switches, the characteristics of the signal are different from those of the other switches. Therefore, the signal matching unit 143 is placed on the corresponding signal line.
3 is provided to achieve matching with other signals. The output signal of the signal matching unit 1433 is connected to the switch driver 143.
2 is input to the V1 terminal.

Next, the input / output circuit section 500 will be described. As shown in FIG. 9, the input / output circuit section 500 includes a prize ball command output circuit section 1510, a lamp command output circuit section 1520, a display command output circuit section 1530, a voice command output circuit section 1540, and a solenoid drive circuit section 15.
50, LED drive / information output circuit 1560, and second
An external input circuit 1570 is provided.

Of the above-described circuit units 1510 to 1570, the award ball command output circuit unit 1510, the lamp command output circuit unit 1520, and the display command output circuit unit 153
0, the voice command output circuit 1540 has the same circuit configuration. Therefore, in this embodiment, in order to avoid the drawing from being redundant, only the prize ball command output circuit unit 1510 is shown (FIG. 14), and the other circuit units 1
As for 520, 1530, and 1540, only reference numerals are shown in parentheses in FIG. 14 and illustration thereof is omitted. That is, each of the output circuit units 1510, 1520, 1530, 1
540 are flip-flop ICs 1511 and 152, respectively.
1, 1531, 1541 and the buffer IC 1512, 1
522, 1532, 1542, strobe signal line buffer ICs 1513, 1523, 1533, 1543, and connectors 1514, 1524, 1534, 1544.

Next, a solenoid driving circuit 1550 shown in FIG. 15 includes a flip-flop IC 1551, three lamp solenoid drivers 1552 to 1554, and a free terminal connected in parallel to the drain terminal of the lamp solenoid driver. Wheel diode 1
555 and an output connector 1556.

The LED driving / information output circuit 1560 shown in FIG. 16 includes a flip-flop IC 1561, a transistor array 1562, a lamp solenoid driver 15
63, a power relay unit 1565, a power adjusting unit 1564, an output connector 1556, and an information output connector 1566, and the flip-flop IC 1551 also plays a part of the configuration. The relay 1565 has two relays 1567, 1
568 are provided, and the power adjustment unit 1564 is provided with ten resistors R4 to R13.

Second external input circuit 1570 shown in FIG.
Are the buffer IC 1571 and the switch driver 157
2. It has a resistance array 1573, a power adjustment unit 1574, and an output connector 1556. The power adjustment unit 1574 includes six resistors R21 to R26.

As shown in FIG. 18, the prize ball command output circuit 1510 and the lamp command output circuit 1
520, display command output circuit 1530, voice command output circuit 1540, solenoid drive circuit 1550
And the flip-flop ICs 1511, 1521, 1531, 1541, of the LED drive / information output circuit 1560.
1551 and 1561 correspond to the output port circuit unit 1390 6.
One output port.

Next, the function of each of the circuit sections 1510 to 1570 of the input / output circuit section 500 will be described. The output port circuit unit 1390 shown in FIG. 18 receives data (OD, D), device selection signals (CS0 to CS5), and a clear signal (CLR) from the main circuit unit 400. An external device is assigned to each port of the output port circuit unit 1390. Examples of the external device include a prize ball device, a lamp device, a display device, a sound device, a solenoid device, an LED device, and a hall computer.

The data (OD) is a flip-flop IC
The data (D) is input to the 1D to 8D terminals of 1511 to 1541, and the data (D) is input to the flip-flop ICs 1551 and 1561.
Are input to the 1D to 8D terminals. Device selection signal (C
S0 to CS5) correspond to the corresponding flip-flop IC15.
Input to the Clock terminals 11 to 1561. In the flip-flop ICs 1511 to 1561 selected by the device selection signals (CS0 to CS5), the data (OD, D) from the main circuit unit 400 is input to the 1D to 8D terminals, and the data of the device selection signals (CS0 to CS5) is output. At the rising edge timing, data is output from the 1Q to 8Q terminals. The output port circuit unit 1390
When the pachinko machine 1 is powered on, the flip-flop ICs 1511 and 1515
21, 1531, 1541, 1551, and 1561 are initialized.

Various command output circuit units 1 shown in FIG.
Reference numerals 510 to 1540 denote prize ball devices which are external devices at the subsequent stage,
The command data is transmitted to the lamp device, the display device, and the audio device. That is, the device selection signals (CS0 to CS3)
Command output circuits 1510 to 1540
Is selected. Then, the flip-flop IC 1511
Command data output from the first through the second output terminals 151-1542 are input to the A1-A8 terminals of the buffer ICs 1512-1542,
Output to connectors 1514 to 1544. The output enable terminals G1 and G2 of the buffer ICs 1512 to 1542 are grounded.
From 12 to 1542, a signal whose drive capability is enhanced is output. Note that various command output circuit units 1510
The control signals handled by 1540 are a total of 9 bits of 8 bits of data and 1 bit of strobe, but the number of data bits may be changed depending on the connected external device.

The solenoid drive circuit 155 shown in FIG.
Numeral 0 is a circuit section which is selected by the device selection signal (CS4) and drives a solenoid device which is an external device in accordance with a game state. In the solenoid drive circuit unit 1550, ramp / solenoid drivers 1552 to 155
4 are provided corresponding to each solenoid. And
The flip-flop ICs 1551 are connected to the corresponding lamp / solenoid drivers 1552 to 155 from the 5Q to 7Q terminals.
4 is output. Further, the flip-flop IC1
551 to lamp / solenoid driver 1552-15
When the input signal to the IN terminal 54 is at the H level, the lamp / solenoid drivers 1552 to 1554 drive the solenoid devices. Also, the flip-flop IC 155
1 is a command output circuit unit 1510 as shown in FIG.
It also functions as a strobe signal generation unit for transmitting a strobe signal to ４０1540. That is, the flip-flop IC 1551 uses the output signals from the 1Q to 4Q terminals as the strobe signal, and
10 to 1540 strobe signal buffer ICs 1513
To 1543.

Returning to FIG. 15, the solenoid drive circuit 155
The freewheeling diode 1555 of 0 returns the continuous current when the output signals of the lamp solenoid drivers 1552 to 1554 are switched from the H level to the L level by maintaining the load current during the high-speed switching operation. The lamp / solenoid driver 15
Instead of 52 to 1554, for example, a transistor, F
It is also possible to drive the solenoid using ET.

The LED drive / information output circuit 1560 shown in FIG. 16 is usually used for driving a design LED and outputting external information to a hall computer or the like. Flip-flop IC 1561 of LED drive / information output circuit 1560
Is output from the transistor array 1562.
Are input to the I1 to I8 terminals. Transistor array 1
In 562, two bits are normally allocated to the symbol LED, six bits are allocated to the external information output, and the outputs of the O1 to O7 terminals are output to the output connector 1556. The output of the O8 terminal is output to the relay 1565.
Is sent to the information output connector 1566 via the relay 1568. The output signal of the transistor array 1562 is current-controlled by the resistors R4 to R13 of the protection resistor 1564.

The second external input circuit 1570 shown in FIG.
Is a circuit unit for inputting the state of various switches to the CPU 401, and the number of signal lines of the data bus (D) to be used corresponds to the number of connected switches. The detection signal from the output connector 1556 is input to the I1 to I6 terminals of the switch driver 1572 via the power adjustment unit 1574. In the power adjusting unit 1574, the resistors R21 to R21
26 and the internal circuit of the switch driver 1572 perform noise removal and voltage adjustment. Output signals from the O1 to O6 terminals of the switch driver 1572 are input to the buffer IC 1571. Further, the switch driver 1572 has a short-circuit detection function, and I1, I2
When the switch connected to the terminal is short-circuited, the output signal changes from H level to L level. Further, the resistor array 1573 is connected to the A of the buffer IC 1571.
The effects of external noise and the like are suppressed by lowering the impedance of the 1 to A8 terminals.

The gate signal (G) from the main circuit section 400 is input to the G2 terminal of the buffer IC 1571, and the buffer IC 1571 amplifies the signal from the switch driver 1572 and outputs it to the data bus (D).

In the pachinko machine 1 of this embodiment, when the power of the pachinko machine 1 is turned on, the power supplied from the outside to the pachinko machine 1 rises, and as will be described later, the sub-control board 3
After supplying power to the sub-control board 36
When there is an operation occurrence signal indicating the start of operation from 0 to 380, a system reset signal (power-on reset signal) is supplied to the main control board 340. Then, when the CPU initialization reset signal as described above is supplied to the CPU 401, the CPU 401 is initialized by the CPU initialization reset signal at L level after the externally supplied power rises. After that, the CPU initialization reset signal once rises, then falls, and returns to the L level. Therefore, the CPU 401 receives the initialization signal again. Then, the CPU initialization reset signal indicates the H level again, and the control of the pachinko machine 1 shifts to a steady state. In other words, according to the pachinko machine 1, since the CPU initialization reset signal is provided with a plurality of variations, the CPU 401 is more reliably and stably compared to a case where only a single variation is provided. Can be initialized, and the operation of the gaming machine can be stabilized. The reason for obtaining such a result is as follows. That is, when the power of the pachinko machine 1 is cut off, the electric charge stored in the capacitor constituting the noise filter or the like in the internal circuit of the CPU 401 remains. As a result, a signal exceeding the threshold is generated partially early, and when the power supply potential rises and when the CPU 401 is initialized,
The influence of the fact that the initialization signal to the CPU 401 indicates the same level and the like also causes an imbalance in the rise, and the stability of the control is impaired. However, as in the case of the pachinko machine 1 of the present embodiment, by providing a plurality of variations to the CPU initialization reset signal, a variation of the additional compensation is included, and it is solved by providing only a single variation. It is possible to eliminate the remaining defective element that could not be achieved.

The CPU initialization reset signal generator 1414 can be provided inside the CPU 401. By doing so, the external circuit of the CPU 401 can be simplified, and the size of the main control board 340 can be reduced. In addition, it is possible to simplify the rear configuration of the pachinko machine 1 and to increase the degree of freedom in the layout design of the gutter through which the game balls flow. Further, in this embodiment,
Although the first variation of the CPU reset signal is a rising edge and the second variation is a falling edge of the same signal, one or both of the variations include a rising edge and a falling edge. It is also possible to consider such fixed waveform patterns and combine them. In this case, the number of times of rising and falling is not limited to one, and one or a plurality of selections can be appropriately performed. For example, the CPU in the present embodiment
The fall of the initialization signal for power supply after the power is turned on and the rise thereafter can be regarded as a second variation.

Next, the configuration of the frame control unit 150 will be described. As shown in FIG. 4, the frame control unit 150 includes a frame control board 350, and the frame control board 350 includes:
As shown in FIG. 19, the same CP as that of the main control board 340 is used.
Main circuit section 600 including U601, input / output circuit section 700
Are formed. Hereinafter, the main circuit unit 600 and the input / output circuit unit 700 of the frame control unit 150 will be described in order.

First, as shown in FIG. 19, the main circuit section 600 has a CPU 601, an oscillation section 1610, a reset circuit section 1650, and an I / O decode circuit section 1620. The components of the main circuit section 600 will be described below.

The CPU 601 has the same configuration as the CPU 401 of the main control unit 140 shown in FIG. 10, and includes a CPU core 1680, a built-in RAM 1681, and a built-in ROM 168.
2, memory control circuit 1683, clock generator 168
4. Address decoder 1685, watchdog timer 1686, counter / timer 1687, parallel input / output port 1688, reset / interrupt controller 168
9 (see FIG. 10). Also, the oscillation unit 1610
Includes a crystal oscillation module 1604 similar to the main control unit 140 as shown in FIG. 20 (see FIG. 11).

As shown in FIG. 21, the reset circuit section 1650 includes a power interruption signal input circuit section 1613 and an initialization reset signal generation section (power-on initialization signal generation section) 161.
2 is provided. Initialization reset signal generator 1612
Are reset input protection resistor 1651, Schmitt trigger inverter ICs 1652, 1654, 1655, filter circuit 1653, Schmitt trigger NAND gate IC
1656 and counter ICs 1657 and 1658. The power interruption signal input circuit 1613
Comprises an input protection resistor 1661, Schmitt trigger inverter ICs 1662 and 1664, and a filter circuit 1663.

The I / O decode circuit section 1620 has the structure shown in FIG.
As shown in (1), a device selection signal generator 1615 and a gate signal generator 1616 are provided. The device selection signal generation unit 1615 includes the NOR gate ICs 1605 and 162
2, 1628, decoder ICs 1623 and 1624, and a resistor array 1621. Further, the gate signal generation unit 1616 is provided with the Schmitt trigger inverter IC 16.
25, OR gate IC 1626, flip-flop IC
1627 and a resistance array 1629. Note that a resistor array 1603 is provided between the CPU 601 and the input / output circuit unit 700, and the resistor array 1603 is provided.
03 reduces the noise entering the bus by reducing the impedance.

Next, the functions of the CPU 601 of the main circuit section 600, the oscillating section 1610, the I / O decode circuit section 1620, the reset circuit section 1650, and the like will be described. C shown in FIG.
Each terminal of the PU 601 is connected to the CPU 401 of the main control unit 140.
Therefore, the description is omitted. The CPU 601 uses the built-in RAM 1681 (see FIG. 10) as a work area based on a program written in the built-in ROM 1682 (see FIG. 10). Further, the CPU 601
When the power is turned off, the contents of the built-in RAM
It has a RAM backup function that is held by a voltage holding unit connected to the B terminal. The voltage holding unit is configured by a backup circuit 769 (see FIG. 34) including an electric double layer capacitor and the like provided in the power supply unit 420 shown in FIG. It is also possible to provide a backup terminal and connect a power storage means composed of a capacitor or the like connected to DC 5 V. In this case, the power storage means can include a capacitor and a charging circuit for charging the capacitor and preventing backflow.

The crystal oscillation module 1604 of the oscillation section 1610 shown in FIG. 20 outputs an operation clock signal of the CPU 601. This operation clock signal is transmitted to the CPU 60
1 EXTAL1 terminal. Note that a crystal oscillator is used instead of the crystal oscillation module 1604, and this crystal oscillator is connected between the EXTAL 1 and 2 terminals, and
It is also possible to generate an oscillation clock by the clock generator 1684 of FIG. However, in this embodiment, the crystal oscillation module 1604 is used and
Since it is connected to the EXTAL1 terminal 601, there is no need to match the crystal oscillator with the clock generation circuit.

In reset circuit section 1650 shown in FIG. 21, initialization reset signal generation section 1612 generates an initialization reset signal. The initialization reset signal generation unit 1612 controls the XS of the CPU 601 based on a system reset signal (hereinafter, also referred to as a power-on reset signal) input from outside via the power input connector 1645.
It outputs a CPU initialization reset signal to the RST terminal and a general-purpose initialization reset signal to the input / output circuit unit 700 (see FIG. 19). The initialization reset signal for CPU is
When the power supply of the CPU 601 is stabilized, H
This is a pulse signal that maintains the level, then temporarily goes low and then further changes to the high level. By generating the CPU initialization reset signal, the CPU 601 is reset.
In, the initialization at the time of turning on the power is reliably performed without being affected by the power signal.

I / O decode circuit section 162 shown in FIG.
0 decodes an address signal from the CPU 601 and outputs device selection signals (WR0, WR1, RD0, RD1) to the input / output circuit unit 700 (see FIG. 19). The device selection signals (WR0, WR1, RD0, RD1) are signals for selecting an external device, and include an output device selection signal (WR0, WR1) and an input device selection signal (RD).
0, RD1).

Output device selection signals (WR0, WR
1) is a case where the CPU 601 is in a state of writing data to the input / output circuit unit 700 (see FIG. 19), and
The range address of the 0 / XCSIO0 terminal is specified and A0
When a predetermined address signal is output from the terminals A4 to A4, the signal is output from the decoder IC 1623 to the flip-flop ICs 1602c and 1602d (see FIGS. 23 and 24). That is, the data of the D0 to D7 terminals of the CPU 601 is transferred to the input / output circuit unit 700 (FIG. 1) via the data bus.
9) is output to the flip-flop IC 1602 shown in FIG. 23 or FIG.
c, 1602d are input to the CK terminal, and data are input to the D1 to D8 terminals. The address signal is decoded by the I / O decode circuit 1620 into an output device selection signal, which is transmitted to the flip-flop ICs 1602c and 1602d shown in FIG. 23 or FIG.

Input device selection signals (RD0, RD
1) When the predetermined address signal is output from the A0 to A4 terminals and the output is output from the PB0 / XCSIO0 terminal, the decoder IC 1624 outputs the buffer IC.
1602a, buffer IC 160 with Schmitt trigger
2b (see FIG. 22). In the gate signal generation unit 1616, the oscillation clock output from the crystal oscillation module 1604 and the XR of the CPU 601 are output.
A gate signal is generated based on the output signals of the D terminal and the XIORQ terminal, and this is output to the decoder IC 1624. Based on the gate signal, the input device selection signals (RD0, RD1) are validated. That is, when the input device selection signals (RD0, RD1) and the gate signal are output to the decoder IC 1624, the buffer IC
Data of the O0 to O7 terminals of the CPU 1602a (see FIG. 22) and the data of the 1Y1 to 1Y4, 2Y1 to 2Y4 terminals of the buffer IC 1602b with the Schmitt trigger (see FIG. 22) are input to the D0 to D7 terminals of the CPU via the data bus. . The address signal is transmitted to the I / O decode circuit 162
At 0, it is decoded into an input device selection signal (RD0, RD1), which is input to the G2B terminal of the decode IC 1624.

In this embodiment, as shown in FIG. 20, the impedance at the input terminal side is reduced by the resistor arrays 1621 and 1629, and the output selection signal, the input selection signal,
The influence of external noise and the like on the gate signal generated by the gate signal generation unit 1616 is suppressed.

Next, the input / output circuit section 700 will be described. As shown in FIG. 19, the input / output circuit unit 700 includes a main board command data input circuit unit 1710, a prize ball motor sensor input circuit unit 1720, and a prize ball counting sensor input circuit unit 1.
730, memory clear switch input circuit 1740, motor output circuit 1750, ball lending counting sensor input circuit 1760, card unit input / output circuit 1770, ball lending information output circuit 1780, solenoid output circuit 17
90, a launch control signal output circuit section 1795.

The main board command data input circuit 1710 shown in FIG. 22 includes a buffer IC 1711, an input protection resistor 1712, pull-down resistors 1713a and 1713b, a Schmitt trigger inverter IC 1714, and an OR gate I
C1715 and an EMI filter 1716 are provided. The prize ball motor sensor input circuit 1720 includes the current limiting resistor 17
21, an input protection resistor 1722, a transistor 1723,
A capacitor 1724 is provided. The prize ball counting sensor input circuit 1730 includes a comparator IC 1731, comparator input voltage determining resistors 1732 and 1733, comparator reference voltage determining resistors 1734 and 1735, and a capacitor 1736. The memory clear switch input circuit 1740 includes an input protection resistor 1741, a transistor I
C1742. The ball lending counting sensor input circuit unit 1760 includes a comparator IC 1761, comparator input voltage determining resistors 1732 and 1733, comparator reference voltage determining resistors 1762 and 1763, and a capacitor 1
764. Note that each of the input circuits 1720 to 1720
40, 1760 and the buffer IC 1602b,
A pull-up resistor 1749 is provided.

Motor output circuit 1750 shown in FIG.
Are a driver IC 1751 for driving a stepping motor, a Schmitt trigger inverter IC 175
2. Schottky barrier diode 1753, capacitors 1754a and 1754b forming a noise filter,
And resistors 1754c and 1754d, resistors 1755a and 1755b for detecting an output setting current, a capacitor and a resistor group 1756 for setting an output OFF time at the time of output switching, and a resistor 17 for setting an input voltage.
57, a bypass capacitor 1758a, 1758b of the driver IC 1751, and a motor supply voltage stabilizing capacitor 1759.

The card unit input / output circuit 1770 shown in FIG. 24 includes photocouplers 1771a and 1771b, forward current limiting resistors 1772a and 1772b, capacitors 1773 and 1774 for stabilizing the power supply, and a minimum load compensating resistor 17.
75, transistor 1776, output current limiting resistor 177
7 is provided. The ball lending information output circuit unit 1780 includes a transistor 1781 and a photo MOS relay 1782. The solenoid output circuit 1790 is
A solenoid driver 1791 and a freewheel diode 1792 are provided. Launch control signal output circuit section 17
95 is an OR gate IC 1796, a filter circuit 179
7 is provided.

Next, the function of each of the circuit sections 1710 to 1795 of the input / output circuit section 700 will be described. In the main board command data input circuit unit 1710 shown in FIG. 22, the prize ball command data 0 to 7 output from the main control unit 140 are input via a connector.
The award ball command strobe signal output from 40 is input. The prize ball command strobe signal is subjected to noise removal by the EMI filter 1716, and is input to the OR gate IC 1715 via the pull-down resistor 1713b and the input protection resistor 1712. Further, the signal is inverted by the Schmitt trigger inverter IC 1714 and the CPU 60
1 (see FIG. 20), the interrupt control of the CPU 601 is performed, and award ball command data 0 to 7 is read. Note that the award ball command data 0 to 7 are sent to the buffer IC 1711 via the pull-down resistor 1713a and the input protection resistor 1712.
The signals are input to the terminals and further input to the D0 to D7 terminals of the CPU 601 via the buffer IC 1602a. In addition,
Output enable terminal O of buffer IC 1711
E1 and OE2 are grounded, and the buffer IC 1711
Outputs a signal with increased drive capability. The output enable terminals OE1 and OE2 of the buffer IC 1602a output a signal whose drive capability is enhanced based on the input of the device selection signal.

In the prize ball motor sensor input circuit section 1720, an input signal (detection signal) from the prize ball motor sensor (photo interrupter) is removed by a filter including an input protection resistor 1722 and a capacitor 1724. Then, the detection signal is output from the transistor 172.
When the signal is input to the base (B) terminal of the prize ball motor 3, a signal relating to the operating state of the prize ball motor is output to the buffer I based on the input.
It is input to the D0 to D7 terminals of the CPU 601 via C1602b.

In the prize ball counting sensor input circuit section 1730,
An input signal (detection signal) from the prize ball counting sensor (proximity switch) is used as a resistor 1 for adjusting a comparator input voltage.
732, 1733 and a capacitor 1736 for stabilizing the input voltage. On the other hand, the comparator reference voltage determining resistor 173
The reference signal is passed through the comparator IC 17
31 and the reference signal is compared with the detection signal by the comparator IC 1731. Based on the comparison result, a signal related to winning ball counting is output to the buffer IC 1602b.
Is input to the D0 to D7 terminals of the CPU 601 via the.

Memory clear switch input circuit 1740
When an input signal (detection signal) from the memory clear switch (tact switch) is input to the base (B) terminal of the transistor 1742 via the input protection resistor 1741, a memory clear signal is generated based on the input. The data is input to the D0 to D7 terminals of the CPU 601 via the buffer IC 1602b.

In the ball lending counting sensor input circuit unit 1760, similarly to the prize ball counting sensor input circuit unit 1730, an input signal (detection signal) from the ball lending counting sensor (proximity switch) is used as a resistor for adjusting a comparator input voltage. 17
62, 1763 and a capacitor 1764 for stabilizing the input voltage. On the other hand, the comparator reference voltage determining resistor 173
The reference signal is passed through the comparator IC 17
61, the reference signal and the detection signal are compared by the comparator IC1761, and based on the result, a signal relating to the ball lending count is output to the buffer IC1602.
The signal is input to the D0 to D7 terminals of the CPU 601 via b.

In the motor output circuit section 1750 shown in FIG. 23, when a signal (drive signal) for driving a stepping motor (prize ball motor) for paying out a prize ball is output from the CPU 601, the drive signal becomes , Driver IC 1751 via Schmitt trigger inverter IC 1752
Sent to. An operation signal corresponding to the operation mode of the stepping motor is output from the driver IC 1751 as an O.
It is output from the UT terminal to the prize ball motor via the output connector. In this case, a Schottky barrier diode 1753 is provided between the driver IC 1751 and the output connector to release the regenerative current from the prize ball motor.

In the driver IC 1751, EN
The operation signal is output from the OUT terminal based on the signals input to the ABLE terminal and the PHASE terminal.
For example, if the ENABLE terminal is “L (0)” and P
When the HASE terminal is “H (1)”, “H (1)” is output from the OUTA terminal, “L (0)” is output from the OUTB terminal, and the ENABLE terminal is “H (1)” and the PHA
When the SE terminal is “L (0)”, “L” is output from the OUTA terminal.
(0) ", and" H (1) "is output from the OUTB terminal.

In the card unit input / output circuit 1770 shown in FIG. 24, a READY signal, a ball lending request signal, and the like from the card unit are transmitted from the buffer IC 1602b shown in FIG. 22 via the forward current limiting resistor 1772a and the photocoupler 1771a. It is input to the CPU 601. Also,
The CPU 601 outputs a READY signal, a lending completion signal, and the like to the transistor 1776 and the forward current limiting resistor 1772.
b, photocoupler 1771b, output current limiting resistor 177
7 to the card unit.

In the ball lending information output circuit 1780, the CP
A signal relating to ball lending information output from U601 is passed through the transistor 1781 and further through a non-polar contact relay (photo MOS relay) as ball lending information to the outside of the gaming machine 1 (for example, a hall computer installed in a game arcade, etc.). (Not shown)).

In the solenoid output circuit 1790, the CP
The signal for driving the solenoid output from U601 is a lamp solenoid driver (power MOSFET) 17
The driver 1791 outputs the signal to a solenoid driving unit (not shown) via a freewheel diode 1792. The freewheel diode 1
Reference numeral 792 plays a role in releasing the back electromotive force generated from the solenoid when the output is turned off.

In the emission control signal output circuit 1795, C
The firing control signal output from PU 601 is output to firing device control board 201 (see FIG. 4) via OR gate IC 1796 and filter circuit 1797.

Next, the power supply path of the electronic control unit 130 of this embodiment will be described. FIG. 25 is an overall circuit diagram illustrating an example of a board connection layout including a power supply unit of the electronic control device 130. 26 to 31 are divided circuit diagrams showing details of FIG. 25. Electronic control unit 13
0 is the power cable 501 on the power receiving board 410.
To receive an AC voltage (AC 24 V). This AC voltage is applied to the connector 413 and the connector 41 within the substrate 410.
4 and distributed. The connector 413 is connected to a transformation supply cable 503, and the AC voltage is supplied to the power supply unit 420. The power receiving board 410 includes:
As shown in FIG. 27, a power supply fuse 416 that cuts off a receiving voltage for overcurrent protection and a prepaid card unit 1
A fuse 417 for cutting off the supply of AC 24 V to the power supply 3 is provided.

As shown in FIG. 32, the power receiving board 410
Is distributed to a plurality of, in this case, four types of voltage converters 425 to 428 by the above-mentioned voltage supply cable 503. Among them, the voltage converters 425, 427, 4
28 is configured as a DC conversion circuit. In each case, a transformer 573 is provided on the AC input side, and the secondary side AC output is converted to DC by full-wave rectification by the diode bridge 574 and smoothing by the capacitor 575, and a desired DC output voltage V0 is obtained by the three-terminal regulator 577. Like that. Note that the capacitor 578 is for preventing the circuit from oscillating due to the wiring inductance and the parasitic capacitance inside the three-terminal regulator IC.
The capacitor 579 is for reducing the output impedance of the three-terminal regulator IC at a high frequency. Further, the diode 580 is for reverse current bypass to the three-terminal regulator IC. Note that a diode 580 may be omitted from a voltage conversion unit (for example, DC 5 V) that is not involved in driving the motor.
Further, depending on the output voltage value (for example, 32 V), the transformer 573 may be omitted, and the AC voltage may be changed to the diode bridge 5.
It is also possible to obtain an output voltage by converting to DC by full-wave rectification by 74 and smoothing by a capacitor 575, and further omitting the three-terminal regulator 577.

As a simpler configuration of the constant voltage power supply, a Zener diode 576 can be used instead of the three-terminal regulator as shown in FIG.

Each of the voltage converters 425, 427, 428
Turn ratio of transformer 573 and three-terminal regulator 577
By appropriately selecting the output voltage of
V (solenoid drive voltage for accessories, etc.), DC12
V (drive voltage of a motor for award ball payout device or other analog control voltage) and DC 5 V (digital control drive voltage) are generated.

On the other hand, the voltage conversion section 426 is for generating a voltage of 24 V which is the same as the input AC voltage, and does not include a transformer. Then, after full-wave rectification by the diode bridge 574, the capacitor 57
5, 578, 579 and a three-terminal regulator 577, which are converted into a drive voltage of a DC24V firing device torque motor and the like, and output. On the other hand, the output of the full-wave rectified pulsating flow is branched from the input side of these DC smoothing circuits. The pulsating flow is used for driving a light emitting device including a resistance filament, for example, a lamp. A pulsating flow output terminal is added to the output connector 422 of the power supply unit 420 for this pulsating flow output (not shown). On the other hand, as shown in FIG.
Is provided with a power supply fuse 416 for protection when an overload is applied to the output side. Further, a power switch 415 is provided for turning on / off the output of the received AC.

The power supply unit 420 is formed with an input connector 421 to which the transformation supply cable 503 is connected, and includes an output terminal for each converted voltage, a ground terminal, a backup terminal, and an input / output terminal for various signals. Connector C
An input / output connector 422 including N2 to N4 is provided. As shown in FIG. 34, CN2 is a sub control board (frame control board 350, symbol control board 360, lamp control board 3
70, an output terminal of a power supply voltage to the voice control board 380), and CN3 includes an output terminal of a memory clear signal, a power cutoff signal, and a system reset signal (for a sub control unit).
Reference numeral 4 includes an output terminal for a power supply voltage and a system reset signal (for the main control unit) to the main control board 340, and an input terminal for an operation occurrence signal (described later) from the sub control board.

More specifically, as shown in FIG. 37, the connector CN2 is connected to the connector CN3a of the power distribution board 430 to output the power supply voltages 5V, 12V-A, B, 24V and 32V to the sub-control board. Terminal. In addition,
A backup power supply for the main control board 340 and the sub control board (frame control board 350) can be output from the third terminal of the connector CN2. The connector CN3 is connected to the connector CN3b of the power distribution board 430, and has a terminal for outputting a memory clear signal, a power interruption signal, and a system reset signal (for a sub control unit) to the main control board 340 and the sub control board 350. Contains. Further, the connector CN4
Is connected to the connector CN3c of the power distribution board 430, outputs a power supply voltage and a system reset signal (for the main control unit) to the main control board 340, and outputs an operation generation signal (described later) from the sub control board to the power supply unit 420. A terminal for inputting to the main control board power supply control unit 870 is included.

Next, distribution of the power supply voltage will be described.
As shown in FIG. 27, the input / output connector 422 (connectors CN2 to CN4) of the power supply unit 420
04 is connected to the input / output connector 433 (connectors CN3a to CN3c) of the distribution board 430 so that, for example, various power supply voltages converted and generated by the power supply unit 420 and various signals are supplied to the distribution board 430. On the other hand, an operation occurrence signal from the sub-control board is input to the power supply unit 422 from the power distribution board 430. As shown in FIG. 25, the distribution board 430 includes a plurality of control boards for controlling the operation of the pachinko machine 1, here, a main control board 340, a frame control board (a first peripheral control board, a prize ball control board). ) 350, special symbol control board (second peripheral control board) 360, lamp control board (third peripheral control board) 370, voice control board (fourth peripheral control board) 380
And a board in which the output terminal of the power supply voltage and the output terminal of various signals used in each board, and the input terminal of the operation occurrence signal from each sub-control board are combined to connect the launch control board 201. Side connectors 431 to 437 are provided, and a power supply voltage from the input connector 433 is distributed to each terminal. In FIG. 27, an output terminal of a backup power supply from the power distribution board 430 to each board, and various signals (memory clear signal,
The input / output terminals of the power interruption signal, the system reset signal, and the operation occurrence signal) and their signal lines are partially omitted.

As shown in FIG. 28, the connector 431 for the main control board 340 includes DC 32 V (No. 2: for driving various solenoids) and DC 12 V (No. 4: for operating various switches).
And three output terminals of DC5V (No. 6: for digital signal power supply) and four ground terminals (No. 1, 3, 5, 7)
Includes a total of seven terminals. Connector 4 for frame control board 350
34 (see FIGS. 27, 28 and 29) is a DC 32 V (1
No .: three output terminals for driving various solenoids, 12 V DC (No. 3: driving a prize ball payout motor) and 5 V DC (No. 5: for digital signal power supply) and three ground terminals (2,
Nos. 4 and 6) and two backup terminals (Nos. 7 and 8 (5 VDC)), for a total of eight terminals. The connector 436 for the special symbol control board 360 is DC12V (2nd:
Two output terminals of a liquid crystal panel drive) and 5 V DC (No. 4: for digital signal power supply) and three ground terminals (1,
3 and 5). The connector 437 of the lamp control board 370 has three output terminals of pulsating current 24V (No. 2: for driving light emission of a bulb), DC12V (No. 4: for driving light emission of an LED) and DC5V (No. 6: for power of a digital signal) and 4 And seven ground terminals (1, 3, 5, 7). Connector 4 for voice control board 380
35 is DC12V (No. 2: for driving speaker) and D
A total of five terminals including two output terminals of C5V (No. 4: digital signal power supply) and three ground terminals (No. 1, 3, 5) are included. Further, the connector 43 of the launch control board 201
2 is DC 24V (No.2: for firing motor drive), DC1
2V (No.4: For ball feed solenoid drive) and DC5V
(No. 6: For digital signal power supply)
And seven ground terminals (1, 3, 5, 7).

Here, as is clear from FIG. 27, all of the board side connectors 431 to 437 have no spare terminal portion, and the wiring toward the corresponding board is connected to all the formed terminals. Connected to the unit. In particular,
The board-side connector includes only an output terminal for each power supply voltage and a ground terminal, or only an output terminal for each power supply voltage, a ground terminal, and a backup power supply terminal. In order to respond flexibly to changes in the power supply system design, etc., it may be convenient to form a spare terminal to facilitate the addition of a new power supply voltage terminal. By adopting a configuration in which all the terminals are used up without excess or shortage without intentionally forming the terminal portion, an advantage that illegal operation using spare terminals can be effectively prevented is brought about.

As shown in FIG. 27, the board side connectors 431 to 437 are provided with wiring cables 511 to 517 in which a group of wirings directed to the corresponding board are bundled, and a wiring side connector 431a formed at the end thereof. 437a. Then, in two or more pairs of the board-side connector and the wiring-side connector corresponding to each other, here, the connector harnesses in all the pairs are colored in different colors between the pairs. (Examples of selecting coloring colors are written in the drawing).
By doing so, it becomes extremely easy to identify the wiring-side connector that matches the board-side connector, and the efficiency and reliability of the connection operation can be improved. The coloring of the connector harness does not necessarily have to be performed for all connectors. However, when two or more board-side connectors having the same number of formed terminals and different combinations of the types of power supply voltages included therein are formed, It is desirable that the board-side connectors be at least the same as the wiring-side connectors forming a pair, and that the connector harness be the same in the pair and be colored in different colors between the pairs. Such a connector having the same number of terminals is liable to cause an erroneous connection due to a mistake or the like. If an operating voltage different from the originally required one is supplied to the board side, an erroneous connection of the board or an electric device connected to the board may occur. There is also a risk of operation or breakage. Therefore, if the corresponding connector harnesses are colored as described above, even if connectors having the same number of terminals are mixed, it can be easily identified, and the occurrence of the above-described problem can be prevented. Can be prevented.

In the following, the form of connecting parts to each substrate will be described.
This will be described with reference to FIGS. The main control board 340 is
As shown in FIGS. 27 and 28, the power supply voltage from the power distribution board 430 is received by the power supply connector 341. Also, the main control board 340 incorporates the shared bus 500a of FIG. 4, and as shown in FIG. 28, connectors 342 to 346 for connecting signal transmission cables to each board.
Are formed. A signal (command) transmission cable to the frame control board 350 is connected to the connector 343 (see FIGS. 25 and 31). A cable for transmitting a signal (command) to the special symbol display board 360 is connected to the connector 345 (see FIGS. 25 and 28). On the other hand, a cable for receiving a sensor signal from the relay board 200 to which various sensors are connected is connected to the connector 342 (see FIGS. 25 and 28). Then, the external information terminal board 440 and the lamp control board 370
And each signal transmission cable 52 to the audio control board 380
4, 521 and 520 are connectors 344, 346 and 3
45 (see FIGS. 25 and 28).

As shown in FIGS. 25 and 29, the frame control board 3
50 receives various power supply voltages from the power distribution board 430 at the connector 352 via the cable 514 connected thereto. The connector 352 is provided with an output terminal for a frame control section operation occurrence signal (not shown). CPU
A signal cable 547 for transmitting the launch control signal emitted by 401 (see FIG. 9) to the launch control board 201 is connected to the connector 358. The reception cable 546 of the detection signal of the ball lending counting sensor 470 is connected to the connector 363. The drive cable 545 of the alarm buzzer board 460 is connected to the connector 356. The cable 533 for the winning ball counting signal from the relay board 200 is connected to the connector 351. On the other hand, the signal transmission cable 542 and the signal reception cable 541 to the upper tray CR board 450 are connected to connectors 361 and 362, respectively. The drive cable of the switching solenoid is connected to the connector 360. Prize ball motor sensor board 10 to which prize ball motor 109b is connected
Cables 543 and 544 for transmitting and receiving signals to and from 9a
Are connected to connectors 353 and 354, respectively. Signal (command) cable 523 from main control board 340
Is connected to the connector 357. External information terminal board 44
The ball lending signal transmission cable 548 to 0 is a connector 359.
Connected to. And the prepaid card unit 13
Is connected to the connector 355.

As shown in FIGS. 25 and 28, the frame relay board 2
To the connectors 221 to 225 of 00, the supply ball out switch 108, the prize ball counting sensor 214, and the lower tray full switch 27 are connected. A transmission cable 534 for transmitting signals from these sensors to the main control board 340 is connected to the connector 224. The cable 533 for award ball counting transmission is connected to the connector 223.

As shown in FIGS. 25 and 30, in the external information terminal board 440, a signal cable 548 from the frame control board 350 is connected to the connector 445. A signal cable 524 from the main control board 340 is connected to the connector 444. A door switch 480 for detecting door opening is connected to the connector 442. Tank ball out switch 1
04 is connected to the connector 441. Connector 443
Include terminals for ball out information output, door (door) open output, jackpot information output, prize ball information output, and ball lending information output. Further, the connectors 446 and 447 include terminals for award ball information output and ball lending information output, respectively.

As shown in FIGS. 25 and 30, in the lamp control board 370, the power distribution board 430 is connected to the connector 371.
A cable 517 for supplying various power supply voltages from is connected. The connector 371 is provided with an output terminal for a lamp control section operation occurrence signal (not shown). Connector 3
73 includes a signal cable 521 from the main control board 340.
Is connected. The connector 372 includes an illumination relay board 49
A cable 550 for supplying the drive voltage of the light emitter and transmitting the control signal is connected to the connector 491 of the 0.
The connector 493 of the illuminated relay board 490 has a board 35f on which a lamp that emits light by a resistance filament is attached.
To the distribution board 430 via the cables 517 and 550.
A cable 551 for supplying a pulsating flow as a lamp driving current received from the power supply and a switching control signal is connected. On the other hand, the LED boards 4f and 4d connected in series by cables 552 and 553 are connected to the connector 492, and DC12V for driving LED light emission and a switching control signal are supplied.

As shown in FIGS. 25 and 27, in the audio control board 380, a cable 515 for supplying various power supply voltages from the power distribution board 430 is connected to the connector 382. Note that the connector 382 is provided with an output terminal for an audio control unit operation occurrence signal (not shown). Connector 38
1, a signal cable 520 from the main control board 340 is connected. And the speaker 400a for audio output is
It is connected to the connector 383 via the volume switch board 12.

As shown in FIGS. 25 and 26, the firing control board 201 has a firing motor 9c, a firing stop switch 9b,
The ball feed solenoid board 9e to which the ball feed solenoid 9f is connected is connected. Further, a firing handle unit 9 including a variable resistor 9d for adjusting the firing force of the firing motor 9c, a start switch 9a and the like is also connected.

In the above-described configuration, power supply unit 420 receives an AC voltage from power supply receiving board 410 and power supply board 430 includes DC-driven prize ball payout device 109.
And a frame control board 350 that controls the operation with the prepaid card unit 13 driven by AC. The DC power supply voltage used in the frame control board 350 is
The power is supplied from the power supply unit 420 to the frame control board 350 via the power distribution board 430. On the other hand, an AC power supply voltage (AC 24 V) for driving the prepaid card unit 13
Are supplied directly from the power receiving board 410 to the frame control board 350. Specifically, an AC output connector 414 is formed on the power receiving board 410, and the frame control board 350
The AC power supply voltage is supplied to the AC power receiving connector 358. In this manner, even when a control board that requires an AC power supply voltage is exceptionally included, such as the frame control board 350, an AC power supply separated from the power supply unit 420 (in this case, the power supply The power supply unit 420 of the DC system is
It is possible to share the circuit board including all the control boards that require the AC power supply voltage, and it becomes easier to respond to design changes and the like.

Next, the output mode of the power supply voltage of power supply unit 420 will be described in more detail. Power supply unit 4
As a modified example of the configuration of the voltage conversion unit shown in FIG. 32 in FIG. 20, as shown in FIG.
V) can be converted and output according to the following procedure.
First, the AC voltage input from the power receiving board 410 is
Rectifier circuit 7 provided with a rectifier circuit element such as a diode
Rectification is performed at 60a (for example, full-wave rectification by the diode bridge 574 or the like). The rectified voltage can be output as a pulsating current (24 V) from, for example, the tenth terminal (see also FIG. 37) of the connector CN2. This pulsating voltage can be smoothed for each purpose on each control board (sub-control board) to which it is supplied, and can be smoothed by a capacitor or a three-terminal regulator. For example, in the case of using a light emitting device including a resistance filament, for example, a lamp control board for driving driving of lamps, a pulsating voltage can be used as it is, and a launch control board for driving a launch device torque motor. In the case of using the liquid crystal panel, it is possible to use a stable DC voltage by smoothing a pulsating flow in the firing control board.

[0157] Also, the power is inputted from the power receiving board 410,
The voltage rectified by the rectifier circuit 760b is transformed and stabilized by the step-down chopper regulator IC 763 having the same three-terminal regulator as described above, and then rectified and smoothed again including the rectifier circuit element and the smoothing circuit element. Unit (smoothing filter) 764 rectifies and smoothes DC1
Output as 2V-A. Note that this DC12V-A
Is the eighth terminal of the connector CN2 (see also FIG. 37)
Through the power distribution board 430 to the symbol control board 360, the lamp control board 370, and the voice control board 380.

[0158] Further, the power is inputted from the power receiving board 410,
The voltage rectified by the rectifier circuit 760c is further rectified, and then converted to DC32V, for example, from the ninth terminal of the connector CN2 (see also FIG. 37) to the sub-control board and the fourth terminal of the connector CN4 (see also FIG. 37). Is output to the main control board 340. On the other hand, the voltage rectified by the rectifier circuit 760c is transformed and stabilized by a two-output chopper regulator IC 765 provided with a three-terminal regulator similar to the above, and then rectified again including the rectifier circuit element and the smoothing circuit element. A smoothing unit (smoothing filter) 764
DC12V-B and DC5
As V, for example, from the 7th, 4th, and 5th terminals (see also FIG. 37) of the connector CN2 to the sub-control board,
The signal is output from the third and second terminals of N4 (see also FIG. 37) to the main control board 340. This DC12V-B is
Main control board 340, frame control board 350, launch control board 2
01 is output to the main control board 340 and the sub-control boards (frame control board 350, symbol control board 360, lamp control board 370, and voice control board 3).
80, to the emission control board 201). Note that the output of DC5V is
To compensate the voltage supply for backing up the contents of the built-in RAMs 1481 and 1681 (see FIG. 10),
Backup circuit 769 including electric double layer capacitor
Is output to the third terminal of CN2 (see also FIG. 37).

Next, an input is made from the power receiving board 410,
The voltage rectified by the rectifier circuit 760c is output to the power interruption detection circuit 771. This power interruption detection circuit 771
A circuit that monitors a power supply voltage, and is a circuit unit that outputs a power interruption signal when the output power supply voltage becomes equal to or lower than a predetermined value. This power interruption signal is output from the output buffer 772 via the filter 773 to the main control board 340 and the frame control board 350 from the second terminal of the connector CN3 (see also FIG. 37). When the power interruption signal is input to the main control board 340 and the frame control board 350, the main control board 340
The frame control board 350 performs a backup process.

[0160] The power interruption detecting circuit 771 outputs a memory clear signal. The memory clear signal is transmitted to the RAM 14 of the main control board 340 and the frame control board 350 when the power is turned on.
Signals for erasing (clearing) the contents of 81 and 1681 (see FIG. 10). More specifically, a memory clear signal is generated by turning on the power while artificially pressing a memory clear switch (not shown) provided only when the power is turned on. , CN3 (see also FIG. 37) are output to the main control board 340 and the frame control board 350.

On the other hand, the power interruption detection circuit 771 outputs a system reset signal for the sub-control board. That is, in this embodiment, the system reset signal for the main control board is generated by the main board power supply control section 870, and the system reset signal for the main control section and the system reset signal for the sub control board are different. And output via different connectors and signal lines. The system reset signal for the sub-control board is supplied to each of the sub-control boards 350 to 380 when the power is turned on, by the third terminal of the connector CN3 (FIG.
7) and output from the sub-control boards 350-38.
Initialization is performed at 0. Thereafter, a system reset signal for the main control board is output from the main board power supply control unit 870, and the main control board 340 is initialized.

The output of the power supply voltage to the main control board (main board) 340 is performed after the output of the power supply voltage to each sub-control board. Such output control is specifically performed by a main board power supply control section (main control board power supply control section) 870 shown in FIG.
The main board power supply control section 870 controls the output of the power supply voltage to the main control board 340, and supplies the power supply voltage to the main control board 340 based on the signal from each sub-control board. It has been. That is, when a power supply voltage is supplied to each sub-control board and the control (operation) in the sub-control board is started, an operation generation signal (start signal) output from the sub-control board is supplied to the main board power control section 87.
When input to 0, the power supply voltage is supplied to the main control board 340. In the sub-control board, an operation occurrence signal output means (main circuit section 600, CPUs 161, 171, 181 and the like (see FIG. 4) for outputting an operation occurrence signal when the power supply voltage is supplied and the control is started) The operation occurrence signal output by the operation occurrence signal output means is input to the fifth to eighth terminals (see also FIG. 37) of the connector CN4 of the power supply unit 420 via the power distribution board 430. The operation occurrence signal may be directly input to the power supply unit 420.

As shown in FIG. 35, the main board power supply control section 870 includes an AND gate (logic circuit) 871 and a relay (relay) 872. 5 of connector CN4
The operation occurrence signal from each sub-control board, which is input to the eighth terminal (see FIG. 34), is input to an AND gate (logic circuit) 871, and when all inputs are at H level,
An H level signal is output from the D gate (logic circuit) 871 to the relay 872, and the relay 872 operates.
Each power supply voltage (5 V, 12 V-B, 32 V) that can be supplied to main board power supply control section 870 by operation of relay 872
Is supplied, and the reset IC 873 generates a system reset signal based on the current, and the system reset signal is output to the main control board 340 to initialize the control of the main control board 340. In addition, each power supply voltage (5
V, 12V-B, 32V) is output to the main control board 340, and the control (operation) of the main control board 340 is started.

The main board power supply control section 870 includes:
As shown in FIG. 36, the CPU 877 is mainly configured,
The CPU may output a power supply voltage to the main control board 340 based on an operation occurrence signal from the sub control board. That is, the operation occurrence signal from each sub-control board is input to the CPU 877 via the I / O port 875 and the decode circuit 876, and the CP is generated based on the input.
U877 may output an operation command signal to relay 872.

By providing such a main board power supply control unit 870 shown in FIGS. 35 and 36, the activation of the control on the sub-control board is faster than the activation of the control of the main control board 340. In such a case, troubles such as the loss of the control signal may be less likely to occur. Note that the same main board power supply control unit 870 as described above can be provided to the power supply unit 420 including the configuration shown in FIG. 32 while the power supply voltage is being supplied to the main control board 340. .

The embodiments of the present invention have been described above.
The present invention is not limited to this, and is not limited to the wording of each claim unless it deviates from the scope described in each claim, and extends to a range that can be easily replaced by those skilled in the art, and It is possible to appropriately add improvements based on the knowledge that those skilled in the art normally have. For example, the input and output of various power supply voltages and signals (memory clear signal, power interruption signal, system reset signal, operation occurrence signal) are directly input to and output from the power supply unit 420 without passing through the power distribution board 430. be able to. It is also possible to use separate connectors for input and output of various power supply voltages and signals (memory clear signal, power cutoff signal, system reset signal, operation occurrence signal).

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko machine according to an embodiment of the present invention.

FIG. 2 is a front view of the game board of the pachinko machine of FIG.

FIG. 3 is a rear view of the pachinko machine shown in FIG. 1;

FIG. 4 is a block diagram showing an example of an electronic control device of the pachinko machine shown in FIG.

FIG. 5 is a flowchart showing a flow of a main job in the electronic control device of FIG. 4;

FIG. 6 is a flowchart illustrating the flow of the success / failure determination job.

FIG. 7 is an explanatory diagram showing an example of the contents of a main memory of the main control unit in FIG. 4;

FIG. 8 is a flowchart showing the flow of a special symbol main job.

FIG. 9 is a block diagram schematically showing a configuration of a main control unit.

FIG. 10 is a block diagram of a CPU used in a main control unit;

FIG. 11 is a circuit diagram showing a connection state between a reset circuit unit and a CPU in the main control unit.

FIG. 12 shows an I / O decode circuit unit and C in a main control unit.
FIG. 3 is a circuit diagram showing a connection state with a PU.

FIG. 13 shows a first external input circuit unit and a CP in the main control unit.
FIG. 4 is a circuit diagram showing a connection state with U.

FIG. 14 is a circuit diagram showing a configuration of a command output circuit unit in the main control unit.

FIG. 15 is a circuit diagram showing a configuration of a solenoid drive circuit unit in the main control unit.

FIG. 16 is a circuit diagram showing a configuration of an LED drive / information output circuit unit in the main control unit.

FIG. 17 is a circuit diagram showing a configuration of a second external input circuit unit in the main control unit.

FIG. 18 is a circuit diagram showing a configuration of an output port unit in the main control unit.

FIG. 19 is a block diagram schematically showing the configuration of a frame control unit.

FIG. 20 shows an I / O decode circuit unit and C in the frame control unit.
FIG. 3 is a circuit diagram showing a connection state with a PU.

FIG. 21 is a circuit diagram showing a configuration of a reset circuit unit in the frame control unit.

FIG. 22 is a circuit diagram showing a configuration of an input / output circuit unit in the frame control unit.

FIG. 23 is a circuit diagram showing a configuration of an input / output circuit unit in the frame control unit.

FIG. 24 is a circuit diagram showing a configuration of an input / output circuit unit in the frame control unit.

FIG. 25 is a circuit diagram showing a configuration example of an electronic control device including a power supply unit.

FIG. 26 is a first detailed circuit diagram of FIG. 25;

FIG. 27 is a second detailed circuit diagram of the same.

FIG. 28 is a third detailed circuit diagram of the same.

FIG. 29 is a fourth detailed circuit diagram of division.

FIG. 30 is a fifth detailed circuit diagram of division.

FIG. 31 is a detailed circuit diagram of a sixth division in the same manner.

FIG. 32 is a circuit diagram illustrating an example of a configuration of a voltage conversion unit.

FIG. 33 is a circuit diagram showing another example of the voltage conversion unit.

FIG. 34 is a block diagram showing a modification of the configuration of the voltage conversion unit.

FIG. 35 is a block diagram showing an example of a configuration of a main board power supply control unit.

FIG. 36 is a block diagram showing a modification of the configuration of the main board power supply control unit.

FIG. 37 is an explanatory diagram showing a connection mode of input / output connectors of the power supply unit.

[Explanation of symbols]

 1 Pachinko machine (ball game machine) 130 Electronic control unit 140 Main control unit 150 Frame control unit (Sub-control unit) 160 Symbol control unit (Sub-control unit) 170 Lamp control unit (Sub-control unit) 180 Voice control unit (Sub-control unit) Control section) 340, 350, 360, 380, 440 Control board 410 Power receiving board 420 Power supply unit 425-428 Voltage conversion section 870 Main board power control section

 ────────────────────────────────────────────────── ─── Continued on the front page F term (reference) 2C088 AA17 AA35 AA36 AA42 BA03 BA04 BA05 BA22 BA27 BA35 BA37 BA41 BA50 BA56 BA78 BA88 BA89 BB21 BC07 BC08 BC58 CA19 EA02 EA08 EA09 EA10 EA15 EB15 EB56 EB58

Claims (4)

[Claims] A main control unit that controls a game, a sub control unit that operates in accordance with the main control unit, and a power supply voltage output unit that outputs a power supply voltage to the control units. The gaming machine, wherein the power supply voltage output unit includes an output control unit that controls the main control unit to output the power supply voltage based on a signal from the sub control unit. 2. The sub-controller is capable of outputting an operation occurrence signal indicating a rise of the operation to the power supply voltage output unit, and the power supply voltage output unit is configured to output the operation occurrence signal based on the input of the operation occurrence signal. The gaming machine according to claim 1, wherein the gaming machine performs control for outputting the power supply voltage to the main control unit. 3. The power supply voltage output unit includes a main control unit power supply voltage output unit that outputs the power supply voltage to the main control unit, and the output control unit is configured to output the power supply voltage based on the operation occurrence signal. 3. The gaming machine according to claim 2, wherein an operation signal as an operation command is output to a main control unit power supply voltage output unit. 4. A main control unit for controlling a game, a sub-control unit which operates according to the main control unit, and a power supply voltage output unit for outputting a power supply voltage to these control units. A gaming machine.