JP2002289832A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that enables carrier injection characteristics to be improved as compared with conventional semiconductor devices, such as Schottky barrier diodes and PiN diodes, and consequently, enables improvement in tradeoff between forward voltage drop (Vf) and reverse recovery charge (Qrr). SOLUTION: A PiN diode of the includes a Si layer 21 of P conductivity-type with a low impurity concentration, a Si layer 22 of N conductivity-type with a low impurity concentration, a Si layer 23 of N conductivity-type with a high impurity concentration, an electrode 24 on the Si layer 21 of P conductivity-type, and an electrode 25 on the Si layer 23 of N conductivity-type; and the electrode 24 is composed of a PtSi layer 31, a diffusion barrier layer 32, and an Al layer 33.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device suitable for use in a high-voltage semiconductor device such as a high-voltage diode for rectification.

[0002]

2. Description of the Related Art Conventionally, a Schottky barrier diode (SBD) has been used as a high-voltage rectifying element.
iode) and PiN diodes are known. FIG. 7 is a sectional view showing a conventional Schottky barrier diode.
In the figure, reference numeral 1 denotes an N-conductivity type silicon (Si) layer having a low impurity concentration, and 2 denotes an N-conductivity type Si layer 1 having an impurity concentration.
An electrode made of a metal forming a Schottky barrier with the N-conductivity-type Si layer 1 and N-conductivity-type Si layer 3 at a higher concentration,
It is an electrode made of gold (Au) or the like which makes ohmic contact with the conductive Si layer 2.

FIG. 8 is a cross-sectional view showing a conventional PiN diode. In the figure, reference numeral 11 denotes a P-conductivity type Si layer having a high impurity concentration, 12 denotes an N-conductivity type Si layer having a low impurity concentration, 13 Is N-conductivity type Si with high impurity concentration
A layer 14, an electrode made of aluminum (Al) which makes ohmic contact with the P-conductivity-type Si layer 11, and a reference numeral 15
An electrode made of Au or the like which makes ohmic contact with the layer 13. In this PiN diode, the amount of injected carriers can be changed by changing the impurity concentration and thickness of the P-conductivity-type Si layer 11.

As one method for reducing the loss of a semiconductor rectifier diode, it is known to use a Schottky barrier diode instead of a pn diode. Although the Schottky barrier diode has a low forward voltage drop Vf, it can reduce the forward loss, but has a disadvantage in that the reverse leakage current increases. On the other hand, the pn diode has an advantage that the leakage current in the reverse direction can be suppressed, but has a disadvantage that the reverse recovery charge Qrr becomes large due to the injection of the minority carrier in the forward direction. This reverse recovery charge Qr
As a method of reducing r, for example, there is a method of controlling the lifetime by diffusing platinum (Pt). Further, by controlling the impurity concentration and the film thickness of the P-conductivity-type Si layer, it is possible to improve the operation characteristics.

[0005]

By the way, in the conventional Schottky barrier diode and PiN diode, it is known that there is a trade-off relationship between the forward voltage drop (Vf) and the reverse recovery charge (Qrr). Have been.
For example, in a PiN diode, this Qrr-Vf
In order to optimize the trade-off, it is necessary to optimally control the amount of carriers flowing into the N-conductivity-type Si layer 12, and for this purpose, the impurity concentration and the thickness of the P-conductivity-type Si layer 11 must be controlled. It may be adjusted optimally. However, when Al is used as the electrode material when the thickness is small, there is a problem that the P-conductivity-type Si layer 11 becomes non-uniform due to a reaction between Al and Si in a manufacturing process. May occur. In particular, P
A problem arises when the impurity concentration of the conductive Si layer 11 is lowered, so that it is necessary to use a metal with excellent uniformity as an electrode material, but this is difficult in the current situation where Al is used as an electrode material. .

Further, the thickness of the P conductive type Si layer 11 is large,
Moreover, the surface impurity concentration is, for example, 1 × 10 ¹⁷ cm.
^-3 If less and less, because the Schottky barrier between the P conductivity type Si layer and an Al electrode occurs, the contact resistance increases, resulting in forward voltage drop (Vf) problem increases point was there. Forward voltage drop (Vf)
In order to reduce the voltage drop, the voltage drop due to the electrode must be reduced by making the electrode and the P-conductivity type Si layer into ohmic contact, but this is difficult in the current situation where Al is used as the electrode material. It is.

The present invention has been made in view of the above circumstances, and has been made in consideration of a conventional Schottky barrier diode or P-type diode.
A semiconductor device capable of improving carrier injection characteristics as compared with a semiconductor device such as an iN diode, and as a result, improving a trade-off between a forward voltage drop (Vf) and a reverse recovery charge (Qrr). The purpose is to provide.

[0008]

In order to solve the above-mentioned problems, the present invention employs the following semiconductor device. That is, in the semiconductor device according to the first aspect, the first semiconductor layer of the P conductivity type, the second semiconductor layer of the N conductivity type, and the N conductivity type having an impurity concentration higher than that of the second semiconductor layer. A third semiconductor layer, wherein a first electrode is provided on the first semiconductor layer, and a second electrode is provided on the third semiconductor layer. A platinum silicide layer is formed between the first semiconductor layer and the first semiconductor layer.

According to a second aspect of the present invention, in the semiconductor device, a first semiconductor layer of P conductivity type, a second semiconductor layer of N conductivity type having a higher impurity concentration than the first semiconductor layer, and an impurity concentration of A third semiconductor layer of a P conductivity type having a higher concentration than the first semiconductor layer, wherein a first electrode is provided in the first semiconductor layer, a second electrode is provided in the second semiconductor layer, In a semiconductor device in which a third electrode is provided on a third semiconductor layer, a platinum silicide layer is formed between the first electrode and the first semiconductor layer.

According to a third aspect of the present invention, there is provided a semiconductor device, comprising: a first P-type semiconductor layer; an N-type second semiconductor layer; a P-type third semiconductor layer; And a first electrode on the first semiconductor layer.
The second electrode is provided on the semiconductor layer of the third type, and the third electrode is provided on the fourth semiconductor layer.
In a semiconductor device provided with the electrodes of
A platinum silicide layer is formed between the first electrode and the first semiconductor layer.

In the semiconductor device of the present invention, a platinum silicide layer, which is a platinum compound, is formed between the first electrode and the first semiconductor layer. Is close to ohmic contact. When platinum is used for the first electrode, the height of the Schottky barrier between the first electrode and the first semiconductor layer having a low impurity concentration is reduced. Originally, the contact part between the semiconductor layer with low impurity concentration and the metal is non-ohmic, but by reducing the height of the Schottky barrier, the characteristics at the contact part can be made close to ohmic characteristics. become. As a result, the carrier injection characteristics are improved as compared with the conventional Schottky barrier diode or PiN diode, and as a result, the trade-off between the forward voltage drop (Vf) and the reverse recovery charge (Qrr), that is, the forward voltage The trade-off between drop (Vf) and reverse recovery time is improved.

The amount of injected carriers can be controlled by changing the impurity concentration and the thickness of the first semiconductor layer. Here, if the impurity concentration of the first semiconductor layer is reduced, the thickness of the first semiconductor layer can be increased accordingly, and the thickness of the first semiconductor layer can be controlled in the manufacturing process. Becomes easier.

[0013] The first semiconductor layer is located on the first electrode side.
Surface impurity concentration is 1 × 10¹⁵cm ^-3~ 1 × 10¹⁸cm
^-3Is preferred. The thickness of the first semiconductor layer is 0.1 to 3
It is preferably μm.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Each embodiment of the semiconductor device of the present invention will be described with reference to the drawings. "First Embodiment" FIG. 1 is a view showing a P of a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing the iN diode (semiconductor device), FIG. 2 is a partial cross-sectional view thereof, and in the figure, reference numeral 21 denotes a P-conductivity type Si layer (first semiconductor layer) having a low impurity concentration, and 22 denotes an impurity concentration. Is formed on the N-conductivity-type Si layer (second semiconductor layer) with a low concentration, 23 is formed on the N-conductivity-type Si layer (third semiconductor layer) with a high impurity concentration, and 24 is formed on the P-conductivity-type Si layer 21. The (first) electrode 25 is a (second) electrode formed on the N-conductivity type Si layer 23.

As shown in FIG. 2, the electrode 24 includes a platinum silicide (PtSi) layer 31, a diffusion barrier layer 32 for preventing a reaction between PtSi and Al, and an Al layer 33. This PtSi layer 31 has a P conductivity type of S
forming a Pt layer on the i-layer 21 by sputtering or the like;
Thereafter, these are heat-treated at a predetermined temperature, for example, 350 ° C., to generate a PtSi layer at a junction between the P-conductivity type Si layer 21 and the Pt layer. For the electrode 25, an Au—Ni—Ti layer or the like other than the Au layer is preferably used.

Here, the metal used to form the PtSi layer 31 is a metal that lowers the barrier height with respect to the p-type semiconductor, that is, the metal that lowers the barrier height with respect to the n-type semiconductor. What is necessary is just to select the metal which raises. Such a metal becomes closer to ohmic contact as the height of the barrier is higher, but the type of metal that forms silicide with Si is limited, and platinum silicide (P
tSi) is preferred. As the platinum silicide, there are other in Pt ₂ Si of PtSi, it can also be used Pt ₂ Si platinum silicide. The height of these PtSi and Pt ₂ Si barriers is about 0.85 e.
V.

In the electrode 24, platinum silicide is used for bonding with the P-conductivity type Si layer 21, so that a stable joint can be formed even when the P-conductivity type Si layer 21 is thin. Can be. Further, the P conductive type Si layer 21
By lowering the impurity concentration of P, the thickness can be increased by that amount.
1 is easy to control.

The P-type Si layer 21 has a surface impurity concentration on the electrode 24 side of 1 × 10 ¹⁵ cm ^-3 to 1 × 10 ¹⁸ cm ^-3.
Is controlled. A more preferable range of the surface impurity concentration is 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ . The thickness of the P-conductivity type Si layer 21 is preferably in the range of 0.1 to 3 μm.

In this PiN diode, the lifetime is controlled to be 30 to 70 ns by electron beam irradiation. In this PiN diode, the life time is set to 30 to 70 ns so as to optimize the carrier injection characteristics in consideration of the trade-off between Vf and Qrr when the life time control is performed.

When the lifetime is extended, Vf tends to be small and Qrr tends to be large. Therefore, the optimum impurity concentration and thickness of the P-conductivity type Si layer 21 at this time also change. As the lifetime becomes longer, it is necessary to suppress the amount of injected carriers. Therefore, it is necessary to reduce the thickness or the impurity concentration. P conductive type Si layer 21
When the impurity concentration and the thickness of the semiconductor layer satisfy the optimum conditions, the carrier injection characteristics can be improved as compared with the conventional Schottky barrier diode or PiN diode, and as a result, the trade-off between Vf and Qrr is improved. be able to.

FIG. 3 is a diagram showing an example of a trade-off between Vf and Qrr based on simulation results in the PiN diode of the present embodiment. Here, the lifetime is set to 30 ns, and the thickness is set to 0.1 to 1 for each of the surface impurity concentrations Cs of the three types of P conductivity type Si layers.
It was changed in the range of 0 μm. The N-conductivity type Si layer has an impurity concentration of 8 × 10 ¹⁴ / cm ³ and a thickness of 16.5 μm.
m. For reference, the trade-off between Vf and Qrr of a conventional Schottky barrier diode (SBD) is also shown in the figure. The range of the thickness of the P-conductivity-type Si layer is a range that can be produced due to the production process.
0.1 μm is a lower limit value obtained as a uniform layer in a normal diffusion step, and 10 μm is a thickness in consideration of a diffusion time of a P-conductivity type Si layer.

In this figure, as the thickness of the P-conductivity-type Si layer is increased, Vf decreases to a certain value and then increases. When the thickness of the P-conductivity-type Si layer increases, Vf decreases because the amount of injected carriers from the P-conductivity-type Si layer increases. On the other hand, Vf increases because the resistance of the P conductivity type Si layer increases. According to this figure, P
The surface impurity concentration Cs of the conductive Si layer is 1 × 10 ¹⁵ to 1 ×
When 10 ¹⁸ / cm ^3, it is seen that good trade-off characteristics than the conventional SBD is obtained. In addition, N conductivity type Si
It is known that when the impurity concentration of the layer is in the range of 2 × 10 ¹⁴ to 2 × 10 ¹⁵ / cm ^3, a better trade-off characteristic than the conventional SBD can be obtained (not shown).

FIG. 4 is a diagram showing another example of a trade-off between Vf and Qrr based on simulation results in the PiN diode of the present embodiment. Here, P
The optimum values obtained when the surface impurity concentration Cs and the thickness of the conductive Si layer are changed are shown for each of six types of lifetimes (20 ns to 1 μs). In addition, N conductivity type Si
The impurity concentration of the layer is 8 × 10 ¹⁴ / cm ³ and the thickness thereof is 1
The thickness was 6.5 μm. For reference, the trade-off between Vf and Qrr of a conventional Schottky barrier diode (SBD) is also shown in the figure.

According to this figure, the lifetime is 70 ns.
It can be seen that a better trade-off characteristic than the conventional SBD can be obtained in the following range. Further, it has been found that when the impurity concentration of the N-conductivity type Si layer is in the range of 2 × 10 ¹⁴ to 2 × 10 ¹⁵ / cm ^3, a better trade-off characteristic than the conventional SBD can be obtained.

As described above, the PiN of this embodiment is
According to the diode, the PtSi
Since the layer 31 is provided, the carrier injection characteristics can be improved as compared with the conventional Schottky barrier diode or PiN diode, and as a result, the trade-off characteristic between Vf and Qrr can be improved.

Further, since the impurity concentration and the thickness of the P-conductivity type Si layer 21 can be changed in a wide range, the amount of injected carriers can be controlled. In addition, P conductivity type Si
When the impurity concentration of the layer 21 is reduced, the thickness of the P-conductivity-type Si layer 21 can be increased accordingly, and the thickness of the P-conductivity-type Si layer 21 can be easily controlled in the manufacturing process.

[Second Embodiment] FIG. 5 is a cross-sectional view showing a pnp type planar transistor (semiconductor device) according to a second embodiment of the present invention. 41 is a P-conductivity-type Si layer (first semiconductor layer) with a low impurity concentration, 42 is an N-conductivity-type Si layer (second semiconductor layer) with a medium impurity concentration, 43 is a high-concentration impurity layer. P conductivity type Si layer (third semiconductor layer), 44 is silicon dioxide formed on a P conductivity type Si layer 41~P conductivity type Si layer 43 (SiO ₂₎ layer, 45 is the P conductivity type Si layer 41 A collector terminal (first electrode) formed on the lower surface, 46 is a base terminal (second electrode), and 47 is an emitter terminal (third electrode).
Electrode). The collector terminal 45 includes a platinum silicide (PtSi) layer 51, a diffusion barrier layer 52, and an Al layer 5.
3 has a three-layer structure.

According to the planar transistor of this embodiment, Pt is formed on the P-conductivity type Si layer 41 of the collector terminal 45.
Since the Si layer 51 is provided, the carrier injection characteristics between the collector and the base can be improved as compared with the conventional planar transistor, and as a result, the trade-off characteristics can be improved.

[Third Embodiment] FIG. 6 is a sectional view showing a three-pole thyristor (silicon controlled rectifier: semiconductor device) according to a third embodiment of the present invention. Layer (first semiconductor layer), 62 is N conductive type S
The i-layer (second semiconductor layer) 63 is a P-conductivity type Si layer (third semiconductor layer).
, 64 is an N-conductivity type Si layer (fourth semiconductor layer), 65 is an anode (first electrode) provided on the P-conductivity type Si layer 61, and 66 is a P-conductivity type Si layer 63. The gate (second electrode) 67 is a cathode (third electrode) provided on the N-conductivity-type Si layer 64. Anode 6
5 has a three-layer structure of a platinum silicide (PtSi) layer 71, a diffusion barrier layer 72, and an Al layer 73.

According to the three-pole thyristor of this embodiment, P
Since the PtSi layer 71 is provided on the conductive Si layer 61, the carrier injection characteristics between the anode and the cathode can be improved as compared with the conventional thyristor, and as a result, the trade-off characteristics can be improved.

Although the embodiments of the semiconductor device of the present invention have been described above with reference to the drawings, the specific configuration is not limited to the above embodiments, and the design is not deviated from the gist of the present invention. Can be changed. For example, in the second embodiment, a pnp type planar transistor has been described as an example, but an npn type planar transistor may be used. In this case, a PtSi layer may be formed on the base terminal. Further, PtSi
The layer may be formed between the low-concentration P-conductivity-type semiconductor layer and the electrode. In addition to the npn-type planar transistor, for example, MOSFET, IGBT, TR
The present invention can be applied to semiconductor devices having various structures such as an IAC.

[0032]

As described above, according to the semiconductor device of the present invention, the platinum silicide layer, which is a platinum compound, is formed between the P-type first semiconductor layer and the first electrode. The junction between the first electrode and the first semiconductor layer can be stabilized, and the carrier injection characteristics can be improved as compared with a conventional Schottky barrier diode, a PiN diode, or the like. Therefore, the trade-off between the forward voltage drop (Vf) and the reverse recovery charge (Qrr), that is, the trade-off between the forward voltage drop (Vf) and the reverse recovery time can be improved. That is,
In the present invention, the forward voltage drop (V
f), the reverse recovery charge (Qrr) can be improved without deteriorating the characteristics of the other, or both can be improved.

The amount of injected carriers can be controlled by changing the impurity concentration and the thickness of the first semiconductor layer. In addition, when the impurity concentration of the first semiconductor layer is reduced, the thickness of the first semiconductor layer can be increased accordingly, so that the thickness of the first semiconductor layer can be easily controlled in the manufacturing process. Can be done.

As described above, the carrier injection characteristics can be improved as compared with a conventional semiconductor device such as a Schottky barrier diode or a PiN diode. As a result, the forward voltage drop (Vf) and the reverse recovery charge (Qrr) are reduced. Semiconductor device capable of improving the trade-off between the two.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a PiN diode according to a first embodiment of the present invention.

FIG. 2 is a partial sectional view showing the PiN diode according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of a trade-off between Vf and Qrr in the PiN diode according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating another example of a trade-off between Vf and Qrr in the PiN diode according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a planar transistor according to a second embodiment of the present invention.

FIG. 6 is a sectional view showing a three-pole thyristor according to a third embodiment of the present invention.

FIG. 7 is a sectional view showing a conventional Schottky barrier diode.

FIG. 8 is a sectional view showing a conventional PiN diode.

[Explanation of symbols]

Reference Signs List 1 N-conductivity-type Si layer 2 N-conductivity-type Si layer 3, 4 electrode 11 P-conductivity-type Si layer 12 N-conductivity-type Si layer 13 N-conductivity-type Si layer 14, 15 electrode 21 P-conductivity-type Si layer 22 N-conductivity-type Si layer 23 N conductive type Si layer 24, 25 electrode 31 PtSi layer 32 Diffusion barrier layer 33 Al layer 41 P conductive type Si layer 42 N conductive type Si layer 43 P conductive type Si layer 44 Silicon dioxide (SiO ₂ ) layer 45 Collector terminal ( (First electrode) 46 base terminal (second electrode) 47 emitter terminal (third electrode) 51 PtSi layer 52 diffusion barrier layer 53 Al layer 61 P conductivity type Si layer 62 N conductivity type Si layer 63 P conductivity type Si Layer 64 N-conductivity-type Si layer 65 Anode (first electrode) 66 Gate (second electrode) 67 Cathode (third electrode) 71 PtSi layer 72 Diffusion barrier layer 73 Al layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/861 (72) Inventor Hideo Kobayashi 1-18-1 Takada, Toshima-ku, Tokyo Origin Electric Co., Ltd. F term (reference) 4M104 AA01 BB09 BB22 CC01 DD37 DD79 DD84 FF16 GG02 GG06 GG07 HH20 5F003 BC08 BH07 BM01 5F005 AA01 AF02 AG03 CA05 GA01

Claims (5)

[Claims] A first semiconductor layer of P conductivity type, a second semiconductor layer of N conductivity type, and a third semiconductor layer of N conductivity type having an impurity concentration higher than that of the second semiconductor layer. Wherein a first electrode is provided on the first semiconductor layer and a second electrode is provided on the third semiconductor layer, wherein the first electrode, the first semiconductor layer, A platinum silicide layer formed between the semiconductor devices. 2. A first semiconductor layer having a P conductivity type, a second semiconductor layer having an impurity concentration higher than that of the first semiconductor layer and an N conductivity type, and an impurity concentration higher than that of the first semiconductor layer. A high-concentration P-conductivity-type third semiconductor layer, wherein the first semiconductor layer has a first electrode, the second semiconductor layer has a second electrode, and the third semiconductor layer has a third electrode. A semiconductor device provided with three electrodes, wherein a platinum silicide layer is formed between the first electrode and the first semiconductor layer. 3. A semiconductor device comprising: a P-type first semiconductor layer; an N-type second semiconductor layer; a P-type third semiconductor layer;
A fourth semiconductor layer of conductivity type, wherein the first electrode is formed on the first semiconductor layer, the second electrode is formed on the third semiconductor layer,
In a semiconductor device in which a third electrode is provided on the fourth semiconductor layer, a platinum silicide layer is formed between the first electrode and the first semiconductor layer. Semiconductor device. 4. The surface impurity concentration of the first semiconductor layer on the first electrode side is set to 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁸ cm.
^4. The semiconductor device according to claim 1, wherein the value is ^-3 . 5. The thickness of the first semiconductor layer is 0.1 to 3
The semiconductor device according to claim 1, wherein the thickness of the semiconductor device is μm.