JP2002289793A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a ferroelectric capacitor having a superior characteristic by a method for manufacturing a semiconductor device with a capacitor. SOLUTION: The method includes the steps of forming a first insulation film 10 on a semiconductor substrate 1, planarizing an upper plane of the first insulation film 10, heating the first insulation film 10, forming a second insulation film 12 consisting of a silicon oxide film or a aluminum oxide film on the first insulation film 10, forming a titanium oxide film 13a on the second insulation film 12, forming a capacitor lower portion electrode 15a consisting of a platinum on the titanium oxide film 13, forming a capacitor ferroelectric film 16a on the capacitor lower electrode 15a, and forming an upper electrode 17a on the capacitor ferroelectric film 16a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a capacitor and a method for manufacturing the same.

[0002]

2. Description of the Related Art Flash memories and ferroelectric memories (FeRAM) are known as nonvolatile memories capable of storing information even when the power is turned off. Flash memory is an insulated gate field effect transistor (IGFE)
T) has a floating gate buried in a gate insulating film, and stores information by storing charges representing stored information in the floating gate. For writing and erasing information, it is necessary to pass a tunnel current passing through an insulating film, which requires a relatively high voltage.

[0003] An FeRAM stores information using the hysteresis characteristic of a ferroelectric substance. A ferroelectric capacitor having a ferroelectric film as a capacitor dielectric between a pair of electrodes generates polarization according to the applied voltage between the electrodes, and has spontaneous polarization even when the applied voltage is removed. If the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed. By inspecting the spontaneous polarization, information can be read. FeRAM is
It operates at a lower voltage than a flash memory, and can perform high-speed writing with low power consumption.

FIGS. 1A and 1B are circuit diagrams of a memory cell of an FeRAM. FIG. 1 (a) shows that 2 bits are used for storing 1-bit information.
One transistor Ta, Tb and two capacitors Ca, Cb
2T / 2C type circuit using the current FeRA
Used for M. The complementary operation of storing information "1" or "0" in one capacitor Ca and storing the opposite information in the other capacitor Cb is performed. Although the configuration is strong against process variations, the cell area is about twice as large as that of the 1T / 1C type described below.

FIG. 1B shows a 1T / 1C type circuit using one transistor T ₁ or T ₂ and one capacitor C ₁ or C ₂ for storing one bit of information.
The structure is the same as that of the first embodiment, the cell area is small, and high integration is possible. However, a reference voltage is required to determine whether the electric charge read from the memory cell is “1” information or “0” information. Since the reference cell C ₀ for generating the reference voltage inverts the polarization every time data is read, the reference cell C ₀ deteriorates faster than the memory cell due to fatigue. Also, 1T / 1C indicates that the margin of judgment is 2
It is narrower than T / 2C, weak against process variations, and has not yet been put to practical use.

The ferroelectric film of FeRAM is made of a PZT-based material such as lead zirconate titanate (PZT), La-doped PZT (PLZT), SrBi ₂ Ta ₂ O ₉ (SBT, Y1), SrBi.
₂ (Ta, Nb) ₂ O ₉ (SBTN, YZ) or the like, and is formed of a Bi layered structure compound or the like. These ferroelectric films are formed by a sol-gel method, a sputtering method, or the like. Usually, an amorphous phase ferroelectric film is formed on the lower electrode by these film forming methods, and the ferroelectric film is crystallized into a perovskite structure by a subsequent heat treatment. In order to produce a good FeRAM, it is necessary to control the orientation of crystal grains of the ferroelectric film.

Since the crystallization of the ferroelectric film is performed in an oxidizing atmosphere, the capacitor electrode is formed of a noble metal such as Pt or IrO ₂ , SrRuO ₃ , La _0.5 Sr _0.5 CoO ₃ which is conductive even if oxidized. You.

[0008]

In forming a ferroelectric capacitor, it is important to form a lower electrode immediately below the ferroelectric film. As a conventional lower electrode,
A laminated structure in which titanium (Ti) and platinum (Pt) are sequentially formed on an insulating film has been used. The Ti film is used to improve the adhesion between the insulating film and the lower electrode. Without the Ti film, there is a high possibility that the Pt electrode will peel off during the manufacturing process of the semiconductor device.

The Pt film is formed by a sputtering method. When the film is formed at a high temperature, a reaction with the Ti film occurs, and as a result, (11)
1) Since a structure with random orientation is obtained without strong self-orientation on the surface, the film was formed at room temperature. The crystallinity of the Pt film affects the quality of the ferroelectric film formed thereon. Further, the crystal grains of the Pt film, which is a refractory metal, were small and needle-like crystals having a grain size of about 20 nm. In order to further improve the characteristics of the ferroelectric capacitor, it is desired that the crystal grains of the Pt film be enlarged to be columnar crystals.

As a solution to these problems, Ti is used instead of Ti.
It is conceivable to use O ₂ , which suppresses the reaction with the underlying metal at the time of forming the Pt film. Therefore, the Pt film can be formed at a high temperature of 500 ° C., and the Pt film remains strongly oriented on the (111) plane. The crystal grains of the film can be made as large as 100 to 150 nm, and can be made into columnar crystals. However, when the TiO ₂ film is formed on the degassed insulating film, the crystallinity of the TiO ₂ film deteriorates, and this lowers the ability to improve the crystallinity of the Pt film. The crystallinity of the ferroelectric film is not sufficiently improved.

An object of the present invention is to provide a semiconductor device having a ferroelectric capacitor having good characteristics and a method of manufacturing the same.

[0012]

According to the present invention, there is provided a first insulating film formed above a semiconductor substrate and having a flattened surface, and a first insulating film formed on a flattened surface of the first insulating film and having the first insulating film formed thereon. Forming a second insulating film made of either a silicon oxide film or an aluminum oxide film having a higher hydrogen content than the insulating film; a titanium oxide film formed on the second insulating film; and the titanium oxide film A capacitor lower electrode made of platinum formed thereon, a capacitor dielectric film formed on the capacitor lower electrode, and a capacitor upper electrode formed on the capacitor dielectric film. It is solved by a semiconductor device. In the above-described semiconductor device, when an aluminum oxide film is used as the second insulating film, a capacitor lower electrode made of platinum may be formed on the second insulating film without using the titanium oxide film.

[0013] The above-described problems include a step of forming a first insulating film above a semiconductor substrate, a step of flattening an upper surface of the first insulating film, a step of heating the first insulating film, and a step of heating the first insulating film. (1) forming a second insulating film made of a silicon oxide film or an aluminum oxide film on the insulating film; forming a titanium oxide film on the second insulating film; and forming a platinum film on the titanium oxide film Forming a capacitor lower electrode; forming a capacitor dielectric film on the capacitor lower electrode; and forming a capacitor upper electrode on the capacitor dielectric film. It is solved by a manufacturing method.

Preferably, the titanium oxide film is formed by thermally oxidizing a titanium film formed on the second insulating film. In the method of manufacturing a semiconductor device described above, when the aluminum oxide film is formed as the second insulating film, a capacitor lower electrode made of platinum is formed on the second insulating film without forming the titanium oxide film. It may be formed.

Next, the operation of the present invention will be described. According to the present invention, after the surface of the first insulating film is planarized and degassed by heating, the second insulating film made of silicon oxide or aluminum oxide is formed on the planarized surface, and the titanium oxide film is formed thereon. After that, a platinum film to be a lower electrode of the capacitor is formed, and further, a dielectric film and an upper electrode of the capacitor are formed. In this case, the titanium oxide film is preferably formed by thermally oxidizing a titanium film formed over the second insulating film.

According to such a step, the degassed first gas
The effect of the insulating film is reduced by the second insulating film to form a titanium film having good crystallinity, and a titanium oxide film obtained by thermally oxidizing the titanium film has a strong (200) peak and is formed thereon It promotes the formation of a platinum film of columnar crystals having a particle size of 100 to 150 nm, and prevents the platinum film from peeling off. As a result, the crystal orientation of the oxide dielectric formed on such a platinum film is aligned in a desired direction, so that the magnitude of the remanent polarization is maximized. That is, a capacitor having high reliability can be obtained.

Since the second insulating film is not heated, even if the second insulating film is made of the same material as the first insulating film, for example, silicon oxide, hydrogen and water contained in the second insulating film are not heated. By adjusting the film thickness, the effect of hydrogen or water on the capacitor can be made almost negligible. According to another aspect of the present invention, after the flattened first insulating film is heated, an aluminum oxide film is formed thereon as a second insulating film, and a platinum film as a lower electrode is further formed. Thereby, there is no possibility of the platinum film being peeled off, and the crystallinity of the platinum film can be stably improved in a state where the particle diameter of the Pt film is as large as 100 to 150 nm.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. 2 to 7 are cross-sectional views illustrating a process of forming a memory cell of the FeRAM according to the embodiment of the present invention. The steps required until a structure shown in FIG.

First, an element isolation insulating film 2 surrounding an active region 3 is formed on the surface of a silicon (semiconductor) substrate 1. The element isolation insulating film 2 may be formed by a LOCOS method, or may be formed by a method in which a groove is formed in the silicon substrate 1 and an insulating film is embedded therein. Further, the silicon substrate 1 may be n-type or p-type. After the formation of the element isolation insulating film 2, impurities are introduced into the active region 3 of the memory cell region of the silicon substrate 1 and the active region of the peripheral circuit region (not shown) to form a p-well and an n-well. I do. In this embodiment, the p-well 3a is formed in the active region 3 in the memory cell region.

Subsequently, after a gate oxide film 4 is formed on the surface of the active region 3 of the silicon substrate 1, a polycrystalline or amorphous silicon film and an SiO ₂ protective film 6a are sequentially formed on the entire surface of the substrate. Thereafter, an n-type impurity is introduced into a portion of the silicon film above the p-type well 3a, and a p-type impurity is introduced into a portion above the n-type well (not shown). After that, silicon film and Si
By patterning the O ₂ film by photolithography, two gate electrodes 5 passing through the active region 3 in the memory cell region and a gate electrode (not shown) passing through the active region in the peripheral circuit region are formed. Note that the memory cell area 3
The gate electrode 5 formed thereon is formed in a shape also serving as a word line.

Subsequently, the p wells 3 on both sides of the gate electrode 5
An n-type impurity is ion-implanted into a to form a low-concentration n-type impurity diffusion layer. An insulating film, for example, an SiO ₂ film is
After the entire surface of the silicon substrate 1 is formed by the method D, the insulating film is uniformly etched by dry etching over the entire surface, and the sidewall insulating film 6 is formed only on both sides of the gate electrode 5.
Leave as b. Further, the gate electrode 5 and the side wall insulating film 6b
Using the mask as a mask, an n-type impurity is ion-implanted again into active region 3 to form a high-concentration n-type impurity diffusion layer. Thereby, on both sides of the gate electrode 5, the first, second and third LDD structures composed of the low-concentration and high-concentration n-type impurity diffusion layers are formed.
N-type impurity diffusion layers 7a and 7b are formed. These n-type impurity diffusion layers 7a and 7b become source / drain regions.

In the same manner, an n-type impurity diffusion layer and a p-type impurity diffusion layer (not shown) are also formed in the peripheral circuit region. Through the above steps, M
The formation of the basic structure of the OS transistor 8 is completed.
Note that a CMOS is also formed in the peripheral circuit region. The above process is a normal MOS transistor manufacturing process, and other known processes may be used.

Next, as shown in FIG.
Antioxidant film 9 made of SiON having a thickness of 200 nm and covering T8
Is formed on the silicon substrate 1 by the CVD method, and then a 600 nm thick SiO ₂ film 10 is
The first interlayer insulating film 11 is formed by these methods. Note that, for example, TEOS is used as a reaction gas for forming the SiO ₂ film 10.

Subsequently, as shown in FIG. 2C, the first interlayer insulating film 11 from the interface with the element isolating insulating film 2 to the upper surface of the SiO ₂ film 10 is chemically etched so as to have a thickness of 785 nm. The first interlayer insulating film 11 is polished and planarized from the upper surface by a mechanical polishing (CMP) method. Then, 650 in N ₂ atmosphere
Annealing at 30 ° C. for 30 minutes is performed to sufficiently degas the first interlayer insulating film 11.

Next, as shown in FIG. 3A, a SiO ₂ cap layer 12 for improving the crystallinity of the ferroelectric capacitor is formed on the first interlayer insulating film 11 by a CVD method using TEOS to a thickness of 130 nm. It is formed to a thickness. Next, in order to form a Pt / TiO ₂ stack that becomes the lower electrode layer of the ferroelectric capacitor,
First, a Ti film 13 having a thickness of 20 nm is formed on the SiO ₂ cap layer 12 by sputtering under the conditions shown in Table 1.

[0026]

[Table 1]

Subsequently, as shown in FIG.
(Rapid thermal annealing) device at 700 ℃, 6
The Ti film 13 is thermally oxidized in an O ₂ atmosphere for 0 second to turn the Ti film 13 into a TiO ₂ film 13a having a rutile crystal structure. The thickness of the TiO ₂ film 13a formed by the RTA process under such conditions is 5
0 nm. In order to form the TiO ₂ film 13a having the rutile-type crystal structure, reactive sputtering may be used, but thermal oxidation of the Ti film at a high temperature is desirable. In the production by reactive sputtering, it is necessary to heat the silicon substrate 1 at a high temperature.
Requires special sputter chamber configuration. Furthermore, oxidation using an RTA apparatus is more frequent than oxidation using a general furnace.
The crystallinity of the TiO ₂ film is improved. This is because, according to the oxidation in a normal heating furnace, a Ti film that is easily oxidized forms several crystal structures other than the rutile crystal structure at a low temperature, so that it is necessary to break it once. Therefore, oxidation by RTA with a high temperature rising rate is more advantageous for forming a good crystal.

When a nitride is used as the cap layer 12, the film quality of the Ti film 13 on the nitride tends not to be improved. Next, as shown in FIG. 3C, a 150 nm-thick Pt film, which is the lower electrode 15 of the capacitor, is formed on the TiO ₂ film 13a by a sputtering method. Table 2 shows an example of conditions for forming the lower electrode 15.

[0029]

[Table 2]

Next, as shown in FIG. 4A, a PLZT (ferroelectric) film 16 having a thickness of 180 nm is formed on the lower electrode layer 14 by sputtering under the conditions shown in Table 3.

[0031]

[Table 3]

Further, the silicon substrate 1 is placed in a mixed atmosphere of Ar and O ₂ having an O ₂ concentration of 2.5%,
The PLZT film 16, which is a ferroelectric film, is subjected to a rapid heat treatment at a rate of 125 ° C./sec from room temperature for a second. As described above, the PLZT film 16 is placed in an inert atmosphere and crystallized at a low temperature, whereby the crystals of the PLZT film 16 are preferentially oriented in a desirable <111> direction.

Next, as shown in FIG. 4B, iridium oxide (IrO ₂ ) having a thickness of 150 nm to become the upper electrode layer 17 is formed.
The PLZT film 16 was formed by sputtering under the conditions shown in Table 4.
Form on top.

[0034]

[Table 4]

Here, the reason that IrO ₂ , which is a conductive oxide, is used as the upper electrode layer 17 is to improve the hydrogen degradation resistance of the PLZT film 16, but the Pt film, SrRuO ₃ (SR
O) may be used. However, Pt is not so preferable because it easily generates hydrogen radicals due to its catalytic action on hydrogen molecules, thereby reducing and deteriorating the PLZT film 16. On the other hand, IrO ₂ and SRO do not have a catalytic action, so it is difficult to generate hydrogen radicals,
The hydrogen degradation resistance of the PLZT film 16 is significantly improved.

Then, the PLZT film 16 is subjected to a rapid heat treatment at a temperature of 725 ° C. for 20 seconds and a temperature rising rate of 125 ° C./sec by placing the silicon substrate 1 in a mixed atmosphere of Ar and O _{2 having} an O ₂ concentration of 1%. Do. As described above, first, the PLZT film 16 is
When crystallized at a low temperature of 5 ° C., the PLZT film 1
The crystal of No. 6 is oriented in the <111> direction. Furthermore, PLZ
The T film 16 is placed in a trace oxygen atmosphere and
By performing the heat treatment at 5 ° C., not only oxygen defects in the crystal lattice of PLZT film 16 are supplemented, but also PLZT
Densification of the film 16 occurs.

Incidentally, the densification of the PLZT film 16 is made of IrO ₂
If it is performed before the upper electrode layer 17 is formed, PLZ
Many bubbles in the T film 16 gather at one place, and when viewed from the surface, a pinhole is opened at the grain boundary of the PLZT film 16, which is not preferable. On the other hand, when a heat treatment for densification of the PLZT film 16 is performed after the upper electrode layer 17 of IrO ₂ is deposited, PLZT
The surface of the film 16 is prevented from being roughened, and a very flat IrO ₂
/ PLZT interface is obtained. It is also easily inferred that the interface defects are reduced. In addition, the desorption of Pb and PbO from the PLZT film 16 due to the high vapor pressure can be prevented by blocking IrO ₂ .

[0038] After densifying the PLZT film 16 is a ferroelectric film as described above, as shown in FIG. 4 (c), IrO ₂
A resist pattern 18 having a pattern of a capacitor upper electrode is formed on an upper electrode layer 17 made of
Is patterned to form an upper electrode 17a of the capacitor.
And After that, the resist pattern 18 is removed.

Next, steps required until a structure shown in FIG. First, the silicon substrate 1 was placed in an O ₂ atmosphere.
Then, annealing is performed at 650 ° C. for 60 minutes. This annealing is performed by PLZT film 1 by sputtering and etching.
It is for recovering the damage that entered 6. Subsequently, a resist pattern (not shown) having a pattern shape of a capacitor ferroelectric is formed, and the PLZT film 16 is etched using the resist pattern as a mask to form a ferroelectric film 16a of the capacitor.

After removing the resist pattern, in order to protect the ferroelectric film 16a which is easily reduced by hydrogen, a PLZT film which easily traps hydrogen is formed as the encapsulation layer 19 to a thickness of 20 nm by sputtering. Further, the encapsulation layer 19 is placed in an O ₂ atmosphere at 70
Under the condition of 0 ° C. for 60 seconds, rapid heat treatment is performed at a temperature increasing rate of 125 ° C./sec.

Thereafter, as shown in FIG. 5B, a resist pattern 20 having the pattern shape of the capacitor lower electrode is formed on the encapsulation layer 19, and the encapsulation layer 19 and the lower portion are formed using the resist pattern 20 as a mask. The electrode layer 15 and the TiO ₂ film 13a are etched, and the resulting pattern of the lower electrode layer 15 is used as the lower electrode 15a of the capacitor.

After removing the resist pattern 20, O ₂
The silicon substrate 1 is placed in an atmosphere, and recovery annealing of the ferroelectric film 16a made of PLZT is performed at 650 ° C. for 60 minutes. By the above steps, the patterned lower electrode 15a, ferroelectric film 16a and upper electrode 17a
Thereby, the capacitor C in the memory cell region is formed.

Subsequently, as shown in FIG.
After a second interlayer insulating film 21 made of SiO ₂ having a thickness of 00 nm is formed on the entire surface of the silicon substrate 1 by a CVD method to cover the capacitor C, the surface of the second interlayer insulating film 21 is planarized by CMP. Next, as shown in FIG. 6A, an opening 22 is formed on each of the impurity diffusion layers 7a and 7b and the lower electrode 20.
After a resist pattern 22 having a, 22b, and 22d is formed on the second interlayer insulating film 21, the second interlayer insulating film 21, the encap layer 19, and the SiO ₂ cap layer 12 are formed using the resist pattern 22 as a mask. , First interlayer insulating film 1
1 is dry-etched. Thereby, the capacitor C
A contact hole 21d is formed on the lower electrode 15a, and the SiO ₂ cap layer 12, the first interlayer insulating film 1
Contact holes 21a and 21b are formed to expose impurity diffusion layers 7a and 7b. After that, the resist pattern 22 is removed.

Next, as shown in FIG. 6B, the process proceeds to the step of forming conductive plugs 23a, 23b and 23d filling the contact holes 21a, 21b and 21d. In order to form the conductive plugs 23a, 23b and 23d, first, a TiN / Ti laminated film is formed in advance as an adhesion layer on the inner surfaces of the contact holes 21a, 21b and 21d and the upper surface of the second interlayer insulating film 21 by a sputtering method. . Subsequently, after a tungsten film is formed on the TiN / Ti laminated film, the tungsten film and the TiN / Ti laminated film are polished by the CMP method and removed from the upper surface of the second interlayer insulating film 21 so that their metal films are formed. Are used only as the conductive plugs 23a, 23b, and 23d while being left only in the contact holes 21a, 21b, and 21d.

Next, as shown in FIG. 6C, the conductive plugs 23a, 23b and 23d and the second interlayer insulating film 21 are formed on the conductive plugs 23a, 23b and 23d to prevent oxidation of the conductive plugs 23a, 23b and 23d. An SiON film serving as the oxidation prevention film 24 is formed to a thickness of 100 nm by a CVD method. Thereafter, as shown in FIG. 7A, an opening 2 is formed on the upper electrode 17a of the capacitor.
A resist pattern 25 having 5a is formed on the antioxidant film 24, and the antioxidant film 24, the second interlayer insulating film 21, and the encap layer 19 are dry-etched using the resist pattern 25 as a mask. 1
A contact hole 21e is formed on 7a. After that, the resist pattern 25 is removed.

Thereafter, recovery annealing of the ferroelectric film 16a is performed by annealing at 550 ° C. for 60 minutes in an O ₂ atmosphere. Next, as shown in FIG.
Of the conductive plug 23
Expose the upper ends of a, 23b and 23d. Thereafter, as shown in FIG. 7C, an aluminum film is formed in the contact hole 21e on the upper electrode 17a and on the second interlayer insulating film 21, and then, the p-well 3a is formed by patterning the aluminum film. Conductive plug 23a on impurity diffusion layer 7a on both sides of
a is formed at the same time as the conductive plug 23 on the impurity diffusion layer 7b at the center of the p-well 3a.
forming a conductive pad 26b for bit line connection on
Further, a wiring 26d connected to the conductive plug 23d on the lower electrode 15a of the capacitor C is formed.

The upper electrode 17a and the impurity diffusion layer 7a
Electrical connection may be made via a local wiring of titanium nitride (TiN), and a bit line may be formed thereon via an insulating film. Subsequently, although not shown, a third interlayer insulating film, a bit line, and a cover film are formed. If necessary, the interlayer insulating film and the wiring process may be repeated to form a multilayer wiring.

As described above, a FeRAM memory cell structure having a ferroelectric capacitor is formed. Next, the Pt film 14 constituting the lower electrode 15a of the ferroelectric capacitor
Will be described. First, the results of the investigation of the crystallinity of the Ti film will be described with reference to FIG.
The crystallinity of the TiO ₂ film obtained by oxidizing the film and the Pt film formed thereon will be described with reference to FIG.

The present inventor conducted an experiment comparing the effect of the cap layer 12 described above with a conventional process. In the experiment, after an insulating film was formed by a CVD method, a Ti film was formed on the insulating film in several process steps by sputtering to examine how the crystallinity of the Ti film was different. First,
Five types of test process (TP) wafers were formed, and the Ti (002) peak intensity on each TP wafer was examined by X-ray diffraction. The results shown in FIG. 8 were obtained.

As a reference TP wafer serving as a reference for comparison, a 200 nm thick SiON film and a 300 nm thick
After the SiO ₂ films are sequentially formed, a Ti film is sputtered on the SiO ₂ film, and the peak intensity of the (002) plane of the Ti film is set to “Refe” in FIG.
rence ", which is set to" 1 ".
Standardize the wafer. In FIG. 8, what is described as “CMP” is a 600 nm thick SiON film on a 200 nm thick SiON film.
SiO ₂ film is formed, a thickness of 300nm of SiO ₂ film C of
This is a TP wafer which is cut by an MP method and a Ti film is formed thereon. As a result, the (002) peak intensity of Ti is reduced to about 80% of the reference. This is CM
This is probably because the surface of the insulating film was roughened by the diluted hydrofluoric acid treatment used for removing the slurry after P.

In FIG. 8, “BEL-AN” is obtained by depositing a 300 nm SiO ₂ film on a 200 nm thick SiON film, and then annealing in a N ₂ atmosphere at 650 ° C. for 30 minutes. Degas the insulating film of SiO ₂ film, and then
This is a TP wafer having a Ti film formed on an SiO ₂ film. By doing so, the water in the SiO ₂ film formed by the CVD method is sufficiently removed, but the water (partial pressure of water) at the time of forming the Ti film is too low and Ti (00
2) The peak intensity seems to be considerably lower at 40% compared to the reference. This hypothesis is supported by the fact that similar results can be obtained on a thermally oxidized film having little moisture absorption. However, degassing is a necessary step before forming a ferroelectric capacitor having poor hydrogen resistance because it has an effect of desorbing hydrogen in the SiON film and the WSi gate.
Otherwise, during crystallization annealing of the PLZT film, which is a ferroelectric film, the ferroelectric capacitor will be degraded due to dehydrogenation from the underlying insulating film.

In FIG. 8, “CMP & BEL-AN” indicates that a SiON film is formed to a thickness of 200 nm, a SiO ₂ film is further formed to a thickness of 600 nm, and then the SiO ₂ film is formed.
After cutting the thickness of 00nm by CMP, in N2 atmosphere,
This is a TP wafer in which annealing is performed at 650 ° C. for 30 minutes, degassing is performed, and then a Ti film is formed on the SiO ₂ film. Then, the Ti (002) peak intensity dropped to about 20% of the reference.

In FIG. 8, "CMP & BEL-AN & SiO CA"
In the case of P ", a 200 nm SiON film is formed,
An SiO ₂ film is formed thereon with a thickness of 600 nm, and after a thickness of 300 nm of the SiO ₂ film is removed by CMP, annealing is performed in an N 2 atmosphere at 650 ° C. for 30 minutes to remove gas. perform a TP wafer formed a Ti film on the subsequently the SiO ₂ cap layer of the above embodiments on the SiO ₂ film was formed to a thickness of 130 nm, the SiO ₂ cap layer. As a result, CM
Despite the P and BEL-AN steps, the (002) peak of the Ti film was recovered to 80% of the reference. Compared with the presence or absence of the SiO ₂ cap layer, the crystallinity was improved four times.

From the above, “CMP” and “CMP &
It was found that the Ti film of “BEL-AN & SiO CAP” had the highest (002) peak. The Ti film on the TP wafer of “CMP” also had a high (002) peak, but was a base.
Since the SiO ₂ film is not degassed, it is not used as a measure for forming a good ferroelectric capacitor.

Next, the above-mentioned five TP wafer Ti film were each thermally oxidized to form a TiO ₂ film, a Pt film in the case of forming a Pt film on the TiO ₂ film (222) When the peak intensities were compared, the results shown in FIG. 9 were obtained.
The higher the (222) peak intensity of the Pt film, the better the quality of the ferroelectric film formed thereon. FIG. 9 is a graph in which the diffraction peak intensities obtained from the X-ray diffraction measurement are normalized for each of the underlying insulating films having different treatments and plotted. In addition,
Each TiO ₂ was prepared by thermally oxidizing a 20 nm Ti film at 600 ° C. for 60 minutes.

“Good TiO ₂ ” in FIG. 9 corresponds to “CMP &
A Ti film of BEL-AN & SiO CAP "After forming the TiO ₂ film by thermal oxidation, is obtained by forming a Pt film on the TiO ₂ film, the (002) peak of the pre-oxidized Ti film" 1 " And the (200) peak of the TiO ₂ film after oxidation is “1”,
Further, the (222) peak of the Pt film is set to “1”, thereby standardizing other TP wafers.

“Bad TiO ₂ ” in FIG. 9 corresponds to “BEL-
AN ”and“ CMP & BEL-AN ”
After forming the TiO ₂ film is obtained by forming a Pt film on the TiO ₂ film. “Al ₂ O ₃ ” in FIG. 9 is obtained by forming a Pt film directly on the Al ₂ O ₃ film, which will be described in the second embodiment.

FIG. 9 shows that when the (200) peak of the rutile crystal structure of TiO ₂ is weak, the Pt (222) peak is weak. The strong TiO ₂ (200) peak has a stronger Pt (222) peak than the amorphous Pt film on the Al ₂ O ₃ film.
(111) orientation is promoted. In addition, Ti (0
02) If the peak is weak, TiO
₂ It can be seen that the (200) peak is weakened.

Therefore, in order to obtain a lower electrode layer of Pt formed at a high temperature with good crystallinity, it is necessary to strengthen the (002) peak of Ti.
P & BEL-AN & SiO CAP ", that is, the process of forming the capacitor of the above embodiment is most preferable. Incidentally, the Ti on the five types of TP wafers shown in FIG.
Each film is oxidized to form a TiO ₂ film, on which a Pt film,
A ferroelectric capacitor was formed through a process of forming a PLZT film and an IrO ₂ electrode, and the polarization charge amount Q _sw and fatigue characteristics of the ferroelectric capacitor were measured. The results shown in Table 5 were obtained. Was.

According to Table 5, "Reference" and "CMP"
& BEL-AN & SiO CAP "fatigue characteristics it can be seen that the improvement according to the present embodiment is viewed from good. Fatigue characteristics, 7V, 10 ⁷ times, a positive and negative pulse is applied between the upper electrode and the lower electrode, the initial _Assuming that Q _sw is 100%, what percentage Q _sw has decreased after fatigue measurement is indicated by a value obtained by averaging three points in the wafer surface.

Table 5 shows the case where the fatigue characteristics were measured, and the Q of the ferroelectric capacitor on each TP wafer was measured.
_sw seems not to be much different, but in fact “Referenc
e ”and“ CMP & BEL-AN & SiO CAP ”TP
Q _sw of a ferroelectric capacitor formed on a wafer tends to be about ² μC / cm ² larger than that of other capacitors.

[0062]

[Table 5]

Although the embodiments have been described above, the present invention is not limited to the above-described embodiments. For example, the present invention can be applied to a case where a Pt / Ti laminated structure is used as a lower electrode. Although the case where PZT or PLZT is used as the dielectric material has been mainly described, other ferroelectric materials can also be used. For example, SBT, SBTN, etc. may be used. In the above embodiment, the case where the ferroelectric film is formed by the sputtering method is mainly described. However, another film forming method, for example, a sol-gel method or an MOCVD method can be used. It will be apparent to those skilled in the art that various other modifications, improvements, and combinations are possible.

Note that Al ₂ O ₃ may be used instead of SiO ₂ as a material for forming the cap layer 12 shown in FIG. The Al ₂ O ₃ film serving as the cap layer 12 is formed to a thickness of, for example, 20 nm by high frequency sputtering under the conditions shown in Table 6.

[0065]

[Table 6]

On such a cap layer 12 of Al ₂ O ₃
A Ti film 13 is formed, and the Ti film 13 is thermally oxidized to form a TiO ₂ film 1.
When 3a was formed, the crystallinity of the TiO ₂ film 13a on the Al ₂ O ₃ film was almost the same as that when SiO ₂ was used as the cap layer 12. (Second Embodiment) Next, the manufacturing process of a semiconductor device according to a second embodiment of the present invention will be described.

First, as shown in FIGS. 2A to 2C, a MOS transistor 8 is formed on a silicon substrate 1, a first interlayer insulating film 11 is formed thereon, and a first interlayer insulating film 11 is formed. Steps until the surface is flattened by the CMP method are the same as in the first embodiment. Subsequently, as shown in FIG. 10A, a cap layer 12a made of Al ₂ O ₃ is formed on the flattened surface of the first interlayer insulating film 11 to a thickness of 20 nm by high frequency sputtering. The sputtering conditions are the same as in Table 6, for example.

Thereafter, as shown in FIG. 10B, a 150 nm-thick Pt film having a single-layer structure is formed as the lower electrode film 14 on the cap layer 12a by sputtering instead of the Pt / TiO ₂ laminated structure. I do. The sputtering conditions are, for example, a time of 18
2 seconds, and the others are the same as in Table 2. Here, the reason why the Pt / Al ₂ O ₃ laminated structure is used instead of the Pt / TiO ₂ / SiO ₂ laminated structure as the lower electrode film 14 and its underlying structure is to improve the process stability. As described with reference to FIG. 9, Al ₂ O ₃ is originally an amorphous material, so it is not affected by the SiO ₂ film 10 underneath, and furthermore, two steps of deposition of the Ti film and oxidation of the Ti film can be shortened. There are advantages too.

After forming the Pt film, a PLZT film 16 and an upper electrode film 17 are sequentially deposited on the lower electrode film 14 in the same manner as in the first embodiment, and these films are patterned to form an upper electrode 17a, A ferroelectric film 16a is formed, and an encapsulation layer 19 is formed thereon, and then, as shown in FIG.
As shown in (1), the lower electrode film 14 is patterned to form the lower electrode 14a of the capacitor C. Subsequent steps are the same as in the first embodiment, and will not be described.

The capacitor C formed by the above steps
In order to investigate the characteristics of the lower electrode 14a,
On the Pt / TiO ₂ / SiO ₂ laminated structure adopted in the first embodiment, P
The amount of switching charge and the like when a ferroelectric capacitor is formed by forming an LZT film and an upper electrode, and a PLZT film and an upper electrode formed on a Pt / Al ₂ O ₃ stacked structure as in the present embodiment. An experiment was performed to compare the switching charge amount and the like when a ferroelectric capacitor was formed, and the results shown in Table 7 were obtained.

In the experiment, measurement was performed by applying a probe to the upper electrode 17a patterned into a 50 μm square and the lower electrode film 15 thereunder. Table 7 shows the results of the electrical characteristics of the samples according to the difference between the lower electrode structure of the first embodiment and the lower electrode structure of the second embodiment.

[0072]

[Table 7]

The first column in Table 7 shows a value obtained by averaging the switching charge amount Q _sw when 3 V is applied at five points in the wafer surface. Although the crystallinity of the Pt / Al ₂ O ₃ sample was lower as shown in FIG. 9, Q _sw was close to that of the Pt / TiO ₂ sample. Next, the second column shows the maximum value of the leakage current when 5 V is applied, similarly measured at five points on the wafer surface. Regarding leakage current,
There is no significant difference between the two samples having the lower electrode structure.

The last third column shows the results of measuring the fatigue characteristics by applying positive and negative pulses at ⁷ V and 107 times. _Assuming that the initial Q _sw is 100%, what percentage Q _sw has decreased after fatigue measurement is indicated by a value obtained by averaging three points in the wafer surface. Here, the sample of Pt / Al ₂ O ₃ has slightly better results. After all, even if a Pt / Al ₂ O ₃ structure is used, Q _sw
It has been found that the process stability can be ensured without deteriorating the fatigue characteristics. Further, the Pt film on the Al ₂ O ₃ film did not peel off.

Although PLZT was used as the ferroelectric film, other PZT or PZT-based materials, SrBi ₂ Ta ₂ O ₉ ,
Bi layered structure compounds such as SrBi ₂ (Ta, Nb) ₂ O ₉ may be used. The above-described formation of the lower electrode may also be employed in a capacitor using an oxide high dielectric material.

[0076]

As described above, according to the present invention, the CM
A step of forming an insulating film once again on the insulating film subjected to P and further degassing is performed before forming the lower electrode layer for the capacitor, so that the Ti film formed on the insulating film is (002) peak can be strengthened,
In addition, there is no possibility that Pt, which is the lower electrode layer, will be peeled off, and the crystallinity of Pt can be improved in a state where the particle size of the Pt film is as large as 100 to 150 nm. Further, in the ferroelectric film of the capacitor, since the crystal orientation in the film is aligned in a desired direction, the magnitude of the remanent polarization is maximized. That is,
A highly reliable ferroelectric capacitor can be obtained.

Further, according to another structure of the present invention, the CM
A step of forming an Al ₂ O ₃ film once again on the insulating film subjected to P is added before forming the lower electrode layer for the capacitor, and then Pt as the lower electrode layer is formed on the Al ₂ O ₃ film. By forming the film, there is no risk of Pt peeling off, and the crystallinity of Pt can be stably improved in a state where the particle diameter of the Pt film is as large as 100 to 150 nm.

[Brief description of the drawings]

FIGS. 1A and 1B are circuit diagrams of an FeRAM memory cell. FIG.

FIGS. 2A to 2C are cross-sectional views (part 1) illustrating a process of forming a memory cell of the FeRAM according to the first embodiment of the present invention.

FIGS. 3A to 3C are cross-sectional views (part 2) illustrating a process of forming a memory cell of the FeRAM according to the first embodiment of the present invention.

FIGS. 4A to 4C are cross-sectional views (part 3) illustrating a process of forming a memory cell of the FeRAM according to the first embodiment of the present invention.

FIGS. 5A to 5C are cross-sectional views (part 4) illustrating a process of forming a memory cell of the FeRAM according to the first embodiment of the present invention.

FIGS. 6A to 6C are cross-sectional views (part 5) illustrating a process of forming a memory cell of the FeRAM according to the first embodiment of the present invention.

FIGS. 7A to 7C are cross-sectional views (part 6) illustrating a process of forming a memory cell of the FeRAM according to the first embodiment of the present invention.

FIG. 8 is a diagram showing a crystal of the Ti film according to the embodiment of the present invention and a Ti film obtained by other processes.

FIG. 9 shows a Ti film, TiO according to an embodiment of the present invention.
FIG. ₂ is a view showing crystals of a Ti film, a TiO ₂ film, and a Pt film by _two films, a Pt film, and other processes.

FIGS. 10A to 10C are cross-sectional views illustrating a process of forming a memory cell of the FeRAM according to the second embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon (semiconductor) substrate, 2 ... Element isolation insulating film, 3
... Active region, 3a well, 4 gate oxide film, 5 gate electrode, 6a protective film, 6b sidewall insulating film, 7a, 7
b, 7c: impurity diffusion layer, 8: MOS transistor, 9
... anti-oxidation film, 10 ... SiO ₂ film, 11 ... interlayer insulation film, 1
2, 12a cap layer, 13 Ti film, 13a TiO
₂ film, 14, 15: lower electrode layer, 14a, 15a: lower electrode, 16: PLZT film, 16a: ferroelectric film, 17:
Upper electrode layer, 17a upper electrode, 18 resist pattern, 19 encapsulation layer, 20 resist pattern,
Reference numeral 21: interlayer insulating film, 23a, 23b, 23d: conductive plug, 24: antioxidant film, 25: resist pattern, 2
6a: wiring, 26b: pad, 26d: wiring.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tomohiro Takamatsu 4-1-1 Kamikadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Tatsuya Yokota 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 Fujitsu Limited F-term (reference) 5F083 FR02 FR03 GA27 JA15 JA17 JA38 JA40 JA42 JA43 JA45 JA56 MA06 MA18 MA20 PR21 PR22 PR34 PR40 PR43 PR53

Claims (5)

[Claims] A first insulating film formed above a semiconductor substrate and having a planarized surface; and an oxide formed on the planarized surface of the first insulating film and having a higher hydrogen content than the first insulating film. A step of forming a second insulating film made of either a silicon film or an aluminum oxide film; a titanium oxide film formed on the second insulating film; and platinum formed on the titanium oxide film A semiconductor device comprising: a capacitor lower electrode; a capacitor dielectric film formed on the capacitor lower electrode; and a capacitor upper electrode formed on the capacitor dielectric film. A first insulating film formed above the semiconductor substrate and having a planarized surface; an aluminum oxide film formed on the first insulating film; and platinum formed on the aluminum oxide film. A semiconductor device comprising: a capacitor lower electrode; a capacitor dielectric film formed on the capacitor lower electrode; and a capacitor upper electrode formed on the capacitor dielectric film. A step of forming a first insulating film above the semiconductor substrate; a step of flattening an upper surface of the first insulating film; a step of heating the first insulating film; Forming a second insulating film made of a silicon oxide film or an aluminum oxide film thereon; forming a titanium oxide film on the second insulating film; and forming a capacitor lower electrode made of platinum on the titanium oxide film Forming a dielectric film on the capacitor lower electrode, and forming a capacitor upper electrode on the dielectric film. 4. The semiconductor device according to claim 3, wherein the titanium oxide film is formed by forming a titanium film on the second insulating film and then thermally oxidizing the titanium film. Manufacturing method. 5. A step of forming a first insulating film above a semiconductor substrate, a step of flattening an upper surface of the first insulating film, a step of heating the first insulating film, and a step of heating the first insulating film. Forming a second insulating film made of aluminum oxide thereon; forming a capacitor lower electrode made of platinum on the second insulating film; forming a capacitor dielectric film on the capacitor lower electrode. Forming a capacitor upper electrode on the capacitor dielectric film.