CN1316573C - Method for producing semiconductor device - Google Patents
Method for producing semiconductor device Download PDFInfo
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- CN1316573C CN1316573C CNB028294734A CN02829473A CN1316573C CN 1316573 C CN1316573 C CN 1316573C CN B028294734 A CNB028294734 A CN B028294734A CN 02829473 A CN02829473 A CN 02829473A CN 1316573 C CN1316573 C CN 1316573C
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Abstract
The present invention relates to a method for manufacturing a semiconductor device, which comprises the following working procedures: forming first insulation films (9), (10) above a semiconductor substrate 1; forming capacitors Q having lower electrodes (11a), dielectric films (13a) and upper electrodes (14c) on the first insulation films (9), (10); forming second insulation films (15), (15a), (16) which cover the capacitors Q; after the second insulation films (15), (15a), (16) are formed, forming a stress control insulation film (30) at the back of the semiconductor substrate 1.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor device, in more detail, relate to the manufacture method of semiconductor device with electric capacity.
Background technology
Even as cut off the electricity supply still can store information nonvolatile memory, known have flash memory (Flash Memory) and a strong dielectric memory (FeRAM).
Flash memory has the floating grid in the gate insulating film that is arranged on insulated gate polar form field effect transistor (IGFET), and it is to carry out information stores by store the electric charge that becomes stored information in floating grid.The channel current that all needs by gate insulating film that writes, deletes of information flows, so need compare higher voltage.
FeRAM has the strong dielectric electric capacity that the hysteresis characteristic of utilizing strong dielectric is carried out information stores.In strong dielectric electric capacity, the strong dielectric film that between upper electrode and lower electrode, forms, and the voltage that is applied between upper electrode and the lower electrode produces polarization accordingly, if apply the polarity reversal of voltage, then the polarity of spontaneous polarization is also put upside down.Can carry out reading of information according to the polarity, the size that detect this spontaneous polarization.
FeRAM compares with flash memory has such advantage, promptly can work under low-voltage, and can save electric power and carry out writing at a high speed.
Described in document 1 (the Japan Patent spy opens the 2001-60669 communique), the memory cell of FeRAM has: be formed on the MOS transistor on the silicon substrate; Be formed on the 1st interlayer dielectric on silicon substrate and the MOS transistor; Be formed on the strong dielectric electric capacity on the 1st interlayer dielectric; Be formed on the 2nd interlayer dielectric on strong dielectric electric capacity and the 1st interlayer dielectric; The conductivity plug-in unit that be embedded in the through hole that is formed on the 1st and the 2nd interlayer dielectric, is connected with MOS transistor; The 1st Wiring pattern that the conductivity plug-in unit is connected with the upper electrode of strong dielectric electric capacity; Be formed on the 3rd interlayer dielectric on the 1st Wiring pattern and the 2nd interlayer dielectric; Be formed on the 2nd Wiring pattern on the 3rd interlayer dielectric.
But, forming with aluminium under the situation of the 1st Wiring pattern, the tensile stress of the 1st Wiring pattern can cause the deterioration of the remnant polarization characteristic of strong dielectric electric capacity.For it is improved, document 2 (the Japan Patent spy opens the 2001-36025 communique) provides a kind of technical scheme, with the temperature of Curie (curie) point of the strong dielectric film that surpass to constitute strong dielectric electric capacity the aluminium film is heated and to relax after the tensile stress, carry out pattern-forming and form Wiring pattern with the aluminium film again.
In addition, provide a kind of technical scheme in the document 3 (Japanese patent laid-open 11-330390 communique), promptly form interlayer dielectric, making becomes tensile stress with respect to strong dielectric electric capacity.
And, also provide a kind of such method in the document 4 (Japanese patent laid-open 6-188249 communique), promptly by before forming electric capacity, on the back side of substrate, form the SiN film, and this SiN film have be formed on substrate surface on composition composition and the thickness identical of SiN film with thickness, thereby suppress the bending of substrate.
According to document 1, cover the interlayer dielectric of strong dielectric electric capacity, strengthened compression (compressive) stress, the power of the direction that self will expand is provided.Therefore, on strong dielectric electric capacity, overlap to form under the situation of a plurality of interlayer dielectrics, when film forming, all increased the convergent force of strong dielectric electric capacity, make strong dielectric electric capacity deterioration.
According to document 2, owing to still have interlayer dielectric in the gap between the 1st Wiring pattern, so exist the stress regardless of the 1st Wiring pattern, the compression stress of interlayer dielectric all makes the problem of strong dielectric electric capacity deterioration.
According to document 3, can produce following other problem, promptly owing to the interlayer dielectric with tensile stress contains than juicy, owing to moisture causes strong dielectric electric capacity deterioration.
In the method for document 4,,, be difficult to carry out uniform stress adjustment owing to the deviation of the stress that puts on electric capacity in wafer (wafer) is bigger according to finding out through investigation of the present application people.
Disclosure of an invention
The object of the present invention is to provide a kind of manufacture method of semiconductor device, can be well and keep or improve the characteristic of the electric capacity that is covered by the interlayer dielectric film uniformly.
The problems referred to above, the manufacture method by a kind of semiconductor device solves, and the feature of the manufacture method of this semiconductor device is to have: the operation that forms the 1st dielectric film above semiconductor substrate; On above-mentioned the 1st dielectric film, form the operation of electric capacity with lower electrode, dielectric film and upper electrode; Form the operation of the 2nd dielectric film that covers above-mentioned electric capacity; After forming above-mentioned the 2nd dielectric film, form the operation of Stress Control dielectric film at the back side of above-mentioned semiconductor substrate.
According to the present invention, after forming the 2nd dielectric film that covers electric capacity, form the Stress Control dielectric film at the back side of substrate.For example, form the Stress Control dielectric film, make to have the compression stress identical, perhaps identical tensile stress with the 2nd dielectric film.Like this, when having relaxed the stress that produces by the 2nd dielectric film, can carry out uniform stress adjustment, consequently can realize well and uniformly keeping or improving the characteristic of electric capacity.According to the present application people's experiment, in the manufacture method of the FeRAM that the present application is applicable to capacitor insulating film with strong dielectric in, the characteristic that can realize switch-charge (ス イ ッ チ Application グ チ ャ one ジ) with and the raising of deviation.
And, owing to can reduce the stress of entire wafer, can prevent the remarkable what is called end deterioration that produces in the FeRAM of planar structure.The end deterioration is exactly and since with the common lower electrode of a plurality of electric capacity on the sidepiece stress of dielectric film of electric capacity of end concentrated, and cause the phenomenon of the easy deterioration of capacitance characteristic.This phenomenon is to produce under the situation that forms the dielectric film that forms as raw material with TEOS on the electric capacity.
In the present application, especially can give the 2nd dielectric film the compression stress identical with the Stress Control dielectric film, under this situation, dielectric film preferably few with the moisture amount, high-quality covers electric capacity.
The Stress Control dielectric film that forms at the back side of semiconductor substrate can not removed the time.Under this situation, can remove the Stress Control dielectric film after following operation, this operation is the operation that forms distribution on the 2nd dielectric film, and this distribution connects the upper electrode of electric capacity by the through hole that connects the 2nd dielectric film.This be because, by the through hole that on the 2nd dielectric film above the upper electrode of electric capacity, forms with etching method, film quality for the dielectric film that improves electric capacity, carried out the operation of annealing at high temperature, but after finishing, this annealing do not carry out the heat treatment of higher temperature, and on the 2nd dielectric film, form after the distribution, even it is also very little to have removed the variation of the temporary transient stress of adjusting of Stress Control dielectric film.
The simple declaration of accompanying drawing
Fig. 1 is the sectional view (its 1) of manufacturing process of the semiconductor device of expression the invention process form.
Fig. 2 (a), Fig. 2 (b) are the sectional views (its 2) of manufacturing process of the semiconductor device of expression the invention process form.
Fig. 3 (a), Fig. 3 (b) are the sectional views (its 3) of manufacturing process of the semiconductor device of expression the invention process form.
Fig. 4 (a), Fig. 4 (b) are the sectional views (its 4) of manufacturing process of the semiconductor device of expression the invention process form.
Fig. 5 (a), Fig. 5 (b) are the sectional views (its 5) of manufacturing process of the semiconductor device of expression the invention process form.
Fig. 6 (a), Fig. 6 (b) are the sectional views (its 6) of manufacturing process of the semiconductor device of expression the invention process form.
Fig. 7 (a), Fig. 7 (b) are the sectional views (its 7) of manufacturing process of the semiconductor device of expression the invention process form.
Fig. 8 (a), Fig. 8 (b) are the sectional views (its 8) of manufacturing process of the semiconductor device of expression the invention process form.
Fig. 9 (a), Fig. 9 (b) are the sectional views (its 9) of manufacturing process of the semiconductor device of expression the invention process form.
Figure 10 is the sectional view (its 10) of manufacturing process of the semiconductor device of expression the invention process form.
Figure 11 is the sectional view (its 11) of manufacturing process of the semiconductor device of expression the invention process form.
The plane graph of the configuration relation between Figure 12 electric capacity that to be expression formed by the manufacture method of the semiconductor device of the invention process form and transistor and distribution, the conductivity pad.
The curve chart that the switch-charge of the electric capacity of Figure 13 FeRAM that to be expression made by the manufacture method of the semiconductor device of the invention process form distributes.
The best mode that carries out an invention
Below, based on accompanying drawing form of implementation of the present invention is described.
Fig. 1～Figure 11 is the sectional view of manufacturing process of FeRAM of the planar structure of expression the invention process form.
The operation that forms structure shown in Figure 1 is described.
At first, as shown in Figure 1, (Local Oxidation of Silicon: local oxidation of silicon) method forms element separating insulation film 2 by LOCOS on silicon (semiconductor) substrate 1 surface of n type or p type.As element separating insulation film 2, except the structure that forms with the LOCOS method, can also adopt STI (Shallow Trench Isolation: shallow-trench isolation) structure.
Form after such element separating insulation film 2, on the active region (transistor formation region territory) of the memory cell region A of silicon substrate 1 and the regulation in the peripheral circuits area B, optionally import p type impurity, n type impurity, form p trap 3a and n trap 3b.And, in order to form CMOS among the circuit region B around, not only form n trap 3b, also form p trap (not shown).
Afterwards, the active regional surface of silicon substrate 1 is carried out thermal oxidation, form the silicon oxide layer that constitutes gate insulating film.
Then, form the film of amorphous silicon or polysilicon on the whole surface of the upside of silicon substrate 1, then, the ion of implanted dopant makes the silicon fiml low resistanceization.Afterwards, be the shape of regulation with photoetching process with the silicon fiml pattern-forming, and form gate electrode 5a, 5b, 5c and distribution 5d.
In memory cell region A, on 1 p trap 3a,, and on the vertical direction of the paper of accompanying drawing, extend with arranged spaced 2 gate electrode 5a, 5b of almost parallel.These gate electrodes 5a, 5b form the part of word line WL.
Then, at memory cell region A, ion injects n type impurity in the p trap 3a of the both sides of gate electrode 5a, 5b, forms 3 n type diffusion of impurities zone 6a of the source/drain that constitutes the p channel MOS transistor.Meanwhile, also form n type diffusion of impurities zone in the p trap (not shown) of circuit region B around.
Then, circuit region B around, the both sides ion of gate electrode 5c injects p type impurity among n trap 3b, forms the p type diffusion of impurities zone 6b of the source/drain that constitutes the p channel MOS transistor.
Then, on the whole surface of silicon substrate 1, form after the dielectric film, this dielectric film is carried out etching, only on the two side portions of gate electrode 5a～5c, left behind as side wall insulating film 7.As this dielectric film, for example (Chemical Vapor Deposition: chemical vapour deposition (CVD)) method forms silica (SiO by CVD
2).
And, gate electrode 5a～5c and side wall insulating film 7 are used as mask, by in p trap 3a, injecting n type foreign ion again, make n type diffusion of impurities zone 6a become the LDD structure, and, make p type diffusion of impurities zone 6b also become the LDD structure by in n trap 3b, injecting p type foreign ion again.
And the differentiation of n type impurity and p type impurity can use the resist pattern to carry out.
As mentioned above, in memory cell region A, with p trap 3a and gate electrode 5a, 5b with and the n type diffusion of impurities zone 6a of both sides etc. constitute n type MOSFET, and, around among the circuit region B, with n trap 3b and gate electrode 5c with and the p type diffusion of impurities zone 6b of both sides etc. constitute p type MOSFET.
Then, on whole, form after the film of high melting point metal film, for example Ti, Co, this high melting point metal film is heated, on the surface of n type diffusion of impurities zone 6a, p type diffusion of impurities zone 6b, form high melting point metal silicide layer 8a, 8b respectively.Afterwards, remove unreacted high melting point metal film with wet etching.
Then, use plasma CVD method, on whole of silicon substrate 1, form thick silicon oxynitride (SiON) film of about 200nm as overlay film 9.And by having adopted the plasma CVD method of TEOS gas, about thickness of growing up on overlay film 9 is the silicon dioxide (SiO of 1.0 micron thickness
2) as the 1st interlayer dielectric.Adopted the dielectric film of the plasma CVD method formation of TEOS gas to be also referred to as the PE-TEOS film below.
Then, with chemical mechanical lapping (CMP:Chemical Mechanical Polishing) method the upper surface of the 1st interlayer dielectric 10 is ground and make its planarization.
Next, the operation that forms the structure shown in Fig. 2 (a) is described.
At first, with ammonia (NH
3) plasma of gas, the surface of the 1st interlayer dielectric 10 that is flattened is improved.And, use NH
3The processing that the plasma of gas is improved the surface of dielectric film is called NH below
3Plasma treatment.
As the NH in this operation
3The condition of plasma treatment for example, can be set at: the NH that imports in the chamber
3Gas flow is 350sccm, pressure in the chamber is 1Torr, substrate temperature is 400 ℃, the power of the high frequency electric source of the 13.56MHz that supplies with to substrate is 100W, the power of the high frequency electric source of the 350KHz that supplies with to plasma generating area is 55W, distance between electrode and the 1st interlayer dielectric is 350mils, and the plasma irradiating time is 60 seconds.
Afterwards, shown in Fig. 2 (b), on the 1st interlayer dielectric 10, form the intermediate layer (auto-orientation layer) 11 that constitutes by material with the tropism that asks for.The intermediate layer for example can form with following operation.
At first, form thick titanium (Ti) film of 20nm with the DC sputtering method on the 1st interlayer dielectric 10, then, (rapid thermal annealing: rapid thermal annealing) method is carried out oxidation and is formed titanium oxide (TiO the Ti film with RTA
x) film, with this TiO
xFilm is as intermediate layer 11.
The oxidizing condition of Ti film can be set at: for example, substrate temperature is at 700 ℃, and oxidization time is 60 seconds, the oxygen (O in the oxidation environment
2) and argon (Ar) be respectively 1%, 99%.And, can will there be the Ti film of oxidation yet, former state is used as intermediate layer 11 and is used.
This intermediate layer 11, be will after the key element that improves of the orientation intensity of the 1st conducting film that forms, but also have the Pb that stops in the PZT class strong dielectric film that further is formed on the 1st conducting film function to lower floor's diffusion.In addition, intermediate layer 11 also have raising after the 1st conducting film 12 that forms and the function of the sealing between the 1st interlayer dielectric 10.
Constituting the material with the tropism that asks in intermediate layer 11, except Ti, can also be aluminium (Al), silicon (Si), copper (Cu), tantalum (Ta), tantalum nitride (TaN), iridium (Ir), yttrium oxide (IrO
x), platinum (Pt) etc.In the following form of implementation, the intermediate layer can be selected from these materials.
Below, the operation that forms the structure shown in Fig. 3 (a) is described.
At first, on intermediate layer 11, form the thick Pt film of 175nm as the 1st conducting film 12 with sputtering method.As the membrance casting condition of Pt film, can be set at: the Ar gas pressure is 0.6Pa, and DC power is 1kW, and substrate temperature is 100 ℃.Target is a platinum.
And, can also form iridium, ruthenium, ruthenium-oxide, ruthenium-oxide strontium (SrRuO as the 1st conducting film 12
3) film that waits.In this form of implementation and the following form of implementation, the 1st conducting film is to be made of the material with the tropism that asks for.
Then, use sputtering method, the PZT that forms thickness and be 100～300nm, for example 240nm on the 1st conducting film 12 is (at (Pb (Zrl-xTix) O
3) in added PLZT (the lead lanthanum zirconatetitanate: lanthanumdoped lead zirconate-lead titanate of lanthanum (La); (Pb
1-3x/2La
x) (Zr
1-yTi
y) O3)) film, it is used as strong dielectric film 13.And, on plzt film, can also add calcium (Ca) and strontium (Sr).
Then, silicon substrate 1 is placed oxygen atmosphere, make the plzt film crystallization by RTA.As the condition of this crystallization, for example can set: substrate temperature is 585 ℃, and the processing time is 20 seconds, and programming rate is 125 ℃/second, the O that imports in oxygen atmosphere
2With the ratio of Ar be 2.5% and 97.5%.
As the formation method of strong dielectric film 13, except above-mentioned sputtering method, also have rotary process, sol-gel transition method, MOD (Metal Organic De position: the metal organic deposit) method, MOCVD (metal organic chemical vapor deposition) method.In addition, except PLZT, can also be PZT, SrBi as the material of strong dielectric film 13
2(Ta
xNb
1-x)
2O
9(wherein, 0＜x≤1), Bi
4Ti
2O
12Deng.And, under the situation that forms DRAM, as long as use (BaSr) TiO
3(BST), the contour dielectric substance of strontium titanates (STO) replaces above-mentioned strong dielectric material to get final product.
Then, shown in Fig. 3 (b), on strong dielectric film 13, form the 2nd conducting film 14.The 2nd conducting film 14 can form with 2 following steps.
At first, on strong dielectric film 13, form thickness with sputtering method and be 20～75nm, for example be the yttrium oxide (IrO of 50nm
x) film is as the downside conductive layer 14a of the 2nd conducting film 14.Afterwards, in oxygen atmosphere, carry out the crystallization of strong dielectric film 13 and to the annealing in process of downside conductive layer 14a with RTA.As the condition of RTA, can be set at substrate temperature is 725 ℃, and the processing time is 1 minute, the O that imports in oxygen atmosphere simultaneously
2Be respectively 1% and 99% with the ratio of Ar.
Then, forming thickness with sputtering method on downside conductive layer 14a is 100～300nm, for example is the yttrium oxide (IrO of 200nm
x) film is as the upside conductive layer 14b of the 2nd conducting film 14.
In addition, as the upside conductive layer 14b of the 2nd conducting film 14, also can form platinum film or ruthenium-oxide strontium (SRO) film by sputtering method.
Below, the operation of the structure that forms Fig. 4 (a) is described.
At first, the resist pattern (not shown) of formation upper electrode flat shape afterwards on the 2nd conducting film 14, this resist pattern is used as mask, the 2nd conducting film 14 is carried out etching, the upper electrode 14c as electric capacity uses with the pattern of the 2nd residual conducting film 14.
And, remove after this resist pattern, at 650 ℃, under 60 minutes the condition, strong dielectric film 13 is annealed in oxygen atmosphere.This annealing in process is carried out in the sputter of the upside conductive layer 14b of the 2nd conducting film 14 and the 2nd conducting film 14 etched the time, so that recover damage that strong dielectric film 13 is caused.
Then, in memory cell region A at electric capacity upper electrode 14c and form on every side under the state of resist pattern (end diagram), strong dielectric 13 is carried out etching, like this, the strong dielectric film 13a of strong dielectric film residual below upper electrode 14c 13 as electric capacity can be used.
And, under the state of removing resist pattern (not shown) strong dielectric film 13 is being annealed in the nitrogen oxygen atmosphere.For example, this annealing for slough strong dielectric film 13 and below film on the moisture that absorbs etc. carry out.
Then, shown in Fig. 4 (b),, form the Al that thickness is 50nm at normal temperatures with sputtering method at upper electrode 14c, strong dielectric film 13a and above the 1st conducting film 12
2O
3Film is as the 1st sealant 15.The 1st sealant 15 is protected the dielectric film 13 of easy reduction with respect to hydrogen, form in order to prevent hydrogen from entering its inside.
As the 1st sealant 15, also can form PZT film, plzt film or oxidation titanium film.Al as sealant
2O
3Film, PZT film, plzt film or oxidation titanium film can also form film with mocvd method, and the stack membrane of perhaps using 2 kinds of such methods of sputtering method and mocvd method to form is also passable.The 1st sealant 15 is under the situation of stack membrane, considers the deterioration of electric capacity, and preferred elder generation forms Al with sputtering method
2O
3Film.
Afterwards, being in the oxygen atmosphere under 550 ℃, 60 minutes the condition, the 1st sealant 15 is heat-treated and the membranous of it improved.
Then, apply resist (not shown) on the 1st sealant 15, it is exposed, develops, at upper electrode 14c with above the dielectric film 13a, and the residual on every side of it is the lower electrode flat shape.And, resist film is used as mask, the 1st sealant the 15, the 1st conducting film 12 and intermediate layer 11 are carried out etching, like this pattern of the 1st residual conducting film 12 lower electrode 11a as electric capacity is used.And intermediate layer 11 also constitutes lower electrode 11a.The etching in sealant the 15, the 1st conducting film 12 and intermediate layer 11, the dryness etching of halogen that can be by having adopted chlorine element, bromo element etc. is carried out.
After removing resist, upper electrode 14c, dielectric film 13a etc. is annealed with 350 ℃, 30 minutes condition in oxygen atmosphere.Such purpose is to prevent the disengaging of the film that forms in subsequent handling.
Like this, shown in Fig. 5 (a), on the 1st interlayer dielectric 10, form the electric capacity Q that constitutes by lower electrode 11a (the 1st conducting film 12/ intermediate layer 11), dielectric film 13a, upper electrode 14c (the 2nd conducting film).
Then, describe forming the structure shown in Fig. 5 (b).
At first, form the thick Al of 20nm with sputtering method
2O
3Film is as the 2nd sealant 15a, and it covers electric capacity Q and the 1st interlayer dielectric 10.As the 2nd sealant 15a, can adopt other the material outside the material that in the 1st sealant 15, is adopted.Then, in oxygen atmosphere,, strong dielectric film 13a is annealed and from injury recovery with 650 ℃, 60 minutes condition.
Then, on sealant 15a, forming film thickness with the CVD method is the SiO of 1500nm
2Film is as the 2nd interlayer dielectric 16.The growth of the 2nd interlayer dielectric 16 can be used silane (SiH
4) and multi-silane compound (Si
2F
6, Si
3F
8, Si
2F
3Cl etc.) and SiF
4Deng as film forming gas, can also use TEOS.As the CVD method of film build method can be the energisation mode that plasma excitation (ECR method: Electron cyclotronResonance (electron cyclotron resonace method), ICP method: Inductively Coupled Plasma (inductively coupled plasma), HDP:High Density Plasma (high-density plasma), EMS:ElectronMagneto-Sonic (electronics magnetosonic)), thermal excitation, laser carry out.An example of the membrance casting condition of the 2nd interlayer dielectric 16 that has adopted plasma CVD method is shown below.
TEOS gas flow: 460sccm
He (vector gas of TEOS) flow: 480sccm
O
2Flow: 700sccm
Pressure: 9.0Torr
The frequency of high frequency electric source: 13.56MHz
The power of high frequency electric source: 400W
Film-forming temperature: 390 ℃
Then, shown in Fig. 6 (a), under the film build method and condition identical with condition with the film build method of the 2nd interlayer dielectric 16, forming by thickness at the back side of silicon substrate 1 is the SiO of 1500nm
2The Stress Control dielectric film 30 that film constitutes.
Afterwards, shown in Fig. 6 (b), the upper surface of the 2nd interlayer dielectric 16 is carried out planarization with the CMP method.The planarization on the surface of the 2nd interlayer dielectric 16, carry out up to the upper surface thickness that becomes from upper electrode 14c is 400nm.Moisture in the slurries that when carrying out planarization, use with the CMP method and after clean in moisture in the detergent remover of use, on the surface attached to the 2nd interlayer dielectric 16, perhaps be absorbed into its inside.
Therefore, the temperature with 390 ℃ in vacuum chamber (not shown) heats the 2nd interlayer dielectric 16, thereby its surface and inner moisture are discharged to the outside.Through after such processed, the 2nd interlayer dielectric 16 is heated and is exposed to N
2Dewater in the O plasma, carry out membranous improvement simultaneously.Like this, prevented the deterioration of the electric capacity that heating in subsequent handling and water cause.Such processed and plasma treatment can also be carried out in same chamber (end diagram).In this chamber, the supporting electrode of configuration carrying silicon substrate 1 with relative with it to opposite electrode, opposite electrode is in the state that can be connected with high frequency electric source.And, in chamber, imported N
2Under the state of O gas, apply high frequency voltage, between electrode, produce N at opposite electrode
2O plasma and carry out the N of dielectric film
2The O plasma treatment.According to this N
2The O plasma treatment makes and contains nitrogen in the surface at least of dielectric film.Such method can also adopt in the operation below.Though preferably use N when then processed is carried out plasma treatment
2The O plasma, but be to use NO plasma, N
2Plasma etc. also can, in the described in the back operation of this point too.And the substrate temperature of processed and the substrate temperature of plasma treatment are roughly the same.
Then, shown in Fig. 7 (a), by the photoetching process that has adopted resist pattern (not shown) the 1st interlayer dielectric the 10, the 2nd sealant 15a, the 2nd interlayer dielectric 16 and overlay film 9 are carried out etching, when on the impurity diffusion layer 6a of memory cell region A, forming contact hole 16a～16c respectively, top formation contact hole 16d, the 16e of the impurity diffusion layer 6b of circuit region B around, in addition, on the distribution 5d on the element separation insulating barrier 2, form contact hole 16f.
The 2nd interlayer dielectric the 16, the 2nd sealant the 15, the 1st interlayer dielectric 10, overlay film 9 adopts CF class gases, for example: CHF
3In added CF
4, Ar mist, carry out etching.
Then, shown in Fig. 7 (b), in order on the 2nd interlayer dielectric 16 and on the inner face of contact hole 16a～16f, to carry out aforementioned processing, after carrying out RF (high frequency) etching, on them with thick titanium (Ti) film of the continuous formation 20nm of sputtering method, titanium nitride (TiN) film that 50nm is thick, with these films as gel layer 17.And, with having used tungsten hexafluoride (WF
6), the CVD method of the mist of argon, hydrogen, formation tungsten (W) film 18 on gel layer 17.And, also use silane (SiH in the early days of growth of tungsten film 18
4) gas.Tungsten film 18 has the thickness that each contact hole 16a～16f is buried fully, for example, is 500nm on the surface, top side of gel layer 17.
Then, shown in Fig. 8 (a), remove tungsten film 18 and gel layer 17 on the 2nd interlayer dielectric 16 upper surfaces, only in each contact hole 16a～16f, have residual with the CMP method.Like this, each tungsten film 18 in contact hole 16a～16f and gel layer 17 are used as conductivity plug-in unit 17a～17f.
Afterwards, for will be in the operation of the clean processing after contact hole 16a～16f forms, CMP clean processing afterwards etc. attached to the 2nd interlayer dielectric 16 surfaces on or soak into to its inner moisture and remove, again, temperature with 390 ℃ in vacuum chamber heats the 2nd interlayer dielectric, and moisture is rejected to the outside.Carry out after such processed, the 2nd interlayer dielectric 16 is heated and is exposed to N
2In the O plasma, carry out for example 2 minutes the membranous annealing in process of improvement.
Then, shown in Fig. 8 (b), on the 2nd interlayer dielectric 16 and conductivity plug-in unit 17a～17f, form the thick SiON of about 100nm with plasma CVD method, as the oxygen-proof film 19 of tungsten.
Then, shown in Fig. 9 (a), resist pattern (not shown) is used as mask, the 2nd interlayer dielectric 16 on the upper electrode 14c and sealant 15,15a are carried out etching, form through hole 16g.Simultaneously, on the lower electrode 11a that exposes from upper electrode 14c on the bearing of trend of word line WL, also form through hole.And, at Fig. 9 (a) though in do not illustrate through hole on the lower electrode 11a, in Figure 12,20g has represented with Reference numeral.
This etching is to adopt CF class gas, for example CHF
3In added CF
4With the mist of Ar, carry out etching.Afterwards, remove the resist pattern.
Afterwards, under the state shown in Fig. 9 (a), in oxygen atmosphere, under 550 ℃ temperature, carry out 60 minutes annealing in process, the membranous of dielectric film 13a improved by through hole 16g.Under this situation, the conductivity plug-in unit 17a～17f owing to the tungsten by easy oxidation constitutes is covered by oxygen-proof film 19, so oxidation can not take place.
Then, shown in Fig. 9 (b), with etching method on the 2nd interlayer dielectric 16 and conductivity plug-in unit 17a～17f on oxygen-proof film 19 carry out etching, expose conductivity plug-in unit 17a～17f.Under this situation, expose from the 2nd interlayer dielectric 16 upper end of conductivity plug-in unit 17a～17f.
Then, under the state that conductivity plug-in unit 17a～17f and upper electrode 14c expose, with the etching (SiO of RF etching method to their the about 10nm in surface
2Convert), expose the cleaning face.
Afterwards, on the 2nd interlayer dielectric 16, conductivity plug-in unit 17a～17f, form the conducting film of 4 layers of structure that contain aluminium with sputtering method.This conducting film from counting order down is: the aluminium film of the cupric (0.5%) of the titanium nitride film of thickness 150nm, thickness 550nm, the titanium film of thickness 5nm, the titanium nitride film of thickness 150nm.
Then, as shown in figure 10, this conducting film is carried out pattern forming, thereby form the 1st～the 5th distribution 20a, 20c, 20d～20f and conductivity pad 20b with photoetching process.And, meanwhile, in through hole 20g, also form the distribution that is connected with lower electrode 11a.
In memory cell region A, the 1st distribution 20a is connected with upper electrode 14c on the side of p trap 3a by through hole 16g, and is connected with conductivity plug-in unit 17a on the nearest p trap 3a on the upper electrode 14c.The 2nd distribution 20c is connected with upper electrode 14a at the opposite side of p trap 3a by through hole 16g, and is connected with conductivity plug-in unit 17c that upper electrode 14c goes up on the nearest p trap 3a.Conductivity pad 20b above the conductivity pad 17b on the central authorities that are formed on p trap 3a, forms island.The the 3rd～the 5th distribution 20d～20f is connected with the conductivity plug-in unit 17d～17f in peripheral circuits zone.
With the configuration relation on distribution 20a, 20c, conductivity pad 20b, electric capacity and the transistorized plane of this operation formation as shown in figure 12.Figure 10 is equivalent to the sectional view along the I-I line of Figure 12.As shown in figure 12, on the lower electrode 11a that continuous band shape is extended, the also continuous band shape of dielectric film 13a is extended, devices spaced apart on a dielectric film 13a and be formed with a plurality of upper electrode 14c.With the parts that other Reference numerals are represented, the represented parts of same reference numerals are identical with using among Fig. 1～Figure 10.
Next, the operation that forms structure shown in Figure 11 is described.
At first, at the 1st～the 5th distribution 20a, 20c, 20d～20f with above the conductivity pad 20b after formation the 3rd interlayer dielectric 21, the upper surface of handling the 3rd interlayer dielectric 21 with CMP carries out planarization.
Then, use mask (not shown) on the 3rd interlayer dielectric 21, to form via hole (via hole) 22a, 22b.Via hole 22a, 22b are formed on that conductivity pad 20b on the p trap 3a of memory cell region A goes up, on the distribution 20e of peripheral circuits area B top and other the position.
And, in via hole 22a, the 22b, form the path 23a, the 23b that constitute by TiN layer and W layer.These paths 23a, 23b form like this: form after TiN layer and the W layer in via hole 22a, 22b and on the 3rd interlayer dielectric 21 with sputtering method and CVD method, remove TiN layer and W layer with the CMP processing from the 3rd interlayer insulating film 21, so residual path 23a, 23b in via hole 22a, 22b.
Then, on the 3rd interlayer dielectric 21, form after the distribution 24a～24e of the second layer, on the distribution 24a～24e of the 3rd interlayer dielectric 21 and the second layer, form the 4th interlayer dielectric 25.And, make after 25 planarizations of the 4th interlayer dielectric, on the 4th interlayer dielectric 25, form the conductive pattern 26 that constitutes by aluminium.Afterwards, on the 4th interlayer dielectric 25 and conductive pattern 26, form the 1st the 2nd covering dielectric film 28 that covers dielectric film 27 and constitute that constitutes by silica in regular turn by silicon nitride.
Afterwards, form diaphragm (not shown) from the teeth outwards with resin etc.And, under situation about need adjust, after forming diaphragm, grind (バ ッ Network グ ラ イ Application ダ) by the back and handle the back side of pruning substrate the thickness of substrate.As above, form the basic structure of FeRAM.
And, can also be with the residual and chipization of Stress Control dielectric film 30 former states, also can be after the operation of distribution 20a that forms Figure 10 etc. and conductivity pad 20b, in any operation before the operation of the substrate back of pruning with the back milled processed, can they be removed with back milled processed etc.Even under the situation of removing Stress Control dielectric film 30, because after the annealing of the membranous improvement usefulness of the dielectric film of electric capacity finishes, in the operation afterwards, the operation that higher temperature of no use is heat-treated, if and after formation such as distribution 20a, do not apply the operation of bigger stress in the later operation substantially, so can keep the stress less to substrate yet.
By the electric capacity Q that above-mentioned form of implementation forms, its characteristic makes moderate progress compared to existing technology.
Therefore, the result about the characteristic of the electric capacity Q that forms with above-mentioned form of implementation is investigated is described in detail below.And following interlayer dielectric and Stress Control dielectric film are silicon oxide film in principle.Difference according to circumstances also can be used the dielectric film of other kinds, for example silicon nitride film, oxygen silicon nitride membrane, pellumina etc.
At first, be ready to form according to the order at (S) → back side, surface (R) FeRAM of this form of implementation of the 2nd interlayer dielectric 16 and Stress Control dielectric film 30 with above-mentioned operation.And, test portion as a comparison, also prepare only to form on surface (S) interlayer dielectric FeRAM, according to the order on (S) → back side (R), surface → surface (S) form the FeRAM of thin interlayer dielectric, thick Stress Control dielectric film and thick interlayer dielectric, according to the order formation Stress Control dielectric film on the back side (R) → surface (S) and the FeRAM of interlayer dielectric.
The relatively interlayer dielectric of test portion and the film build method and the membrance casting condition of Stress Control dielectric film are identical with the film build method and the membrance casting condition of the 2nd interlayer dielectric 16 of above-mentioned form of implementation and Stress Control dielectric film 30.But, in the test portion on (S) → back side (R), surface → surface (S), though form thin interlayer dielectric and thick interlayer dielectric two membranes from the teeth outwards, the thickness of the interlayer dielectric of the one deck in the thickness of this two-layer interlayer dielectric and other the test portion is identical.
Figure 13 is the curve chart of expression at the result of switch-charge (Qsw) distribution of above-mentioned each FeRAM investigation electric capacity Q.The longitudinal axis of Figure 13 is represented accumulative total generation rate (%), and transverse axis illustrates switch-charge (Qsw) (the μ C/cm that represents with linear graduation
2).
Among the figure, zero symbol, the characteristic of the FeRAM that forms interlayer dielectric is only gone up in expression on surface (S), the symbol, expression has formed the characteristic of FeRAM of this form of implementation of interlayer dielectric and Stress Control dielectric film according to the order at surperficial (S) → back side (R) by above-mentioned operation, the △ symbol, expression forms interlayer dielectric according to the order on (S) → back side (R), surface → surface (S), the characteristic of the FeRAM of Stress Control dielectric film and interlayer dielectric, the ◇ symbol, expression forms the characteristic of the FeRAM of Stress Control dielectric film and interlayer dielectric according to the back side (the R) → order on surface (S).
According to Figure 13, under the situation of FeRAM (symbol) according to this form of implementation of the order film forming at (S) → back side, surface (R), and only compare under the situation of the FeRAM of film forming (zero symbol) from the teeth outwards, improving 1 μ C/cm
2Or its above switch-charge (Qsw) characteristic the time, deviation has been improved to 9.97% from 13%.
Under the situation of FeRAM (◇ symbol) according to the order film forming on the back side (R) → surface (S), the distribution of switch-charge (Qsw) has increased on low direction, and deviation is 36%, has worsened.
As mentioned above, manufacture method according to the semiconductor device of this form of implementation, after forming the 2nd interlayer dielectric 16 that covers electric capacity, owing on the back side of silicon substrate 1, form Stress Control dielectric film 30, so in the stress that can relax the 2nd interlayer dielectric 16, can carry out the adjustment of uniform stress.As a result, can access well and uniformly with the characteristic of the electric capacity headed by the switch-charge and to keep, perhaps can realize the raising of its characteristic.
And, owing to reduced the stress of wafer integral body, can prevent that the FeRAM of planar structure from going up the phenomenon of the significant what is called end deterioration that produces.The phenomenon that comes to this of end deterioration: since with the common lower electrode 11a of a plurality of electric capacity on the sidepiece upper stress of dielectric film of electric capacity of end concentrate, and cause the easy deterioration of capacitance characteristic.This phenomenon is to produce under the situation that forms the dielectric film that forms as raw material with TEOS on the electric capacity.
And, because as long as on Stress Control dielectric film 30, give stress with the stress same type of the 2nd interlayer dielectric 16, so do not need to carry out the adjustment of membrane stress, make owing to the moisture amount in the film becomes mutually opposite stress, but also can use the dielectric film of the high-quality that for example has compression stress, as the 2nd interlayer dielectric 16 and Stress Control dielectric film 30, the moisture amount is few simultaneously.
Above, though the present invention is had been described in detail with concrete form of implementation, but the present invention is not subjected to the qualification of the concrete shown example of above-mentioned form of implementation, and the change of in the scope that does not break away from aim of the present invention above-mentioned form of implementation being carried out is included within the scope of the present invention.
For example, in above-mentioned form of implementation, though be to be illustrated, also go under the lower electrode 11a of electric capacity, to obtain directly and the FeRAM of the stacked structure that is connected to feature between the transistor under the lower electrode 11a by the conductivity plug-in unit about the lower electrode 11a that obtains electric capacity Q with top and the FeRAM of the planar structure that is connected to feature between the transistor under the lower electrode 11a from electric capacity Q.
In addition, the film build method and the membrance casting condition of the 2nd interlayer dielectric 16 and Stress Control dielectric film 30 also can be considered laminated construction, materials used and other factors and carry out suitable selection.
In above-mentioned form of implementation, because the stress influence maximum of the 2nd interlayer dielectric 16 directly over electric capacity, so mainly be for the stress at the 2nd interlayer dielectric 16 places directly over the electric capacity being offset, making the film build method of Stress Control dielectric film 30 and membrance casting condition identical with the film build method and the membrance casting condition of the 2nd interlayer dielectric 16.But, in fact, owing to also there is the stress influence of wiring layer 20a etc. and conductivity pad 20b, the 3rd and the 4th interlayer dielectric 21,25, so the film build method of Stress Control dielectric film 30 and membrance casting condition, needn't be identical with the film build method and the membrance casting condition of the 2nd interlayer dielectric 16, can carry out suitable selection so that finally make the stress of electric capacity diminish.
Though the 2nd interlayer dielectric 16 and Stress Control dielectric film 30 are respectively the SiO with individual layer
2Film constitutes, but replaces SiO respectively
2Film also can wait with silicon nitride film, the pellumina of individual layer to constitute.
Though the 2nd interlayer dielectric 16 and Stress Control dielectric film 30 constitute with individual layer respectively, the sandwich construction more than 2 layers that also can use dielectric film or different types of dielectric film by identical type to constitute respectively constitutes.
The 2nd interlayer dielectric 16 and Stress Control dielectric film 30 form with the chemical vapor-phase growing method under the condition of 390 ℃ of film-forming temperatures, but also can be at 400 ℃ or below it, form with the chemical vapor-phase growing method of film-formable film-forming temperature condition.
According to above-mentioned the present invention, after forming the 2nd dielectric film that covers electric capacity, form the Stress Control dielectric film at the back side of substrate.Like this, when relaxing the stress that the 2nd dielectric film produces, can adjust stress uniformly, its result can realize well and uniformly keeping or improving the characteristic of electric capacity.
And, owing to can reduce the stress of wafer integral body, go up the significant so-called end deterioration that produces so can prevent the FeRAM of planar structure.
Claims (20)
1. the manufacture method of a semiconductor device is characterized in that, comprising:
Above semiconductor substrate, form the operation of the 1st dielectric film;
On above-mentioned the 1st dielectric film, form the operation of electric capacity with lower electrode, dielectric film and upper electrode;
Form the operation of the 2nd dielectric film that covers above-mentioned electric capacity;
After forming above-mentioned the 2nd dielectric film, form the operation of Stress Control dielectric film at the back side of above-mentioned semiconductor substrate.
2. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, above-mentioned the 2nd dielectric film and above-mentioned Stress Control dielectric film all have identical compression stress or identical tensile stress.
3. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, above-mentioned the 2nd dielectric film and Stress Control dielectric film have the sandwich construction more than 2 layers or 2 layers respectively.
4. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, above-mentioned the 2nd dielectric film and Stress Control dielectric film are individual layer or the sandwich constructions that includes the dielectric film of silicon.
5. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, above-mentioned the 2nd dielectric film and Stress Control dielectric film are film forming by the chemical vapor-phase growing method.
6. the manufacture method of semiconductor device as claimed in claim 5 is characterized in that, above-mentioned the 2nd dielectric film and Stress Control dielectric film are to form under the film-forming temperature below 400 ℃ or 400 ℃.
7. the manufacture method of semiconductor device as claimed in claim 5 is characterized in that, above-mentioned the 2nd dielectric film and Stress Control dielectric film are film forming under identical chemical vapor-phase growing method and the membrance casting condition.
8. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the material of the dielectric film of above-mentioned electric capacity is a strong dielectric.
9. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, before the operation that forms above-mentioned the 1st dielectric film, has the transistorized operation of formation on above-mentioned semiconductor substrate.
10. the manufacture method of semiconductor device as claimed in claim 9 is characterized in that, is formed with a plurality of electric capacity on above-mentioned lower electrode, and above-mentioned lower electrode is common for above-mentioned a plurality of electric capacity.
11. the manufacture method of semiconductor device as claimed in claim 9 is characterized in that, comprising:
The lower electrode of above-mentioned electric capacity has not the contact area that is covered by above-mentioned dielectric film and upper electrode, after forming above-mentioned the 2nd dielectric film, in the above-mentioned operation that forms the 1st through hole that connects the above-mentioned the 1st and the 2nd dielectric film above transistorized;
Above above-mentioned contact area, form the operation of the 2nd through hole that connects above-mentioned the 2nd dielectric film;
Above the upper electrode of above-mentioned electric capacity, form the operation of the 3rd through hole that connects above-mentioned the 2nd dielectric film;
On above-mentioned the 2nd dielectric film, form the operation that is connected above-mentioned lower electrode and above-mentioned transistorized distribution with the 2nd through hole by the above-mentioned the 1st;
On above-mentioned the 2nd dielectric film, form the operation that connects above-mentioned upper electrode and above-mentioned transistorized distribution by above-mentioned the 3rd through hole.
12. the manufacture method of semiconductor device as claimed in claim 10 is characterized in that, comprising:
The lower electrode of above-mentioned electric capacity has not the contact area that is covered by above-mentioned dielectric film and upper electrode, after forming above-mentioned the 2nd dielectric film, in the above-mentioned operation that forms the 1st through hole that connects the above-mentioned the 1st and the 2nd dielectric film above transistorized;
Above above-mentioned contact area, form the operation of the 2nd through hole that connects above-mentioned the 2nd dielectric film;
Above the upper electrode of above-mentioned electric capacity, form the operation of the 3rd through hole that connects above-mentioned the 2nd dielectric film;
On above-mentioned the 2nd dielectric film, form the operation that is connected above-mentioned lower electrode and above-mentioned transistorized distribution with the 2nd through hole by the above-mentioned the 1st;
On above-mentioned the 2nd dielectric film, form the operation that connects above-mentioned upper electrode and above-mentioned transistorized distribution by above-mentioned the 3rd through hole.
13. the manufacture method of semiconductor device as claimed in claim 11 is characterized in that, after the operation that forms above-mentioned electric capacity, has the operation that above-mentioned electric capacity is annealed.
14. the manufacture method of semiconductor device as claimed in claim 13, it is characterized in that, the operation that above-mentioned electric capacity is annealed, be above the upper electrode of above-mentioned electric capacity, to form after the operation of the 3rd or the 4th through hole that connects above-mentioned the 2nd dielectric film, in oxygen atmosphere, carry out by the 3rd or the 4th through hole.
15. the manufacture method of semiconductor device as claimed in claim 11 is characterized in that, after the operation that forms above-mentioned distribution, has the operation of removing above-mentioned Stress Control dielectric film.
16. the manufacture method of semiconductor device as claimed in claim 9 is characterized in that, has:
Through hole by the 1st dielectric film under the lower electrode that connects above-mentioned electric capacity connects above-mentioned lower electrode and above-mentioned transistor, after forming above-mentioned the 2nd dielectric film, above the upper electrode of above-mentioned electric capacity, form the operation of the 4th through hole that connects above-mentioned the 2nd dielectric film;
On above-mentioned the 2nd dielectric film, form the operation that connects the distribution of above-mentioned upper electrode by above-mentioned the 4th through hole.
17. the manufacture method of semiconductor device as claimed in claim 10 is characterized in that, has:
Through hole by the 1st dielectric film under the lower electrode that connects above-mentioned electric capacity connects above-mentioned lower electrode and above-mentioned transistor, after forming above-mentioned the 2nd dielectric film, above the upper electrode of above-mentioned electric capacity, form the operation of the 4th through hole that connects above-mentioned the 2nd dielectric film;
On above-mentioned the 2nd dielectric film, form the operation that connects the distribution of above-mentioned upper electrode by above-mentioned the 4th through hole.
18. the manufacture method of semiconductor device as claimed in claim 16 is characterized in that, after the operation that forms above-mentioned electric capacity, has the operation that above-mentioned electric capacity is annealed.
19. the manufacture method of semiconductor device as claimed in claim 18, it is characterized in that, the operation that above-mentioned electric capacity is annealed, be above the upper electrode of above-mentioned electric capacity, to form after the operation of the 3rd or the 4th through hole that connects above-mentioned the 2nd dielectric film, in oxygen atmosphere, carry out by the 3rd or the 4th through hole.
20. the manufacture method of semiconductor device as claimed in claim 16 is characterized in that, after the operation that forms above-mentioned distribution, has the operation of removing above-mentioned Stress Control dielectric film.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP0231485 | 2002-12-25 |
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| CN1650430A CN1650430A (en) | 2005-08-03 |
| CN1316573C true CN1316573C (en) | 2007-05-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB028294734A Expired - Fee Related CN1316573C (en) | 2002-12-25 | 2002-12-25 | Method for producing semiconductor device |
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| CN112054031B (en) * | 2019-06-06 | 2023-06-27 | 夏普株式会社 | Active matrix substrate and method for manufacturing same |
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|---|---|---|---|---|
| JPS6126227A (en) * | 1984-07-16 | 1986-02-05 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JPS63248137A (en) * | 1987-04-02 | 1988-10-14 | Nec Corp | Manufacture of semiconductor device |
| CN1115119A (en) * | 1994-06-21 | 1996-01-17 | 松下电子工业株式会社 | Semiconductor unit and manufacture of same |
| JPH11354727A (en) * | 1998-06-05 | 1999-12-24 | Toshiba Corp | Nonvolatile semiconductor memory and its manufacture |
| CN1337063A (en) * | 1999-11-22 | 2002-02-20 | 索尼株式会社 | Functional device and method of mfg. the same |
| JP2002270788A (en) * | 2001-03-14 | 2002-09-20 | Fujitsu Ltd | Semiconductor device and method of manufacturing the same |
| JP2002289793A (en) * | 2001-03-28 | 2002-10-04 | Fujitsu Ltd | Semiconductor device and method for manufacturing the same |
-
2002
- 2002-12-25 CN CNB028294734A patent/CN1316573C/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6126227A (en) * | 1984-07-16 | 1986-02-05 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JPS63248137A (en) * | 1987-04-02 | 1988-10-14 | Nec Corp | Manufacture of semiconductor device |
| CN1115119A (en) * | 1994-06-21 | 1996-01-17 | 松下电子工业株式会社 | Semiconductor unit and manufacture of same |
| JPH11354727A (en) * | 1998-06-05 | 1999-12-24 | Toshiba Corp | Nonvolatile semiconductor memory and its manufacture |
| CN1337063A (en) * | 1999-11-22 | 2002-02-20 | 索尼株式会社 | Functional device and method of mfg. the same |
| JP2002270788A (en) * | 2001-03-14 | 2002-09-20 | Fujitsu Ltd | Semiconductor device and method of manufacturing the same |
| JP2002289793A (en) * | 2001-03-28 | 2002-10-04 | Fujitsu Ltd | Semiconductor device and method for manufacturing the same |
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| CN1650430A (en) | 2005-08-03 |
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