JP2009094200A - Semiconductor device and method of manufacturing thereof - Google Patents

Semiconductor device and method of manufacturing thereof Download PDF

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JP2009094200A
JP2009094200A JP2007261987A JP2007261987A JP2009094200A JP 2009094200 A JP2009094200 A JP 2009094200A JP 2007261987 A JP2007261987 A JP 2007261987A JP 2007261987 A JP2007261987 A JP 2007261987A JP 2009094200 A JP2009094200 A JP 2009094200A
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film
conductive oxide
type conductive
oxide film
semiconductor device
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Koji Yamakawa
川 晃 司 山
Soichi Yamazaki
崎 壮 一 山
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Toshiba Corp
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Toshiba Corp
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Priority to US12/923,117 priority patent/US8062950B2/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device with improved resistance characteristic against processing damage. <P>SOLUTION: The semiconductor device has a semiconductor substrate 101, and a capacitor which is provided on the upper side of the semiconductor substrate and composed by placing a dielectric film 116 in between a lower electrode 115 and an upper electrode 117. The upper electrode has a first MOx type conductive oxide film ("M" is a metal element, "O" is an oxygen element, and x>0) 117b having a crystal structure, and a second MOx type conductive oxide film ("M" is a metal element, "O" is an oxygen element, and x>0) 117c which is formed on the first MOx type conductive oxide film, has a crystal structure, and has a smaller oxygen ratio than the first MOx type conductive oxide film. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体装置及びその製造方法に関するものである。   The present invention relates to a semiconductor device and a manufacturing method thereof.

強誘電体メモリ(FeRAM:Ferroelectric Random Access Memory)は、キャパシタ部分にPZT(Pb(ZrTi1−x)O)、BIT(BiTi12)、SBT(SrBiTa)などの強誘電体膜を用い、その残留分極を利用してデータを保持する不揮発性メモリである。強誘電体膜の成膜プロセスには半導体メモリ製造プロセスと整合性をとることができるスパッタ法、MOCVD(Metal Organic Chemical Vapor Deposition:有機金属気相成長)法、ゾルゲル法などが用いられる。 A ferroelectric memory (FeRAM: Ferroelectric Random Access Memory) is a capacitor portion PZT (Pb (Zr x Ti 1 -x) O 3), BIT (Bi 4 Ti 3 O 12), SBT (SrBi 2 Ta 2 O 9 This is a nonvolatile memory that uses a ferroelectric film such as) and retains data by utilizing the residual polarization. For the film formation process of the ferroelectric film, a sputtering method, a MOCVD (Metal Organic Chemical Vapor Deposition) method, a sol-gel method, or the like that can be consistent with the semiconductor memory manufacturing process is used.

PZT等の強誘電体は酸化物であるため、水素を主としたガスが侵入すると還元されて結晶特性が崩れ、あるいは電極界面部分に水素コンタミによる空間電荷が形成されて、強誘電体特性が劣化する。キャパシタサイズの微小化に伴い、水素による影響はより大きくなる。半導体装置の製造工程では水素を含んだ雰囲気中での処理が多いため、強誘電体膜への水素の侵入を防止する必要がある。   Since ferroelectrics such as PZT are oxides, they are reduced when a gas mainly containing hydrogen enters and the crystal characteristics are lost, or space charges due to hydrogen contamination are formed at the electrode interface, and the ferroelectric characteristics are reduced. to degrade. As the capacitor size becomes smaller, the influence of hydrogen becomes larger. Since many semiconductor device manufacturing processes are performed in an atmosphere containing hydrogen, it is necessary to prevent hydrogen from entering the ferroelectric film.

このような問題を解決するために、下部電極と、下部電極上に形成された強誘電体膜と、強誘電体膜上に形成された上部電極を備え、この上部電極は酸化物よりなる第1の層と、第1の層上に形成され酸化物よりなり第1の層より酸化の割合が高い第2の層とを有する強誘電体キャパシタが提案されている(例えば特許文献1参照)。酸化物は例えばIrOxである。   In order to solve such a problem, a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film are provided. A ferroelectric capacitor having a first layer and a second layer formed on the first layer and made of an oxide and having a higher oxidation rate than the first layer has been proposed (see, for example, Patent Document 1). . The oxide is, for example, IrOx.

この強誘電体キャパシタは、酸化の割合の高い上部電極の第2の層(上層)のプロセスダメージ耐性により、水素の侵入による強誘電体膜の特性劣化を抑制する。   This ferroelectric capacitor suppresses deterioration of the characteristics of the ferroelectric film due to hydrogen intrusion due to the process damage resistance of the second layer (upper layer) of the upper electrode having a high oxidation rate.

一方、上部電極の第1の層(下層)は酸化の割合が小さく、酸素欠損を多量に含む膜になっている。強誘電体膜と上部電極との界面における酸素欠損などの欠陥は、キャパシタ製造プロセスでの還元性プロセスダメージ耐性低下、疲労特性劣化、リテンション特性劣化、インプリント特性(一方向に書き込まれた分極がその方向で安定化する現象)劣化などの問題を引き起こし、信頼性を低下させる。
特許第3661850号明細書
On the other hand, the first layer (lower layer) of the upper electrode is a film containing a small amount of oxygen deficiency and a large amount of oxygen vacancies. Defects such as oxygen vacancies at the interface between the ferroelectric film and the upper electrode are caused by reduced resistance to reducing process damage in the capacitor manufacturing process, deterioration of fatigue characteristics, deterioration of retention characteristics, imprint characteristics (polarization written in one direction (Phenomenon that stabilizes in that direction) This causes problems such as deterioration and decreases reliability.
Japanese Patent No. 3661850

本発明はプロセスダメージ耐性を向上させ、信頼性の高い半導体装置及びその製造方法を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing the same that improve process damage resistance.

本発明の一態様による半導体装置は、半導体基板と、前記半導体基板の上方に設けられた、誘電体膜を下部電極と上部電極とで挟んでなるキャパシタと、を備え、前記上部電極は、結晶構造をなす第1のMOx型導電性酸化膜(Mは金属元素、Oは酸素元素、x>0)と、前記第1のMOx型導電性酸化膜上に形成され、結晶構造をなし、前記第1のMOx型導電性酸化膜より酸素比率が小さい第2のMOx型導電性酸化膜(Mは金属元素、Oは酸素元素、x>0)と、を有するものである。   A semiconductor device according to an aspect of the present invention includes a semiconductor substrate and a capacitor provided above the semiconductor substrate and sandwiching a dielectric film between a lower electrode and an upper electrode, and the upper electrode includes a crystal A first MOx-type conductive oxide film (M is a metal element, O is an oxygen element, x> 0) and a first MOx-type conductive oxide film having a crystal structure, And a second MOx type conductive oxide film (M is a metal element, O is an oxygen element, x> 0) having an oxygen ratio smaller than that of the first MOx type conductive oxide film.

本発明の一態様による半導体装置の製造方法は、半導体基板の上方に、キャパシタを構成する下部電極膜を形成し、前記下部電極膜上に、前記キャパシタを構成する誘電体膜を形成し、前記誘電体膜上に、金属Mのターゲットを用いた反応性スパッタ法により第1のMOx型導電性酸化膜(Mは金属元素、Oは酸素元素、x>0)を形成し、前記第1のMOx型導電性酸化膜上に、金属Mを含むターゲットを用い、前記第1のMOx型導電性酸化膜の形成時よりもAr流量に対するO流量の割合が小さいか若しくはスパッタパワーが大きい条件での反応性スパッタ法により第2のMOx型導電性酸化膜(Mは金属元素、Oは酸素元素、x>0)を形成するものである。 According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a lower electrode film constituting a capacitor above a semiconductor substrate; forming a dielectric film constituting the capacitor on the lower electrode film; A first MOx type conductive oxide film (M is a metal element, O is an oxygen element, x> 0) is formed on the dielectric film by reactive sputtering using a metal M target, and the first MOx type conductive oxide film is formed. A target containing metal M is used on the MOx type conductive oxide film, and the ratio of the O 2 flow rate to the Ar flow rate is smaller or the sputtering power is higher than when forming the first MOx type conductive oxide film. A second MOx type conductive oxide film (M is a metal element, O is an oxygen element, x> 0) is formed by the reactive sputtering method.

本発明によればプロセスダメージ耐性を向上させ、信頼性を高くすることができる。   According to the present invention, process damage resistance can be improved and reliability can be increased.

以下、本発明の実施の形態を図面に基づいて説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(第1の実施形態)図1に本発明の第1の実施形態に係る強誘電体メモリの概略構成を示す。半導体基板101上には、溝型の素子分離(図示せず)が形成されており、ゲート絶縁膜103、ワード線となるゲート電極(例えばポリシリコン膜104及びタングステンシリサイド膜105からなるポリサイド構造)、シリコン窒化膜からなるゲートキャップ膜及びゲート側壁膜106、及びソース・ドレイン拡散層102によってMOSトランジスタが形成されている。   (First Embodiment) FIG. 1 shows a schematic configuration of a ferroelectric memory according to a first embodiment of the present invention. A trench type element isolation (not shown) is formed on the semiconductor substrate 101, and a gate insulating film 103 and a gate electrode to be a word line (for example, a polycide structure including a polysilicon film 104 and a tungsten silicide film 105). A MOS transistor is formed by the gate cap film and gate sidewall film 106 made of a silicon nitride film and the source / drain diffusion layer 102.

このMOSトランジスタを取り囲むように形成された層間絶縁膜107(シリコン酸化膜)は平坦化され、さらにその上に層間絶縁膜108(シリコン酸化膜)、109(シリコン窒化膜)、及び110(シリコン酸化膜)が形成されている。   The interlayer insulating film 107 (silicon oxide film) formed so as to surround the MOS transistor is planarized, and further, the interlayer insulating films 108 (silicon oxide film), 109 (silicon nitride film), and 110 (silicon oxide film) are further formed thereon. Film) is formed.

これら層間絶縁膜107、108、109、及び110中に、MOSトランジスタのソース・ドレイン拡散層102とキャパシタのバリア層114とを接続するコンタクトプラグ111及びタングステンプラグ113が形成されている。さらにタングステンプラグ113を取り囲むように拡散防止膜(コンタクトバリア膜)112が形成されている。   In these interlayer insulating films 107, 108, 109 and 110, contact plugs 111 and tungsten plugs 113 connecting the source / drain diffusion layers 102 of the MOS transistors and the barrier layers 114 of the capacitors are formed. Further, a diffusion prevention film (contact barrier film) 112 is formed so as to surround the tungsten plug 113.

層間絶縁膜110上にキャパシタが形成される。キャパシタは、順次積層されたバリア層(キャパシタバリア膜)114、下部電極115、キャパシタ誘電体膜116、上部電極117を有する。   A capacitor is formed on interlayer insulating film 110. The capacitor includes a barrier layer (capacitor barrier film) 114, a lower electrode 115, a capacitor dielectric film 116, and an upper electrode 117 that are sequentially stacked.

さらに、キャパシタ全体を囲むように例えばAlOx膜の水素防止膜118が形成される。その上に形成された層間絶縁膜(シリコン酸化膜)120中に、隣同士のキャパシタの上部電極間を接続するためのコンタクト119が形成される。   Furthermore, a hydrogen prevention film 118 of, for example, an AlOx film is formed so as to surround the entire capacitor. A contact 119 for connecting the upper electrodes of adjacent capacitors is formed in an interlayer insulating film (silicon oxide film) 120 formed thereon.

バリア層114はTiAl膜114a及びTiAlN膜114bを含む。   The barrier layer 114 includes a TiAl film 114a and a TiAlN film 114b.

下部電極115は例えばIr膜である。また、キャパシタ誘電体膜116は例えばPZT膜である。   The lower electrode 115 is, for example, an Ir film. The capacitor dielectric film 116 is a PZT film, for example.

上部電極117は順次積層されたSRO膜(ABOxペロブスカイト型導電性酸化物(AとBは金属元素、Oは酸素元素、x>0))117a、IrOx膜(MOx型導電性酸化物(Mは金属元素、Oは酸素元素、x>0))117b、IrOx膜117cを含む。   The upper electrode 117 is an SRO film (ABOx perovskite type conductive oxide (A and B are metal elements, O is an oxygen element, x> 0)) 117a, IrOx film (MOx type conductive oxide (M is Metal element, O includes oxygen element, x> 0)) 117b, and IrOx film 117c.

IrOx膜117bはIrO結晶構造をもち、組成比では酸素リッチでO/Ir比が2より大きくなる。また密度は10.5g/cm程度であり、100A程度かそれ以下の大きさの微細粒子からなる。 The IrOx film 117b has an IrO 2 crystal structure, and is rich in oxygen in the composition ratio and has an O / Ir ratio larger than 2. The density is about 10.5 g / cm 3 and consists of fine particles having a size of about 100 A or less.

IrOx膜117b上に形成されるIrOx膜117cは、結晶性の高いIrO結晶構造をもち、組成は化学量論組成に近く、O/Ir比が2程度となる。また密度はIrOx膜117bよりも高く11.5g/cm程度で、緻密な微細構造をもつ。 The IrOx film 117c formed on the IrOx film 117b has an IrO 2 crystal structure with high crystallinity, the composition is close to the stoichiometric composition, and the O / Ir ratio is about 2. The density is higher than that of the IrOx film 117b and is about 11.5 g / cm 3 , and has a dense microstructure.

SRO膜117a上に形成するIrOx膜117bは酸素含有量が多くSRO膜117a部分あるいはSRO膜117a/PZT膜116界面に十分な酸素を供給することができる。そのため、界面に欠陥の少ない上部電極を形成できる。   The IrOx film 117b formed on the SRO film 117a has a high oxygen content and can supply sufficient oxygen to the SRO film 117a portion or the SRO film 117a / PZT film 116 interface. Therefore, an upper electrode with few defects can be formed at the interface.

これにより、分極量劣化、インプリント特性劣化、リテンション特性劣化を防止することができる。また、IrOx膜117b上に形成されるIrOx膜117cが、水素雰囲気中の処理における水素侵入をブロックし、還元性ダメージを抑制することができる。   Thereby, polarization amount deterioration, imprint characteristic deterioration, and retention characteristic deterioration can be prevented. In addition, the IrOx film 117c formed on the IrOx film 117b can block hydrogen intrusion in the treatment in the hydrogen atmosphere and suppress reductive damage.

このように本実施形態による半導体装置はプロセスダメージ耐性が向上し、信頼性の高いものとなる。   Thus, the semiconductor device according to the present embodiment has improved process damage resistance and high reliability.

次にこのような半導体装置の製造方法を図2〜図7を用いて説明する。   Next, a method for manufacturing such a semiconductor device will be described with reference to FIGS.

図2に示すように、公知のプロセスでシリコン基板201にトランジスタTを作り込み、CMOS構造を形成する。そして、CVD(化学気相成長)法及びCMP(化学的機械研磨)を用いてシリコン酸化膜202、シリコン酸化膜203、シリコン窒化膜204、シリコン酸化膜205を堆積し、層間絶縁膜を形成する。   As shown in FIG. 2, a transistor T is formed on a silicon substrate 201 by a known process to form a CMOS structure. Then, a silicon oxide film 202, a silicon oxide film 203, a silicon nitride film 204, and a silicon oxide film 205 are deposited by CVD (chemical vapor deposition) and CMP (chemical mechanical polishing) to form an interlayer insulating film. .

ここでキャパシタとトランジスタのアクティブエリア(ソース、ドレイン)との接続をタングステンやポリシリコンからなるプラグを用いて行うため、あらかじめプラグ206を形成する。   Here, in order to connect the capacitor and the active area (source, drain) of the transistor using a plug made of tungsten or polysilicon, the plug 206 is formed in advance.

プラグ206はコンタクトプラグ207、タングステンプラグ208、及びタングステンプラグ208を取り囲むように形成されるコンタクトバリア膜209からなる。プラグ206の形成にはブランケットCVD法とCMPとを併用する。   The plug 206 includes a contact plug 207, a tungsten plug 208, and a contact barrier film 209 formed so as to surround the tungsten plug 208. The formation of the plug 206 uses both blanket CVD and CMP.

図3に示すように、シリコン酸化膜205及びプラグ206上にバリア金属層300を形成する。バリア金属層300はTiAl膜301及びTiAlN膜302の積層構造となる。DCマグネトロンスパッタ法により膜厚5nmのTiAl膜301、膜厚30nmのTiAlN膜302を形成する。   As shown in FIG. 3, a barrier metal layer 300 is formed on the silicon oxide film 205 and the plug 206. The barrier metal layer 300 has a laminated structure of a TiAl film 301 and a TiAlN film 302. A TiAl film 301 having a thickness of 5 nm and a TiAlN film 302 having a thickness of 30 nm are formed by DC magnetron sputtering.

バリア金属層300は強誘電体膜の形成又はその後のキャパシタ特性確保のための酸素中アニールプロセスにおいてプラグ206表面が酸化することを防止する。   The barrier metal layer 300 prevents the surface of the plug 206 from being oxidized during the formation of the ferroelectric film or the subsequent annealing process in oxygen for securing the capacitor characteristics.

図4に示すように、バリア金属層300上に下部電極となる膜厚100nmのIr膜401をスパッタ法により形成する。   As shown in FIG. 4, an Ir film 401 having a thickness of 100 nm to be a lower electrode is formed on the barrier metal layer 300 by a sputtering method.

図5に示すように、Ir膜401上にスパッタ法を用いてキャパシタ誘電体膜となる膜厚100nmのPZT膜501を形成する。この場合、RFマグネトロンスパッタ法を用いる。ここでは、Pb量を10%程度多くしたPZTセラミックターゲットを使用する。ターゲットの組成は、Pb1.10La0.05Zr0.4Ti0.6である。PZTセラミックターゲットは、密度の高いものはスパッタ速度が大きく水分などに対する耐環境性も良好であるため、理論密度98%以上のセラミック焼結体を使用する。 As shown in FIG. 5, a 100-nm-thick PZT film 501 serving as a capacitor dielectric film is formed on the Ir film 401 by sputtering. In this case, an RF magnetron sputtering method is used. Here, a PZT ceramic target in which the amount of Pb is increased by about 10% is used. The composition of the target is Pb 1.10 La 0.05 Zr 0.4 Ti 0.6 O 3 . A high-density PZT ceramic target has a high sputtering rate and good environmental resistance against moisture and the like, and therefore a ceramic sintered body having a theoretical density of 98% or more is used.

スパッタ時には、プラズマによる基板温度の上昇や飛来粒子によるボンバードメントがあるために、Si基板からのPbの蒸発や再スパッタが起こり、膜中のPb量の欠損が生じやすい。   At the time of sputtering, since there is an increase in substrate temperature due to plasma and bombardment due to flying particles, evaporation of Pb from the Si substrate and re-sputtering easily occur, and loss of the amount of Pb in the film tends to occur.

ターゲット中の過剰Pbはそれを補償し、かつRTA(Rapid Thermal Annealing:高速熱アニール)時のPZT膜501の結晶化を促進させるために加えてある。Zr、Ti、Laなどの元素はターゲット組成とほぼ同じ量で膜に取り込まれるため、望ましい組成の量比のものを用いればよい。   Excess Pb in the target is added to compensate for this and promote crystallization of the PZT film 501 during RTA (Rapid Thermal Annealing). Since elements such as Zr, Ti, and La are incorporated into the film in substantially the same amount as the target composition, elements having a desired composition ratio may be used.

そしてRTAを使用してPZT膜501の結晶化を行う。   Then, the PZT film 501 is crystallized using RTA.

図6に示すように、PZT膜501上に上部電極600を形成する。上部電極はSRO膜601、IrOx膜602、IrO膜603の積層構造になっている。 As shown in FIG. 6, the upper electrode 600 is formed on the PZT film 501. The upper electrode has a laminated structure of an SRO film 601, an IrOx film 602, and an IrO 2 film 603.

まず、直径300mmのSROセラミックターゲットに対して、スパッタパワー1kW、室温、圧力0.5Pa、アルゴン・酸素混合ガス、酸素流量比50%の条件でDCマグネトロンスパッタを行い、膜厚10nmのSRO膜601を形成する。   First, DC magnetron sputtering was performed on an SRO ceramic target having a diameter of 300 mm under the conditions of sputtering power 1 kW, room temperature, pressure 0.5 Pa, argon / oxygen mixed gas, oxygen flow rate ratio 50%, and SRO film 601 having a film thickness of 10 nm. Form.

SRO膜601の形成後、RTO(Rapid Thermal Oxidation)等により550〜650℃にて結晶化処理を行う。   After the formation of the SRO film 601, a crystallization process is performed at 550 to 650 ° C. by RTO (Rapid Thermal Oxidation) or the like.

次に、直径300mmのIrターゲットに対して、スパッタパワー0.2kW、室温、圧力0.5Pa、アルゴン・酸素混合ガス(Ar/O=20/80)の条件でDCマグネトロンスパッタを行い、膜厚30nmのIrOx膜602を形成する。 Next, DC magnetron sputtering was performed on an Ir target having a diameter of 300 mm under the conditions of sputtering power 0.2 kW, room temperature, pressure 0.5 Pa, and argon / oxygen mixed gas (Ar / O 2 = 20/80). An IrOx film 602 having a thickness of 30 nm is formed.

IrOx膜602は高い酸素濃度(高酸素分圧)、低いスパッタリング・パワー密度にてスパッタ成膜し、酸素リッチとなるように形成する。好ましくはスパッタリング・パワー密度が0.1〜1W/cm、スパッタガス総流量中にO流量の占める割合を50%以上100%未満とする。 The IrOx film 602 is formed by sputtering with a high oxygen concentration (high oxygen partial pressure) and a low sputtering power density so as to be oxygen-rich. Preferably, the sputtering power density is 0.1 to 1 W / cm 2 , and the proportion of the O 2 flow rate in the total sputtering gas flow rate is 50% or more and less than 100%.

スパッタリング・パワー密度が0.1W/cmよりも小さいと安定して放電がたたなくなり、かつ成膜速度が非常に遅くなるため現実的でない。 If the sputtering power density is less than 0.1 W / cm 2 , it is not practical because the discharge is stably prevented and the deposition rate becomes very slow.

また、スパッタリング・パワー密度が1W/cmよりも大きいと粒径が大きくなるとともに、酸素リッチなIrOx膜を形成するために多量の酸素導入が必要となり、膜特性(膜厚、抵抗等)のばらつきが拡大する。 Further, when the sputtering power density is larger than 1 W / cm 2 , the particle size becomes large, and a large amount of oxygen needs to be introduced to form an oxygen-rich IrOx film, so that the film characteristics (film thickness, resistance, etc.) Variability increases.

続いて、IrOx膜602形成時よりも高スパッタパワーかつ酸素量を少なくした状態でIrO膜603をスパッタ成膜する。例えば、直径300mmのIrターゲットに対して、スパッタパワー2kW、室温、圧力0.5Pa、アルゴン・酸素混合ガス(Ar/O=50/50)の条件でDCマグネトロンスパッタを行い、膜厚50nmのIrO膜603を形成する。 Subsequently, an IrO 2 film 603 is formed by sputtering with a higher sputtering power and a smaller amount of oxygen than when the IrOx film 602 is formed. For example, DC magnetron sputtering is performed on an Ir target having a diameter of 300 mm under the conditions of a sputtering power of 2 kW, a room temperature, a pressure of 0.5 Pa, and an argon / oxygen mixed gas (Ar / O 2 = 50/50). An IrO 2 film 603 is formed.

IrOx膜602は熱処理後にIrO結晶構造を持ち、組成比では酸素リッチでO/Ir比が2より大きくなる。一方、IrO膜603は熱処理後に結晶性の高いIrO結晶構造を持ち、組成は化学量論組成に近く、O/Ir比は2程度となる。また、IrO膜603はIrOx膜602よりも緻密な微細構造を持ち、密度が大きい。 The IrOx film 602 has an IrO 2 crystal structure after the heat treatment, is oxygen-rich in composition ratio, and has an O / Ir ratio larger than 2. On the other hand, the IrO 2 film 603 has an IrO 2 crystal structure with high crystallinity after the heat treatment, the composition is close to the stoichiometric composition, and the O / Ir ratio is about 2. Further, the IrO 2 film 603 has a finer fine structure and a higher density than the IrOx film 602.

図7に示すように、上部電極600、PZT膜501、Ir膜401、バリア金属層300をハードマスク(図示せず)を用いてRIE加工し、キャパシタ構造を形成する。マスク除去後、キャパシタ構造を覆うように水素防止膜となるAlOx膜(例えばAl膜)701を形成する。 As shown in FIG. 7, the upper electrode 600, the PZT film 501, the Ir film 401, and the barrier metal layer 300 are RIE processed using a hard mask (not shown) to form a capacitor structure. After removing the mask, an AlOx film (for example, an Al 2 O 3 film) 701 serving as a hydrogen prevention film is formed so as to cover the capacitor structure.

その後、層間絶縁膜(シリコン酸化膜)702を形成し、層間絶縁膜702中に隣同士のキャパシタの上部電極間を接続するためのコンタクト703が形成される。   Thereafter, an interlayer insulating film (silicon oxide film) 702 is formed, and a contact 703 for connecting the upper electrodes of adjacent capacitors is formed in the interlayer insulating film 702.

IrOx膜602は酸素含有量が多く、SRO膜601部分あるいはSRO膜601/PZT膜501界面に十分な酸素を供給することが可能である。また、成膜時のスパッタパワーが低いため、SRO膜601に対する元素打ち込みなどによるスパッタダメージを小さくすることができる。これにより強誘電体膜/上部電極界面における欠陥発生を抑制することができる。   The IrOx film 602 has a high oxygen content and can supply sufficient oxygen to the SRO film 601 part or the SRO film 601 / PZT film 501 interface. Further, since the sputtering power at the time of film formation is low, sputtering damage caused by element implantation on the SRO film 601 can be reduced. As a result, generation of defects at the ferroelectric film / upper electrode interface can be suppressed.

また、緻密な微細構造を持つIrO膜603が、ハードマスクCVD成膜プロセス、キャパシタ加工RIEプロセス、還元性アニールなどによるキャパシタ劣化及び水素拡散を防止する。 Further, the IrO 2 film 603 having a fine microstructure prevents capacitor deterioration and hydrogen diffusion due to a hard mask CVD film formation process, a capacitor processing RIE process, reductive annealing, or the like.

このようにプロセスダメージ耐性が向上し、信頼性の高い半導体装置を製造することができる。   Thus, process damage resistance is improved, and a highly reliable semiconductor device can be manufactured.

上述した実施の形態は一例であって限定的なものではないと考えられるべきである。   The above-described embodiment is an example and should not be considered as limiting.

例えば図8に示すように上部電極117にSRO膜を含まず、IrO結晶構造をもち、組成比では酸素リッチでO/Ir比が2より大きくなるIrOx膜117bと、結晶性の高いIrO結晶構造をもち、組成は化学量論組成に近く、O/Ir比が2程度となり密度がIrOx膜117bよりも高く緻密な微細構造をもつIrO膜117cとの積層構造にしても良い。 For example, as shown in FIG. 8, the upper electrode 117 does not include an SRO film, has an IrO 2 crystal structure, has an oxygen rich composition, and has an O / Ir ratio greater than 2, and an IrO 2 film having high crystallinity. It may have a laminated structure with an IrO 2 film 117c having a crystal structure, a composition close to the stoichiometric composition, an O / Ir ratio of about 2, a density higher than that of the IrOx film 117b, and a fine microstructure.

PZT膜116上に酸素リッチなIrOx膜117bが形成されるため、PZT膜116と上部電極117との界面に十分な酸素が供給される。従って、酸素欠損などの欠陥の発生を防止することができ、信頼性の高い半導体装置が得られる。   Since the oxygen-rich IrOx film 117 b is formed on the PZT film 116, sufficient oxygen is supplied to the interface between the PZT film 116 and the upper electrode 117. Therefore, generation of defects such as oxygen vacancies can be prevented, and a highly reliable semiconductor device can be obtained.

上記実施形態では上部電極のMOx型導電性酸化物にIrOxを用いたが、RuOx、OsOx、RhOx、PdOxを用いるようにしても良い。   In the above embodiment, IrOx is used for the MOx type conductive oxide of the upper electrode, but RuOx, OsOx, RhOx, and PdOx may be used.

また、ABOx型導電性酸化物には、SRO(SrRuO)以外に、LNO(LaNiO)、LSCO((La,Sr)CoO)、YBCO(超伝導体)などを用いることができる。 In addition to SRO (SrRuO 3 ), LNO (LaNiO 3 ), LSCO ((La, Sr) CoO 3 ), YBCO (superconductor), or the like can be used as the ABOx type conductive oxide.

上記実施形態では図5に示すように、スパッタ法を用いてキャパシタ誘電体膜となるPZT膜を形成したが、MOCVD法を用いて成膜してもよい。MOCVD法は電極構造に対してステップカバレッジが良好であること、組成制御性に優れること、大面積に均一な高品質膜が得られること、成膜速度が速いこと、強誘電体膜の薄膜化が可能なこと(低電圧動作が可能なこと)などの利点をもつ。   In the above embodiment, as shown in FIG. 5, the PZT film to be the capacitor dielectric film is formed by sputtering, but it may be formed by MOCVD. The MOCVD method has good step coverage for the electrode structure, excellent composition controllability, a uniform high quality film can be obtained over a large area, the film formation speed is fast, and the ferroelectric film is thinned. Has the advantage that it can be operated (low voltage operation is possible).

MOCVD法に用いるPZT用原料は、代表的なもので、PbソースとしてPb(dpm)、ZrソースとしてZr(dpm)やZr(O−tC、TiソースとしてTi(O−iCやTi(O−iC(dpm)などがあり、THF(テトラハイドロフラン)や酢酸ブチルと混合することで溶液気化法として使用される。 The raw materials for PZT used in the MOCVD method are typical, Pb (dpm) 2 as the Pb source, Zr (dpm) 4 or Zr (O-tC 4 H 9 ) 4 as the Zr source, and Ti (O) as the Ti source. -iC 3 H 7) 4 and Ti (O-iC 3 H 7 ) 2 (dpm) 2 include, be used as a solution vaporization method by mixing with THF (tetrahydrofuran) and butyl acetate.

気化器の種類も多く、超音波で溶液を噴霧化するものや、熱板に溶液を吹き付けるもの、アトマイザーを利用するものなどを用いて、ソース原料の気化を行う。   There are many types of vaporizers, and the source material is vaporized using a device that atomizes the solution with ultrasonic waves, a device that sprays the solution on a hot plate, or a device that uses an atomizer.

基板温度は原料にもよるが、600℃前後が適当である。NOやOを酸化剤として同時に供給する。結晶化はIn−situで起こり、Ir膜401上にPZT<111>配向結晶膜を得ることができる。 Although the substrate temperature depends on the raw material, approximately 600 ° C. is appropriate. N 2 O and O 2 are simultaneously supplied as an oxidizing agent. Crystallization occurs in-situ, and a PZT <111> oriented crystal film can be obtained on the Ir film 401.

また、IrO膜603の形成後に500℃にてRTO処理を行っても良い。これによりIrO膜603がより緻密になり、還元性ダメージ抑制効果を増大させることができる。 Further, RTO treatment may be performed at 500 ° C. after the IrO 2 film 603 is formed. Thereby, the IrO 2 film 603 becomes denser, and the reducing damage suppressing effect can be increased.

本発明の技術的範囲は特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。   The technical scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

本発明の実施形態に係る半導体装置の概略構成図である。1 is a schematic configuration diagram of a semiconductor device according to an embodiment of the present invention. 本発明の実施形態に係る半導体装置の製造方法を説明する工程断面図である。It is process sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 同実施形態に係る半導体装置の製造方法を説明する工程断面図である。FIG. 8 is a process cross-sectional view illustrating the manufacturing method of the semiconductor device according to the embodiment. 同実施形態に係る半導体装置の製造方法を説明する工程断面図である。FIG. 8 is a process cross-sectional view illustrating the manufacturing method of the semiconductor device according to the embodiment. 同実施形態に係る半導体装置の製造方法を説明する工程断面図である。FIG. 8 is a process cross-sectional view illustrating the manufacturing method of the semiconductor device according to the embodiment. 同実施形態に係る半導体装置の製造方法を説明する工程断面図である。FIG. 8 is a process cross-sectional view illustrating the manufacturing method of the semiconductor device according to the embodiment. 同実施形態に係る半導体装置の製造方法を説明する工程断面図である。FIG. 8 is a process cross-sectional view illustrating the manufacturing method of the semiconductor device according to the embodiment. 変形例による半導体装置の概略構成図である。It is a schematic block diagram of the semiconductor device by a modification.

符号の説明Explanation of symbols

101 半導体基板
102 ソース・ドレイン拡散層
103 ゲート絶縁膜
104 ポリシリコン膜104
105 タングステンシリサイド膜
106 ゲートキャップ膜及びゲート側壁膜
107、108、109、110、120 層間絶縁膜
111 コンタクトプラグ
112 拡散防止膜
113 タングステンプラグ
114 キャパシタバリア膜
115 下部電極115
116 キャパシタ誘電体膜
117 上部電極
117a SRO膜
117b、117c IrOx膜
118 水素防止膜
119 コンタクト
101 Semiconductor substrate 102 Source / drain diffusion layer 103 Gate insulating film 104 Polysilicon film 104
105 Tungsten silicide film 106 Gate cap film and gate sidewall films 107, 108, 109, 110, 120 Interlayer insulating film 111 Contact plug 112 Diffusion prevention film 113 Tungsten plug 114 Capacitor barrier film 115 Lower electrode 115
116 Capacitor dielectric film 117 Upper electrode 117a SRO film 117b, 117c IrOx film 118 Hydrogen prevention film 119 Contact

Claims (5)

半導体基板と、
前記半導体基板の上方に設けられた、誘電体膜を下部電極と上部電極とで挟んでなるキャパシタと、を備え、
前記上部電極は、
結晶構造をなす第1のMOx型導電性酸化膜(Mは金属元素、Oは酸素元素、x>0)と、
前記第1のMOx型導電性酸化膜上に形成され、結晶構造をなし、前記第1のMOx型導電性酸化膜より酸素比率が小さい第2のMOx型導電性酸化膜(Mは金属元素、Oは酸素元素、x>0)と、
を有することを特徴とする半導体装置。
A semiconductor substrate;
A capacitor provided above the semiconductor substrate and having a dielectric film sandwiched between a lower electrode and an upper electrode;
The upper electrode is
A first MOx type conductive oxide film having a crystal structure (M is a metal element, O is an oxygen element, x>0);
A second MOx type conductive oxide film (M is a metal element, formed on the first MOx type conductive oxide film, having a crystal structure and having an oxygen ratio smaller than that of the first MOx type conductive oxide film) O is an oxygen element, x> 0),
A semiconductor device comprising:
前記上部電極は前記第1のMOx型導電性酸化膜の下方に結晶構造をなすABOx型導電性酸化膜(AとBは金属元素、Oは酸素元素、x>0)をさらに有することを特徴とする請求項1に記載の半導体装置。   The upper electrode further includes an ABOx type conductive oxide film (A and B are metal elements, O is an oxygen element, and x> 0) having a crystal structure below the first MOx type conductive oxide film. The semiconductor device according to claim 1. 前記第1のMOx型導電性酸化膜は組成比が化学量論組成比よりも大きくなる数の酸素を含有することを特徴とする請求項1又は2に記載の半導体装置。   3. The semiconductor device according to claim 1, wherein the first MOx type conductive oxide film contains a number of oxygens having a composition ratio larger than a stoichiometric composition ratio. 4. 半導体基板の上方に、キャパシタを構成する下部電極膜を形成し、
前記下部電極膜上に、前記キャパシタを構成する誘電体膜を形成し、
前記誘電体膜上に、金属Mのターゲットを用いた反応性スパッタ法により第1のMOx型導電性酸化膜(Mは金属元素、Oは酸素元素、x>0)を形成し、
前記第1のMOx型導電性酸化膜上に、前記金属Mを含むターゲットを用い、前記第1のMOx型導電性酸化膜の形成時よりもAr流量に対するO流量の割合が小さいか若しくはスパッタパワーが大きい条件での反応性スパッタ法により第2のMOx型導電性酸化膜(Mは金属元素、Oは酸素元素、x>0)を形成する半導体装置の製造方法。
Forming a lower electrode film constituting the capacitor above the semiconductor substrate;
Forming a dielectric film constituting the capacitor on the lower electrode film;
A first MOx type conductive oxide film (M is a metal element, O is an oxygen element, x> 0) is formed on the dielectric film by a reactive sputtering method using a target of metal M,
Using a target containing the metal M on the first MOx type conductive oxide film, the ratio of the O 2 flow rate to the Ar flow rate is smaller than that at the time of forming the first MOx type conductive oxide film, or sputtering is performed. A method for manufacturing a semiconductor device, wherein a second MOx type conductive oxide film (M is a metal element, O is an oxygen element, x> 0) is formed by a reactive sputtering method under a high power condition.
前記金属MはIrであることを特徴とする請求項4に記載の半導体装置の製造方法。   5. The method of manufacturing a semiconductor device according to claim 4, wherein the metal M is Ir.
JP2007261987A 2007-10-05 2007-10-05 Semiconductor device and method of manufacturing thereof Pending JP2009094200A (en)

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JPWO2013094171A1 (en) * 2011-12-22 2015-04-27 キヤノンアネルバ株式会社 Method for forming SrRuO3 film

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