JP2002289756A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing methodInfo
- Publication number
- JP2002289756A JP2002289756A JP2001087010A JP2001087010A JP2002289756A JP 2002289756 A JP2002289756 A JP 2002289756A JP 2001087010 A JP2001087010 A JP 2001087010A JP 2001087010 A JP2001087010 A JP 2001087010A JP 2002289756 A JP2002289756 A JP 2002289756A
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- Prior art keywords
- semiconductor device
- lead frame
- electrode
- lead
- semiconductor
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
- H01L2924/15159—Side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は一枚の基板に複数の
半導体素子を一括で搭載、成形し、個々に分割して複数
の半導体装置を一括で製造する一括成形型の半導体装置
およびその製造方法に関するものであり、特に二次実装
性に優れた半導体装置およびその製造方法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a batch-molded semiconductor device in which a plurality of semiconductor elements are collectively mounted on a single substrate, molded, and divided into individual parts to produce a plurality of semiconductor devices collectively. More particularly, the present invention relates to a semiconductor device having excellent secondary mountability and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】近年、半導体装置の製造においては、個
々の半導体素子に対応した配線構造を一枚の基板に複数
配した一括配線基板（支持体）を用い、その配線基板上
に半導体素子を複数個搭載、電気的な接続を行った後、
樹脂成形を一括で基板全面に行い、ダイシングブレード
を用いて個々の半導体装置に分割するという一括成形工
法を用いた半導体装置の製造方法が開発されている。2. Description of the Related Art In recent years, in the manufacture of semiconductor devices, a batch wiring board (support) in which a plurality of wiring structures corresponding to individual semiconductor elements are arranged on a single substrate is used, and the semiconductor elements are mounted on the wiring board. After mounting multiple units and making electrical connections,
2. Description of the Related Art A method of manufacturing a semiconductor device using a collective molding method has been developed in which resin molding is collectively performed on the entire surface of a substrate and divided into individual semiconductor devices using a dicing blade.
【０００３】従来の半導体装置の製造方法について図面
を参照しながら説明する。A conventional method for manufacturing a semiconductor device will be described with reference to the drawings.
【０００４】まず図７，図８は従来の半導体装置の製造
方法を示す断面図である。First, FIGS. 7 and 8 are cross-sectional views showing a conventional method for manufacturing a semiconductor device.
【０００５】まず図７（ａ）に示すように、その上面に
複数の半導体素子が個々に搭載されるもので、また上面
に個々の半導体素子に対応した配線電極が設けられ、下
面には上面の配線電極と基板内部で接続した電極が設け
られ、個々の半導体素子単位ごとに分割され得る構造の
配線基板１を用意する。そして用意した配線基板１上の
各ボンディングパッド部に複数の半導体素子２をそれぞ
れ接着剤により接着固定して搭載する。First, as shown in FIG. 7A, a plurality of semiconductor elements are individually mounted on the upper surface, wiring electrodes corresponding to the individual semiconductor elements are provided on the upper surface, and the upper surface is formed on the lower surface. A wiring board 1 having a structure in which the electrodes connected to the above wiring electrodes and inside the substrate are provided and can be divided into individual semiconductor element units is prepared. Then, a plurality of semiconductor elements 2 are mounted on the respective bonding pad portions on the prepared wiring board 1 by bonding with an adhesive.
【０００６】次に図７（ｂ）に示すように、配線基板１
上に搭載された複数の半導体素子２の電極パッド（図示
せず）と配線基板１の上面の電極とを各々、金線、アル
ミニウム線などの金属細線３により電気的に接続する。[0006] Next, as shown in FIG.
The electrode pads (not shown) of the plurality of semiconductor elements 2 mounted thereon and the electrodes on the upper surface of the wiring board 1 are electrically connected by thin metal wires 3 such as gold wires and aluminum wires.
【０００７】次に図７（ｃ）に示すように、半導体素子
２が搭載され、金属細線３で各々接続された配線基板１
の上面の端部のマージン領域や基板送り部分などを除い
た略全面を封止樹脂４で一括封止する。封止樹脂４によ
る一括成形には、金型を用いたトランスファーモールド
工法を用いる。[0007] Next, as shown in FIG. 7 (c), the wiring board 1 on which the semiconductor element 2 is mounted and which is connected to each other by the thin metal wires 3.
Substantially the entire surface excluding the margin area at the end of the upper surface of the substrate and the substrate feeding portion are sealed at once with the sealing resin 4. The transfer molding method using a mold is used for the collective molding with the sealing resin 4.
【０００８】そして図７（ｄ）に示すように、配線基板
１の封止樹脂４が形成された面側から、配線基板の個々
の分割領域ラインに対応させてウェハーダイシングで採
用している回転ブレードによる切断法を用い、回転ブレ
ード５を当接させ、切断するものである。Then, as shown in FIG. 7 (d), from the surface of the wiring substrate 1 on which the sealing resin 4 is formed, the rotation employed in wafer dicing corresponding to each divided region line of the wiring substrate. The rotary blade 5 is brought into contact with and cut by a blade cutting method.
【０００９】図７（ｅ）は回転ブレード５により個々の
半導体装置６単位に分割した状態を示している。FIG. 7E shows a state where the semiconductor device is divided into individual semiconductor devices 6 by a rotating blade 5.
【００１０】以上のように、従来は配線基板上に半導体
素子を複数個搭載、電気的な接続を行った後、樹脂成形
を一括で基板全面に行い、ダイシングブレードを用いて
個々の半導体装置に分割するという一括成形工法を用い
ていた。As described above, conventionally, after mounting a plurality of semiconductor elements on a wiring board and making an electrical connection, resin molding is collectively performed on the entire surface of the board, and a dicing blade is used to form individual semiconductor devices. The batch molding method of dividing was used.
【００１１】次に従来の一括成形によって製造された半
導体装置について図面を参照しながら説明する。図８は
従来のＢＧＡ（ボール・グリッド・アレイ）型の半導体
装置を示す断面図である。Next, a conventional semiconductor device manufactured by batch molding will be described with reference to the drawings. FIG. 8 is a sectional view showing a conventional BGA (ball grid array) type semiconductor device.
【００１２】図８に示すように、従来の半導体装置は、
底面に導電性材料による半田ボールなどのボール電極を
備えたものであって、上面に電極と、下面にその上面の
電極と接続した電極を有した配線基板１と、配線基板１
の上面に搭載された半導体素子２と、その半導体素子２
の電極パッドと配線基板１の上面の電極とを電気的に接
続した接続部材である金属細線３と、配線基板１の上面
の半導体素子２、金属細線３の外囲を封止した封止樹脂
４とよりなり、配線基板１の底面の電極上にはボール電
極７が形成されてＢＧＡ型の半導体装置を構成している
ものである。[0012] As shown in FIG.
A wiring board 1 having a ball electrode such as a solder ball made of a conductive material on a bottom surface, having an electrode on an upper surface, and an electrode connected to an electrode on the upper surface on a lower surface;
Element 2 mounted on the upper surface of the semiconductor device, and the semiconductor element 2
Metal wire 3 which is a connection member electrically connecting the electrode pad of FIG. 1 with the electrode on the upper surface of the wiring board 1, and the sealing resin which seals the outer periphery of the semiconductor element 2 and the metal fine wire 3 on the upper surface of the wiring board 1. 4, a ball electrode 7 is formed on an electrode on the bottom surface of the wiring board 1 to constitute a BGA type semiconductor device.
【００１３】[0013]
【発明が解決しようとする課題】しかしながら従来の半
導体装置では、図９の断面図に示すように、配線基板１
の底面の端部には、一括成形時のダイシングブレードの
切断によって形成されたカエリ部８が形成されてしま
い、半導体装置をプリント基板などの二次実装基板に実
装（二次実装）する際、突起物であるカエリ部８が半導
体装置の底面に突出するため、実装上の障害となってい
た。なお、カエリ部８は、分割切断時の回転ブレードの
回転によって配線基板を構成する材料、例えば樹脂など
の基板材料、基板内に内層されている配線材料、基板底
面の配線電極材料などが巻き上げられたり、または高速
回転で溶融し、切断面とブレードとの間にはみ出して残
存することにより発生する所謂、製造上の異物（突起
物）である。特にカエリ部８の影響は、配線基板１の底
面に設けたボール電極７と実装基板上の電極とを接続す
る際、半田ブリッジや、接続不良を誘発し、二次実装上
の課題となっていた。However, in the conventional semiconductor device, as shown in the sectional view of FIG.
The burrs 8 formed by cutting the dicing blade at the time of collective molding are formed at the end of the bottom surface of the semiconductor device. When the semiconductor device is mounted on a secondary mounting board such as a printed board (secondary mounting), The burrs 8 as protrusions protrude from the bottom surface of the semiconductor device, which is an obstacle to mounting. Note that the burrs 8 are wound up by rotating the rotary blade at the time of split cutting, for example, a substrate material such as a resin, a wiring material layered in the substrate, a wiring electrode material on the bottom surface of the substrate, and the like. This is a so-called foreign matter (protrusion) in manufacturing that is generated by being melted or melted by high-speed rotation and protruding and remaining between the cut surface and the blade. In particular, the influence of the burrs 8 causes solder bridges and connection failures when connecting the ball electrodes 7 provided on the bottom surface of the wiring board 1 to the electrodes on the mounting board, and is a problem in secondary mounting. Was.
【００１４】このような一括成形時のカエリ部に対し
て、従来は配線基板部分を切断するブレードと、封止樹
脂部を切断するブレードとを、その材質、幅、形状など
種類を分けて使用し、「２度切り」により分割したり、
発生したカエリ部を後工程として除去するなどの対策が
行われていた。しかし後工程で除去するにしても、また
２種類のブレードで「２度切り」をするにしても製造上
のコストがかかり、工程数としても増大するため、より
良い製造方法が望まれていた。Conventionally, a blade for cutting the wiring board portion and a blade for cutting the sealing resin portion are used for the burrs at the time of the collective molding by dividing the material, width, shape and the like into different types. And split it by "cut twice"
Measures have been taken to remove the generated burrs as a post-process. However, even if it is removed in a post-process, or "cut twice" with two types of blades, the manufacturing cost is increased and the number of processes is increased, so a better manufacturing method has been desired. .
【００１５】本発明は、前記した従来の課題を解決する
ものであり、一括成形工法を用いた半導体装置の製造工
法において、カエリ部の影響を解消した半導体装置およ
びその製造方法を提供することを目的とする。An object of the present invention is to solve the above-mentioned conventional problems, and to provide a semiconductor device in which the influence of a flash portion is eliminated in a semiconductor device manufacturing method using a batch molding method, and a method of manufacturing the same. Aim.
【００１６】[0016]
【課題を解決するための手段】前記従来の課題を解決す
るために本発明の半導体装置は、リードフレームのダイ
パッド部上に搭載された半導体素子と、前記半導体素子
の電極パッドとリードフレームの電極リードとを電気的
に接続した接続部材と、前記リードフレームの少なくと
もダイパッド部、電極リードの底面を除いて前記半導体
素子、前記接続部材の外囲を封止した封止樹脂とよりな
る半導体装置であって、前記リードフレームの電極リー
ドの外方側面は前記封止樹脂の側面と同一面に露出し、
前記電極リード底面の端部は断面方向にテーパー部を有
している半導体装置である。In order to solve the above-mentioned conventional problems, a semiconductor device according to the present invention comprises a semiconductor element mounted on a die pad portion of a lead frame, an electrode pad of the semiconductor element and an electrode of the lead frame. A semiconductor device comprising: a connection member electrically connected to a lead; and at least a die pad portion of the lead frame, the semiconductor element except for a bottom surface of the electrode lead, and a sealing resin that seals an outer periphery of the connection member. The outer side surface of the electrode lead of the lead frame is exposed on the same surface as the side surface of the sealing resin,
An end of the bottom surface of the electrode lead is a semiconductor device having a tapered portion in a sectional direction.
【００１７】そして具体的には、電極リードの底面の端
部のテーパー部には、カエリ部が形成され、前記カエリ
部の高さは前記電極リードの底面を超えない高さである
半導体装置である。More specifically, in the semiconductor device, a burring portion is formed at a tapered portion at the end of the bottom surface of the electrode lead, and the height of the burring portion does not exceed the bottom surface of the electrode lead. is there.
【００１８】前記構成の通り、本発明の半導体装置は、
リードフレームの電極リード底面の外方の端部は断面方
向にテーパー部を有し、そのテーパー部には、カエリ部
が残存して形成され、カエリ部の高さは電極リードの底
面を超えない高さであるため、半導体装置を実装基板に
二次実装する際、半田ブリッジや、接続不良を解消でき
るものである。すなわち本発明の半導体装置では、たと
え製造過程でのカエリ部が残存していたとしても基板の
リード端部のテーパー部にカエリ部が位置し、高さがリ
ード底面を超えないため、実装上、何ら問題が起こらな
いようにしたものである。As described above, the semiconductor device of the present invention comprises:
The outer end of the bottom surface of the electrode lead of the lead frame has a tapered portion in the cross-sectional direction, and a burrow portion is formed on the tapered portion, and the height of the burring portion does not exceed the bottom surface of the electrode lead. Because of the height, when the semiconductor device is secondarily mounted on a mounting board, solder bridges and connection failures can be eliminated. That is, in the semiconductor device of the present invention, even if the burrs in the manufacturing process remain, the burrs are located at the tapered portion of the lead end of the substrate, and the height does not exceed the bottom of the lead. This is to avoid any problems.
【００１９】本発明の半導体装置の製造方法は、そのダ
イパッド部上面に複数の半導体素子が個々に搭載され、
個々の半導体素子に対応した電極リードが設けられ、個
々の半導体素子単位ごとに分割され得る構造のリードフ
レームであって、前記リードフレームの個々の半導体素
子単位ごとに分割する際の分割箇所のリードフレームの
少なくとも下面に凹部が設けられたリードフレームを用
意する工程と、前記リードフレームのダイパッド部に複
数の半導体素子をそれぞれ搭載する工程と、前記リード
フレームに搭載された複数の半導体素子の電極パッドと
前記リードフレームの電極リードとを接続部材で各々電
気的に接続する工程と、前記リードフレームの上面の略
全面を封止樹脂で一括封止する工程と、前記リードフレ
ームの封止樹脂が形成された面側または前記リードフレ
ーム裏面側から、前記リードフレームに設けられた凹部
に対応させてブレードを当接させ、個々の半導体素子単
位に分割して半導体装置を得る工程とよりなる半導体装
置の製造方法である。According to the method of manufacturing a semiconductor device of the present invention, a plurality of semiconductor elements are individually mounted on the upper surface of the die pad portion,
An electrode lead corresponding to each semiconductor element is provided, and the lead frame has a structure that can be divided for each individual semiconductor element unit. A step of preparing a lead frame provided with a concave portion on at least the lower surface of the frame; a step of mounting a plurality of semiconductor elements on a die pad portion of the lead frame; and an electrode pad of the plurality of semiconductor elements mounted on the lead frame Electrically connecting the lead frame and the electrode leads of the lead frame with a connecting member; sealing substantially the entire upper surface of the lead frame with a sealing resin; and forming the sealing resin of the lead frame. From the side of the lead frame or the back of the lead frame corresponding to the recess provided in the lead frame. Is brought into contact with de, a method of manufacturing a more becomes a semiconductor device and to obtain a semiconductor device is divided into individual semiconductor elements units.
【００２０】そして具体的には、凹部はリードフレーム
の電極リードの下面に設けられている半導体装置の製造
方法である。More specifically, this is a method for manufacturing a semiconductor device in which the concave portion is provided on the lower surface of the electrode lead of the lead frame.
【００２１】また、凹部は断面形状でＶ型の凹部である
半導体装置の製造方法である。Further, in the method of manufacturing a semiconductor device, the concave portion is a V-shaped concave portion in cross section.
【００２２】また、凹部は断面形状でＵ型の凹部である
半導体装置の製造方法である。In the method for manufacturing a semiconductor device, the concave portion is a U-shaped concave portion in cross section.
【００２３】また、凹部は当接するブレードの幅よりも
広い幅の凹部である半導体装置の製造方法である。Further, in the method of manufacturing a semiconductor device, the concave portion is a concave portion having a width larger than the width of the blade to be in contact with.
【００２４】また、ブレードは１種類の回転ブレードを
用いる半導体装置の製造方法である。The blade is a method of manufacturing a semiconductor device using one kind of rotating blade.
【００２５】また、接続部材は金属細線を用いる半導体
装置の製造方法である。In the method of manufacturing a semiconductor device using a thin metal wire as a connecting member.
【００２６】前記構成の通り、本発明の半導体装置の製
造方法は、リードフレームの個々の半導体素子単位ごと
に分割する際の分割箇所のリード下面に凹部が設けられ
たリードフレームを用い、個々の半導体装置への分割時
は、凹部に対応させてブレードを当接させ、個々の半導
体素子単位に分割するため、回転ブレードによるカエリ
部は凹部内に形成され、切断分離後は、リードの正規の
底面にはカエリ部には形成されないので、半導体装置と
して二次実装上、何ら問題が起こらないようにしたもの
である。特にリードの切断箇所に設ける凹部は当接する
ブレードの幅よりもその凹部幅を大きくしているので、
カエリ部は確実に凹部内に形成され、リード面への突出
を防止できるものである。したがって１種類のブレード
で一括成形品を切断することができるものである。As described above, the method of manufacturing a semiconductor device according to the present invention uses a lead frame in which a concave portion is provided on the lower surface of the lead at the division point when dividing the semiconductor device into individual semiconductor elements. At the time of division into semiconductor devices, blades are brought into contact with the concave portions to divide the semiconductor devices into individual semiconductor elements, so that the burrs formed by the rotating blades are formed in the concave portions. Since no burrs are formed on the bottom surface, no problems occur in secondary mounting as a semiconductor device. In particular, since the concave portion provided at the cutting portion of the lead has a larger concave portion width than the width of the abutting blade,
The burrs are surely formed in the recesses, and can prevent the protrusions on the lead surface. Therefore, the batch molded product can be cut with one kind of blade.
【００２７】[0027]
【発明の実施の形態】以下、本発明の半導体装置および
その製造方法の一実施形態について、説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor device and a method for manufacturing the same according to the present invention will be described below.
【００２８】本実施形態の半導体装置の製造方法は、主
として、その上面に複数の半導体素子が個々に搭載され
るもので、また個々の半導体素子に対応した電極、リー
ドが設けられ、個々の半導体素子単位ごとに分割され得
る構造の基板などの支持体であって、その支持体の個々
の半導体素子単位ごとに分割する際の分割箇所の支持体
下面に凹部が設けられた支持体を用意する工程と、その
支持体上の対応した箇所に複数の半導体素子をそれぞれ
搭載する工程と、その支持体上に搭載された複数の半導
体素子の電極パッドと支持体上の電極またはリードとを
金属細線、突起電極（バンプ）などの接続部材で各々電
気的に接続する工程と、その支持体の上面の実効的なほ
ぼ全面を封止樹脂で一括封止する工程と、その支持体の
封止樹脂が形成された面側、または支持体の支持体裏面
側から、支持体に設けられた凹部に対応させてブレード
を当接させ、個々の半導体素子単位に分割して半導体装
置を得る工程とよりなるものであり、支持体の切断箇所
に設けられた凹部は断面形状でＶ型，Ｕ型の凹部であ
り、さらに当接するブレードの幅よりも広い幅の凹部で
ある。The method of manufacturing a semiconductor device according to the present embodiment mainly includes a method in which a plurality of semiconductor elements are individually mounted on the upper surface, and electrodes and leads corresponding to the individual semiconductor elements are provided. Prepare a support such as a substrate having a structure that can be divided for each element unit, and provided with a concave portion on the lower surface of the support at the division point when dividing the support for each individual semiconductor element unit. A step of mounting a plurality of semiconductor elements at corresponding locations on the support, and a step of mounting a plurality of semiconductor element electrode pads mounted on the support and electrodes or leads on the support using thin metal wires. A step of electrically connecting each with a connection member such as a bump electrode (bump), a step of collectively sealing substantially the entire effective upper surface of the support with a sealing resin, and a sealing resin of the support. Formed From the side of the support, or from the back side of the support of the support, the blade is brought into contact with the recess provided in the support, and the semiconductor device is divided into individual semiconductor element units to obtain a semiconductor device. In addition, the concave portion provided at the cut portion of the support is a V-shaped or U-shaped concave portion in cross-sectional shape, and is a concave portion having a width wider than the width of the blade to be abutted.
【００２９】次に本実施形態の具体的な例について図面
を参照しながら説明する。Next, a specific example of this embodiment will be described with reference to the drawings.
【００３０】まず第１の実施形態の半導体装置の製造方
法について説明する。第１の実施形態ではＢＧＡ型の半
導体装置の製造方法について説明する。First, a method of manufacturing the semiconductor device according to the first embodiment will be described. In the first embodiment, a method for manufacturing a BGA type semiconductor device will be described.
【００３１】図１，図２は本実施形態の半導体装置の製
造方法を示す工程ごとの主要な断面図である。FIG. 1 and FIG. 2 are main cross-sectional views for each step showing a method for manufacturing a semiconductor device of this embodiment.
【００３２】まず図１（ａ）に示すように、その上面に
複数の半導体素子が個々に搭載されるもので、また上面
に個々の半導体素子に対応した配線電極（図示せず）が
設けられ、下面には上面の配線電極と基板内部で接続し
た端子電極（図示せず）が設けられ、個々の半導体素子
単位ごとに分割され得る構造の配線基板９を用意する。
ここでは、配線基板９の個々の半導体素子単位ごとに分
割する際の分割箇所の基板下面に凹部１０が設けられた
配線基板９を用意する。本実施形態では基板の上下面に
凹部１０を設けたものを用いている。また、基板に設け
る凹部１０について、凹部形状は断面形状でＶ型，Ｕ型
の凹部であり、本実施形態ではＶ型の凹部を採用してい
る。また凹部１０は後工程で使用するブレードの幅より
も広い幅の例えば１００［μｍ］幅、深さ３０［μｍ］
の凹部とする。なお本実施形態では、多層の樹脂基板を
用いているが、配線基板９としては単層、多層基板のい
ずれでもよく、セラミック基板、樹脂基板、フィルム基
板などのいずれでもよい。First, as shown in FIG. 1A, a plurality of semiconductor elements are individually mounted on the upper surface, and wiring electrodes (not shown) corresponding to the individual semiconductor elements are provided on the upper surface. The lower surface is provided with terminal electrodes (not shown) connected to the upper surface wiring electrodes inside the substrate, and a wiring substrate 9 having a structure that can be divided for each semiconductor element unit is prepared.
Here, a wiring substrate 9 having a concave portion 10 provided on the lower surface of the substrate at the division location when dividing the wiring substrate 9 into individual semiconductor element units is prepared. In the present embodiment, a substrate provided with a concave portion 10 on the upper and lower surfaces is used. Further, the concave portion 10 provided on the substrate has a V-shaped or U-shaped concave portion in cross-sectional shape, and the present embodiment employs a V-shaped concave portion. The recess 10 has a width, for example, 100 [μm] and a depth of 30 [μm] wider than the width of a blade used in a subsequent process.
Recess. In this embodiment, a multilayer resin substrate is used, but the wiring substrate 9 may be a single-layer or multilayer substrate, or may be a ceramic substrate, a resin substrate, a film substrate, or the like.
【００３３】次に図１（ｂ）に示すように、そして用意
した配線基板９上の各ボンディングパッド部に相当する
箇所に複数の半導体素子１１をそれぞれ接着剤により接
着固定して搭載する。Next, as shown in FIG. 1B, a plurality of semiconductor elements 11 are mounted on the prepared wiring board 9 at positions corresponding to the respective bonding pad portions by bonding with an adhesive.
【００３４】次に図１（ｃ）に示すように、配線基板９
上に搭載された複数の半導体素子１１の電極パッド（図
示せず）と配線基板９の上面の電極とを各々、金線、ア
ルミニウム線などの金属細線１２により電気的に接続す
る。この場合、接続部材として金属細線１２の代わりに
金バンプなどの突起電極を用い、半導体素子１１をフェ
ースダウン（フリップチップ）で接続してもよい。Next, as shown in FIG.
The electrode pads (not shown) of the plurality of semiconductor elements 11 mounted thereon and the electrodes on the upper surface of the wiring board 9 are electrically connected by thin metal wires 12 such as gold wires and aluminum wires. In this case, the semiconductor element 11 may be connected face down (flip chip) by using a protruding electrode such as a gold bump instead of the thin metal wire 12 as the connecting member.
【００３５】次に図１（ｄ）に示すように、半導体素子
１１が搭載され、金属細線１２で各々接続された配線基
板９の上面の端部のマージン領域や基板送り部分などを
除いた略全面を封止樹脂１３で一括封止する。封止樹脂
１３による一括成形には、金型を用いたトランスファー
モールド工法を用いる。Next, as shown in FIG. 1D, a semiconductor element 11 is mounted, and a marginal area at the end of the upper surface of the wiring board 9 connected to each of the thin metal wires 12 and a board feeding portion are removed. The entire surface is collectively sealed with a sealing resin 13. The transfer molding method using a mold is used for the collective molding using the sealing resin 13.
【００３６】そして図１（ｅ）に示すように、配線基板
９の封止樹脂１３が形成された面側から、配線基板９の
個々の切断箇所のラインに対応させ、また配線基板９に
設けられた凹部１０に対応させてウェハーダイシングで
採用している回転ブレードによる切断法を用い、回転ブ
レード１４を当接させ、切断するものである。また、切
断の面方向については配線基板９の裏面側の凹部１０か
ら切断してもよい。Then, as shown in FIG. 1E, the wiring board 9 is provided on the wiring board 9 from the surface on which the sealing resin 13 is formed so as to correspond to the line of each cut portion of the wiring board 9. The rotating blade 14 is brought into contact with the wafer 10 and cut by using a cutting method using a rotating blade employed in wafer dicing corresponding to the recess 10 formed. Further, regarding the cutting surface direction, the cutting may be performed from the concave portion 10 on the back surface side of the wiring board 9.
【００３７】通常、このブレード切断の段階で凹部１０
とブレード１４との切断界面にはカエリ部が発生する場
合があるが、発生するカエリ部は凹部内の面上に発生す
るため、基板の主要な底面には突出しない。Usually, at the stage of cutting the blade, the concave portion 10 is formed.
In some cases, burrs may be generated at the cutting interface between the blade and the blade 14, but the generated burrs are generated on the surface in the concave portion and do not protrude from the main bottom surface of the substrate.
【００３８】図２(ａ)は回転ブレード１４により個々の
半導体装置１５単位に分割した状態を示している。切断
後の状態では半導体装置１５は、それを構成している配
線基板９の底面の外方の端部は、テーパー部１６を有し
ている。このテーパー部の形成は、前工程でＶ型の凹部
を切断することによって形成された形状である。FIG. 2A shows a state where the semiconductor device 15 is divided into individual semiconductor devices 15 by the rotary blade 14. In the state after the cutting, the semiconductor device 15 has a tapered portion 16 at the outer end of the bottom surface of the wiring board 9 constituting the semiconductor device 15. The formation of the tapered portion is a shape formed by cutting the V-shaped concave portion in the previous step.
【００３９】なお本実施形態においてＢＧＡ型の半導体
装置の製造では、配線基板９の底面の電極上に半田ボー
ルなどのボール電極を形成する工程をさらに付加するも
のである。図２（ｂ）は１枚の配線基板から切断分離し
た１つの半導体装置１５を示し、さらにボール電極１７
を基板底面の電極上に付加した状態を示している。In the manufacture of the BGA type semiconductor device in this embodiment, a step of forming a ball electrode such as a solder ball on the electrode on the bottom surface of the wiring board 9 is further added. FIG. 2B shows one semiconductor device 15 cut and separated from one wiring board, and further includes a ball electrode 17.
On the electrode on the bottom surface of the substrate.
【００４０】以上のように本実施形態の半導体装置の製
造方法によって、配線基板９の個々の半導体素子１１単
位ごとに分割する際の分割箇所の基板下面に凹部１０が
設けられた配線基板９を用い、個々の半導体装置への分
割時は、凹部１０に対応させてブレード１４を当接さ
せ、個々の半導体素子１１単位に分割するため、回転ブ
レード１４によるカエリ部は凹部１０内に形成され、切
断分離後は、基板の正規の底面にはカエリ部には形成さ
れないので、半導体装置として二次実装上、何ら問題が
起こらない半導体装置を実現できるものである。特に基
板の切断箇所に設ける凹部１０は当接するブレードの幅
よりもその凹部幅を大きくしているので、カエリ部は確
実に凹部領域内に形成され、基板面への突出を防止でき
るものである。したがって１種類のブレードで一括成形
品を切断することができるものである。As described above, according to the method of manufacturing a semiconductor device of the present embodiment, the wiring board 9 having the concave portion 10 provided on the lower surface of the substrate at the dividing position when the semiconductor substrate 11 is divided into the individual semiconductor elements 11 is divided. When the semiconductor device is divided into individual semiconductor devices, a blade 14 is brought into contact with the concave portion 10 to divide the semiconductor device into individual semiconductor elements 11, so that the burrs formed by the rotary blade 14 are formed in the concave portion 10. After the cutting and separation, since no burrs are formed on the regular bottom surface of the substrate, it is possible to realize a semiconductor device which does not cause any problem in secondary mounting as a semiconductor device. In particular, since the width of the concave portion 10 provided at the cut portion of the substrate is larger than the width of the blade to be abutted, the burrs are reliably formed in the concave region, and the protrusion on the substrate surface can be prevented. . Therefore, the batch molded product can be cut with one kind of blade.
【００４１】次に本実施形態の半導体装置について図面
を参照しながら説明する。図３は本実施形態の半導体装
置を示す断面図である。Next, the semiconductor device of this embodiment will be described with reference to the drawings. FIG. 3 is a sectional view showing the semiconductor device of the present embodiment.
【００４２】図３に示すように、本実施形態のＢＧＡ型
の半導体装置は、底面に導電性材料による半田ボールな
どのボール電極１７を備えたものであって、上面に電極
と、下面にその上面の電極と接続した電極を有した配線
基板９と、配線基板９の上面に搭載された半導体素子１
１と、その半導体素子１１の電極パッドと配線基板９の
上面の電極とを電気的に接続した接続部材である金属細
線１２と、配線基板９の上面の半導体素子１１、金属細
線１２の外囲を封止した封止樹脂１３とよりなる半導体
装置である。また配線基板９の底面の端部は断面方向に
テーパー部１６を有し、そのテーパー部１６には、製造
過程でのカエリ部１８が形成され、カエリ部１８の高さ
は配線基板９の底面を超えない高さである。As shown in FIG. 3, the BGA type semiconductor device of the present embodiment has a ball electrode 17 such as a solder ball made of a conductive material on a bottom surface, and has an electrode on an upper surface and a ball electrode 17 on a lower surface. A wiring board 9 having electrodes connected to the electrodes on the upper surface, and a semiconductor element 1 mounted on the upper surface of the wiring board 9
1, a thin metal wire 12 which is a connection member electrically connecting the electrode pad of the semiconductor element 11 and an electrode on the upper surface of the wiring board 9, and the outer periphery of the semiconductor element 11 and the thin metal wire 12 on the upper surface of the wiring board 9. Is a semiconductor device comprising a sealing resin 13 in which is sealed. The end of the bottom surface of the wiring board 9 has a tapered portion 16 in the cross-sectional direction, and the burrs 18 are formed in the tapered portion 16 during the manufacturing process. Not exceed the height.
【００４３】以上のように本実施形態の半導体装置は、
配線基板９の底面の端部は断面方向にテーパー部１６を
有し、そのテーパー部１６には、カエリ部１８が残存し
て形成され、カエリ部１８の高さは配線基板９の底面を
超えない高さであるため、半導体装置を実装基板に二次
実装する際、半田ブリッジや、接続不良を解消できるも
のである。すなわち本実施形態の半導体装置では、たと
え製造過程でのカエリ部１８が残存していたとしても基
板の底面端部のテーパー部１６にカエリ部１８が位置
し、高さが基板底面を超えないため、実装上、何ら問題
が起こらない半導体装置である。As described above, the semiconductor device of this embodiment is
The end of the bottom surface of the wiring board 9 has a tapered portion 16 in the cross-sectional direction, and the flash portion 18 is formed in the tapered portion 16 so that the height of the flash portion 18 exceeds the bottom surface of the wiring substrate 9. Since the height is not so large, when the semiconductor device is secondarily mounted on the mounting board, the solder bridge and the connection failure can be eliminated. That is, in the semiconductor device of the present embodiment, even if the burrs 18 remain during the manufacturing process, the burrs 18 are located at the tapered portions 16 at the bottom end of the substrate, and the height does not exceed the bottom of the substrate. The semiconductor device does not cause any problem in mounting.
【００４４】次に第２の実施形態の半導体装置の製造方
法について説明する。第２の実施形態ではＱＦＮ（Ｑｕ
ａｄ Ｆｌａｔ Ｎｏｎ−ｌｅａｄｅｄ Ｐａｃｋａｇ
ｅ）型の半導体装置の製造方法について説明する。Next, a method of manufacturing the semiconductor device according to the second embodiment will be described. In the second embodiment, QFN (Quu
ad Flat Non-leaded Package
The method for manufacturing the semiconductor device of type e) will be described.
【００４５】図４，図５は本実施形態の半導体装置の製
造方法を示す工程ごとの主要な断面図である。FIGS. 4 and 5 are main cross-sectional views showing the steps of a method for manufacturing a semiconductor device according to this embodiment.
【００４６】まず図４（ａ）に示すように、ダイパッド
部１９の上面に複数の半導体素子が個々に搭載されるも
のであり、また個々の半導体素子に対応した電極リード
２０が設けられ、個々の半導体素子単位ごとに分割され
得る構造の１枚の金属板よりなるリードフレーム２１で
あって、リードフレーム２１の個々の半導体素子単位ご
とに分割する際の分割箇所のリードフレーム２１の電極
リード２０の上下面に凹部１０が設けられたリードフレ
ームを用意する。凹部１０は電極リード２０の下面にの
み設けてもよく、切断時のカエリ部が突出するであろう
方向に設ければよい。なお、用意するリードフレーム２
１は、１枚の金属板よりなるものであり、その材質は銅
（Ｃｕ）材、４２アロイ（Ｎｉ／Ｆｅ）材、いずれでも
よく、通常、表面には金属メッキが形成されているもの
である。First, as shown in FIG. 4A, a plurality of semiconductor elements are individually mounted on the upper surface of the die pad portion 19, and electrode leads 20 corresponding to the individual semiconductor elements are provided. A lead frame 21 made of a single metal plate having a structure that can be divided for each semiconductor element unit, and the electrode lead 20 of the lead frame 21 at the division point when dividing for each individual semiconductor element unit of the lead frame 21 A lead frame provided with a concave portion 10 on the upper and lower surfaces is prepared. The concave portion 10 may be provided only on the lower surface of the electrode lead 20, or may be provided in a direction in which the burrs at the time of cutting will protrude. The lead frame 2 to be prepared
Reference numeral 1 denotes a single metal plate, which may be made of a copper (Cu) material or a 42-alloy (Ni / Fe) material, and usually has metal plating on the surface. is there.
【００４７】次に図４（ｂ）に示すように、用意したリ
ードフレーム２１のダイパッド部１９に接着剤により接
着固定して複数の半導体素子２２をそれぞれ搭載する。Next, as shown in FIG. 4B, the plurality of semiconductor elements 22 are mounted on the die pad portion 19 of the prepared lead frame 21 by bonding with an adhesive.
【００４８】次に図４（ｃ）に示すように、リードフレ
ーム２１に搭載された複数の半導体素子２２の電極パッ
ドと、リードフレーム２１の電極リード２０の上面とを
接続部材として金線、銅線、アルミニウム線などの金属
細線２３で各々電気的に接続する。Next, as shown in FIG. 4C, a gold wire, a copper wire, and the like are used as connection members between the electrode pads of the plurality of semiconductor elements 22 mounted on the lead frame 21 and the upper surfaces of the electrode leads 20 of the lead frame 21. Each of them is electrically connected by a thin metal wire 23 such as a wire or an aluminum wire.
【００４９】次に図４（ｄ）に示すように、リードフレ
ーム２１の上面の端部のマージン領域や送り部分などを
除いた略全面を封止樹脂２４で一括封止する。封止樹脂
２４による一括成形には、金型を用いたトランスファー
モールド工法を用いる。また、ここではリードフレーム
２１の少なくともダイパッド部１９、電極リード２０の
底面を除いて半導体素子２２、金属細線２３の外囲を封
止するが、リードフレームの底面に封止シートを密着さ
せて封止することによりいわゆる片面封止が可能であ
る。Next, as shown in FIG. 4D, substantially the entire surface of the lead frame 21 except for the margin region and the feed portion at the upper end is sealed with a sealing resin 24 at a time. The transfer molding method using a mold is used for the collective molding using the sealing resin 24. In addition, here, the outer periphery of the semiconductor element 22 and the thin metal wire 23 is sealed except for at least the die pad portion 19 of the lead frame 21 and the bottom surface of the electrode lead 20, but the sealing sheet is adhered to the bottom surface of the lead frame. By stopping, so-called single-sided sealing is possible.
【００５０】そして図４（ｅ）に示すように、リードフ
レーム２１の封止樹脂２４が形成された面側、またはリ
ードフレーム２１の裏面側から、切断箇所のラインに対
応させ、またリードフレーム２１の電極リード２０に設
けられた凹部１０に対応させて回転ブレード２５を当接
させ、個々の半導体素子２２単位に分割する。Then, as shown in FIG. 4E, the lead frame 21 is made to correspond to the line of the cut portion from the side on which the sealing resin 24 is formed or from the back side of the lead frame 21. The rotating blade 25 is brought into contact with the concave portion 10 provided in the electrode lead 20 of the above-described electrode lead 20 to divide the semiconductor device 22 into individual semiconductor elements 22.
【００５１】図５(ａ)は回転ブレード２５により個々の
半導体装置２６単位に分割した状態を示している。切断
後の状態では半導体装置２６は、それを構成しているリ
ードフレームの電極リード２０の底面の外方の端部は、
テーパー部１６を有している。このテーパー部の形成
は、前工程でＶ型の凹部１０を切断することによって形
成された形状である。FIG. 5A shows a state where the semiconductor device 26 is divided into individual semiconductor devices 26 by the rotating blade 25. In the state after the cutting, the semiconductor device 26 has an outer end on the bottom surface of the electrode lead 20 of the lead frame constituting the semiconductor device 26.
It has a tapered portion 16. The formation of this tapered portion is a shape formed by cutting the V-shaped concave portion 10 in the previous step.
【００５２】図５（ｂ）は１枚のリードフレーム基板か
ら切断分離した１つの半導体装置２６を示し、電極リー
ド２０の底面の外方の端部は、テーパー部１６を有して
いる。FIG. 5B shows one semiconductor device 26 cut and separated from one lead frame substrate, and the outer end of the bottom surface of the electrode lead 20 has a tapered portion 16.
【００５３】以上のように本実施形態の半導体装置の製
造方法によって、リードフレーム２１の個々の半導体素
子単位ごとに分割する際の分割箇所の電極リード２０下
面に凹部１０が設けられたリードフレームを用い、個々
の半導体装置への分割時は、凹部１０に対応させて回転
ブレード２５を当接させ、個々の半導体素子２２単位に
分割するため、回転ブレード２５によるカエリ部は凹部
内に形成され、切断分離後は、リードの正規の底面には
カエリ部には形成されないので、半導体装置として二次
実装上、何ら問題が起こらないようにできるものであ
る。特に電極リード２０の切断箇所に設ける凹部１０は
当接する回転ブレード２５の幅よりもその凹部幅を大き
くしているので、カエリ部は確実に凹部内に形成され、
電極リード２０の底面への突出を防止できるものであ
る。したがって１種類のブレードで一括成形品を切断す
ることができるものである。なお、カエリ部の突出量は
１０〜２０［μｍ］である。As described above, according to the method of manufacturing the semiconductor device of the present embodiment, the lead frame having the concave portion 10 provided on the lower surface of the electrode lead 20 at the division position when dividing the semiconductor device into individual semiconductor elements of the lead frame 21 is obtained. When the semiconductor device is divided into individual semiconductor devices, the rotating blade 25 is brought into contact with the concave portion 10 to divide the semiconductor device into individual semiconductor elements 22. Therefore, the burrs formed by the rotating blade 25 are formed in the concave portion. After the cutting and separation, no burrs are formed on the regular bottom surface of the lead, so that there is no problem in secondary mounting as a semiconductor device. In particular, since the concave portion 10 provided at the cut portion of the electrode lead 20 has a larger concave portion width than the width of the rotating blade 25 that abuts, the burrs are reliably formed in the concave portion,
The protrusion of the electrode lead 20 to the bottom surface can be prevented. Therefore, the batch molded product can be cut with one kind of blade. The protrusion of the burrs is 10 to 20 [μm].
【００５４】次に本実施形態の半導体装置について図面
を参照しながら説明する。図６は本実施形態のＱＦＮ型
の半導体装置を示す断面図である。Next, the semiconductor device of this embodiment will be described with reference to the drawings. FIG. 6 is a sectional view showing a QFN type semiconductor device of the present embodiment.
【００５５】図６に示すように本実施形態の半導体装置
は、ＱＦＮ型の半導体装置であって、リードフレームの
ダイパッド部１９上に搭載された半導体素子２２と、そ
の半導体素子２２の電極パッドと電極リード２０の上面
とを電気的に接続した接続部材である金属細線２３と、
少なくともダイパッド部１９、電極リード２０の底面を
除き、また電極リード２０の外方側面を露出させ、半導
体素子２２、金属細線２３の外囲を封止した封止樹脂２
４とよりなる樹脂封止型の半導体装置であって、電極リ
ード２０の外方側面は封止樹脂２４の側面と同一面に露
出し、電極リード２０底面の端部は断面方向にテーパー
部１６を有しているものである。そして電極リード２０
の底面の端部のテーパー部１６には、製造過程でのカエ
リ部２７が形成され、そのカエリ部２７の高さは電極リ
ード２０の底面を超えない高さである。なお、本実施形
態の半導体装置のカエリ部２７はリードフレーム、電極
リードの材質が回転ブレードの回転摩擦により、銅など
のリード材質が延出した突起異物である。As shown in FIG. 6, the semiconductor device according to the present embodiment is a QFN type semiconductor device, in which a semiconductor element 22 mounted on a die pad portion 19 of a lead frame and an electrode pad of the semiconductor element 22 are formed. A thin metal wire 23 which is a connection member electrically connecting the upper surface of the electrode lead 20;
At least the die pad portion 19, the bottom surface of the electrode lead 20 is removed, and the outer side surface of the electrode lead 20 is exposed.
4, the outer side surface of the electrode lead 20 is exposed to the same surface as the side surface of the sealing resin 24, and the end of the bottom surface of the electrode lead 20 has a tapered portion 16 in the cross-sectional direction. It has. And the electrode lead 20
The burrs 27 during the manufacturing process are formed on the tapered portion 16 at the end of the bottom surface of the electrode lead 20, and the height of the burrs 27 does not exceed the bottom surface of the electrode lead 20. Note that the burrs 27 of the semiconductor device of the present embodiment are projecting foreign substances in which the lead material such as copper is extended due to the rotational friction of the rotating blade and the material of the lead frame and the electrode leads.
【００５６】以上のように本実施形態の半導体装置は、
リードフレームの電極リード２０の底面の外方の端部は
断面方向にテーパー部１６を有し、そのテーパー部１６
には、カエリ部２７が製造過程上、残存して形成され、
カエリ部２７の高さは電極リード２０の底面を超えない
高さであるため、半導体装置を実装基板に二次実装する
際、半田ブリッジや、接続不良を解消できるものであ
る。すなわち本実施形態の半導体装置では、たとえ製造
過程でのカエリ部２７がリード面に残存していたとして
もリード端部にはテーパー部があり、そこにカエリ部２
７が位置し、高さが電極リード２０の底面を超えないた
め、実装上、何ら問題が起こらない半導体装置である。As described above, the semiconductor device of this embodiment is
The outer end of the bottom surface of the electrode lead 20 of the lead frame has a tapered portion 16 in the cross-sectional direction.
In the manufacturing process, the burrs 27 remain in the manufacturing process,
Since the height of the burrs 27 does not exceed the bottom surface of the electrode lead 20, solder bridges and connection failures can be eliminated when the semiconductor device is secondarily mounted on the mounting board. That is, in the semiconductor device of the present embodiment, even if the flash portion 27 in the manufacturing process remains on the lead surface, the lead end has a tapered portion, and the flash portion 2 is located there.
7 is located and the height does not exceed the bottom surface of the electrode lead 20, so that there is no problem in mounting.
【００５７】以上、各実施形態で説明した通り、半導体
装置の製造方法は、その上面に複数の半導体素子が個々
に搭載されるもので、また個々の半導体素子に対応した
電極、リードが設けられ、個々の半導体素子単位ごとに
分割され得る構造の基板なとの支持体であって、その支
持体の個々の半導体素子単位ごとに分割する際の分割箇
所の支持体下面に凹部が設けられた支持体を用意する工
程と、その支持体上の対応した箇所に複数の半導体素子
をそれぞれ搭載する工程と、その支持体上に搭載された
複数の半導体素子の電極パッドと支持体上の電極または
リードとを金属細線、突起電極（バンプ）なとの接続部
材で各々電気的に接続する工程と、その支持体の上面の
実効的なほぼ全面を封止樹脂で一括封止する工程と、そ
の支持体の封止樹脂が形成された面側、または支持体の
支持体裏面側から、支持体に設けられた凹部に対応させ
てブレードを当接させ、個々の半導体素子単位に分割し
て半導体装置を得る工程とよりなるものであり、支持体
の個々の半導体素子単位ごとに分割する際の分割箇所の
基板下面に凹部が設けられた支持体を用い、個々の半導
体装置への分割時は、凹部に対応させてブレードを当接
させ、個々の半導体素子単位に分割するため、回転ブレ
ードによるカエリ部は凹部内に形成され、切断分離後
は、基板の正規の底面にはカエリ部には形成されないの
で、半導体装置として二次実装上、何ら問題が起こらな
い半導体装置を実現できるものである。特に基板の切断
箇所に設ける凹部は当接するブレードの幅よりもその凹
部幅を大きくしているので、カエリ部は確実に凹部領域
内に形成され、基板面への突出を防止できるものであ
る。したがって１種類のブレードで一括成形品を切断す
ることができるものである。As described in each of the embodiments, the method of manufacturing a semiconductor device is such that a plurality of semiconductor elements are individually mounted on the upper surface, and electrodes and leads corresponding to the individual semiconductor elements are provided. A support such as a substrate having a structure that can be divided for each semiconductor element unit, wherein a concave portion is provided on the lower surface of the support at the division point when the support is divided for each semiconductor element unit. A step of preparing a support, a step of mounting a plurality of semiconductor elements at corresponding locations on the support, and an electrode on the support and electrode pads of the plurality of semiconductor elements mounted on the support. A step of electrically connecting the lead with a connecting member such as a thin metal wire and a protruding electrode (bump); a step of encapsulating substantially the entire effective upper surface of the support with a sealing resin; Supporting tree A step of contacting a blade corresponding to a concave portion provided in the support from the surface side on which the support is formed, or the back surface side of the support, and obtaining a semiconductor device by dividing into individual semiconductor element units. A support having a concave portion provided on the lower surface of the substrate at the division point when dividing the support into individual semiconductor element units is used, and when dividing into individual semiconductor devices, it is necessary to correspond to the concave portion. Since the blade is brought into contact and divided into individual semiconductor element units, the burrs formed by the rotating blade are formed in the recesses. After cutting and separating, the burrs are not formed on the regular bottom surface of the substrate in the burrs. As a result, a semiconductor device which does not cause any problem in secondary mounting can be realized. Particularly, since the width of the concave portion provided at the cut portion of the substrate is larger than the width of the blade to be in contact with, the burrs are reliably formed in the concave region, and the protrusion to the substrate surface can be prevented. Therefore, the batch molded product can be cut with one kind of blade.
【００５８】[0058]
【発明の効果】以上のように本発明の半導体装置は、配
線基板やリードなどの支持体の底面の端部は断面方向に
テーパー部を有し、そのテーパー部には製造過程でのカ
エリ部が残存して形成され、カエリ部の高さは支持体の
底面を超えない高さであるため、半導体装置を実装基板
に二次実装する際、半田ブリッジや、接続不良を解消で
きるものである。すなわち、たとえ製造過程でのカエリ
部が残存していたとしても支持体の底面端部のテーパー
部にカエリ部が位置し、高さが支持体底面を超えないた
め、実装上、何ら問題が起こらない半導体装置を実現で
きるものである。As described above, in the semiconductor device of the present invention, the end of the bottom surface of a support such as a wiring board or a lead has a tapered portion in a cross-sectional direction, and the tapered portion in the manufacturing process has a tapered portion. Are formed, and the height of the burrs is not higher than the bottom surface of the support. Therefore, when the semiconductor device is secondarily mounted on the mounting board, solder bridges and connection failures can be eliminated. . That is, even if the burrs in the manufacturing process remain, the burrs are located at the tapered portion at the bottom end of the support, and the height does not exceed the bottom of the support, so there is no problem in mounting. Semiconductor device can be realized.
【００５９】また本発明の半導体装置の製造方法によ
り、一括成形方法による半導体装置の製造においては、
配線基板、リードフレームなどの支持体の個々の半導体
素子単位ごとに分割する際の分割箇所の基板下面に凹部
が設けられた支持体を用い、個々の半導体装置への分割
時は、凹部に対応させてブレードを当接させ、個々の半
導体素子単位に分割するため、回転ブレードによるカエ
リ部は凹部内に形成され、切断分離後は、基板、リード
面の正規の底面にはカエリ部には形成されないので、半
導体装置として二次実装上、何ら問題が起こらない半導
体装置を製造できるものであり、製造工数、製造コスト
に優れ、量産に適した半導体装置の製造方法を実現でき
るものである。According to the method of manufacturing a semiconductor device of the present invention, when manufacturing a semiconductor device by a batch molding method,
Use a support with a recess on the bottom surface of the substrate at the division point when dividing into individual semiconductor element units of the support such as a wiring board and a lead frame. When dividing into individual semiconductor devices, support the recess The blade is brought into contact with the blade to divide it into individual semiconductor elements, so that the burrs formed by the rotating blade are formed in the recesses.After cutting and separation, the burrs are formed on the regular bottom surface of the substrate and lead surfaces. Therefore, it is possible to manufacture a semiconductor device that does not cause any problem in secondary mounting as a semiconductor device, and it is possible to realize a method of manufacturing a semiconductor device which is excellent in man-hour and cost and is suitable for mass production.
【図１】本発明の一実施形態の半導体装置の製造方法を
示す断面図FIG. 1 is a sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention;
【図２】本発明の一実施形態の半導体装置の製造方法を
示す断面図FIG. 2 is a sectional view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention;
【図３】本発明の一実施形態の半導体装置を示す断面図FIG. 3 is a sectional view showing a semiconductor device according to one embodiment of the present invention;
【図４】本発明の一実施形態の半導体装置の製造方法を
示す断面図FIG. 4 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図５】本発明の一実施形態の半導体装置の製造方法を
示す断面図FIG. 5 is a sectional view showing the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図６】本発明の一実施形態の半導体装置を示す断面図FIG. 6 is a sectional view showing a semiconductor device according to one embodiment of the present invention;
【図７】従来の半導体装置の製造方法を示す断面図FIG. 7 is a sectional view showing a conventional method of manufacturing a semiconductor device.
【図８】従来の半導体装置を示す断面図FIG. 8 is a sectional view showing a conventional semiconductor device.
【図９】従来の半導体装置の課題を示す断面図FIG. 9 is a cross-sectional view illustrating a problem of a conventional semiconductor device.
１ 配線基板 ２ 半導体素子 ３ 金属細線 ４ 封止樹脂 ５ 回転ブレード ６ 半導体装置 ７ ボール電極 ８ カエリ部 ９ 配線基板 １０ 凹部 １１ 半導体素子 １２ 金属細線 １３ 封止樹脂 １４ 回転ブレード １５ 半導体装置 １６ テーパー部 １７ ボール電極 １８ カエリ部 １９ ダイパッド部 ２０ 電極リード ２１ リードフレーム ２２ 半導体素子 ２３ 金属細線 ２４ 封止樹脂 ２５ 回転ブレード ２６ 半導体装置 ２７ カエリ部 DESCRIPTION OF SYMBOLS 1 Wiring board 2 Semiconductor element 3 Fine metal wire 4 Sealing resin 5 Rotating blade 6 Semiconductor device 7 Ball electrode 8 Flash part 9 Wiring board 10 Depression 11 Semiconductor element 12 Fine metal wire 13 Sealing resin 14 Rotating blade 15 Semiconductor device 16 Tapered portion 17 Ball electrode 18 Flash part 19 Die pad part 20 Electrode lead 21 Lead frame 22 Semiconductor element 23 Fine metal wire 24 Sealing resin 25 Rotating blade 26 Semiconductor device 27 Flash part
フロントページの続き Ｆターム(参考） 5F061 AA01 BA01 BA03 CA21 CB13 DD12 EA13 5F067 AA01 AA09 AB03 AB04 BA08 BC12 BC13 DB00 DE20 Continued on the front page F term (reference) 5F061 AA01 BA01 BA03 CA21 CB13 DD12 EA13 5F067 AA01 AA09 AB03 AB04 BA08 BC12 BC13 DB00 DE20
Claims (9)
された半導体素子と、 前記半導体素子の電極パッドとリードフレームの電極リ
ードとを電気的に接続した接続部材と、 前記リードフレームの少なくともダイパッド部、電極リ
ードの底面を除いて前記半導体素子、前記接続部材の外
囲を封止した封止樹脂とよりなる半導体装置であって、 前記リードフレームの電極リードの外方側面は前記封止
樹脂の側面と同一面に露出し、前記電極リード底面の端
部は断面方向にテーパー部を有していることを特徴とす
る半導体装置。A semiconductor element mounted on a die pad part of a lead frame; a connection member electrically connecting an electrode pad of the semiconductor element and an electrode lead of the lead frame; at least a die pad part of the lead frame; A semiconductor device comprising a sealing resin that seals an outer periphery of the semiconductor element and the connection member except for a bottom surface of an electrode lead, wherein an outer side surface of the electrode lead of the lead frame is a side surface of the sealing resin. A semiconductor device which is exposed on the same plane as the above, and has an end portion of the bottom surface of the electrode lead tapered in a cross-sectional direction.
は、カエリ部が形成され、前記カエリ部の高さは前記電
極リードの底面を超えない高さであることを特徴とする
請求項１に記載の半導体装置。2. A burring portion is formed at a tapered portion at an end of a bottom surface of the electrode lead, and the height of the burring portion is a height not exceeding the bottom surface of the electrode lead. 2. The semiconductor device according to 1.
子が個々に搭載され、個々の半導体素子に対応した電極
リードが設けられ、個々の半導体素子単位ごとに分割さ
れ得る構造のリードフレームであって、前記リードフレ
ームの個々の半導体素子単位ごとに分割する際の分割箇
所のリードフレームの少なくとも下面に凹部が設けられ
たリードフレームを用意する工程と、 前記リードフレームのダイパッド部に複数の半導体素子
をそれぞれ搭載する工程と、 前記リードフレームに搭載された複数の半導体素子の電
極パッドと前記リードフレームの電極リードとを接続部
材で各々電気的に接続する工程と、 前記リードフレームの上面の略全面を封止樹脂で一括封
止する工程と、 前記リードフレームの封止樹脂が形成された面側または
前記リードフレーム裏面側から、前記リードフレームに
設けられた凹部に対応させてブレードを当接させ、個々
の半導体素子単位に分割して半導体装置を得る工程とよ
りなることを特徴とする半導体装置の製造方法。3. A lead frame having a structure in which a plurality of semiconductor elements are individually mounted on an upper surface of a die pad portion, electrode leads corresponding to the individual semiconductor elements are provided, and the semiconductor device can be divided into individual semiconductor element units. Preparing a lead frame provided with a concave portion on at least the lower surface of the lead frame at a division point when dividing the semiconductor device into individual semiconductor element units of the lead frame; and providing a plurality of semiconductor elements on a die pad portion of the lead frame. Mounting each; electrically connecting the electrode pads of the plurality of semiconductor elements mounted on the lead frame to the electrode leads of the lead frame with connecting members, respectively; and substantially covering the entire upper surface of the lead frame. Encapsulating with the encapsulating resin, and the side of the lead frame on which the encapsulating resin is formed or the lead Producing a semiconductor device by contacting a blade corresponding to a concave portion provided in the lead frame from the back side of the frame and dividing the semiconductor device into individual semiconductor element units to obtain a semiconductor device. .
面に設けられていることを特徴とする請求項３に記載の
半導体装置の製造方法。4. The method according to claim 3, wherein the recess is provided on a lower surface of the electrode lead of the lead frame.
を特徴とする請求項３に記載の半導体装置の製造方法。5. The method according to claim 3, wherein the recess is a V-shaped recess having a sectional shape.
を特徴とする請求項３に記載の半導体装置の製造方法。6. The method according to claim 3, wherein the recess is a U-shaped recess having a sectional shape.
幅の凹部であることを特徴とする請求項３に記載の半導
体装置の製造方法。7. The method of manufacturing a semiconductor device according to claim 3, wherein the recess is a recess having a width larger than a width of a blade that abuts.
ることを特徴とする請求項３に記載の半導体装置の製造
方法。8. The method according to claim 3, wherein one kind of rotating blade is used.
とする請求項３に記載の半導体装置の製造方法。9. The method according to claim 3, wherein the connection member uses a thin metal wire.
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|---|---|---|---|
| JP2001087010A JP2002289756A (en) | 2001-03-26 | 2001-03-26 | Semiconductor device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001087010A JP2002289756A (en) | 2001-03-26 | 2001-03-26 | Semiconductor device and its manufacturing method |
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| Publication Number | Publication Date |
|---|---|
| JP2002289756A true JP2002289756A (en) | 2002-10-04 |
Family
ID=18942306
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|---|---|---|---|
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| JP (1) | JP2002289756A (en) |
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| JP2004214233A (en) * | 2002-12-26 | 2004-07-29 | Renesas Technology Corp | Semiconductor device and manufacturing method therefor |
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2001
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| EP1556894A2 (en) * | 2002-09-30 | 2005-07-27 | Advanced Interconnect Technologies Limited | Thermal enhanced package for block mold assembly |
| EP1556894A4 (en) * | 2002-09-30 | 2009-01-14 | Advanced Interconnect Tech Ltd | Thermal enhanced package for block mold assembly |
| JP2004214233A (en) * | 2002-12-26 | 2004-07-29 | Renesas Technology Corp | Semiconductor device and manufacturing method therefor |
| JP2008112961A (en) * | 2006-10-04 | 2008-05-15 | Rohm Co Ltd | Method for manufacturing semiconductor device, and semiconductor device |
| JP2009117450A (en) * | 2007-11-02 | 2009-05-28 | Rohm Co Ltd | Module and its manufacturing method |
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| JP2017162903A (en) * | 2016-03-08 | 2017-09-14 | 株式会社ジェイデバイス | Semiconductor package and manufacturing method of semiconductor package |
| TWI756078B (en) * | 2016-03-08 | 2022-02-21 | 日商安靠科技日本公司 | Semiconductor package and manufacturing method thereof |
| US11322431B2 (en) | 2016-03-08 | 2022-05-03 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device having outer terminal portions with conductive layer on outer end surfaces and method of manufacturing a semiconductor device |
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