JP2002270716A - Method of manufacturing two-layer wiring semiconductor device, and its semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a two-layer wiring semiconductor device which is of two- layer wiring structure where the number of layers is minimum out of a muitilayer interposer to mount a semiconductor element, has rigidity though it is a resin layer not containing reinforcing fibers, prevents microvoids in the underfill injection or resin sealing process at mounting of the semiconductor element by horizontal surface structure which is free of a difference in circuit level at a mounting face, and has excellent handling property, mountability, and reliability on device after mounting, and to provide its manufacturing method. SOLUTION: This is a manufacturing method for the two-layer wiring semiconductor device which includes a process of forming barrier metal and a conductor wiring layer by electrolytic plating, with a conductive frame as a lead for electrolytic plating, and a process of etching off the conductive frame.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device obtained by the method.

[0002]

2. Description of the Related Art In recent years, with the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration and high-density mounting of electronic components have been advanced. Semiconductor devices used in these electronic devices have become smaller and have more pins.

[0003] With the miniaturization of semiconductor devices, there is a limit to miniaturization in a device using a conventional lead frame. Therefore, semiconductor devices have recently been mounted on a semiconductor mounting substrate. As an example, BGA (Ball
Grid Array) and CSP (Chip Sca)
le Package), a new device system of an area mounting type has been proposed. In these semiconductor devices, the mainstream structure is to mount the semiconductor element on a semiconductor mounting board called an interposer in order to rearrange the electrodes of the semiconductor element into an area type and match the pitch with the wiring terminals of the mounting board. Has become. As the interposer, a flexible printed board or a glass epoxy resin laminate is used.

The wiring of these interposers tends to increase in density, and a multi-layer wiring structure that has been built up is employed. An interposer having a multilayer wiring structure
Generally, since wiring layers formed on an insulating layer are formed by stacking them, irregularities due to a conductor wiring pattern are formed on the mounting surface of the outermost semiconductor element. In this case, especially in a wiring pattern having a narrow pitch, there is a problem that underfill injection at the time of flip-chip connection and microvoids generated in a sealing process with a resin lower package reliability and mounting reliability of a semiconductor device. May have occurred.

As a method of forming a wiring pattern, there are generally a method of etching a copper foil (subtractive method) and a method of electrolytic copper plating (full semi-additive method). The subtractive method is characterized in that the formed circuit height is determined by the thickness of the copper foil used, and there is a limit depending on the reaction characteristics of the etchant and the capability of the device used. It is not suitable for high density. In addition, in the semi-additive method, it may be difficult to sufficiently remove the power supply layer by flash etching after forming the wiring layer using a fine pattern, and a problem such as a short circuit due to ion migration between circuits may occur. was there. On the other hand, the full additive method has begun to receive particular attention because of its merit of being able to freely design circuits.

In connection between layers, a laser, a laser, is used instead of a conventional mechanical drill.
The diameter can be reduced by forming a blind via by a photo method, and the density can be increased by a via-on-via and via-on-pad structure by filling the via with a conductor.

In a semiconductor device having such a multilayer wiring structure, the number of pins is usually very large in many cases, and the interposer is larger than the semiconductor element. Therefore,
From the viewpoint of handling and the problem of substrate warpage during mounting of semiconductor elements, it is common that the interposer is required to have rigidity. A glass epoxy substrate such as FR-4 is used as a core and laminated on both sides to mount the semiconductor element.・ Currently, sealing is performed. However, the number of layers may increase more than necessary, not only lowering the yield and increasing the manufacturing cost, but also causing dielectric breakdown at the interface between the glass fiber and the resin used for reinforcement. Yes, there is a problem in insulation reliability.

[0008]

SUMMARY OF THE INVENTION The present invention provides a two-layer wiring structure having a minimum number of layers in a multi-layered interposer on which a semiconductor element is mounted. With a horizontal surface structure that has no circuit steps on the mounting surface, it prevents underfill injection and microvoids in the resin encapsulation process when mounting semiconductor elements, low cost, excellent handling properties, mountability, It is an object to provide a two-layer wiring semiconductor device having device reliability.

[0009]

The present invention includes a step of forming a barrier metal and a conductor wiring layer by electrolytic plating using a conductive frame as a lead for electrolytic plating, and a step of removing the conductive frame by etching. The present invention relates to a method for manufacturing a layer wiring semiconductor device.

According to the method of manufacturing a two-layer wiring semiconductor device of the present invention, a step of forming a barrier metal and a conductive wiring layer by electrolytic plating using a conductive frame as a lead for electrolytic plating, and an insulating resin layer on the conductive wiring layer Forming a;
Forming a via in the insulating resin layer such that a part of the conductor wiring layer is exposed; forming a conductor post by electrolytic plating using the conductive frame as a lead for electrolytic plating; Forming a bonding metal layer on at least one of the surface or the surface of the connected portion of the connected layer with a conductive frame formed in the same manner as described above, and at least the surface of the insulating resin layer or the surface of the connected layer. A step of forming an adhesive layer on one side, and bonding the conductor post and the portion to be bonded to each other through the adhesive layer and the bonding metal layer, and bonding the insulating resin layer and the layer to be connected to each other; Bonding with an agent layer, removing the conductive frame on the side on which the semiconductor element is mounted by etching, mounting and sealing the semiconductor element, and removing the conductive frame on the back surface by etching. When Forming a solder resist layer on the exposed back side of the barrier metal of the surface other than the external connection pads, it is preferable that the solder balls on the external connection pads the step of reflowing mounted. Further, the conductive frame on the back surface may be partially etched away to form external connection lands.

Further, the present invention is obtained by the method for manufacturing a two-layer wiring semiconductor device, wherein the surface of the conductor circuit on which the semiconductor element is mounted and the surface of the insulating resin layer have a horizontal plane structure, that is, the semiconductor element mounting surface A two-layer wiring semiconductor device having a horizontal structure with no circuit steps.

[0012]

Embodiments of the present invention will be described below with reference to the drawings, but the present invention is not limited to these embodiments.

FIG. 1A to FIG. 4R-2 are diagrams for explaining an example of a method for manufacturing a two-layer wiring semiconductor device according to an embodiment of the present invention.

In the method of manufacturing a two-layer wiring semiconductor device according to the present invention, first, a patterned plating resist 102 is formed on a conductive frame 101. (Figure 1
(A)). As the material of the conductive frame 101, any material can be used as long as it has a function as a lead (cathode electrode) at the time of electrolytic plating and resistance to a used chemical and can be finally removed by etching. But,
Examples include copper, copper alloys, 42 alloys, nickel, iron, and the like. The plating resist 102 is, for example,
It can be formed by laminating an ultraviolet-sensitive dry film resist on the conductive frame 101, pattern-exposing it using an exposure mask or the like, and then developing it.

Next, using the conductive frame 101 as a lead for electrolytic plating, a barrier metal 103 is formed by electrolytic plating in a portion where the plating resist 102 is not formed (FIG. 1B). As the material of the barrier metal 103, any metal can be used as long as it is resistant to an etchant used when the conductive frame 101 is finally removed by etching. Examples include nickel, gold, tin,
Silver, tin-silver solder, eutectic solder, palladium and the like can be mentioned. When the wiring layer 104 shown in FIG. 1C has resistance to an etchant used when the conductive frame 101 is removed by etching, the barrier metal 103 is used.
Is unnecessary.

Next, the wiring layer 104 is formed by electrolytic plating using the conductive frame 101 as a lead for electrolytic plating (FIG. 1C). By this electrolytic plating, a wiring layer 104 is formed on a portion of the conductive frame 101 where the plating resist 102 is not formed, thereby forming a conductor circuit including a barrier metal and a wiring layer. The material of the wiring layer 104 is, for example, copper, nickel, gold, tin, silver,
Palladium and the like can be mentioned, but it is preferable to use copper having excellent conduction characteristics.

Next, the plating resist 102 is removed (FIG. 1D), and the insulating resin layer 10 is formed on the formed wiring layer 104.
5 is formed (FIG. 1E). As the resin forming the insulating resin layer 105, any resin suitable for this manufacturing method can be used. Epoxy, phenol, bismaleimide, bismaleimide triazine, triazole, polycyanurate, polyisocyanurate, benzocyclobutene, polyamide, polyimide, polyamideimide, polyetherimide, polyesterimide, polyetheretherketone, polyphenylene sulfide,
Polyquinoline, polynorbornene, polybenzoxazole, polybenzimidazole and the like can be used. These resins may be used alone or in combination of two or more. In particular, it is better to form the insulating resin layer 105 only with resin without including reinforcing fibers such as glass cloth.
The method for forming the insulating resin layer 105 may be a method suitable for the resin form to be used. A resin varnish may be directly applied by printing, coating, or the like. A method of laminating by a method such as a press or a vacuum press may be used.

Next, a via 1 is formed in the formed insulating resin layer 105.
06 (FIG. 1F). The via 106 may be formed by a method suitable for this manufacturing method, and may be formed by dry etching using laser or plasma, or by photosensitive patterning and chemical etching.

Next, using the conductive frame 101 as a lead for electrolytic plating, the conductor post 201 is formed by electrolytic plating (FIG. 2 (g)). By this electrolytic plating, a portion of the insulating resin layer 105 where the via 106 is formed,
The conductor posts 201 are filled and formed. If the conductor posts 201 are filled and formed by electrolytic plating, the tip shape of the conductor posts 201 can be freely controlled relatively easily as compared with printing of a conductive paste or the like. The material of the conductor post 201 may be any material as long as it is suitable for this manufacturing method, such as copper, nickel, gold, tin, silver, palladium, bismuth, or a composite of these metal species. Can be In particular, by using copper, the conductor post 201 having excellent resistance characteristics can be obtained.

Next, on the surface of the conductor post 201 (tip)
Next, a bonding metal layer 202 is formed (FIG. 2H). Examples of the method for forming the bonding metal layer 202 include a method of forming the conductive frame 101 as a lead for electrolytic plating by electrolytic plating, a method of forming by electroless plating, and a method of paste printing. In the printing method,
It is necessary to accurately position the screen mask for printing with respect to the conductor posts 201, but since the bonding metal layer 202 is not formed except on the surface of the conductor posts 201 by the plating method, the It is easy to cope with miniaturization and high density. In particular, the method using electrolytic plating is more suitable than the method using electroless plating because there are a wide variety of metals that can be plated and the management of the chemical solution is relatively easy. As the material of the bonding metal layer 202, any material can be used as long as it can be alloyed with the portion to be bonded 206 shown in FIG. 2 (j), and a material that liquefies in a relatively low temperature region such as solder is suitable. . Among the solders, it is preferable to use solder composed of at least two kinds of lead, tin, silver, copper, bismuth, indium, zinc, and gold. In recent years, the use of lead-free solder seems to be very suitable especially from the environmental point of view. In FIG. 2 (h),
Although the example in which the bonding metal layer 202 is formed on the surface of the conductor post 201 has been described, the bonding metal layer 202 is
Since the purpose is to bond the first and second parts 206 to each other, the bonding metal layer 202 may be formed on the part 206 to be bonded. Further, the conductor post 201 and the portion to be joined 2
06 may be formed on both surfaces.

Next, an adhesive layer 203 is formed on the surface of the insulating resin layer 105 (FIG. 2 (i)). Adhesive layer 203
Is formed by a method suitable for the form of the adhesive resin to be applied. The resin ink is directly applied by printing, coating, or the like, or a dry film type resin is laminated, pressed (normal pressure, vacuum), etc. Can be formed. Note that FIG.
In (i), the adhesive layer 203 is provided on the surface of the insulating resin layer 105.
Has been shown, but the adhesive layer 203 is
Since the purpose is to bond the insulating resin layer 105 and the insulating resin layer 105, an adhesive layer 203 may be formed on the surface of the connected layer 205. Further, it may be formed on both surfaces of the insulating resin layer 105 and the connected layer 205. Note that the connection layer 205 can be formed in the same manner as the steps shown in FIGS. 1A to 1D.

The connection layer 204 obtained by the above steps
And the connection layer 205 are aligned (FIG. 2 (j)). The alignment is performed by connecting layer 204 and connected layer 205.
A method for adjusting the reading position of a positioning mark formed in advance by an image recognition device,
In addition, a method of mechanically aligning by inserting guide pins for alignment into guide holes formed in advance in the connection layer 205 can be used.

Next, the connecting layer 204 and the connected layer 205
Are laminated (FIG. 2 (k)). As a lamination method, for example, by using a vacuum press, the conductor post 201 is pressed through the adhesive layer 203 until it is joined to the portion 206 to be joined by the joining metal layer 202, and further heated to form an adhesive. The connection layer 204 and the connection target layer 205 are cured by thermosetting the layer 109.
Can be bonded.

Next, the conductive frame 1 on the connection layer 204 side
01 is removed by etching. In the figure, the connection layer 20
Although the example in which the semiconductor element is mounted on the fourth side is shown,
When a connection pad with a semiconductor element is formed on the 05 side,
First, the conductive frame 207 of the connected layer 205 is removed. Conductive frame 101 on connection layer 204 side
Is removed by etching, barrier metal 103 is removed.
Is resistant to the etchants used,
The wiring layer 104 is not eroded or corroded. When the material of the conductive frame 101 is copper and the material of the barrier metal 103 is nickel, tin, or various solders, a commercially available ammonia-based etchant can be used. When the material of the conductive frame 101 is copper and the material of the barrier metal 103 is gold or silver, almost all commercially available etchants of iron chloride or copper chloride can be used. Considering that the barrier metal 103 also serves as a mounting surface of the semiconductor element, it is most preferable to use gold from the viewpoint of surface cleanliness, stability, and mounting reliability.

Further, in the thus obtained semiconductor mounting substrate 301 (FIG. 3 (l)), the connection layer 205
Because the rigidity of the substrate is ensured by the rigidity of the conductive frame 207 on the side, even if the insulating resin layer 105 does not include reinforcing fibers or the like, there is no problem such as warpage of the substrate at the time of semiconductor mounting, This is very convenient in terms of mounting yield.

Next, the semiconductor element 302 is mounted (FIG.
(M)). As a mounting method, a wire bonding method using a gold wire, an aluminum wire, or the like, and a batch bonding of flip chips via a conductor bump 303 such as a gold stud bump, a solder bump, or a copper post can be applied. Here, when the wiring layer 104 is made of copper, if the barrier metal 103 has a two-layer structure of gold and nickel, it is possible to prevent gold on the mounting surface of the semiconductor element from diffusing into copper of the wiring layer 104. It is possible. Further, the hardness of the mounting surface can be increased, the bonding pressure can be ensured, and the improvement of the mounting reliability can be expected. When flip-chip connection is performed, the underfill 304 is usually filled between the semiconductor element 302 and the semiconductor mounting substrate 301. However, since the surface of the semiconductor mounting substrate 301 has no step due to the circuit, the underfill 304 is not filled. 304 is very advantageous for the filling reliability. On the other hand, a step of forming the underfill 304 on the mounting surface of the semiconductor element 302 in advance may be adopted.

Next, the semiconductor element 302 is sealed with a sealing resin 305.
(FIG. 3 (n)). As a sealing method, resin can be filled using a mold or the like, or sealing can be performed by potting. Although the entire surface of the semiconductor element 302 may be sealed, only the side surface of the semiconductor element 302 may be sealed in consideration of heat radiation characteristics.

Next, the conductive frame 207 on the connected layer 205 side is removed by etching (FIG. 3 (o-
1)). In the same manner as described above, a barrier metal 306 for preventing erosion and corrosion of the etchant is also formed on the connected layer 205 side. As a result, the pads for making an electrical connection with the outside and the wiring pattern are exposed. When the wiring layer is made of copper, considering that the surface of the barrier metal 306 is used as a solder ball mounting pad, the barrier metal 306 is used.
It is very preferable to use a two-layer structure consisting of gold and nickel in advance, since both the wettability of the solder balls and the prevention of the diffusion of gold into the wiring layer can be achieved. At this time, since the sealing resin 305 has a function of imparting rigidity, the handling property in the subsequent steps is secured, so that the conductive frame may be completely etched. Further, a part of the conductive frame 207 is connected to a conductor terminal 307 for external connection.
(FIG. 3 (o-2)) can also be left. In this case, improvement in the mounting reliability of the two-layer wiring semiconductor device can be expected.

Next, a solder resist layer 401 is formed on the surface of the exposed wiring pattern other than the external connection portion (FIG. 4 (p-1, 2)). As a method for forming the solder resist layer 401, any method can be applied as long as it is suitable for this manufacturing method. For example, a solder resist liquid resin may be directly applied by printing or coating to form a solder resist layer, or in the case of a dry film type, the solder resist layer may be laminated on the solder resist layer forming surface, and then subjected to normal pressure or vacuum lamination, vacuum Crimping can be performed using a press or the like. If the solder resist to be applied is photosensitive, the external connection pad 402 can be obtained through photosensitive patterning and development. Even if the applied solder resist is non-photosensitive, the external connection pad 402 can be formed by a method such as a printing mask or laser opening.

Next, the solder balls 403 are mounted on the external connection pads 402 by reflow, and the two-layer wiring semiconductor device 404 (FIG. 4 (r-1, 2)) of the present invention can be obtained.

The method of manufacturing a two-layer wiring semiconductor device according to the present invention and the features of the manufactured two-layer wiring semiconductor device are as follows. (1) Since the horizontal structure has no circuit steps on the exposed wiring pattern, particularly the mounting surface of the semiconductor element, underfill injection at the time of flip chip connection is easy,
In addition, the problem of embedding at the time of resin sealing does not occur. (2) When the semiconductor element is mounted, the conductive frame 207 on the connected layer 205 side provides rigidity. Therefore, even when the insulating resin layer 105 does not include reinforcing fibers such as glass cloth, warpage of the substrate, etc. And the mounting yield is improved. (3) partially etching the conductive frame 207;
It is also possible to form a conductor terminal 307 for external connection, and an improvement in mounting reliability can be expected due to a stress relaxation function. (4) When the solder balls 403 are mounted on the external connection pads 402, the sealing resin 305 imparts the rigidity of the device, so that the mounting is relatively easy and the mounting yield is improved.

[0032]

EXAMPLES The present invention will be described in more detail with reference to the following Examples, but it should not be construed that the invention is limited thereto.

Formulation example of adhesive m, p-cresol novolak resin (PAS-1: trade name, manufactured by Nippon Kayaku Co., Ltd.)
And 100 g of bisphenol F-type epoxy resin (RE-404S, trade name, manufactured by Nippon Kayaku Co., Ltd.) dissolved in 60 g of cyclohexane. 2 g was added to prepare an adhesive varnish.

Example of Manufacturing Method of Two-Layer Wiring Semiconductor Device Using a 70 μm thick electrolytic copper foil (manufactured by Mitsui Mining & Smelting Co., Ltd., 3EC-VLP: trade name) as a conductive frame, after performing surface roughening treatment , A dry film resist (Nichigo Morton Co., Ltd., NIT1015: trade name) is laminated and exposed and developed using a predetermined negative patterning mask to form a plating resist necessary for forming the wiring layer 104 did. Next, using the electrolytic copper foil as a lead for electrolytic plating, the barrier metal is electrolytic gold plated,
This was continuously performed so as to have a two-layer structure of electrolytic nickel plating, and a wiring layer was formed by electrolytic copper plating. The wiring layer has a line width / space / thickness of 15/15/10 μ at the minimum part
m. Next, the unevenness of the wiring layer was embedded by using vacuum lamination in a dry film resin (CFP-1122: trade name, manufactured by Sumitomo Bakelite Co., Ltd.)
An insulating resin layer having a thickness of μm was formed. Next, the surface of the insulating resin layer was irradiated with a UV-YAG laser to form a via having a diameter of 40 μm. Next, using the electrolytic copper foil as a lead for electrolytic plating, the via was filled by electrolytic copper plating to form a copper post. Further, Sn / 2.5 was applied to the surface of the obtained copper post.
A joining metal layer made of Ag solder was formed by electrolytic plating. On the other hand, a 150 μm-thick rolled copper sheet having a roughened surface (EFTEC-64T, trade name, manufactured by Furukawa Electric Co., Ltd.)
Was used as a conductive frame, a barrier metal was formed by gold plating / nickel plating in the same process as described above, and a wiring layer was formed continuously by electrolytic copper plating to obtain a connected layer having pads. Next, the adhesive varnish obtained above was applied using a bar coater, and dried at 80 ° C. for 20 minutes to form an adhesive layer. The positioning marks formed in advance on the connection layer and the connection layer are read by an image recognition device, the two are aligned, and temporarily press-bonded at a temperature of 100 ° C., and then heated and pressed at a temperature of 220 ° C. by a vacuum press. Then, the copper post penetrated the adhesive and was soldered to the pad, and the adhesive bonded the connection layer and the connection target layer. next,
The electrolytic copper foil on the connection layer side was removed using a ferric chloride-based etchant, and a flip chip was mounted on the exposed semiconductor mounting surface via gold stud bumps. The gap between the mounted chip and the semiconductor mounting surface is filled with an underfill (CRP-4055: trade name, manufactured by Sumitomo Bakelite Co., Ltd.), and a sealing resin (manufactured by Sumitomo Bakelite, EME-630)
0: Trade name) After the molding, the rolled copper plate on the connected layer side was removed by etching, and solder resist (manufactured by Taiyo Ink Co., Ltd., PSR-4;
000: trade name). Next, a eutectic solder ball was reflow mounted on the external connection terminal, and a two-layer wiring semiconductor device was obtained.

[0035]

According to the manufacturing method of the present invention, it is possible to obtain a horizontal structure having no circuit steps on the surface on which the semiconductor element is mounted, and to avoid underfilling and defective filling of the sealing resin. Furthermore, the rigidity of the substrate is always ensured during the manufacturing process, so that the handling performance at the time of mounting a semiconductor or mounting a solder ball and the process yield can be improved.
Further, since the wiring layers and the conductor posts are formed by electrolytic plating, it can be easily applied to a high density wiring rule, and a reduction in the number of layers can be expected to shorten the process and reduce the manufacturing cost.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an example of a method for manufacturing a two-layer wiring semiconductor device of the present invention.

FIG. 2 is a cross-sectional view (continued from FIG. 1) illustrating an example of a method for manufacturing a two-layer wiring semiconductor device of the present invention.

FIG. 3 is a cross-sectional view (continued from FIG. 2) illustrating an example of a method for manufacturing a two-layer wiring semiconductor device of the present invention.

FIG. 4 is a cross-sectional view (continued from FIG. 3) showing an example of a method for manufacturing a two-layer wiring semiconductor device of the present invention and a structural cross-sectional view of the obtained two-layer wiring semiconductor device.

[Explanation of symbols]

101, 207 Conductive frame 102 Plating resist layer 103, 305 Barrier metal 104 Wiring layer 105 Insulating resin layer 106 Via 201 Conductive post 202 Bonding metal layer 203 Adhesive layer 204 Connection layer 205 Connected layer 206 Connected portion 301 Semiconductor mounting Substrate 302 Semiconductor element 303 Bump 304 Underfill 305 Sealing resin 306, 307 External connection terminal 401 Solder resist layer 402 External connection pad 403 Solder ball 404 Two-layer wiring semiconductor device obtained by the manufacturing method of the present invention

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Jin Aoki 2-58 Higashishinagawa, Shinagawa-ku, Tokyo Inside Sumitomo Bakelite Co., Ltd. (72) Inventor Kensuke Nakamura 2-5-2-8 Higashishinagawa, Shinagawa-ku, Tokyo Sumitomo Bakelite Co., Ltd.

Claims (5)

[Claims] 1. A two-layer wiring comprising: a step of forming a barrier metal and a conductive wiring layer by electrolytic plating using a conductive frame as a lead for electrolytic plating; and a step of removing the conductive frame by etching. A method for manufacturing a semiconductor device. 2. A step of forming a barrier metal and a conductor wiring layer by electrolytic plating using a conductive frame as a lead for electrolytic plating, a step of forming an insulating resin layer on the conductor wiring layer, Forming a via in the insulating resin layer so that a part thereof is exposed, forming a conductive post by electrolytic plating using the conductive frame as a lead for electrolytic plating, and forming a conductive post on the surface of the conductive post or in the same manner as described above. Forming a bonding metal layer on at least one of the surfaces of the connected portions of the formed connected layer with a conductive frame,
Forming an adhesive layer on at least one of the surface of the insulating resin layer or the surface of the connected layer; and bonding the conductor post and the bonded portion via the adhesive layer and the bonding metal layer. A step of bonding the insulating resin layer and the layer to be connected to each other with the adhesive layer; a step of removing the conductive frame on the side on which the semiconductor element is mounted by etching; and mounting and sealing the semiconductor element Removing the conductive frame on the back surface by etching, forming a solder resist layer on the exposed back surface of the barrier metal other than the external connection pads, and soldering on the external connection pads. 2 characterized by comprising a step of reflow mounting the ball.
A method for manufacturing a layer wiring semiconductor device. 3. A step of forming a barrier metal and a conductor wiring layer by electrolytic plating using the conductive frame as a lead for electrolytic plating, a step of forming an insulating resin layer on the conductor wiring layer, Forming a via in the insulating resin layer so that a part thereof is exposed, forming a conductive post by electrolytic plating using the conductive frame as a lead for electrolytic plating, and forming a conductive post on the surface of the conductive post or in the same manner as described above. Forming a bonding metal layer on at least one of the surfaces of the connected portions of the formed connected layer with a conductive frame,
Forming an adhesive layer on at least one of the surface of the insulating resin layer or the surface of the connected layer; and bonding the conductor post and the bonded portion via the adhesive layer and the bonding metal layer. A step of bonding the insulating resin layer and the layer to be connected to each other with the adhesive layer; a step of removing the conductive frame on the side on which the semiconductor element is mounted by etching; and mounting and sealing the semiconductor element Forming a solder resist layer on a surface other than the external connection lands; and forming a solder resist layer on a surface other than the external connection lands. A method for manufacturing a two-layer wiring semiconductor device, comprising a step of forming a bonding metal layer on a land. 4. The method for manufacturing a two-layer wiring semiconductor device according to claim 2, wherein said insulating resin layer does not use reinforcing fibers. 5. A method for manufacturing a two-layer wiring semiconductor device according to claim 1, wherein the surface of the conductor circuit on which the semiconductor element is mounted and the surface of the insulating resin layer have a horizontal plane structure. A two-layer wiring semiconductor device characterized by the above-mentioned.