JP2002261229A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To precisely position two chips with reference to a lead frame. SOLUTION: The method of manufacturing the semiconductor device comprising a first chip and a second chip which are laminated, in a state such that their centers on respective main faces on one side are separated in X-direction comprises a process preparing the lead frame which is provided with a first lead group, a second lead group, a support, a first positioning mark used to position the first chip in the X-direction, a second positioning mark used to position the second chip in the X-direction and are arranged, so as to be separated in the X-direction with reference to the first positioning mark and a third positioning part used to position the first and second chips in Y-direction at right angles to the X-direction; and a process in which the first chip is fixed to the support after the first chip has been positioned, so as to be aligned with the first and third positioning marks and a process, in which after the second chip has been positioned so as to be aligned with the second and third positioning marks, the second chip is fixed to the first chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly to a technology effective when applied to a semiconductor device manufacturing technology in which two semiconductor chips are stacked and sealed with one resin sealing body. It is about.

[0002]

2. Description of the Related Art For the purpose of high-density mounting of a semiconductor chip with a built-in storage circuit, two semiconductor chips with a built-in storage circuit of the same capacity are stacked, and these two semiconductor chips are sealed with one resin. There has been proposed a stacked semiconductor device which is sealed with a semiconductor device. For example, Japanese Patent Laying-Open No. 7-58281 (Patent Document 1) discloses a stacked semiconductor device having a LOC (Lead On Chip) structure. In addition, Japanese Unexamined Patent Publication No.
Japanese Patent Publication No. 302165 (publicly known document 2) discloses a stacked semiconductor device having a tab structure.

[0003]

SUMMARY OF THE INVENTION The present inventors are developing a stacked semiconductor device having a new structure. The stacked semiconductor device includes a first semiconductor chip having a plurality of electrodes arranged along a first side on a first side of a first side and a second side opposed to each other on a circuit forming surface. A first semiconductor chip and a first semiconductor chip,
A plurality of first leads electrically connected to the electrodes of the semiconductor chip via conductive wires; and a plurality of first leads disposed outside the second side of the first semiconductor chip, wherein the conductive wires are connected to the electrodes of the second semiconductor chip. A plurality of second leads which are electrically connected to each other via the first and second semiconductor chips, a support lead fixed to a circuit forming surface of the first or second semiconductor chip, and a plurality of first and second semiconductor chips and the first and second leads. It has a resin sealing body for sealing the inner part, the wires, the support leads, and the like. First
And the second semiconductor chip is in a state where the respective back surfaces face each other such that the first side of the second semiconductor chip is located on the opposite side to the first side of the first semiconductor chip, and
The center of each of the semiconductor chips is such that the first side is located outside the second side of the second semiconductor chip and the first side of the second semiconductor chip is located outside the second side of the first semiconductor chip. Are bonded and fixed to each other in a state where they are separated in one direction.

However, the present inventors have found a new problem during the development of the aforementioned stacked semiconductor device.

A stacked semiconductor device is manufactured by an assembly process using a single lead frame. The lead frame has a configuration in which a first lead group, a second lead group, a support lead, and the like are arranged in a region surrounded by a frame. The first and second lead groups are spaced apart from each other in the X direction. The support lead is disposed between the first lead group and the second lead group, and extends along a Y direction orthogonal to the X direction.

In manufacturing a stacked semiconductor device, a first semiconductor chip is bonded and fixed to support leads of a lead frame, and then a second semiconductor chip is bonded and fixed to the first semiconductor chip. Therefore, the first side of the first semiconductor chip (the side on which the electrodes are arranged) is located outside the second side of the second semiconductor chip (the side on which the electrodes are not arranged), and
First and second semiconductors such that a first side (side on which electrodes are arranged) of the semiconductor chip is located outside a second side (side on which electrodes are not arranged) of the first semiconductor chip. In order to separate the centers of the chips in the X direction, it is necessary to accurately position the first and second semiconductor chips in the X direction in the chip bonding step.

However, since the positioning of the first and second semiconductor chips in the X direction is performed with reference to the first and second lead groups which are arranged apart from each other in the X direction, the first and second semiconductor chips are positioned. It has been difficult to accurately position the chip in the X direction.

When the positioning in the X direction becomes inaccurate, the distance (position shift) between the centers of the first and second semiconductor chips in the X direction becomes extremely larger than a predetermined dimension. In such a case, a problem that the size becomes extremely small is likely to occur, which leads to a decrease in manufacturing yield.

An object of the present invention is to provide a technique capable of accurately positioning two semiconductor chips with respect to a lead frame.

Another object of the present invention is to provide a technique capable of improving the production yield of a semiconductor device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A method of manufacturing a semiconductor device having a first semiconductor chip and a second semiconductor chip stacked in a state where the center of each main surface is separated in the X direction.
A first lead group and a second lead group disposed apart from each other in a direction, a support disposed between the first lead group and the second lead group, and the first semiconductor in the X direction. A first positioning mark used for positioning the chip, and a second positioning mark used for positioning the second semiconductor chip in the X direction, wherein the second positioning mark is separated from the first positioning mark in the X direction. Preparing a lead frame having a second positioning mark arranged as described above, and a third positioning mark used for positioning the first and second semiconductor chips in a Y direction orthogonal to the X direction; Fixing the first semiconductor chip to the support after positioning the first semiconductor chip in accordance with the first and third positioning marks; After positioning the second semiconductor chip in accordance with the serial second and third positioning mark, and a step of fixing the second semiconductor chip to the first semiconductor chip.

(2) In the method of manufacturing a semiconductor device according to the means (1), two first and second positioning marks are respectively arranged on the first and second lead group sides. The two first and second positioning marks respectively disposed on the first and second lead group sides are spaced apart in the Y direction.

(3) In the method of manufacturing a semiconductor device according to the means (2), the two first positioning marks arranged on the first lead group side are arranged on the first lead group side. The two first positioning marks which are located on the first lead group side with respect to the two second positioning marks and which are disposed on the second lead group side are the second positioning marks.
It is located on the first lead group side with respect to the two second positioning marks arranged on the lead group side.

(4) In the method of manufacturing a semiconductor device according to the means (3), the first and second lead groups include a plurality of leads arranged along the Y direction, and The two first and second arranged on the group side
One positioning mark is provided for each of the leads located at the first stage and the last stage of the lead arrangement of the first lead group, and the two first and second positioning marks arranged on the second lead group side are provided. One mark is provided for each of the leads located at the first stage and the last stage of the lead arrangement of the second lead group.

(5) In the method of manufacturing a semiconductor device according to the additional step (3), the lead frame may include the first frame.
And a frame in which the leads of the second lead group and the support are connected, and the first and second alignment marks are provided on the frame.

According to the above-described means, the first semiconductor chip is positioned according to the first and third positioning marks, and the second semiconductor chip is positioned according to the second and third positioning marks. The two semiconductor chips can be accurately positioned with respect to the lead frame.

Further, there is a problem that the distance (positional deviation) for separating the respective centers of the first and second semiconductor chips in the X direction becomes extremely larger or smaller than a predetermined dimension. Because the occurrence can be suppressed,
The manufacturing yield of the semiconductor device can be improved.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

[0021] In the present embodiment, TSOP (T hin S mall
In O ut-line P ackage) type, for example of applying the present invention to a semiconductor device of the type I having an array of leads on two short sides facing each other of the resin sealing body will be described.

FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention in which an upper portion of a resin sealing body is removed.
FIG. 2 is a sectional view taken along line AA of FIG. 1, and FIG.
It is sectional drawing which follows the BB line of FIG.

As shown in FIGS. 1, 2 and 3, the semiconductor device 1 of this embodiment has two semiconductor chips (2, 4).
, A first lead group including a plurality of leads 11, a second lead group including a plurality of leads 12, a plurality of conductive wires 7, and two support leads 14 as a support, for example.
And a resin sealing body 8 for sealing them. Semiconductor chip (hereinafter simply referred to as chip) 2
And 4 are stacked with their respective back surfaces facing the respective circuit forming surfaces (2A, 4A) facing each other. The planar shape of the resin sealing 8 is formed in a square shape, and in this embodiment, is formed in a rectangular shape.

The chips 2 and 4 have the same outer dimensions. The planar shape of the chips 2 and 4 is formed in a square shape, and in the present embodiment, is formed in, for example, a rectangular shape. Each of the chips 2 and 4 has, as a storage circuit, a 64-megabit EEP called a flash memory, for example.
ROM (E lectrically E rasable P rogrammable R ea
d O nly M emory) has been built.

On the circuit forming surface (one main surface) 2A of the chip 2, a plurality of electrodes (on one short side 2A1 side) of the two short sides facing each other are arranged along one short side 2A1. Bonding pads) 3 are arranged. On the circuit forming surface 4A of the chip 4,
A plurality of electrodes (bonding pads) are formed along one short side 4A1 on one short side 4A1 side of the two short sides.
5 are arranged.

The circuit pattern of the flash memory built in the chip 2 is the same as the circuit pattern of the flash memory built in the chip 4. Also, chip 2
The arrangement pattern of the electrodes 3 formed on the circuit formation surface 2A is the same as the arrangement pattern of the electrodes 5 formed on the circuit formation surface 4A of the chip 4. That is, chips 2 and 4
Have the same structure.

The resin sealing body 8 is formed by, for example, a transfer molding method using a biphenyl-based thermosetting resin to which a phenol-based curing agent, silicone rubber, a filler and the like are added for the purpose of reducing the stress. ing. The transfer molding method is a method of using a mold having a pot, a runner, an injection gate, a cavity, and the like, and injecting a resin from the pot into the cavity through the runner and the injection gate to form a resin sealing body. .

A first lead group consisting of a plurality of leads 11 and a second lead group consisting of a plurality of leads 12 are spaced apart from each other in the X direction (in this embodiment, the direction in which the long side of the chip extends). I have. A plurality of leads 1 of the first lead group
1 is arranged along one of the two short sides of the resin sealing body 8 facing each other, and the plurality of leads 12 of the second lead group are arranged along the other short side of the resin sealing body 8. Are arranged. The plurality of leads 11 and 12 extend over the inside and outside of the resin sealing body 8 and have an inner part located inside the resin sealing body 8 and an outer part located outside the resin sealing body 8. It has become. Each inner part of the plurality of leads 11 is arranged outside one short side 2A1 of the chip 2 and is electrically connected to each electrode 3 of the chip 2 via a conductive wire 7. Each inner part of the plurality of leads 12 is arranged outside the other short side 2A2 of the chip 2 and is electrically connected to each electrode 5 of the chip 4 via a conductive wire 7. A plurality of leads 11 and 12
Are bent and formed in a gull wing shape, which is one of the surface mount type lead shapes.

The chips 2 and 4 are stacked with their back surfaces facing each other such that one short side 4A1 of the chip 4 is located on the opposite side to one short side 2A1 of the chip 2. . In the chips 2 and 4, one short side 2A1 of the chip 2 is located outside the other short side 4A2 of the chip 4, and one short side 4A1 of the chip 4 is
Are stacked such that their centers (2P, 4P) are spaced apart from each other in the X direction so as to be located outside the other short side 2A2. An insulating adhesive resin film 6 made of, for example, a thermosetting resin is interposed between the chip 2 and the chip 4 as an adhesive, and the chips 2 and 4 are bonded and fixed to each other by the adhesive resin film 6. I have.

Here, the center 2P of the chip 2 and the chip 4
4P means the intersection of diagonal lines on the circuit formation surface of each chip. In addition, 8P in FIG.
The center 8P is the intersection of diagonal lines in the plane of the resin sealing body 8.

The two support leads 14 are adhesively fixed to the circuit forming surface 2A of the chip 2 with an insulating adhesive resin film 15 made of, for example, a thermosetting resin as an adhesive. Further, the two support leads 14 extend along the Y direction orthogonal to the X direction, and cross the two long sides of the chip 2. Further, the two support leads 14 are arranged apart from each other in the X direction. Note that the two support leads 14 are subjected to offset processing for providing a height difference between a portion extending on the circuit forming surface 2A of the chip 2 and a portion extending outside the chip 2.

As shown in FIG. 1, the lead 11 located at the first stage and the last stage of the lead arrangement of the first lead group has a longer inner portion than the other leads 11. Further, the length of the inner portion of each of the leads 12 located at the first stage and the last stage of the lead array of the second lead group is longer than those of the other leads 12. The inner portions of the leads 11 and 12 located at the first stage and the last stage are stretched so that the tips thereof face the long sides of the chips 2 and 4.

Positioning marks 16 and 17 are provided at the tips of the inner portions of the leads 11 and 12 located at the first and last stages of the first and second lead groups, respectively. The two positioning marks 16 provided on the leads 11 of the first lead group are located closer to the first lead group than the two positioning marks 17 provided on the leads 11 of the first lead group. 2 on County Lead 12
One positioning mark 16 corresponds to the lead 1 of the second lead county.
2 is more than the two positioning marks 17 provided in
It is located on the Reed County side.

The four positioning marks 16 and 17 are:
It is composed of a protrusion protruding from the tip of the inner part of the lead toward the chip. The four positioning marks 16 are used for positioning the chip 2 in the X direction in the chip bonding step. In the chip bonding step, the four positioning marks 17
Is used for positioning in the X direction.

Each of the two support leads 14 is provided with two positioning marks 18. Two positioning marks 18 respectively provided on the two support leads 14
Are arranged apart from each other in the Y direction. The two positioning marks 18 provided on the first lead group side support lead 14 are formed by protrusions protruding from the support lead 14 toward the first lead group, and are provided on the second lead group side support lead 14. The two positioning marks 18 provided are
It is configured by a projection projecting from the support lead 14 toward the second group of leads. The four positioning marks 14
In the chip bonding step, Y of chips 2 and 4
Used for directional positioning.

The first and last leads 11 of the first lead group
Are located on the first imaginary line extending along the Y direction, and the two positioning marks 16 provided on the first and last leads 12 of the second lead group. Are located on a second virtual line extending along the Y direction. The distance between the first virtual line and the second virtual line is substantially equal to the length of the chip 2 in the X direction. That is, the chip 2 is positioned in the X direction in accordance with the four positioning marks 16 in the chip bonding step.

The first and last leads 11 of the first lead county
Are located on the third imaginary line extending along the Y direction, and the two positioning marks 17 provided on the first and last leads 12 of the second lead group are It is located on a fourth imaginary line extending along the Y direction. The distance between the third virtual line and the fourth virtual line is substantially the same as the width of the chip 4 in the X direction.
That is, in the chip bonding process, the chip 4
Positioning in the X direction is performed according to the four positioning marks 17.

The two support leads 14 are provided with two
Of the two positioning marks 18, two positioning marks 18 located on one long side of the chip 2 are located on a fifth imaginary line extending along the X direction, and the other long side of the chip. Are located on the sixth virtual line extending along the X direction. The distance between the fifth virtual line and the sixth virtual line is chip 2
And 4 are substantially the same as the width in the Y direction. That is, the chips 2 and 4 are 4 in the chip bonding process.
Positioning in the Y direction is performed according to the two positioning marks 18.

Next, a lead frame used for manufacturing the semiconductor device 1 will be described with reference to FIGS. FIG. 4 is a plan view of the lead frame, and FIG.
FIG. 4 is an enlarged plan view of a part of the main part. The actual lead frame has a multiple structure in which one block composed of two product formation regions arranged vertically in FIG. 4 is arranged in a plurality in the horizontal direction as viewed in FIG. FIG. 4 shows one block to make it easier to see.

As shown in FIGS. 4 and 5, the lead frame LF is placed inside a product forming region surrounded by the frame 10.
A first lead group including a plurality of leads 11, a second lead group including a plurality of leads 12, two support leads 14, 4
In this configuration, two positioning marks (16, 17, 18) and the like are arranged.

The first and second lead groups are arranged apart from each other in the X direction. Each lead (11, 12) of the first and second lead groups is arranged along the Y direction, and each outer portion is integrated with the frame 10. First and second
The leads (11, 12) of the lead group are connected to each other via a tie bar 13.

The two support leads 14 extend along the Y direction between the first lead group and the second lead group,
They are separated from each other in the X direction. Two support leads 14
Each of both ends is integrated with the frame body 10. 2
An adhesive resin film 15 used for bonding to a chip is attached to the support leads 14 of the book.

The lead frame LF is made of, for example, iron (Fe).
-It is formed by subjecting a flat plate made of a nickel (Ni) -based alloy or copper (Cu) or a copper-based alloy to etching or pressing to form a predetermined lead pattern.

The positioning marks (16, 17, 1)
8) is the same as that described above at the stage of the lead frame LF, and the description is omitted here.

Further, 8P1 shown in FIG. 5 is the center of the resin-sealed-body forming region, and the center 8P1 of the resin-sealed-body forming region is the intersection of the diagonal lines of the resin-sealed-body forming region having a square planar shape. Say

Next, the manufacture of the semiconductor device 1 will be described with reference to FIG.
This will be described with reference to FIGS. 6 and 9 are views for explaining the chip bonding step ((a) is a cross-sectional view along the X direction, (b) is a cross-sectional view along the Y direction), and FIGS. 7 and 10 are chip bonding steps. 8 and 11 are cross-sectional views for explaining a chip bonding step, and FIGS. 12A and 12B are views for explaining a wire bonding step ((a) and (b)).
Is a cross-sectional view), and FIG. 13 is a cross-sectional view for explaining a molding step.

First, the chip 2 is bonded and fixed to the lead frame LF. The bonding between the lead frame LF and the chip 2 is performed by mounting the chip 2 on the heat stage 20 as shown in FIG. 6, and then aligning the chip 2 with the positioning marks 16 and 18 as shown in FIG. After that, as shown in FIG. 8, the support leads 14 are thermocompression-bonded to the circuit forming surface 2A of the chip 2 with a bonding tool 21. The chip 2 is bonded and fixed in a state where one short side 2A1 is located on the first lead group (lead 11) side (see FIG. 7). The chip 2 is bonded and fixed with its center 2P shifted from the center 8P1 of the resin-sealed body formation region toward the first lead group along the X direction (see FIG. 7).

As shown in FIGS. 6 and 7, one of the short sides of the chip 2 is positioned on a first imaginary line connecting the two positioning marks 16 on the first lead group (lead 11) side, as shown in FIGS. 2A1 is located and the second lead group (lead 12)
The other short side 2A2 of the chip 2 is located on a second imaginary line connecting the two positioning marks 16 on the two sides, and the two positioning marks 18 on one end of each of the two support leads 14 are located.
One long side of the chip 2 is located on the fifth virtual line connecting the two, and the other of the chip 2 is placed on the sixth virtual line connecting the two positioning marks 18 on the other end sides of the two support leads 14. This is performed by moving the heat stage 20 in the X direction and the Y direction so that the long side is positioned. The movement of the heat stage 20 in the X and Y directions is performed based on the read data by reading the positions of the positioning marks 16 and 18 and the position of the chip 2 with an image recognition device. Therefore, since the chip 2 is positioned in the X direction and the Y direction according to the positioning marks 16 and 18, the chip 2 can be accurately positioned with respect to the lead frame LF.

When the chip 2 is mounted on the heat stage 20, a rotational displacement may occur in which each side of the chip 2 is inclined with respect to four virtual lines corresponding to each side.
In such a case, the heat stage 20 is rotated together with the movement in the X direction and the Y direction so that each side of the chip 2 is substantially parallel to the four virtual lines corresponding to the respective sides, and the rotational deviation is caused. Is corrected.

Next, after the lead frame LF is inverted so that the back surface of the chip 2 faces upward, the chip 4 is bonded and fixed to the chip 2. As shown in FIG. 9, the chip 2 and the chip 4 are bonded and fixed by transporting the chip 4 onto the chip 2 with the bonding resin film 6 attached to the back of the chip 4 facing the back of the chip 2. 23, and then, as shown in FIG.
Position the chip 4 according to 7 and 18 and then
As shown in FIG. 11, the chip 4 is mounted on the chip 2 by the transport collet 23, and thereafter, the chip 4 is thermocompression-bonded to the chip 2 with a bonding tool.
The chip 4 is bonded and fixed in a state where one short side 4A1 is located on the second lead group (lead 12) side (FIG. 10).
reference). The chip 4 is bonded and fixed with its center 4P shifted from the center 8P1 of the resin sealing body forming region toward the second lead group along the X direction (see FIG. 10).

As shown in FIGS. 9 and 10, the position of the chip 4 is determined by placing the other short side of the chip 4 on a third virtual line connecting the two positioning marks 17 on the first lead group (lead 11) side. 4A2 is located in the second lead group (lead 1).
2) One short side 4A1 of the chip 4 is located on a fourth imaginary line connecting the two positioning marks 17 on the side, and connects the two positioning marks 18 on one end side of each of the two support leads 14. One long side of the chip 4 is located on the fifth imaginary line, and the other long side of the chip 4 is located on the sixth imaginary line connecting the two positioning marks 18 on the other end sides of the two support leads 14. This is performed by moving the transport collet 23 in the X direction and the Y direction so that the side is positioned. The transfer collet 23 is moved in the X and Y directions by reading the positions of the positioning marks 17 and 18 and the position of the chip 4 with an image recognition device, and based on the read data. Therefore, since the chip 4 is positioned in the X direction and the Y direction in accordance with the positioning marks 17 and 18, it is possible to accurately position the chip 4 with respect to the lead frame LF.

When the chip 4 is mounted on the chip 2, there may be a case where a rotational displacement occurs in which each side of the chip 4 is inclined with respect to four virtual lines corresponding to each side. In such a case, the transport collet 23 is rotated together with the movement in the X direction and the Y direction so that each side of the chip 4 is substantially parallel to the four virtual lines corresponding to each side, and the chip 4 is rotated. Is corrected.

According to this step, the chips 2 and 4 face each other with their back surfaces facing each other such that one short side 4A1 of the chip 4 is located on the opposite side to one short side 2A1 of the chip 2. It is laminated. Also, chips 2 and 4
Is that one short side 2A1 of the chip 2 is located outside the other short side 4A2 of the chip 4,
The chips are stacked with their centers separated in the X direction so that A1 is located outside the other short side 2A2 of the chip 2.

Next, after the lead frame LF is inverted so that the circuit forming surface 2A of the chip 2 faces upward, the electrodes 3 of the chip 2 and the leads 11 are electrically connected by conductive wires 7. The connection between the electrode 3 of the chip 2 and the lead 11 is performed by mounting the chips 2 and 4 on the heat stage 24 with the heat stage 24 and the circuit forming surface 4A of the chip 4 facing each other, as shown in FIG. Do it. For example, an Au wire is used as the wire 7. As a method for connecting the wires 7, for example, a ball bonding (nail head bonding) method using ultrasonic vibration in combination with thermocompression bonding is used.

In this step, since one short side 2A of the chip 2 is located outside the other short side 4A2 of the chip 4, the protruding portion 2A comes into contact with the back surface of the chip 2.
By providing 4A on the heat stage 24, the back surface of the chip 2 can be brought into direct contact with the heat stage 24. As a result, the heat of the heat stage 24 is effectively transmitted to the electrode 3 of the chip 2, so that a poor connection between the electrode 3 of the chip 2 and the wire 7 can be reduced.

In this step, since the chip 4 is mounted on the heat stage 24 with the circuit forming surface 4A facing the heat stage 24, the chip 4 is heated to prevent the electrodes 5 of the chip 4 from being damaged. The stage 24 is provided with a depression 24B.

Next, after the lead frame LF is inverted so that the circuit forming surface 4A of the chip 4 faces upward, the electrodes 5 of the chip 4 and the leads 12 are electrically connected by conductive wires 7. As shown in FIG. 12B, the electrodes 5 of the chip 4 are connected to the leads 12 by mounting the chips 2 and 4 on the heat stage 25 with the heat stage 25 facing the circuit forming surface 2A of the chip 2. Do it.

In this step, since the one short side 4A1 of the chip 4 is located outside the other short side 2A2 of the chip 2, the projecting portion 25A is brought into contact with the back surface of the chip 4 by the heat stage 25. By setting in
The back surface of the chip 4 can be brought into direct contact with the heat stage 24. In the present embodiment, since the entire back surface of the chip 4 is covered with the bonding resin film 6, the back surface of the chip 4 is indirectly contacted with the heat stage 25 via the bonding resin film 6. As a result, heat stage 2
Since the heat of No. 4 is effectively transmitted to the electrodes 3 of the chip 2, the connection failure between the electrodes 3 of the chip 2 and the wires 7 can be reduced.

In this step, since the chip 2 is mounted on the heat stage 25 with the circuit forming surface 2A facing the heat stage 25, the wires electrically connecting the electrodes 5 of the chip 2 and the leads 11 are formed. In order not to damage the heat sink 7, the heat stage 25 is provided with a depression 25B.

Next, after inverting the lead frame LF so that the circuit forming surface 2A of the chip 2 faces upward, FIG.
As shown in FIG. 3, the lead frame LF is transferred to the upper mold 26A and the lower mold 26 of the mold 26 of the transfer molding apparatus.
B. At this time, inside the cavity 27 formed by the upper mold 26A and the lower mold 26B,
The chips 2 and 4, the inner portions of the leads 11 and 12, the support leads 14, the wires 7, and the like are arranged.

Next, a fluid thermosetting resin (molten resin) is injected from the pot of the mold 26 through the runner and the injection gate into the cavity 27 to form the resin sealing body 8. In this step, the chips 2 and 4, the inner portions of the leads 11 and 12, the support leads 14, the wires 7, and the like are sealed with a resin sealing body 8.

Next, the lead frame LF is taken out from the mold 26, and then the tie bar connected to the leads 11 and 12) is cut.
Cutting the outer portions of the leads 11 and 12 from the frame 10 of F, then forming the outer portions of the leads 11 and 12 into a gull wing shape, and then cutting the support leads 14 from the frame 10 of the lead frame LF. Thereby, the semiconductor device 1 shown in FIGS. 1 to 3 is almost completed.

As described above, according to the present embodiment, the following effects can be obtained.

In the method of manufacturing the semiconductor device 1, the step of preparing the lead frame LF and the positioning mark 16
After positioning the chip 2 in accordance with the steps 18 and 18, the step of fixing the support lead 14 chip 2 and the step of positioning the chip 4 in accordance with the positioning marks 17 and 18 and then fixing the chip 4 to the chip 2 are performed. Including.

As a result, the chip 2 is positioned in accordance with the positioning marks 16 and 18, and the chip 4 is positioned in accordance with the positioning marks 17 and 18, so that the two chips (2, 2
The positioning of 4) can be performed accurately.

The center (2) of each of chips 2 and 4
(P, 4P) in the X direction can be suppressed from being extremely large or extremely smaller than a predetermined dimension, so that the production yield of the semiconductor device 1 can be suppressed. Can be improved.

In the present embodiment, an example has been described in which two positioning marks 18 are provided at each of one end and the other end of the support lead extending in the Y direction. 1 at one end and at the other end
They may be provided one by one.

In the present embodiment, as shown in FIG. 7, an example in which the positioning marks 16 and 17 are provided on the leads (11, 12) of the first and second lead groups has been described. As a modified example, as shown in FIG. 14 (a plan view of a main part of a lead frame in a state where a wire bonding step has been performed), positioning marks 16 and 17 may be provided on frame 10 of lead frame LF. The positioning marks 16 and 17 are formed by protrusions projecting from the frame body 10 toward the inside of the resin sealing body forming region. It is desirable that the projections be projected to such an extent that they can be recognized by the image recognition device and do not enter the inside of the resin sealing body.

In recent years, the leads of the lead group have been reduced in mechanical strength due to miniaturization accompanying the increase in the number of pins and miniaturization of the semiconductor device, and the leads have been easily deformed. Therefore, when the positioning marks 16 and 17 are provided on the lead, a problem that the position is changed due to deformation of the lead easily occurs. On the other hand, the mechanical strength of the frame body 10 is stronger than that of the lead, and the frame body 10 is unlikely to be deformed. Therefore, it is necessary to suppress the problem that the positions of the positioning marks 16 and 17 change. Can be. As a result, the semiconductor device 1 can be manufactured stably.

As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

For example, the present invention provides a TSOP type
The present invention can be applied to a type II semiconductor device in which leads are arranged on two long sides facing each other of a resin sealing body.

[0072]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

The positioning of the two semiconductor chips with respect to the lead frame can be performed accurately. Further, the production yield of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view showing a state in which an upper portion of a resin sealing body of a semiconductor device according to an embodiment of the present invention has been removed.

FIG. 2 is a sectional view taken along line AA shown in FIG.

FIG. 3 is a sectional view taken along line BB shown in FIG.

FIG. 4 is a plan view showing a schematic configuration of a lead frame used for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is an enlarged plan view of a part of FIG. 4;

FIGS. 6A and 6B are views for explaining a chip bonding step in manufacturing a semiconductor device according to an embodiment of the present invention (FIG. 6A is a cross-sectional view along the X direction, and FIG. 6B is a cross-sectional view along the Y direction); It is.

FIG. 7 is a plan view for explaining a chip bonding step in manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 8 is a cross-sectional view for explaining a chip bonding step in manufacturing the semiconductor device according to one embodiment of the present invention;

FIGS. 9A and 9B are views for explaining a chip bonding step in manufacturing a semiconductor device according to an embodiment of the present invention (FIG. 9A is a cross-sectional view along the X direction, and FIG. 9B is a cross-sectional view along the Y direction); It is.

FIG. 10 is a plan view for explaining a chip bonding step in manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 11 is a cross-sectional view for explaining a chip bonding step in manufacturing the semiconductor device according to one embodiment of the present invention;

FIGS. 12A and 12B are diagrams (FIGS. 12A and 12B are cross-sectional views) for explaining a wire bonding step in manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 13 is a cross-sectional view for explaining a molding step in the manufacture of the semiconductor device according to one embodiment of the present invention.

FIG. 14 is a plan view of relevant parts of a lead frame in a state where a wire bonding step has been performed in the manufacture of a semiconductor device which is a modification of the embodiment of the present invention;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2, 4 ... Semiconductor chip, 3, 5 ... Electrode, 6 ... Adhesive resin film, 7 ... Wire, 8 ... Resin sealing body, LF ... Lead frame, 10 ... Frame body, 11, 12
… Lead, 13… tie bar, 14… support lead, 15…
Adhesive resin film, 20, 22, 24, 25: heat stage, 21: bonding tool, 23: transport collet, 26: mold.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tamaki Wada 5-22-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Super-LSI Systems Co., Ltd. (72) Inventor Masachika Masuda Tokyo 5-20-1, Josuihoncho, Kodaira-shi F-term (reference) in the semiconductor group, Hitachi, Ltd. 5F067 AA02 BA06 BB01 CB00

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device having a first semiconductor chip and a second semiconductor chip stacked such that centers of respective one main surfaces are separated in an X direction, wherein the semiconductor devices are separated from each other in the X direction. A first lead group and a second lead group arranged in a horizontal direction, and the first lead group and the second lead group.
A support disposed between the lead group and a first semiconductor chip used for positioning the first semiconductor chip in the X direction;
A positioning mark, and a second positioning mark used for positioning the second semiconductor chip in the X direction, wherein the second positioning mark is spaced apart from the first positioning mark in the X direction. Preparing a lead frame having a mark for use and a third mark for use in positioning the first and second semiconductor chips in a Y direction orthogonal to the X direction; The first according to the mark
After positioning the semiconductor chip, the first
Fixing a semiconductor chip; and aligning the second and third positioning marks with the second and third positioning marks.
Fixing the second semiconductor chip to the first semiconductor chip after positioning the semiconductor chip. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first and second positioning marks are arranged two each on the first and second lead group sides. The method of manufacturing a semiconductor device according to claim 1, wherein the two first and second positioning marks respectively disposed on the second lead group side are separated from each other in the Y direction. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the two first positioning marks arranged on the first lead group side are the two first positioning marks arranged on the first lead group side.
The two first positioning marks are located closer to the first lead group than the two second positioning marks, and the two first positioning marks are located closer to the second lead group.
A method of manufacturing a semiconductor device, wherein the semiconductor device is located closer to the first lead group than two second positioning marks. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the first and second lead groups include a plurality of leads arranged along the Y direction, and the first and second lead groups are arranged on the first lead group side. The two first and second positioning marks that are arranged are provided one each for the leads located at the first and last stages of the lead arrangement of the first lead group, and are arranged on the second lead group side. Wherein the two first and second positioning marks are respectively provided on leads located at the first and last stages of the lead arrangement of the second lead group, respectively. . 5. The method of manufacturing a semiconductor device according to claim 3, wherein the lead frame has a frame body in which the leads of the first and second lead groups and the support are connected. And a second alignment mark is provided on the frame body.