JP2002261060A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for preventing an adhesive agent of a surface protection tape from remaining on an electrode. SOLUTION: In a wafer rear surface grinding process, before sticking a surface-protecting adhesive tape for protecting the surface of the wafer, the surface of the wafer is coated with a resister and the wafer rear surface is ground with the surface protected. After grinding, the wafer is put into a solvent to remove the resist on the surface of the wafer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a backside grinding of a semiconductor wafer.

[0002]

2. Description of the Related Art In semiconductor devices, after forming circuit elements and wirings, a passivation film is formed on the entire surface of a wafer to protect the surface. Thereafter, in order to electrically connect with the external wiring, a through-hole is formed on the passivation film by using a photolithography technique to expose an electrode portion. Thereafter, in order to reduce the thickness of the wafer, an adhesive tape for protecting the surface is attached to the surface of the wafer, and the back surface of the wafer is ground while the surface is protected.

Incidentally, a surface protective film such as a polyimide film having a thickness of about 1 to 15 μm may be provided on the passivation film. In recent years, there has been an increasing number of cases where the circuit inspection is changed before the grinding process of the back surface of the wafer, instead of after the grinding process. Therefore, the wafer may be subjected to the grinding process in a state where ink dots having a height of about 10 to 40 μm are provided on the wafer surface.

[0004] Further, due to the increase in the package form such as a chip size package, the height of the wafer surface is 10 to 10 mm.
There are also increasing examples of providing bumps of about 100 μm, and in this state, the bumps may be subjected to the above-mentioned grinding step.

[0005]

As described above, in the conventional manufacturing of a semiconductor device, the surface protection adhesive tape is stuck in a state where the electrodes electrically connected to the external wiring are exposed. The adhesive of the surface protection tape will be attached. Then, after grinding the back surface of the wafer, the surface protection tape is unnecessary and thus physically peeled off, but at that time, the adhesive is transferred to the electrode portion. There has been a problem that the residue of the adhesive causes poor connection.

On the surface of the wafer on the passivation other than the electrodes, the surface of the wafer cannot be sufficiently protected by sticking the surface protection adhesive tape due to the unevenness of 5 to 100 μm. Has caused various adverse effects. In particular, when the above-described ink dots and bumps are provided, they are particularly noticeably observed, which is a serious problem.

[0007]

The present invention uses the following means to solve the above-mentioned problems. In a grinding process for reducing the thickness of the wafer, a liquid resist is coated on the entire surface of the wafer before applying a surface protection adhesive tape for protecting the wafer surface. Then, after the resist is cured by heat treatment or the like, an adhesive tape for surface protection is attached, and the back surface of the wafer is ground while the surface is protected. Then, after grinding, the wafer is put into a solvent to remove the coated resist, whereby the surface protection tape is peeled off.

As described above, by coating the resist between the surface protection tape and the wafer, the unevenness on the wafer surface is flattened, and at the time of peeling, the adhesive remains on the electrode portion to remove the resist with a solvent. This has been eliminated, and the reliability of the connection with the external terminal has been improved.

[0009]

Embodiments of the present invention will be described below in detail. FIG. 1 is a sectional view of a wafer back surface grinding step showing an embodiment of the present invention.

First, as shown in FIG. 1A, a pad electrode 2 for wiring connection with an external circuit is provided on the surface of a semiconductor wafer 1, and a passivation film for protecting the wiring and the circuit on the semiconductor wafer 1 is provided. After forming the through holes 3, through holes are formed on the pad electrodes 2 by a conventional photolithography and etching process.

Next, as shown in FIG. 1B, a resist 4 is formed on the surface of the semiconductor wafer 1 having the pad electrodes 2 and circuits.
Is applied. At this time, the thickness of the resist 4 is determined by the unevenness of the surface of the semiconductor wafer 1. That is, the resist 4 is coated with an optimum coating amount so as to absorb the unevenness and perform the flattening.
Is applied. After the application, the resist 4 is cured by heat treatment or the like.

Next, as shown in FIG. 1C, a surface protection tape 5 is attached to the surface of the cured resist 4. At this time, the surface protection tape 5 is applied to the resist 4 by pressurization and / or heating, and is sufficiently adhered to the resist 4 to uniformly protect the surface of the semiconductor wafer 1. Further, since the surface of the pad electrode 2 is protected by the resist 4 and the surface protection tape adhesive 6 of the surface protection tape 5 does not directly touch the surface of the pad electrode 2, there is no concern about contamination from the adhesive. Next, as shown in FIG. 1D, the back surface of the semiconductor wafer 1 is ground while the front surface of the semiconductor wafer 1 is protected, and the semiconductor wafer 1 is ground.
To the desired thickness. Grinding is performed using conventional technology,
At this time, water for cooling and cleaning is jetted at a high pressure. However, since the resist 4 flattens the irregularities on the surface of the semiconductor wafer 1, the surface protection tape 5 can be sufficiently adhered to the surface of the semiconductor wafer 1, Infiltration of water into the scribe line portion is prevented, and there is no particular concern that water may enter the circuit and break down the wafer or cause contamination of the pad electrode 2. After further grinding,
By removing the resist 4 using a solvent, the surface protection tape 5 is lifted off to peel off from the semiconductor wafer 1 and complete the semiconductor wafer back surface grinding step.

FIG. 2 shows a case where bumps 7 are provided on the surface of the semiconductor wafer 1 in place of the pad electrodes 2 and ink dots 8 are provided on the circuit forming surface for identifying defective chips after the circuit inspection. ing.

First, as shown in FIG. 2A, bumps 7 for wiring connection to an external circuit are formed on the surface of the semiconductor wafer 1 and a circuit forming surface is used for identifying a defective chip after inspection of the circuit. Ink dots 8 are provided. The height of the bump 7 and the ink dot mark 8 is 5 μm or more.

Next, as shown in FIG. 2B, when there is a projection on the semiconductor wafer 1 having a high height, the resist 4 is used for flattening. That is, the application amount of the resist 4 is determined in accordance with the highest one, and the entire surface is applied. After the application, the back surface grinding step is completed through the steps of FIGS. 1 (C) to 1 (D).

[0016]

As described above, according to the present invention, the following effects can be obtained.

Since the adhesive of the surface protection tape does not directly contact the pad electrode, there is no contamination from the adhesive. The peeling of the surface protection tape is performed by removing the resist with a solvent and lifting off the surface protection tape, so that the adhesive does not remain. Therefore, there is an effect of reducing the occurrence of mounting defects in a mounting step, for example, wire bonding after the grinding step.

By applying a resist, surface irregularities can be flattened and a surface protection tape can be applied thereon to grind the back surface, so that the thickness variation in the ground wafer can be reduced. In addition, when a wafer having bumps or the like is ground, a part of the wafer is locally thinned due to the influence of the bumps.

In addition, even if foreign matter adheres to the wafer surface before the grinding step, the wafer is flattened to avoid cracking of the wafer during grinding. As described above, the present invention has an effect of reducing the defect occurrence rate in the grinding process.

[Brief description of the drawings]

FIG. 1 is a sectional view of a wafer back surface grinding step of the present invention.

FIG. 2 is a cross-sectional view of a wafer back surface grinding step when there are bumps and ink dots of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Pad electrode 3 Passivation film 4 Resist 5 Surface protection tape 6 Surface protection tape adhesive 7 Bump 8 Ink dot mark

Claims (4)

[Claims] In manufacturing a semiconductor device, a circuit is formed on a surface of the semiconductor wafer, and a resist is coated on the surface of the semiconductor wafer. A method of manufacturing a semiconductor device, characterized in that the back surface of the semiconductor device is ground, the resist is removed with a solvent, and the pressure-sensitive adhesive sheets are lifted off and peeled off. 2. The semiconductor wafer according to claim 1, wherein a maximum of 1
The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device has irregularities of about 100 μm. 3. The method for manufacturing a semiconductor device according to claim 1, further comprising a passivation film on the circuit formation surface of the semiconductor wafer or a surface protection film thereon. 4. The method according to claim 1, wherein the semiconductor wafer has ink dots or bumps on a circuit formation surface.