JP2002260389A5 - - Google Patents
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- Publication number
- JP2002260389A5 JP2002260389A5 JP2001056392A JP2001056392A JP2002260389A5 JP 2002260389 A5 JP2002260389 A5 JP 2002260389A5 JP 2001056392 A JP2001056392 A JP 2001056392A JP 2001056392 A JP2001056392 A JP 2001056392A JP 2002260389 A5 JP2002260389 A5 JP 2002260389A5
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- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001056392A JP2002260389A (ja) | 2001-03-01 | 2001-03-01 | 連想メモリ |
| US10/082,229 US6611445B2 (en) | 2001-03-01 | 2002-02-26 | Content addressable memory having redundant circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001056392A JP2002260389A (ja) | 2001-03-01 | 2001-03-01 | 連想メモリ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002260389A JP2002260389A (ja) | 2002-09-13 |
| JP2002260389A5 true JP2002260389A5 (enExample) | 2008-04-03 |
Family
ID=18916425
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001056392A Pending JP2002260389A (ja) | 2001-03-01 | 2001-03-01 | 連想メモリ |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6611445B2 (enExample) |
| JP (1) | JP2002260389A (enExample) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002197873A (ja) * | 2000-12-27 | 2002-07-12 | Kawasaki Microelectronics Kk | 連想メモリ |
| US6714467B2 (en) * | 2002-03-19 | 2004-03-30 | Broadcom Corporation | Block redundancy implementation in heirarchical RAM's |
| JP4004847B2 (ja) * | 2002-05-08 | 2007-11-07 | 川崎マイクロエレクトロニクス株式会社 | 連想メモリ装置 |
| US6888731B2 (en) | 2002-11-29 | 2005-05-03 | Mosaid Technologies Incorporated | Method and apparatus for replacing defective rows in a semiconductor memory array |
| JP2004265528A (ja) * | 2003-03-03 | 2004-09-24 | Kawasaki Microelectronics Kk | 連想メモリ |
| JP2004288347A (ja) * | 2003-03-03 | 2004-10-14 | Renesas Technology Corp | 連想メモリ |
| KR100505684B1 (ko) | 2003-04-25 | 2005-08-02 | 삼성전자주식회사 | 칼럼 결함 복구가 가능한 캠 및 캄럼 결함 복구 방법 |
| US7065694B2 (en) * | 2003-09-25 | 2006-06-20 | International Business Machines Corporation | Adaptive runtime repairable entry register file |
| DE102004059206B4 (de) * | 2004-12-09 | 2016-03-31 | Polaris Innovations Ltd. | Speicherbauelement und Adressierung von Speicherzellen |
| JP4861012B2 (ja) | 2005-03-31 | 2012-01-25 | ルネサスエレクトロニクス株式会社 | Ｃａｍ装置 |
| KR100725096B1 (ko) * | 2005-05-10 | 2007-06-04 | 삼성전자주식회사 | 캠 장치 및 그의 리페어 방법 |
| JP2008257835A (ja) * | 2007-03-13 | 2008-10-23 | Renesas Technology Corp | 半導体装置 |
| US7996710B2 (en) * | 2007-04-25 | 2011-08-09 | Hewlett-Packard Development Company, L.P. | Defect management for a semiconductor memory system |
| CN102906739A (zh) * | 2010-02-18 | 2013-01-30 | 井上克己 | 具备信息过滤检测功能的存储器、使用该存储器的信息检测方法、含有该存储器的装置、信息检测方法、存储器使用方法及存储器地址比较电路 |
| JP4588114B1 (ja) * | 2010-02-18 | 2010-11-24 | 克己 井上 | 情報絞り込み検出機能を備えたメモリ、その使用方法、このメモリを含む装置。 |
| JP2013191255A (ja) * | 2012-03-14 | 2013-09-26 | Renesas Electronics Corp | 内容参照メモリシステム |
| US20150154317A1 (en) * | 2012-03-28 | 2015-06-04 | Katsumi Inoue | Memory provided with set operation function, and method for processing set operation processing using same |
| JP2015225675A (ja) * | 2014-05-26 | 2015-12-14 | ルネサスエレクトロニクス株式会社 | 連想メモリおよび半導体装置 |
| JP2019114311A (ja) * | 2017-12-22 | 2019-07-11 | ルネサスエレクトロニクス株式会社 | 検索メモリおよび検索システム |
| US20250383947A1 (en) * | 2024-06-17 | 2025-12-18 | Advanced Micro Devices, Inc. | Per row activation counting error handling |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3816560B2 (ja) * | 1995-12-25 | 2006-08-30 | 株式会社ルネサステクノロジ | 連想メモリ回路のテスト方法及び連想メモリ回路のテスト回路 |
| US6275406B1 (en) * | 1999-09-10 | 2001-08-14 | Sibercore Technologies, Inc. | Content address memory circuit with redundant array and method for implementing the same |
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2001
- 2001-03-01 JP JP2001056392A patent/JP2002260389A/ja active Pending
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2002
- 2002-02-26 US US10/082,229 patent/US6611445B2/en not_active Expired - Fee Related