JP2002257901A - Device for adjusting skew timing and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device for adjusting skew timing and its method by which the timing can be adjusted with high accuracy. SOLUTION: In this device having a circuit 2 for compensating the timing, a driver 1, a comparator 4, and parts 5, 6 for detecting transmission time, the circuit 2 for correct the timing corrects the timing of a test signal given to a device 3 to be measured, the driver 1 transmits the test signal corrected by the circuit 2 for correcting the timing to the device 3 to be measured, the comparator 4 inputs a waveform at an output terminal of the driver 1 and compares the waveform with prescribed comparison levels and outputs comparison result, and based on the comparison result outputted from the comparators 4, the parts 5, 6 for detecting the transmission time detect the transmission time of the test signal in a testing device for an IC, the prescribed comparison levels in the comparator 4 are determined based on the amplitude or the waveform inputted to the comparator 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a skew timing adjusting device and a skew timing adjusting method in an IC test apparatus.

[0002]

2. Description of the Related Art To adjust skew timing in an IC test apparatus, first, it is necessary to measure the transmission time of a test signal in the IC test apparatus. That is, FIG.
The timing of the test signal input to each pin (for example, point Y) of the device under test 3 shown in FIG.
This is because the transmission time of the test signal differs for each pin because the pattern length until the test signal is input to each pin of the device under test 3 differs for each pin. Therefore, it is necessary to measure the transmission time Tpd required for transmitting the test signal from the point X to the point Y.

Conventionally, the transmission time Tpd has been measured by the following method. First, the device under test 3 is set to I
The point Y is opened by removing from the C test apparatus, the mechanical relay 8 is turned on, and the mechanical relay matrix 10 is turned off. Then, a predetermined waveform is output from the driver 1. Then, since the point Y is open, the reflection coefficient is 1, and the waveform output from the driver 1 is totally reflected at the point Y, and the reflected wave returns. Then, the waveform observed at the point X is a staircase waveform in which the output waveform output from the driver 1 and the reflected wave from the point Y overlap as shown in FIG.

[0004] The staircase waveform at the point X is input to an analog comparator 4, which
The input staircase waveform voltage and the fixed comparison voltages VO1, V
Compare with O2. Then, the analog comparator 4 outputs an output signal whose state changes at times T1 and T2 when the magnitude relationship between the input voltage and the comparison voltage is switched.

The time K from time T1 to time T2 is determined by the digital comparator 5 and the timing signal generator 6.
(TG6). That is, while changing the timing signal output by the TG 6, the timing signal is compared with the output signal output from the analog comparator 4.
The time of the timing signal output from G6 is detected.

In such a method, the transmission time Tpd required for transmitting the test signal from the point X, which is the output terminal of the driver 1, to the point Y, which is the pin of the device under test 3, has been measured.

[0007]

However, in the above-described measuring method, the waveform at the point X changes as shown in FIG. 5 due to the variation in the output resistance of each driver 1, so that the time K cannot be measured. Since an error M occurs and high-precision measurement cannot be performed, high-precision timing adjustment cannot be performed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a skew timing adjustment apparatus and a skew timing adjustment method capable of adjusting timing with high accuracy.

[0009]

According to a first aspect of the present invention, there is provided a timing correction circuit for correcting the timing of a test signal supplied to a device under test, and a test signal corrected by the timing correction circuit is supplied to the device under test. A driver to be transmitted, a waveform at an output terminal of the driver, a comparator for comparing the waveform with a predetermined comparison level, and outputting a comparison result, and an IC based on the comparison result output from the comparator. In a skew timing adjustment device of an IC test device having a transmission time detecting unit for detecting a transmission time of a test signal in the test device, a predetermined comparison level in the comparator is determined by an amplitude of a waveform input to the comparator. A skew timing adjustment device characterized by being determined based on the skew timing.

According to a second aspect of the present invention, the predetermined comparison level in the comparator is a value obtained by multiplying the amplitude of a waveform input to the comparator by a predetermined coefficient. 1 is a skew timing adjustment device.

According to a third aspect of the present invention, the comparator includes:
3. The skew timing adjustment according to claim 1, wherein a waveform at an output terminal of the driver is input, the waveform is compared with a first comparison level and a second comparison level, and a comparison result is output. Device.

According to a fourth aspect of the present invention, the comparator includes:
At a first time when the magnitude relationship between the waveform at the output terminal of the driver and the first comparison level is switched, and at a second time when the magnitude relationship between the waveform at the output terminal of the driver and the second comparison level is switched. An output signal whose state changes is output, and the transmission time detector detects a time from a first time to a second time from a time at which a state of the output signal output from the comparator changes, From this time,
The skew timing adjusting device according to claim 3, wherein a transmission time of the test signal in the IC test device is calculated.

According to a fifth aspect of the present invention, a test signal is transmitted from a driver to a device under test, a waveform at an output terminal of the driver is input, the waveform is compared with a predetermined comparison level, and a comparison result is output. In the skew timing adjustment method of the IC test apparatus for detecting the transmission time of the test signal in the IC test apparatus based on the output comparison result, the predetermined comparison level may include a waveform amplitude at an output terminal of the driver. Is a skew timing adjustment method characterized by being determined based on

The invention according to claim 6 is the skew timing according to claim 5, wherein the timing of transmitting the test signal is corrected according to the transmission time of the test signal in the IC test apparatus. This is the adjustment method.

According to the present invention, the comparison level is determined based on the amplitude of the waveform input to the comparator, instead of fixing the comparison level in the comparator to a fixed value, and using the comparison level. Then, the transmission time of the test signal in the IC test apparatus is obtained. According to such a method, even if the waveform input to the comparator changes due to variations in the output resistance of the driver, it is possible to accurately measure the transmission time of the test signal in the IC test apparatus, and as a result, ,
High-precision timing adjustment becomes possible.

[0016]

FIG. 1 is a schematic configuration diagram of an IC test apparatus according to a first embodiment of the present invention. This IC test apparatus includes a DESKEW circuit 2 for correcting the timing of a test signal given to the device under test 3, and a DESKE circuit 2.
And a driver for providing the device under test 3 with a Hi logic level, a Lo logic level, and a termination level of the device under test 3 based on the test signal corrected by the W circuit 2. An analog comparator 4 for comparing an output signal output from the device under test 3 with a predetermined comparison voltage.
And a timing signal generator 6 for generating a timing signal
(TG6), and a digital comparator 5 for comparing a timing signal generated by the TG6 with an output signal output from the analog comparator 4.

One end of a mechanical relay 8 is connected to a point X which is an output terminal of the driver 1, and the other end of the mechanical relay 8 is connected to a connector 7.
One end of a coaxial cable 13 is connected to the connector 7, and the other end of the coaxial cable 13 is connected to the connector 9. The connector 9 is connected to a point Y, that is, a pin of the device under test 3.

A DESKEW circuit 2, a driver 1, an analog comparator 4, a mechanical relay 8, a connector 7,
9, circuit blocks including the coaxial line 13 are provided by the number of pins of the device under test 3.

One end of a mechanical relay matrix 10 is connected to the point X, and the other end of the mechanical relay matrix 10 has a reference driver 11 capable of outputting a Hi logic level, a Lo logic level, and a termination level. Output terminals are connected. Reference driver 11
Is connected to the input terminal of the reference analog comparator 12. Reference analog comparator 12
Compares the input signal with a predetermined comparison voltage. The output signal output from the reference analog comparator 12 is input to the digital comparator 15. The timing signal output from the timing signal generator 16 (TG 16) is also input to the digital comparator 15.

Next, the operation of this embodiment, that is, the procedure for measuring the transmission time required for transmitting the test signal from point X to point Y will be described. First, the device under test 3 is set to I
The point Y is opened by removing from the C test apparatus, the mechanical relay 8 is turned on, and the mechanical relay matrix 10 is turned off. Then, a predetermined waveform is output from the driver 1. Then, since the point Y is open, the reflection coefficient is 1, and the waveform output from the driver 1 is totally reflected at the point Y, and the reflected wave returns.

Then, the waveform observed at the point X is the output waveform output from the driver 1 as shown in FIG.
It becomes a staircase waveform in which the reflected wave from is overlapped. The reflected wave from the point Y is a waveform that is delayed from the output waveform output from the driver 1 by twice the transmission time required for transmitting the waveform from the point X to the point Y.

The step waveform at the point X is input to the analog comparator 4. This analog comparator 4
First, while changing the comparison voltage, the comparison voltage is compared with the input voltage of the staircase waveform. The digital comparator 5 compares the timing signal output from the analog comparator 4 with the timing signal output from the TG 6 while changing the timing signal output from the TG 6. If the two match, the timing output from the TG 6 at that time is obtained. Detect the time of the signal. From the detected time and the comparison voltage of the analog comparator 4, the amplitude voltage V of the staircase waveform input to the analog comparator 4
3, V5 is detected.

Next, the comparison voltage VO1 in the analog comparator 4 is, for example, 2 of the detected amplitude voltage V3.
The value is set to 0%, and the comparison voltage VO2 is set to, for example, a value of 20% of the detected amplitude voltage V5. Then, the analog comparator 4 compares the input voltage of the staircase waveform with the set comparison voltages VO1 and VO2. Then, the analog comparator 4 detects the times T1 and T1 when the magnitude relationship between the input voltage and the comparison voltage is switched.
2 to output an output signal whose state changes.

The time K from time T1 to time T2 is measured by digital comparator 5 and TG6. That is, while changing the timing signal output by the TG 6, the timing signal is compared with the output signal output from the analog comparator 4, and if they match, the time of the timing signal output from the TG 6 at that time is compared. Is detected.

That is, the comparison voltages VO1 and VO2 in the analog comparator 4 are changed to the amplitude voltages VO3 and VO5.
If the output resistance of the driver 1 varies and the staircase waveform changes, the times T1 and T2 do not shift. For this reason, the transmission time Tpd required for transmitting the test signal from the point X to the point Y can be measured accurately, and as a result, the skew timing can be adjusted with high accuracy. That is, the DESKEW circuit 2 is adjusted based on the measured transmission time.

However, before measuring the transmission time Tpd required for transmitting the test signal from the point X to the point Y, the point X
, The timing of the test signal is adjusted. The procedure for this adjustment will be described below. First, mechanical relay 8
OFF, mechanical relay matrix 10 ON
Then, the output terminal of the reference driver 11 is set to the termination level.
Next, a predetermined waveform is output from the driver 1, and this waveform is input to the reference analog comparator 12. The reference analog comparator 12 calculates the voltage of the input waveform,
A comparison is performed with a predetermined comparison voltage, and an output signal whose state changes at a time when the magnitude relationship between the input voltage and the comparison voltage is switched is output.

A fixed timing signal is output from the TG 16 and this timing signal is output to the digital comparator 15.
Input. The digital comparator 15 compares the timing signal with the output signal output from the reference analog comparator 12. In this state, DESKE
The W circuit 2 is adjusted so that the output signal output from the reference analog comparator 12 matches the timing signal output from the TG 16. The above adjustment is performed for all the drivers 1, and the output terminals of all the drivers 1, that is, the timings of the test signals at the point X are matched.

In the adjustment of the timing of the test signal at the point X, the method of determining the amplitude voltage of the waveform input to the reference analog comparator 12 and determining the comparison voltage in the reference analog comparator 12 based on the amplitude voltage is used. Even if the waveform input to the reference analog comparator 12 changes due to variations in the output resistance of the driver 1, accurate timing adjustment can be performed.

FIG. 3 is a schematic configuration diagram of an IC test apparatus according to a second embodiment of the present invention. This second embodiment differs from the first embodiment in that the second embodiment does not include the analog comparator 4, the digital comparator 5, and the TG 6. That is, in the present embodiment, the reference analog comparator 12, digital comparator 15, T
The transmission time Tpd is measured by G16.

Hereinafter, the transmission time Tpd in the present embodiment will be described.
The method for measuring is described. First, the device under test 3 is connected to an IC
Disconnect from the test equipment, open point Y, turn on mechanical relay 8 and mechanical relay matrix 10
Then, the output terminal of the reference driver 11 is set to the termination level.
Then, a predetermined waveform is output from the driver 1. Then, the output waveform reaches the point Y via the mechanical relay 8. Since the point Y is open, the reflection coefficient is 1, and the waveform output from the driver 1 is totally reflected at the point Y, and the reflected wave returns. Then, the waveform observed at the point X is different from the output waveform output from the driver 1 and the point Y.
It becomes a staircase waveform in which the reflected wave from is overlapped. The reflected wave from the point Y is a waveform that is delayed from the output waveform output from the driver 1 by twice the transmission time required for the waveform to be transmitted from the point X to the point Y.

The staircase waveform at the point X is input to the reference analog comparator 12 via the mechanical relay matrix 10. This reference analog comparator 1
2 first compares the comparison voltage with the input voltage of the staircase waveform while changing the comparison voltage. The digital comparator 15 compares this timing signal with the output signal output from the reference analog comparator 12 while changing the timing signal output by the TG 16,
If they match, the time of the timing signal output from the TG 16 at that time is detected. From the detected time and the comparison voltage in the reference analog comparator 12, the amplitude voltage of the staircase waveform input to the reference analog comparator 12 is detected.

Next, the comparison voltage in the reference analog comparator 12 is, for example, 20% of the detected amplitude voltage.
Is set to the value of Then, the reference analog comparator 12 compares the input voltage of the staircase waveform with the set comparison voltage. Then, the reference analog comparator 12 outputs an output signal whose state changes at the time when the magnitude relationship between the input voltage and the comparison voltage is switched.

The time between the times when the magnitude relationship between the input voltage and the comparison voltage is switched is measured by the digital comparator 15 and the TG 16. That is, while changing the timing signal output by the TG 16, the timing signal is compared with the output signal output from the reference analog comparator 12, and if they match, the timing signal output from the TG 16 at that time is compared. Detect time.

That is, the reference analog comparator 12
Is changed according to the amplitude voltage,
Even when the output resistance of the driver 1 varies and the staircase waveform changes, the time when the magnitude relationship between the input voltage input to the reference analog comparator 12 and the comparison voltage is switched does not shift. Therefore, it is possible to accurately measure the transmission time Tpd required for transmitting the test signal from the point X to the point Y, and as a result, it is possible to adjust the skew timing with high accuracy.

The mechanical relay matrix 10
If a semiconductor relay is used in place of
Although the staircase waveform input to the reference analog comparator 12 changes due to the variation in the N resistance, as in the above-described embodiment, if the comparison voltage in the reference analog comparator 12 is determined based on the amplitude voltage of the staircase waveform,
As in the above embodiment, highly accurate measurement of the transmission time becomes possible, and as a result, highly accurate skew timing adjustment becomes possible.

[0036]

According to the present invention, the comparison voltage in the comparator is determined based on the amplitude of the waveform input to the comparator, and a test signal is transmitted in the IC test apparatus using the comparison voltage. Since the transmission time required for the measurement is measured, the transmission time can be measured accurately even if the waveform input to the comparator changes due to the variation in the output resistance of the driver or the variation in the ON resistance of the semiconductor relay. As a result, highly accurate timing adjustment becomes possible.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an IC test apparatus according to a first embodiment of the present invention.

FIG. 2 is a waveform chart showing a waveform observed at a point X in the first embodiment of the present invention.

FIG. 3 is a schematic configuration diagram of an IC test apparatus according to a second embodiment of the present invention.

FIG. 4 is a waveform diagram showing a waveform observed at a point X in the related art.

FIG. 5 is a waveform chart showing a change in a waveform observed at a point X in the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Driver 2 DESKEW circuit (timing correction circuit) 3 Device under test 4 Analog comparator (comparator) 5 Digital comparator (transmission time detection unit) 15 Digital comparator 6 Timing signal generator (transmission time detection unit) 16 Timing signal generator 7 , 9 Connector 8 Mechanical relay 10 Mechanical relay matrix 11 Reference driver 12 Reference analog comparator 13 Coaxial cable

Claims (6)

[The claims] 1. A timing correction circuit for correcting the timing of a test signal supplied to a device under test, a driver for sending the test signal corrected by the timing correction circuit to the device under test, and a waveform at an output terminal of the driver. A comparator for comparing the waveform with a predetermined comparison level and outputting a comparison result; and a transmission for detecting a transmission time of a test signal in the IC test apparatus based on the comparison result output from the comparator. A skew timing adjustment apparatus for an IC test apparatus having a time detection unit, wherein a predetermined comparison level in the comparator is determined based on an amplitude of a waveform input to the comparator. apparatus. 2. The skew timing adjustment according to claim 1, wherein the predetermined comparison level in the comparator is a value obtained by multiplying the amplitude of a waveform input to the comparator by a predetermined coefficient. apparatus. 3. The comparator according to claim 1, wherein a waveform at an output terminal of the driver is input, the waveform is compared with a first comparison level and a second comparison level, and a comparison result is output. Item 3. The skew timing adjustment device according to item 1 or 2. 4. The comparator according to claim 1, wherein a first time at which a magnitude relationship between a waveform at an output terminal of the driver and a first comparison level is switched, and a waveform at the output terminal of the driver and a second comparison level. Outputting an output signal whose state changes at a second time at which the magnitude relationship is switched, wherein the transmission time detection unit outputs a first signal from a first time from a time at which the state of the output signal output from the comparator changes; 4. The skew timing adjustment device according to claim 3, wherein a time until time 2 is detected, and a transmission time of the test signal in the IC test device is calculated from the detected time. 5. A test signal is sent from a driver to a device under test, a waveform at an output terminal of the driver is input, the waveform is compared with a predetermined comparison level, a comparison result is output, and the output comparison result is output. A skew timing adjustment method for an IC test apparatus for detecting a transmission time of a test signal in the IC test apparatus based on the following: the predetermined comparison level is determined based on an amplitude of a waveform at an output terminal of the driver. A skew timing adjustment method. 6. The skew timing adjustment method according to claim 5, wherein a timing of transmitting the test signal is corrected according to a transmission time of the test signal in the IC test apparatus.