JP2002250754A - Semiconductor test apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor test apparatus which can perform a yes-no decision even regarding the difference voltage between the positive-polarity gradation output voltage and the negative-polarity gradation output voltage of a semiconductor device which is provided with a plurality of output pins and which is constituted in such a way that multistage positive-polarity voltages and negative-polarity voltages are changed over and output. SOLUTION: The semiconductor test apparatus is provided with a first D/A converter 10 which outputs an expected-value voltage corresponding to the gradation output voltage of the semiconductor device, subtracters 20 which detect the voltage difference between an output voltage in each pin and the output voltage of the converter 10, a second D/A converter 40 which outputs a reference voltage corresponding to the output voltage of the subtracter 20 in each pin, first comparators 50 which compare the magnitude relationship between the output of the subtracter 20 is each pin and the reference voltage of the converter 40, counters 80 which count the number of clocks corresponding to the difference voltage between the positive-polarity gradation voltage and the negative-polarity gradation voltage in each pin and magnitude comparators 90 which perform the yes-no decision on the basis of the counted value of each counter.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus, and more particularly, to an output voltage of a semiconductor integrated circuit having a large number of output pins configured to output multi-stage voltages for driving a liquid crystal display. It is about speeding up testing.

[0002]

2. Description of the Related Art For example, there are two types of driving methods for a TFT liquid crystal: dot inversion and line inversion by polarity switching. Here, focusing on the liquid crystal driving voltage output from the liquid crystal driving semiconductor integrated circuit (hereinafter referred to as a liquid crystal driver), the maximum voltage 3, 5, 13 V, etc. is divided into a multi-step predetermined voltage according to the display gradation. Output as D / A conversion voltage. For example, in the case of 256 gradation display, 512 dots are used in the dot inversion method.
Step drive voltages are output, and in the line inversion method, 256
The drive voltage of the step is output.

[0003] Current TFT liquid crystal drivers are RGB 3
One package 3 so that the system is driven by 128 dots at a time.
It is common to have 84 pins. Vertical 1
When driving an SXGA standard liquid crystal display device having 024 dots * 1280 horizontal dots, such one package 3
Ten 84-pin drivers will be used. When shipping such a liquid crystal driver, a 100% test is performed to selectively remove those that do not satisfy a predetermined specification.

FIG. 3 is a block diagram showing an example of such a conventional liquid crystal driver test apparatus. In the figure,
LCD driver to be tested (hereinafter referred to as DUT)
1 are connected to an A / D converter 3 via a switch 2.
It is connected to the. The A / D converter 3 converts the output voltage of each pin of the DUT 1 input via the switch 2 into a digital signal. Output data of the A / D converter 3 is temporarily stored in the memory 4. Then, the output data stored in the memory 4 is taken into the digital signal processing unit 5, and the magnitude of the absolute value of the output voltage of each pin, the magnitude of the variation of the output voltage between the pins, and the like are calculated and processed. Is determined.

However, according to such a conventional configuration,
In measuring the output voltage of each pin of DUT1, DUT1
Since the output voltage of each pin is switched by the switch 2 and input to the A / D converter 3, a considerable measurement time is required. For example, in the case of a dot inversion type driver having a 384-pin structure and 256 gradations, the measurement time per one gradation / pin is 2
Assuming 0 μs, it takes 4 seconds to measure one DUT 1 with one A / D converter 3, as is clear from 20 μs * 512 * 384 ≒ 4 sec.

As a method of shortening the time required for such a measurement, the number of A / D converters 3 provided in a plurality of n-systems is measured in parallel to reduce the required time to 4 / n. The use of a plurality of A / D converters 3 is a factor of cost increase and is not preferred.

[0007] Further, the digital signal processing section 5 is also required to have high-speed processing performance, which is a factor of high cost.

The applicant has proposed an apparatus as shown in FIG. 4 to solve these problems.

In FIG. 4, a differential amplifier 20 is provided for each output pin system of the DUT, and the output voltage of each output pin of the DUT and a D / A used as first voltage generating means.
A difference voltage from the output voltage of the converter 10 is obtained. The voltage amplifier 30 expands the difference voltage and inputs the difference voltage to one input terminal of the comparator 40. The output voltage of the D / A converter 50 used as the second voltage generating means is input to the other input terminal of the comparator 40. The comparison outputs of the comparators 40 are input to a digital comparator 60 used as a change detection unit for determining the quality of the DUT.

The operation of FIG. 4 will be described. At the time of inspection,
From each output pin of the DUT, for example, a stepwise waveform gradation voltage that monotonically increases as shown in FIG. 5 is simultaneously and simultaneously output. On the other hand, the D / A converter 10 used as the first voltage generating means
Outputs, for example, a voltage waveform equivalent to an expected voltage of each gradation voltage output from the DUT as indicated by a broken line in FIG. 6 and a voltage that changes in a mountain shape as indicated by a solid line. In this case, the D / A used as the second voltage generating means
The converter 40 uses, for example, DU as a reference voltage of the comparator 50.
An offset voltage of the test apparatus with respect to T and a voltage for correcting a value (normally 0 V) for correcting an error of the D / A converter 10 are output.

FIG. 7 is a partially enlarged view of FIG. In FIG. 7, V1 is a voltage lower than the lower limit value in the inter-pin variation test of each gradation voltage of the DUT output, and V2 is the DUT output.
The output voltage is a voltage higher than the upper limit in the pin-to-pin variation inspection. The chevron is from voltage V1 to voltage V2
, And slightly increases in a stepwise manner toward the voltage V2. When the voltage reaches the voltage V2, the voltage slightly decreases in a stepwise manner toward the voltage V2. The magnitude of such a mountain-shaped step change can be arbitrarily set by changing the value of digital data input to the D / A converter 10.

[0012] Even if the output voltage of such a DUT is set to the same gradation voltage, there is a variation depending on the output pin, and if the variation exceeds an allowable value, it may cause display color unevenness or the like, which is not preferable.

Therefore, in the configuration of FIG. 4, the quality is determined by executing the following measurement.

In an initial state where the output voltage of the D / A converter 10 is set to V1, all outputs of the digital comparator 60 are H (the voltage of the DUT is higher than the comparison value). When the output voltage of the D / A converter 10 is gradually increased from V1 to V2 from such an initial state, the output of the digital comparator 60 sequentially changes from H in accordance with the variation of the output voltage of each pin of the DUT. Inverts to L. Then, the maximum value VA of the variation between the DUT output pins is obtained from the output voltage of the D / A converter 7 when all the pins are inverted to L.

Next, the initial voltage of the D / A converter 10 is set to V2
And At this time, all the pins of the output of the digital comparator 60 are at L level. When the output voltage of the D / A converter 10 is gradually decreased toward V1, the output of the digital comparator 60 is sequentially inverted from L to H according to the variation of the output voltage of each pin of the DUT. Then, DU is calculated from the output voltage of the D / A converter 10 when all the pins are inverted.
A minimum value VB of variation between T output pins is obtained. The detection of whether all the pins are H or L by the digital comparator 60 uses a pattern matching function which is conventionally and generally used in a semiconductor tester.

In this manner, voltages VA and VB at which all pins of each gradation are inverted are obtained, and output voltage deviations (variations) VA-VB of all pins and all gradations are obtained. The value is, for example, ± 3
The test is passed if the standard is within mV or ± 5 mV, and is rejected if the standard is not met.

For example, when calculating the output deviation of a 300-pin DUT with 64 gradations, it is necessary to calculate 64 × 300 = 19200 data according to the conventional A / D converter system shown in FIG. However, in the method of the present invention shown in FIG.
An operation of 4 × 2 = 128 data is sufficient.

According to the configuration shown in FIG. 4, the number of arithmetic processing steps can be remarkably reduced, and a high-precision A / D converter and a digital signal processing section for performing high-speed processing are not required. It is only necessary to use a D / A converter as a circuit, and the cost can be greatly reduced and the circuit can be realized at low cost. Since the same circuit is used for all the pins of the DUT and the same circuit is used for simultaneous measurement, the test time can be greatly reduced.

[0019]

However, in the configuration using the differential amplifier 20 and the comparator 50 as shown in FIG.
Is a dot inversion type TFT source driver, and a positive voltage and a negative voltage are alternately output as the output voltage thereof.
When the output accuracy index of the driver is represented by the difference voltage between the positive electrode voltage and the negative electrode voltage, there is a problem that a pass / fail judgment cannot be made.

The present invention has been made to solve the above problems, and has as its object to drive a display device which has a large number of output pins and alternately outputs a multi-stage positive voltage and negative voltage alternately. It is an object of the present invention to provide a semiconductor test apparatus capable of making a pass / fail judgment even on a difference voltage between output voltages of a semiconductor integrated circuit.

[0021]

According to a first aspect of the present invention, there is provided a semiconductor test apparatus which has a plurality of output pins and alternately outputs a multi-stage positive voltage and a negative voltage to each pin. A first voltage generating means for outputting an expected value voltage corresponding to a gradation output voltage of a semiconductor device, and a pin for each pin of the semiconductor device. A voltage difference detecting means provided for each system for detecting a voltage difference between an output voltage of each pin and an output voltage of the first voltage generating means, and a reference voltage corresponding to the output voltage of the voltage difference detecting means, A second voltage generating means, and a first comparing means provided for each pin system of the semiconductor device and comparing the magnitude relationship between the output of the voltage difference detecting means of each pin and the reference voltage of the second voltage generating means. , Each pin system of semiconductor device A counter that counts the number of clocks corresponding to the difference voltage between the positive gray scale output voltage and the negative gray scale output voltage of each pin; and a determination unit that performs pass / fail determination of the semiconductor device based on the count value of each counter. And characterized in that:

In such a configuration, each counter is
The number of clocks corresponding to the difference voltage between the positive gradation output voltage and the negative gradation output voltage of each pin is counted. That is, the positive gradation output voltage, the negative gradation output voltage, and the difference voltage between the positive gradation output voltage and the negative gradation output voltage for each pin can be measured from the count value of each counter.

According to a second aspect of the present invention, in the semiconductor test apparatus of the first aspect, the first voltage generating means is common to all pin outputs of the semiconductor device.

Thus, the configuration of the entire apparatus can be simplified.

According to a third aspect of the present invention, in the semiconductor test apparatus of the first aspect, the first voltage generating means is provided for each group of even-numbered pins and odd-numbered pins of the semiconductor device.

As a result, the test of the even-numbered pins and the test of the odd-numbered pins can be performed simultaneously, and the test time can be reduced to half.

According to a fourth aspect of the present invention, in the semiconductor test apparatus according to any one of the first to third aspects, the pass / fail determination means is provided for each pin system of the semiconductor device, and determines whether a count value of each counter is equal to a predetermined value. A comparison means for comparing the magnitude relation with the reference value.

Thus, the pass / fail judgment can be made by using the pattern matching function provided in the semiconductor test apparatus.

According to a fifth aspect of the present invention, in the semiconductor test apparatus according to any one of the first to third aspects, the pass / fail determination means is a digital signal processor.

Thus, the pass / fail judgment can be made from the unique viewpoint of the digital signal processor without using the pattern matching function provided in the semiconductor test apparatus.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and portions common to FIG. 4 are denoted by the same reference numerals. In the figure, an output signal of the comparator 50 is input to one input terminal of the AND gate 70, and a clock signal CLK is input to the other input terminal from outside. The output signal of the AND gate 70 is input to a clock terminal of a counter 80 that counts up and down. An UP / DOWN control signal for instructing up-counting or down-counting is input to a control terminal of the counter 80. The output signal of the counter 80 is input to a magnitude comparator 90 which compares a comparison value set in advance and outputs a magnitude as a digital value.

The operation of FIG. 1 will be described with reference to the timing chart of FIG. The DUT is a dot inversion TFT source driver, and it is assumed that the Nth pin outputs a grayscale output voltage of positive polarity at the time point a.

The D / A converter 10 increases the output voltage while sequentially updating from a voltage lower by XmV than the ideal gradation output PmV of the positive polarity. The timing at which the output voltage of the D / A converter 10 is updated is synchronized with the operation clock of the counter 80. The output signal of the comparator 50 is supplied to the AND gate 7 until the output voltage of the D / A converter 10 exceeds the output voltage of the DUT (PmV + ΔPmV).
Open 0 and input the clock CLK to the counter 80.
In this state, the counter 80 is set to the count-up mode, and starts counting up from the initial value.

The output voltage of the D / A converter 10 becomes higher than the output voltage (PmV +
ΔPmV), the output of the comparator 50 is inverted.
When the output of the comparator 50 is inverted, the AND gate 7
0 is closed, and the count-up operation of the counter 80 stops.

Here, since the number of clocks input to the counter 80 changes in accordance with the error voltage ΔPmV with respect to the ideal gradation output voltage PmV of the DUT, the count value of the counter 80 after the count is stopped indicates ΔPmV + XmV. become.

In the example of FIG. 2, the count value at the initial count-up value is 1000, and the count value at the ideal gradation output voltage is 1500, but the output voltage of the pin N at the point c is the ideal gradation output voltage. Therefore, the count value of the counter 80 was 1521 because the voltage was higher by 21 in the number of voltage update clocks of the D / A converter 10 than in the first embodiment.

Next, at the time point d, a negative gradation output voltage is output to the pin N of the DUT. The D / A converter 10 increases the output voltage while sequentially updating the output voltage from a voltage lower by XmV than the ideal grayscale output voltage NmV of the negative polarity. D / A
The timing at which the output voltage of the converter 10 is updated is synchronized with the operation clock of the counter 80 as in the case of the positive polarity.

The output signal of the comparator 50 is the D / A converter 1
The output voltage of 0 is the output voltage of the DUT (NmV + ΔNmV)
Open AND gate 70 until it exceeds
The clock CLK is input to 0. In this state, the counter 8
0 is set to the countdown mode, and the countdown starts from the initial value.

The output voltage of the D / A converter 10 rises at time e in the process of rising, and the output voltage of the DUT (NmV +
ΔNmV), the output of the comparator 50 is inverted.
When the output of the comparator 50 is inverted, the AND gate 7
0 is closed, and the countdown operation of the counter 80 stops.

The number of clocks input to the counter 80 is
Error voltage ΔN with respect to ideal gradation output voltage NmV of DUT
It changes according to mV. Since the initial value of the counter 70 immediately before the countdown is (ΔPmV + XmV), the count value after the stop is (ΔPmV + XmV) − (ΔNmV + XmV) = ΔPm
V−ΔNmV, which indicates a difference voltage between the positive gradation output voltage and the negative gradation output voltage.

In FIG. 2, the initial value of the countdown (= the final value of the countup) is 1521, and the output voltage of the pin N is obtained from the negative ideal tone output voltage NmV by the D / A converter 1.
Since the number of update clocks of the output voltage of 0 is 49 clocks higher, the number of clocks is 549 clocks (50 counts to the ideal gradation).
0 clock + 49 clocks) count down, time point g
The final countdown value of the counter 80 is 972
(1521-549).

The magnitude of the count value of these counters 80 is compared with a preset comparison value in a magnitude comparator 90 and output as a digital value. Based on the output pattern of these magnitude comparators 90, pass / fail determination of the DUT is performed. That is,
A pass / fail judgment can be made using the pattern matching function provided in the semiconductor test apparatus.

It is also possible to monitor the number of clocks until a carry is output for each pin while inputting a clock synchronized with the test rate from the outside to the counter 80 and counting it up. Also in this case, the pattern matching function of the semiconductor test device can be used for monitoring.

Also, a digital signal processor (DSP) may be connected to the counter 80 via a bus, and the count value of the counter 80 may be read out by the DSP to determine the acceptability of the DUT. As a result, the pass / fail judgment can be made based on a unique viewpoint of the digital signal processor without using the pattern matching function of the semiconductor test apparatus.

In the configuration of FIG. 1, the D / A converter 10 for generating the ideal voltage corresponding to the output voltage of the DUT is configured to be common to all the pin outputs. A plurality may be provided for each.

When the DUT is a dot inversion TFT source driver, a positive output voltage and a negative output voltage are alternately output along the pin arrangement direction. Therefore, by providing a D / A converter for each group of even-numbered pins and odd-numbered pins, it is possible to perform tests of both polarities at the same time.
2 can be obtained.

When the DUT is a dot inversion TFT source driver, a D / A converter having half the number of output pins of the DUT is prepared, and the measurement is performed by switching between even and odd groups. Halve.

In the above series of description, an example is shown in which the present invention is applied to a test apparatus for a driver for driving a TFT liquid crystal. However, a D / A converter having a large number of output pins configured to output various multi-step voltages is described. The present invention is also applicable to a test device for a semiconductor integrated circuit such as a tester.

[0048]

As described above, according to the present invention,
The semiconductor test apparatus of the type in which the subtractor and the comparator are combined can determine whether or not the semiconductor has a positive output voltage and a negative output voltage, such as a dot inversion TFT source driver output, which are output alternately.

In the conventional semiconductor test apparatus, only the variation between pins (maximum output voltage, minimum output voltage) for each gradation can be measured. According to the semiconductor test apparatus of the present invention, the count value of the counter is read. Thus, the positive gradation output voltage, the negative gradation output voltage, and the difference voltage between the positive gradation output voltage and the negative gradation output voltage for each pin can be measured.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart illustrating the operation of FIG.

FIG. 3 is a block diagram showing an example of a conventional device.

FIG. 4 is a block diagram showing another example of a conventional device.

FIG. 5 is a diagram illustrating an example of a voltage waveform output from the DUT of FIG. 4;

FIG. 6 is an example diagram of an expected voltage waveform input to the subtractor of FIG. 4;

FIG. 7 is an enlarged waveform diagram of a main part of FIG. 6;

[Explanation of symbols]

 Reference Signs List 20 subtractor 10, 40 D / A converter 30 amplifier 50 comparator 70 AND gate 80 counter 90 magnitude comparator

Claims (5)

[Claims] 1. A semiconductor test apparatus for testing output voltage characteristics of a semiconductor device having a plurality of output pins and configured to alternately output a multi-stage positive voltage and a negative voltage to each pin and output the voltage, First voltage generating means for outputting an expected value voltage corresponding to the gradation output voltage of the semiconductor device; and an output voltage of each pin and an output voltage of the first voltage generating means provided for each pin system of the semiconductor device. Voltage difference detecting means for detecting a voltage difference between the output voltage of the semiconductor device and a second voltage generating means for outputting a reference voltage corresponding to the output voltage of the voltage difference detecting means. First comparing means for comparing the magnitude relationship between the output of the voltage difference detecting means and the reference voltage of the second voltage generating means; provided for each pin system of the semiconductor device; The difference between the negative gradation output voltage A counter for counting the number of clocks, and judging means for performing acceptance judgment of the semiconductor device based on the count value of each counter, a semiconductor test apparatus characterized by comprising the city. 2. The semiconductor test apparatus according to claim 1, wherein said first voltage generating means is common to all pin outputs of the semiconductor device. 3. The semiconductor test apparatus according to claim 1, wherein said first voltage generating means is provided for each group of even-numbered pins and odd-numbered pins of the semiconductor device. 4. The semiconductor device according to claim 1, wherein said pass / fail determination means is provided for each pin system of said semiconductor device, and is a comparison means for comparing a magnitude relationship between a count value of each counter and a predetermined reference value. The semiconductor test apparatus according to claim 1. 5. The semiconductor test apparatus according to claim 1, wherein said pass / fail determination means is a digital signal processor.