JP2002241194A - Method for producing epitaxial silicon wafer and epitaxial silicon wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the gettering capability of an epitaxial silicon wafer and to provide an epitaxial silicon wafer in which shortening of the carrier diffusion length is suppressed. SOLUTION: A method for producing the epitaxial silicon wafer comprises the steps of: growing a nitrogen-doped silicon single crystal rod by a Czochralski method; slicing the silicon single crystal rod into silicon single crystal wafers; subjecting the silicon single crystal wafers to heat treatment so as to diminish the crystal defects in the vicinity of the surface of each silicon single crystal wafer; further forming a silicon epitaxial layer on the surface of each silicon single crystal wafer; and subjecting each resultant silicon single crystal wafer to heat treatment comprising rapid heating and rapid cooling. The objective epitaxial silicon wafer is characterized in that the silicon epitaxial layer is formed on the nitrogen-doped silicon single crystal wafer, dislocation loops are contained in the bulk, the BMD density in the bulk is >=5×108 pieces/cm3, and the carrier diffusion length is 300 to 600 μm.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing an epitaxial silicon wafer having a high gettering ability and a long carrier diffusion length, and an epitaxial silicon wafer.

[0002]

2. Description of the Related Art Epitaxial silicon wafers have been used for a long time as wafers for producing individual semiconductors, bipolar ICs and the like because of their excellent characteristics. MOS LSIs are also widely used in microprocessor units and flash memory devices because of their excellent soft errors and latch-up characteristics. Furthermore, the demand for epitaxial silicon wafers is increasing more and more in order to reduce the poor reliability of DRAMs caused by so-called grown-in defects introduced during the production of silicon single crystals.

[0003] If heavy metal impurities are present on an epitaxial silicon wafer used for such a semiconductor device, the characteristics of the semiconductor device will be poor.
In particular, the degree of cleanliness required for the most advanced devices is considered that the concentration of heavy metal impurities is 1 × 10 ⁹ atoms / cm ² or less, and the heavy metal impurities existing on the silicon wafer must be reduced as much as possible.

As one of the techniques for reducing such heavy metal impurities, the importance of the gettering technique is increasing more and more. Conventionally, to manufacture an epitaxial silicon single crystal wafer, a substrate having a high gettering effect and a high boron concentration (for example, 3 × 10 ¹⁸ atoms / cm ³ or more,
0.02 Ω · cm or less), so that the epitaxial silicon single crystal wafer has a higher device yield than a normal resistance silicon single crystal wafer manufactured by the Czochralski method.

However, recently, as a substrate of an epitaxial silicon single crystal wafer for a CMOS device, a substrate having a lower boron concentration than before has been increasingly used, and the gettering ability is higher than that of a substrate having a high boron concentration. The problem of low prices has arisen. Further, even for a substrate having a high boron concentration, there is a problem that the gettering ability is insufficient depending on the concentration.

In view of the above, the present applicant has proposed in a previous application a method of providing an epitaxial wafer having a high gettering ability irrespective of boron concentration by doping nitrogen into the substrate of the epitaxial wafer (Japanese Patent Laid-Open No. 2000-2000). 44389).

According to this method, heavy metal impurities and the like generated during the device fabrication process can be gettered to oxygen precipitates in the bulk, so that an epitaxial wafer capable of preventing the deterioration of the characteristics of the epitaxial layer can be obtained. It was highly productive and easy to manufacture, and was extremely effective. However, if the disadvantages are argued, since gettering sites for heavy metal impurities are mainly only oxygen precipitates, not all types of metal impurities can be efficiently gettered. The introduction was desired. In addition, it was found that the diffusion length of carriers in the epitaxial wafer was not as long as expected, and there was a concern that the influence on device characteristics would be caused.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and further improves the gettering ability of an epitaxial wafer doped with nitrogen, and furthermore, the diffusion length of carriers in the epitaxial wafer. It is an object of the present invention to provide an epitaxial silicon wafer in which a decrease in (ie, carrier lifetime) is suppressed.

[0009]

According to the present invention, there is provided a method of manufacturing an epitaxial silicon wafer, comprising the steps of: growing a silicon single crystal rod doped with nitrogen by a Czochralski method; Is sliced and processed into a silicon single crystal wafer, heat treatment is performed to eliminate crystal defects near the surface of the silicon single crystal wafer, and further, after forming a silicon epitaxial layer on the surface of the silicon single crystal wafer, A method for producing an epitaxial silicon wafer, characterized by performing a rapid heating / cooling heat treatment (claim 1).

[0010] CZ wafers doped with nitrogen can be obtained from Grow
Since the size of n-in defects is small and stable oxygen precipitate nuclei are formed at high temperature, defects near the surface are easily eliminated by subsequent heat treatment, and the oxygen precipitate nuclei in the bulk are grown without disappearing. Thus, an oxygen precipitate having gettering ability can be formed. Then, the formed oxygen precipitate does not disappear in the subsequent epitaxial growth step, and furthermore, rapid heating and
A large amount of dislocation loops as new gettering sites are added in the bulk by rapid cooling heat treatment,
An improvement in gettering ability can be expected. In addition, the diffusion length (lifetime) of the carrier is improved, and the electrical characteristics are also improved.

Here, the rapid heating / cooling heat treatment (hereinafter referred to as RTA (Rapid Thermal Anneal)
eal)) refers to annealing performed by instantaneously applying heat for several microseconds to several hundred seconds. Each wafer is introduced into a chamber having a small heat capacity, and the temperature is rapidly increased mainly by a heat source such as an infrared lamp, and the temperature is rapidly decreased. Unlike the conventional batch type furnace, the temperature rise by ramp-up and the temperature fall by ramp-down are not performed.

In this case, the Czochralski method is used.
When growing a silicon single crystal rod doped with nitrogen,
The concentration of nitrogen doped in the single crystal rod is 1 × 10¹²~ 1 ×
10 ¹⁴Pieces / cm³It is preferable that
2). This is because the nitrogen concentration is 1 × 10¹⁴Pieces / cm³Over
As a result, crystal defects (dislocation loops and product
This is because layer defects are likely to occur. On the other hand, 1 × 1
0¹²Pieces / cm³If less than, oxygen precipitation by nitrogen doping
Because the effect of promoting
You.

In this case, it is preferable to perform a heat treatment at 1100 to 1300 ° C. for 10 to 300 minutes as a heat treatment for eliminating crystal defects near the surface of the silicon single crystal wafer. This is 1100
In heat treatment of less than 10 ° C or less than 10 minutes, Gr near the surface
This is because the disappearance of the own-in defect may be insufficient, and the defect may be easily formed in the epitaxial layer. If the temperature is higher than 1300 ° C., the durability of the heat treatment furnace and metal contamination are concerned, and the heat treatment time of 300 minutes or more causes a decrease in productivity.

In this case, it is preferable to perform a heat treatment at 1100 to 1350 ° C. for 1 to 120 seconds as the rapid heating / rapid cooling heat treatment. This is 110
If the heat treatment is performed at a temperature of less than 0 ° C. or less than 1 second, a dislocation loop as a new gettering site in the bulk may not be sufficiently formed, and the improvement of the gettering ability may not be expected. Further, at a temperature higher than 1350 ° C., disadvantages such as generation of metal contamination and slip dislocation are remarkably generated. Further, if a heat treatment for more than 120 seconds is performed by a rapid heating / rapid cooling heat treatment apparatus (RTA apparatus), not only does durability of the apparatus become a problem, but productivity is extremely reduced due to the single-wafer treatment. .

The present invention also relates to an epitaxial silicon wafer wherein a silicon epitaxial layer is formed on the surface of a nitrogen-doped silicon single crystal wafer, and dislocation loops and 5 × 10 ⁸ / c
An epitaxial silicon wafer having a BMD density of at least m ³ and a carrier diffusion length of at least 300 μm (claim 5). Thus, a wafer having a sufficient BMD (Bulk Micro Defect) density of 5 × 10 ⁸ / cm ³ or more in the bulk of a wafer and further having a dislocation loop in the bulk is a dislocation loop. Is added as a gettering site, so it can be expected to have excellent gettering ability. Further, since the carrier diffusion length is 300 μm or more, the device characteristics are also excellent.

Hereinafter, the present invention will be described in more detail.
The present invention is not limited to these. As described above, although the gettering ability of a wafer having an epitaxial layer formed on the surface of a silicon single crystal wafer doped with nitrogen is improved as compared with the conventional one, the one serving as a gettering site is mainly an oxygen precipitate. Therefore, not all types of metal impurities and the like can be efficiently gettered, and introduction of other types of gettering sites has been desired. Another drawback is that the diffusion length of carriers in the wafer is shorter than expected.

Therefore, the present inventors have introduced a new gettering site into the wafer and studied the manufacturing conditions of the epitaxial silicon wafer in order to increase the carrier diffusion length. And Japanese Patent Laid-Open No. 2000-44
No. 389, an epitaxial silicon wafer having an epitaxial layer formed on the surface of a silicon single crystal wafer which has been subjected to a heat treatment for eliminating crystal defects in the vicinity of the wafer surface is subjected to rapid heating. The following facts were found as a result of an experimental study with the idea of performing rapid cooling heat treatment.

The rapid heating / cooling heat treatment after the epitaxial growth hardly changes the BMD density and the BMD size of the wafer. Therefore, even if the rapid heating / rapid cooling heat treatment is performed after the epitaxial growth, the BMD density and the size are not affected, and it is found that the gettering effect by the BMD like the conventional nitrogen-doped wafer is secured.

When the wafer after the epitaxial growth is subjected to a rapid heating / rapid cooling heat treatment, the diffusion length and the lifetime of carriers in the wafer are improved. Therefore,
A short-time rapid heating / cooling heat treatment after epitaxial growth can increase the carrier diffusion length, which was short in conventional wafers.

Further, in the wafer after the rapid heating / rapid cooling heat treatment, the form of the defect changes from a stacking fault to a dislocation loop. Therefore, a large amount of dislocation loops are introduced as new gettering sites in the wafer bulk, so that different types of defects from the conventional wafer can contribute to gettering, and gettering of various heavy metal impurities and the like. The effect can be expected. The present invention has been completed by scrutinizing various conditions based on the above findings.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, a silicon single crystal rod doped with nitrogen by the CZ method may be grown by a known method described in, for example, Japanese Patent Application Laid-Open No. 60-251190. .

That is, this method is a method in which a silicon single crystal rod is grown from a polycrystalline silicon raw material melt accommodated in a quartz crucible in the CZ method. By introducing a nitride into the silicon melt or setting the atmosphere gas to an atmosphere containing nitrogen, nitrogen can be doped into the pulled crystal. At this time, the doping amount in the crystal can be controlled by adjusting the amount of the nitride, the concentration of the nitrogen gas, the introduction time, and the like.

In this case, the nitrogen concentration for doping the single crystal rod is
Degree 1 × 10¹²~ 1 × 10¹⁴Pieces / cm³To do
Is preferred. As mentioned above, the nitrogen concentration is 1 × 10¹⁴Pieces/
cm ³Over the surface of the resulting silicon wafer
In the vicinity, there is a defect that cannot be eliminated by heat treatment.
And an epitaxy formed on it
This is because crystal defects tend to occur in the taxi layer.
You. On the other hand, 1 × 10¹²Pieces / cm³If it is less than
The oxygen precipitation promoting effect of
This is because there is a possibility that the taring ability becomes insufficient.

In this way, a silicon single crystal rod doped with a desired concentration of nitrogen is manufactured, and sliced with a cutting device such as an inner peripheral blade slicer or a wire saw according to a conventional method, followed by chamfering, lapping, etching and polishing. Through these steps, it is processed into a silicon single crystal wafer.
Of course, these steps are only exemplified and listed, and there may be various other steps such as washing and heat treatment, and the steps are appropriately changed and used according to the purpose such as a change in the order of the steps and a partial omission.

Next, before performing the epitaxial growth, the obtained silicon single crystal wafer is subjected to a heat treatment for eliminating crystal defects near the surface of the silicon single crystal wafer. By doing so, C in the vicinity of the wafer surface
Crystal defects such as OPs and minute oxygen precipitates can be removed, and nitrogen and oxygen near the wafer surface can be diffused outward to eliminate the crystal defects. As described above, this heat treatment is preferably performed at 1100 to 1300 ° C. for 10 to 300 minutes. This is less than 1100 ° C, or 1
This is because if the heat treatment is performed for less than 0 minute, the Gronn-in defects near the surface will not be sufficiently eliminated, and there is a fear that defects may be easily formed in the epitaxial layer formed thereon. If the temperature is higher than 1300 ° C., the durability of the heat treatment furnace and metal contamination are concerned, and the heat treatment time of 300 minutes or more causes a decrease in productivity.

The atmosphere for the heat treatment is not particularly limited, and may be hydrogen, an inert gas such as argon, or a mixed gas thereof, or oxygen in some cases. However, when the atmosphere is oxygen, OSF nuclei on the wafer surface may grow depending on the heat treatment conditions, and an oxide film may be formed on the surface. If an oxide film is formed on the surface, a step of removing the oxide film is required. Therefore, it is preferable to use an atmosphere in which a film is not formed, such as hydrogen or argon.

As an apparatus used for this heat treatment, if the heat treatment time is relatively short, an epitaxial growth apparatus is used to perform the heat treatment and the epitaxial deposition continuously. Can be processed.
In addition, when the heat treatment is performed for a relatively long time, it is efficient to perform batch processing using a heat treatment furnace of a heater heating method capable of simultaneously heat treating several tens or more wafers.

After heat treatment for eliminating crystal defects near the wafer surface, a silicon epitaxial layer is formed on the wafer surface. This epitaxial growth can be performed by a general CVD method. In this CVD method, for example, silicon is epitaxially grown on a silicon single crystal wafer by introducing trichlorosilane into a radiation heating type epitaxial growth furnace in which a susceptor on which a silicon substrate is mounted is placed in a cylinder type bell jar.

After forming an epitaxial layer on the surface of the wafer, a rapid heating / rapid cooling heat treatment is performed. Examples of the apparatus for rapidly heating and cooling a silicon wafer used in the present invention include an apparatus such as a lamp heater using heat radiation. Examples of commercially available devices include, for example, devices such as SHS-2800 manufactured by STEACH MICROTECH INTERNATIONAL, which are not particularly complicated and are not expensive.

Here, an example of a rapid heating / rapid cooling apparatus (RTA apparatus) for a silicon single crystal wafer used in the present invention will be described. FIG. 5 is a schematic diagram of an RTA apparatus. The heat treatment apparatus 10 shown in FIG. 5 has a chamber 1 made of quartz, and heats a wafer in the chamber 1. Heating is performed by a heating lamp 2 arranged so as to surround the chamber 1 from above, below, left and right. The lamps can independently control the power supplied.

The supply side of the gas is connected to a supply source such as an oxygen gas supply source or a nitrogen gas (not shown) so that the atmosphere gas can be mixed at an arbitrary mixing ratio and supplied into the chamber 1. Has been. The gas exhaust side is equipped with an auto shutter 3 to block outside air. The automatic shutter 3 is provided with a wafer insertion opening (not shown) that can be opened and closed by a gate valve. Also,
The auto shutter 3 is provided with a gas exhaust port,
The atmosphere pressure in the furnace can be adjusted.

Then, the wafer 8 is placed on the three-point support 5 formed on the quartz tray 4. A buffer 6 made of quartz is provided on the gas inlet side of the tray 4.
The introduction gas is prevented from directly hitting the wafer 8. Further, a special window (not shown) for temperature measurement is provided in the chamber 1, and a wafer 8 is passed through the special window by a pyrometer 7 installed outside the chamber 1.
Temperature can be measured.

The processing for rapidly heating / cooling the wafer by the heat treatment apparatus 10 as described above is performed as follows. First, the wafer 8 is put into the chamber 1 from the insertion port by a wafer handling device (not shown) arranged adjacent to the heat treatment device 10, placed on the tray 4, and then the automatic shutter 3 is closed. The inside of the chamber 1 is filled with a predetermined atmosphere.

Then, electric power is supplied to the heating lamp 2 to raise the temperature of the wafer 8 to a predetermined temperature of 1100 to 1350 ° C. At this time, the time required to reach the target temperature is, for example, about 20 seconds. Next, by holding the wafer at that temperature for a predetermined time, the wafer 8 can be subjected to a high-temperature heat treatment. When a predetermined time has elapsed and the high-temperature heat treatment has been completed, the output of the lamp is reduced to lower the temperature of the wafer. This cooling can be performed in about 20 seconds, for example. Finally,
The heat treatment is completed by removing the wafer by the wafer handling device.

This rapid heating / rapid cooling heat treatment is performed at 110
It is preferable to perform heat treatment at 0 to 1350 ° C. for 1 to 120 seconds. This is because, as described above, the dislocation loop as a new gettering site in the bulk is not sufficiently formed by the heat treatment at less than 1100 ° C. or less than 1 second, so that an improvement in gettering ability cannot be expected. Also,
At a temperature higher than 1350 ° C., disadvantages such as metal contamination and occurrence of slip dislocation are remarkably generated. further,
This is because if the heat treatment is performed for more than 120 seconds with the RTA apparatus, not only the durability of the apparatus becomes a problem but also the productivity is extremely reduced due to the single-wafer processing.

[0036]

EXAMPLES The present invention will now be described specifically with reference to examples and comparative examples, but the present invention is not limited to these examples. (Examples and Comparative Examples) A diameter 1 having an initial oxygen concentration of 13 ppma (JEIDA: Japan Electronics Industry Development Association Standard) and a nitrogen concentration of 5 × 10 ¹³ / cm ³ by the Czochralski method.
50 mm, p-type, resistivity 10 Ωcm, plane orientation (100)
Prepare a CZ silicon single crystal wafer of 100% Ar
Heat treatment (annealing) at 1150 ° C. for 4 hours was performed in an atmosphere to remove crystal defects (COP, minute oxygen precipitates, etc.) near the wafer surface. Thereafter, epitaxial growth was performed on the surface of the wafer by the CVD method under the following conditions, and further, an epitaxial wafer subjected to rapid heating / rapid cooling heat treatment under the following conditions was produced, and the following items were evaluated. The following items were also evaluated and compared at the stage where only the heat treatment of the wafer was performed in the Ar 100% atmosphere and the stage where the epitaxial growth was performed thereafter.

(Epitaxial growth conditions) Source gas: trichlorosilane Deposition conditions: 1130 ° C., 3 μm Resistivity: 10 Ωcm

(RTA treatment conditions) Heat treatment temperature: 1200 ° C. Heat treatment time: 30 seconds Atmosphere gas: N ₂ atmosphere containing 3% O ₂ Applicable equipment: SHS-2800 manufactured by STEACH MICROTECH INTERNATIONAL CO., LTD.

(Evaluation items) 1) Measurement of BMD density and size by OPP (Optical Precipitate Profiler) method 2) Measurement of carrier diffusion length and lifetime by SPV (Surface Photo Voltage) method 3) BMD by TEM (transmission electron microscope) Morphological observation

Here, the OPP (Optical Precipitate Profiler) method used for measuring the BMD density and size is an application of a normal ski type differential interference microscope. First, laser light emitted from a light source is applied to a polarizing prism.
The beams are separated into linearly polarized beams orthogonal to each other and having a phase difference of 90 °, and are incident from the wafer mirror side. At this time, when one beam crosses the defect, a phase shift occurs, and a phase difference occurs with another beam. The size of the grown-in defect can be detected by detecting this phase difference with a polarization analyzer after passing through the back surface of the wafer.

The SPV method (Surface) used for measurement of carrier diffusion length and lifetime as one of the evaluation items was used.
In the Photovoltage Method, first, an epitaxial silicon wafer with a transparent electrode is irradiated with light of different wavelengths to induce minority carriers. The induced minority carriers are collected on the wafer surface to generate a surface electromotive force. Next, the irradiation light intensity is changed so that the surface electromotive force at each wavelength becomes constant. Since the absorption coefficient changes when the wavelength of the irradiation light differs, the reciprocal of the absorption coefficient and the irradiation light intensity are plotted. Then, a linear relationship can be obtained from both, and this line can be extrapolated and the diffusion length can be obtained from the value across the axis of the absorption coefficient.

The TEM (transmission electron microscope) used for BMD morphology observation was developed with the aim of increasing the spatial resolution by using an electron beam having a shorter wavelength than light instead of light from an optical microscope. It was done. The spatial resolution cannot be less than 0.2 μm when using an optical microscope, but it can be as small as 0.1 nm when using a TEM.

FIG. 1 and FIG.
4 shows the results of OPP measurement of BMD density and size. Arua
The BMD density in the neal only stage is 1 × 10⁹Pieces/
cm ³It is weak even after epi growth or RTA heat treatment.
No change was observed in the density and size of. The reason is Ar
Epitaxial growth heat treatment below Neil temperature
Considers that it did not work in the direction of eliminating BMD
available. For RTA, use Ar annealing
High temperature but short time to grow BMD
Is considered to have had little effect.

Therefore, even if epitaxial growth is performed on an as-annealed wafer that has been subjected only to Ar annealing, and then RTA is performed, the BM
It is found that there is no influence on the D density and the size, and that the gettering effect by the BMD like the conventional nitrogen-doped wafer is secured.

FIGS. 3 and 4 show SPV measurement results of the carrier diffusion length and lifetime at each stage. From the results of FIGS. 3 and 4, the diffusion length and the lifetime do not change even when the epi growth is performed. However, it can be seen that the diffusion length increases when RTA is performed after the epitaxial growth. In other words, the diffusion length tends to be reduced when epitaxial growth is performed, and is below 300 μm.
On the other hand, when RTA is performed as in the present invention, the thickness becomes 300 μm or more, and reaches 400 or 500 μm. Further, as shown in FIG. 4, this tendency was the same even in the measurement results of the lifetime.

Here, the information on the diffusion length and lifetime by SPV is considered to correspond to the integration of the entire wafer thickness. In other words, it can be understood that the epitaxial growth is performed on the as-annealed wafer and the RTA is performed, thereby improving the diffusion length (life time).

Here, a plot of the diffusion length in FIG.
Black circles) show the measurement results before and after the heat treatment at 210 ° C. in the SPV measurement, respectively. The reason for applying the heat treatment at 210 ° C. will be described below for reference.

It is known that there are two types of Fe in p-type Si, one between lattices (denoted as Fei) and a complex of Fe and B (denoted as Fe-B). Of these, Fe
Since i has a positive charge and B has a negative charge, it sometimes attracts to form a complex. The conversion temperature is about 200 ° C.
However, below this temperature, Fe-B predominates.

For this reason, in the SPV method, the heat treatment at about 200 ° C. is performed, and the diffusion length is measured before and after the heat treatment. Thus, the principle is that not only the diffusion length but also the Fe concentration can be measured. From the results shown in FIG. 3, it is understood that the diffusion length of Fei is shorter, and the electrical characteristics are further deteriorated.
However, since the diffusion length is increased in any of the measurements, it can be seen that the diffusion length can be reliably improved by the rapid heating / cooling heat treatment after the epitaxial growth.

When the type and morphology of the BMD were examined by TEM observation, only a typical plate-like oxygen precipitate was observed in the wafer subjected to only Ar annealing. Further, plate-like oxygen precipitates were also present in the wafer subjected to the epitaxial growth, but it was confirmed that stacking faults and dislocation loops were additionally generated. That is, an epitaxial wafer which is an embodiment of Japanese Patent Application Laid-Open No. 2000-44389, in which an epitaxial growth is performed after annealing a nitrogen-doped substrate, has not only oxygen precipitates as gettering sites but also stacking faults and dislocation loops. It was discovered that On the other hand, in a wafer obtained by further performing RTA on such a wafer, stacking faults were no longer observed, and only a large number of dislocation loops having a characteristic hexagonal shape were observed in addition to oxygen precipitates. Therefore, it is understood that such a dislocation loop can be introduced as a gettering site by rapid heating / rapid cooling heat treatment.

The reason why the form of the defect changes is as follows.
It is estimated as follows. That is, the oxygen precipitates that existed by the as-annealing sweep out the interstitial Si during the epi-growth, and they accumulate during cooling to form stacking faults.
When RTA is further performed, unstable stacking faults change into characteristic hexagonal dislocation loops for some reason. With this consideration, the state of defect seed formation can be understood.

Although the reason why the RTA is used to increase the carrier diffusion length and the lifetime is not clear at present, the gettering effect due to the stacking faults in the wafer forming dislocation loops is not clear. It can be considered as a cause that the life time is affected by the increase of the defect or the change of the defect form itself.

The present invention is not limited to the above embodiment. The above embodiment is an exemplification, and has substantially the same configuration as the technical idea described in the scope of the claims of the present invention. It is included in the technical scope of the invention.

For example, in growing a silicon single crystal rod doped with nitrogen by the Czochralski method in the present invention, it does not matter whether a magnetic field is applied to the melt or not. The Czochralski method includes a so-called MCZ method in which a magnetic field is applied.

Further, the epitaxial growth is not limited to the epitaxial growth by CVD.
The present invention can be applied to a case where an epitaxial silicon wafer is manufactured by performing epitaxial growth by BE.

[0056]

As described above, according to the present invention, a silicon wafer doped with nitrogen is used as a substrate of an epitaxial silicon wafer, and a heat treatment for eliminating crystal defects near the surface of the silicon single crystal wafer is performed. Furthermore, after a silicon epitaxial layer is formed on the surface of the silicon single crystal wafer, a rapid heating / cooling heat treatment is performed, so that the diffusion length of carriers in the wafer can be increased, and the electrical characteristics of the wafer can be improved. be able to. Further, since a large amount of dislocation loops can be introduced as gettering sites into the bulk portion of the wafer, it is expected that gettering of metal impurities and the like different from the conventional type can be achieved.

[Brief description of the drawings]

FIG. 1 is a diagram showing OPP measurement results of a BMD density at each evaluation stage of an epitaxial silicon wafer.

FIG. 2 is a diagram showing results of OPP measurement of a BMD size at each evaluation stage of an epitaxial silicon wafer.

FIG. 3 is a diagram showing SPV measurement results of the carrier diffusion length at each evaluation stage of an epitaxial silicon wafer.

FIG. 4 is a diagram showing SPV measurement results of the lifetime of a carrier at each evaluation stage of an epitaxial silicon wafer.

FIG. 5 is a schematic sectional view showing an example of an apparatus capable of rapidly heating and rapidly cooling a silicon wafer.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Chamber, 2 ... Heat lamp, 3 ... Auto shutter, 4 ... Quartz tray, 5 ... Three-point support part, 6 ... Buffer, 7 ... Pyrometer, 8 ... Wafer, 10 ...
Heat treatment equipment.

Claims (5)

[Claims] In a method of manufacturing an epitaxial silicon wafer, a silicon single crystal rod doped with nitrogen is grown by the Czochralski method, and the silicon single crystal rod is sliced and processed into a silicon single crystal wafer. After performing a heat treatment to eliminate crystal defects near the surface of the single crystal wafer, and further forming a silicon epitaxial layer on the surface of the silicon single crystal wafer,
A method for producing an epitaxial silicon wafer, comprising performing a rapid heating / rapid cooling heat treatment. 2. When growing a silicon single crystal rod doped with nitrogen by the Czochralski method, the concentration of nitrogen doped into the single crystal rod is 1 × 10 ¹² to 1 × 10 ^14.
2. The method for producing an epitaxial silicon wafer according to claim 1, wherein the number is set to the number of pieces / cm < ³ >. 3. A heat treatment for eliminating crystal defects near the surface performed on the silicon single crystal wafer includes the steps of:
3. The method for producing an epitaxial silicon wafer according to claim 1, wherein a heat treatment is performed at 00 to 1300 [deg.] C. for 10 to 300 minutes. 4. The rapid heating / rapid cooling heat treatment includes:
4. The method according to claim 1, wherein the heat treatment is performed at 1100 to 1350 [deg.] C. for 1 to 120 seconds.
13. The method for producing an epitaxial silicon wafer according to the above item. 5. An epitaxial silicon wafer comprising a silicon single crystal wafer doped with nitrogen and a silicon epitaxial layer formed on a surface thereof.
Dislocation loops in the bulk and more than 5 × 10 ⁸ B / cm ³ B
MD density and carrier diffusion length is 300μm
An epitaxial silicon wafer characterized by the above.