JP2002231956A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can prevent parasitic bipolar effects caused by board floating effect and besides can reduce the gate capacitance. SOLUTION: A p channel region 6, a p body lead electrode 7 connected to the channel region 6, and a p high-concentration body contact region 8 connected to the body lead region 7 are made in the region of a semiconductor layer 3 surrounded by an element isolating insulating film 4. Moreover, the gate electrode 9 is composed of the first gate electrode part 9a on the body lead region 7, the second gate electrode part 9b on the channel region 6, and the third gate electrode 9c on the element isolating insulating film 4. Moreover, on the body lead region 7, an insulating film 20 thicker than the gate insulating film 10 is made under the first gate electrode part 9b. Then, a sidewall insulating film 11 is made at the sidewall of the gate electrode 9, and an interlayer insulating film 12 is made on the substrate where the gate electrode 9 is made.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an SOI device insulated by an insulating layer.
(Silicon On Insulator) The present invention relates to a semiconductor device having a MIS transistor formed on a substrate and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the demand for higher speed, higher density, and lower power consumption of a semiconductor device, an element is formed on a semiconductor layer made of silicon provided on an insulating layer.
A semiconductor device in which a MIS transistor (hereinafter, referred to as an “SOI MIS transistor”) is formed on a substrate is being developed. This SOI MIS transistor can be completely insulated and separated including the substrate side, which is the bottom surface of the transistor, by insulating and separating the elements.
It is possible to reduce a leak current, improve a current driving capability, suppress a short channel effect, and the like. For this reason, it is expected to be used as a basic transistor structure for micro memory devices and logic circuits on the order of quarter microns in the future.

However, in a general SOI type MIS transistor, a channel region (hereinafter referred to as a “body region”) surrounded by a source / drain diffusion layer and an element isolation insulating film.
) Is in a floating state without applying a potential from the outside, and there is a problem that transistor characteristics fluctuate due to a substrate floating effect caused by the majority carriers generated by the hot carrier effect being accumulated in the body. For example, in “Semiconductor Research 40” published by the Industrial Research Council, as described in P166 to P167,
Rise steep current found in I _D -V _G characteristics, I _D -
Kink phenomena in V _D characteristics, reduction of the source / drain breakdown voltage, a latch phenomena such as found in I _D -V _G characteristics occurs,
The characteristics of the SOI MIS transistor deteriorate. Such deterioration in characteristics is due to the fact that the substrate is in a floating state, and is called a parasitic bipolar effect.

As a method of preventing the parasitic bipolar effect caused by the floating state of the substrate, an SOI type MIS transistor (hereinafter, referred to as "S with body contact") capable of forming an electrode in a body contact region and fixing the potential of the body.
OI MIS transistor ").

Hereinafter, a conventional SOI with body contact will be described.
A semiconductor device having a type MIS transistor will be described. FIG. 9 shows a conventional SOI type M with a body contact.
FIG. 3A is an example of an IS transistor, and FIG.
(B) is XX sectional drawing of (a).

As shown in FIG. 9, an SOI MIS transistor with a body contact includes a supporting substrate 51 formed of a semiconductor substrate, an insulating layer 52 formed of a silicon oxide film formed on the supporting substrate 51, and an insulating layer 52 formed on the insulating layer 52. The semiconductor device is formed using an SOI substrate 50 composed of a semiconductor layer 53 made of silicon formed on the substrate. The support substrate 51 and the semiconductor layer 53 are electrically insulated and separated from each other by an insulating layer 52.

In the region of the semiconductor layer 53 surrounded by the element isolation insulating film 54, an n-type high-concentration source / drain diffusion layer 55 and a p-type channel sandwiched between the high-concentration source / drain diffusion layers 55 are provided. Region 56 and channel region 56
Are formed, and a p-type high-concentration body contact region 58 connected to the body extraction region 57 is formed.

The gate electrode 59 is composed of a body extraction region 57, a channel region 56 and an element isolation insulating film 54.
A first gate electrode portion 59a located above the body leading region 57, a second gate electrode portion 59b located above the channel region 56, and And a third gate electrode 59c located above the element isolation insulating film 54.
A side wall insulating film 61 is formed on the side wall of the gate electrode 59, and an interlayer insulating film 62 is formed on the substrate on which the gate electrode 59 is formed.

A third gate electrode portion 59c of the gate electrode 59 located on the element isolation insulating film 54 is provided with a wiring 64 via a contact 63a provided on the interlayer insulating film 62.
a, and the high-concentration body contact region 58
Is connected to a wiring 64b via a contact 63b. Further, a contact 63c is also provided on the high concentration source / drain diffusion layer 55, and each is connected to a wiring. Note that, in FIG.
a and 64b are not shown and are omitted.

FIGS. 10A to 10D are cross-sectional views showing the steps of manufacturing a semiconductor device having a conventional SOI MIS transistor with a body contact.

First, in the step shown in FIG.
The substrate 50 includes a supporting substrate 51 made of a semiconductor substrate, an insulating layer 52 made of a silicon oxide film having a thickness of 100 nm formed on the supporting substrate 51, and a semiconductor layer made of silicon having a thickness of 150 nm formed on the insulating layer 52. SOI in which the supporting substrate 51 and the silicon semiconductor layer 53 are electrically insulated from each other by the insulating layer 52.
It has a structure. The semiconductor layer 53 of this SOI substrate 50
An element isolation insulating film 54 reaching the insulating layer 52 is formed in the element isolation region. Then, after forming a gate insulating film 60x made of a silicon oxide film, the gate insulating film 60x is formed.
A polycrystalline silicon film 59x serving as a gate electrode is formed thereon.

Next, in a step shown in FIG. 10B, a resist 70 for forming a gate electrode is formed on the polycrystalline silicon film 59x.
Is formed, the polycrystalline silicon film 59x and the gate insulating film 60x are etched using the resist 70 as a mask to form the gate electrode 59 and the gate insulating film 60.
At this time, the gate electrode 59 is connected to the body extraction region 5.
7a, channel region 56a and element isolation insulating film 54
The polycrystalline silicon film 59x on the body contact region 58a is removed. After that, the resist 70 is removed. Next, an extension implantation resist (not shown) is formed, ions are implanted using the extension implantation resist and the gate electrode 59 as a mask, and a high-concentration extension diffusion layer (not shown) is selectively formed in the source / drain regions. To form After that, the extension injection resist is removed.

Next, in a step shown in FIG. 10C, after an insulating film is deposited on the entire surface, the insulating film is etched by anisotropic etching to form a side wall insulating film 61 on the side wall of the gate electrode 59. . Thereafter, a source / drain implantation resist (not shown) is formed, and ion implantation is performed using the source / drain implantation resist, the gate electrode 59 and the side wall insulating film 61 as a mask, and a high-concentration is selectively formed in the source / drain regions. A source / drain diffusion layer 55 is formed. The high-concentration source / drain diffusion layer 55 is shown only in FIG. Thereafter, the source / drain implantation resist is removed. Next, the body contact region 58
After a resist 71 having an opening 72 is formed on a, a p-type impurity is ion-implanted using the resist 71 as a mask to form a high-concentration body contact region 58.
As a result, a structure is obtained in which the p-type channel region 56 sandwiched between the high-concentration source / drain diffusion layers 55 is connected to the p-type high-concentration body contact region 58 via the p-type body lead-out region 57.

Next, in a step shown in FIG. 10D, the resist 71 is removed and an interlayer insulating film 62 is formed on the entire surface.
A contact window is formed on the gate electrode 59, the high concentration source / drain diffusion layer 55, and the high concentration body contact region 58. Thereafter, a metal film is buried in the contact window to form contacts 63a, 63b, and 63c, respectively. The contact 63c is shown only in FIG. After that, wirings 64a and 64b connected to the contacts 63a and 63b are formed. At this time, a wiring connected to the contact 63c is formed at the same time. Thus, SOI with body contact as shown in FIG.
A semiconductor device having a type MIS transistor can be formed.

[0015]

However, in the above-described conventional semiconductor device having an SOI MIS transistor with a body contact and a method of manufacturing the same, FIG.
As shown in FIG. 10B and FIG.
6 and the body extraction region 57 have substantially the same impurity concentration and impurity profile, and the gate insulating film 60 and the gate electrode 59 on the channel region 56 and the body extraction region 57 are formed in the same manner. Therefore, with the miniaturization of the element, the proportion of the unnecessary gate capacitance formed between the body lead-out region 57 and the gate electrode 59 (first gate electrode portion 59a) in the total gate capacitance increases, so that the transistor There is a problem that the processing speed cannot be increased.

According to the present invention, there is provided a semiconductor device having an SOI MIS transistor with a body contact capable of preventing a parasitic bipolar effect due to a substrate floating effect, reducing gate capacitance and contact resistance, and improving transistor characteristics. And a method for producing the same.

[0017]

In order to achieve the above-mentioned object, a solution taken by the present invention is to provide means for making the threshold value in the body lead-out region deeper than the threshold value in the channel region. .

A basic structure of a semiconductor device according to the present invention is formed on an SOI substrate including a supporting substrate, an insulating layer formed on the supporting substrate, and a semiconductor layer formed on the insulating layer. A MIS transistor, wherein the MIS transistor is an element isolation insulating film reaching the insulating layer provided in the element isolation region of the semiconductor layer;
A source / drain region of the first conductivity type, a channel region of the second conductivity type sandwiched between the source / drain regions, and a body of the second conductivity type connected to the channel region; A semiconductor layer region including a lead region, a second conductivity type body contact region connected to the body lead region, a first gate electrode portion formed above the body lead region, and a semiconductor layer region formed above the channel region; A gate electrode including a second gate electrode portion and a third gate electrode formed on the element isolation insulating film, and a threshold in a body lead-out region below the first gate electrode portion is defined as an effective channel region. The threshold is deeper than the threshold in the channel region below the second gate electrode portion.

In the structure of the present invention, the threshold value in the body lead-out region below the first gate electrode portion is deeper than the threshold value in the channel region below the second gate electrode portion, which is to be an effective channel region (threshold). Since the absolute value of the value increases), the gate capacitance in the body extraction region is reduced, the operation speed of the transistor is improved, and a high-performance semiconductor device can be obtained.

In the above-mentioned semiconductor device, the work function difference between the first gate electrode portion and the underlying body lead region is the second.
The difference is larger than the work function difference between the gate electrode portion and the underlying channel region.

In the above-mentioned semiconductor device, the insulating film formed between the first gate electrode portion and the underlying body lead-out region may include a gate formed between the second gate electrode portion and the underlying channel region. The thickness is larger than that of the insulating film.

In the above semiconductor device, the first gate electrode portion contains a material having a larger work function than the second gate electrode portion.

In the above semiconductor device, the impurity concentration of the first conductivity type in the first gate electrode portion is lower than the impurity concentration of the first conductivity type in the second gate electrode portion.

In the semiconductor device, the impurity concentration of the second conductivity type in the body lead region is higher than the impurity concentration of the second conductivity type in the channel region.

According to a first method of manufacturing a semiconductor device according to the present invention, an SOI substrate including a supporting substrate, an insulating layer formed on the supporting substrate, and a semiconductor layer formed on the insulating layer is formed on an SOI substrate. In a method of manufacturing a semiconductor device having a MIS transistor in which a channel region of a second conductivity type is connected to a body contact region of a second conductivity type via a body lead-out region of the second conductivity type, insulating is provided in an element isolation region in a semiconductor layer. (A) forming an element isolation insulating film reaching the layer;
A step (b) of forming an insulating film on at least the body lead-out region, a step (c) of forming a gate insulating film thinner than the insulating film on the channel region, and a step of forming an insulating film on the body lead-out region via the insulating film A gate electrode including a first gate electrode portion formed by the above, a second gate electrode portion formed on the channel region via a gate insulating film, and a third gate electrode portion formed on the element isolation insulating film. Forming a source / drain region by introducing an impurity of a first conductivity type into the semiconductor layer;

According to this manufacturing method, the insulating film formed between the body extraction region and the first gate electrode portion is smaller than the gate insulating film formed between the channel region and the second gate electrode portion. The threshold value in the body lead-out region below the first gate electrode portion is
The threshold value can be made deeper than the threshold value in the channel region below the second gate electrode portion that becomes the effective channel region.
Thus, the gate capacitance in the body extraction region is reduced, the operation speed of the transistor is improved, and a high-performance semiconductor device can be obtained.

According to a second method of manufacturing a semiconductor device according to the present invention, an SOI substrate including a supporting substrate, an insulating layer formed on the supporting substrate, and a semiconductor layer formed on the insulating layer is formed on an SOI substrate. In a method of manufacturing a semiconductor device having a MIS transistor in which a channel region of a second conductivity type is connected to a body contact region of a second conductivity type via a body lead-out region of the second conductivity type, insulating is provided in an element isolation region in a semiconductor layer. (A) forming an element isolation insulating film reaching the layer;
A step (b) of forming a gate insulating film on the semiconductor layer after the step (a), a first gate electrode portion formed on the body lead-out region via the gate insulating film, and a gate insulating film on the channel region (C) forming a gate electrode including a second gate electrode portion formed through the first gate electrode portion and a third gate electrode portion formed on the element isolation insulating film; and forming a first gate electrode portion on at least the second gate electrode portion. Step (d) of introducing impurities
And introducing a second impurity into the first gate electrode portion having a work function larger than that of the second gate electrode portion (e).
And introducing a first conductivity type impurity into the semiconductor layer to
(F) forming a drain region.

According to this manufacturing method, the first gate electrode portion on the body lead region contains an impurity whose work function is larger than that of the second gate electrode portion on the channel region. The work function difference between the underlying body lead region and the work function difference between the second gate electrode portion and the underlying channel region becomes larger. Therefore, the threshold value in the body lead region below the first gate electrode portion is
The threshold value can be made deeper than the threshold value in the channel region below the second gate electrode portion that becomes the effective channel region.
Thus, the gate capacitance in the body extraction region is reduced, the operation speed of the transistor is improved, and a high-performance semiconductor device can be obtained.

In the second method for manufacturing a conductor device,
The first impurity is at least one of arsenic and phosphorus, and the second impurity is Ti, Hf, Zr,
It is made of at least one of V, Cr, Mo, Ta, W, Ni, Co, Pt, Pd and Rh.

According to a third method of manufacturing a semiconductor device according to the present invention, an SOI substrate including a supporting substrate, an insulating layer formed on the supporting substrate, and a semiconductor layer formed on the insulating layer is formed on an SOI substrate. In a method of manufacturing a semiconductor device having a MIS transistor in which a channel region of a second conductivity type is connected to a body contact region of a second conductivity type via a body lead-out region of the second conductivity type, insulating is provided in an element isolation region in a semiconductor layer. (A) forming an element isolation insulating film reaching the layer;
After the step (a), a step (b) of forming a gate insulating film on the semiconductor layer, and a first gate electrode portion formed on the body lead-out region via the gate insulating film and a gate insulating film on the channel region Forming a gate electrode including a second gate electrode portion formed through the film and a third gate electrode portion formed on the element isolation insulating film; and (c) forming a first conductive type impurity in the semiconductor layer. (D) to form a source / drain region by introducing an impurity, and a step (e) of forming the first conductive type impurity concentration of the first gate electrode portion to be lower than that of the second gate electrode portion. ).

According to this manufacturing method, the first gate electrode portion on the body lead region has a lower impurity concentration of the first conductivity type than the second gate electrode portion on the channel region.
The work function difference between the first gate electrode portion and the underlying body lead region is larger than the work function difference between the second gate electrode portion and the underlying channel region. Therefore, the threshold value in the body extraction region below the first gate electrode portion can be made deeper than the threshold value in the channel region below the second gate electrode portion, which is an effective channel region. Thus, the gate capacitance in the body extraction region is reduced, the operation speed of the transistor is improved, and a high-performance semiconductor device can be obtained.

In the third method of manufacturing a semiconductor device, in the step (d), the first impurity of the first conductivity type is introduced into the first gate electrode portion and the second gate electrode portion, and then the first impurity is introduced.
A second impurity of a second conductivity type is introduced into the gate electrode portion,
The concentration of the first conductivity type impurity contained in the first gate electrode portion is made lower than the concentration of the first conductivity type impurity contained in the second gate electrode portion.

In the third method of manufacturing a semiconductor device, the step of introducing the first impurity of the first conductivity type into the first gate electrode portion and the second gate electrode portion may include the step of (d) The step of introducing the second impurity of the second conductivity type into the first gate electrode portion simultaneously with the introduction of the first conductivity type impurity for forming the drain region is performed by the second step of forming the body contact region; This is performed simultaneously with the introduction of the conductive impurity. Thereby, the second impurity of the second conductivity type for forming the body contact region is introduced into the first gate electrode portion on the body lead region, and the first impurity of the first conductivity type in the first gate electrode portion is introduced. The first impurity is offset, and the impurity concentration of the first impurity of the first conductivity type is lower than that of the second gate electrode portion formed over the channel region.

According to a fourth method of manufacturing a semiconductor device according to the present invention, an SOI substrate including a supporting substrate, an insulating layer formed on the supporting substrate, and a semiconductor layer formed on the insulating layer is formed on an SOI substrate. In a method of manufacturing a semiconductor device having a MIS transistor in which a channel region of a second conductivity type is connected to a body contact region of a second conductivity type via a body lead-out region of the second conductivity type, insulating is provided in an element isolation region in a semiconductor layer. (A) forming an element isolation insulating film reaching the layer;
After the step (a), a step (b) of introducing an impurity of the second conductivity type into the body lead region so as to have a higher concentration than the impurity concentration of the second conductivity type of the channel region; and a step (b).
Forming a gate insulating film on the semiconductor layer after the step (c), forming a first gate electrode portion formed on the body lead-out region via the gate insulating film, and forming a gate insulating film on the channel region via the gate insulating film Forming a gate electrode including the second gate electrode portion and the third gate electrode portion formed on the element isolation insulating film; and (d) introducing a first conductivity type impurity into the semiconductor layer to form a source electrode. And (e) forming a drain region.

According to this manufacturing method, since the impurity concentration of the second conductivity type in the body extraction region is made higher than the p-type impurity concentration in the channel region, the work function of the body extraction region is reduced to the work function of the channel region. It is smaller than that. Therefore, the work function difference between the first gate electrode portion and the underlying body extraction region is larger than the work function difference between the second gate electrode portion and the underlying channel region. Therefore, the threshold value in the body extraction region below the first gate electrode portion can be made deeper than the threshold value in the channel region below the second gate electrode portion, which is an effective channel region. Thus, the gate capacitance in the body extraction region is reduced, the operation speed of the transistor is improved, and a high-performance semiconductor device can be obtained.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment First, a semiconductor device having an SOI MIS transistor with a body contact according to a first embodiment of the present invention and a method for manufacturing the same will be described. FIG. 1 is an example of a semiconductor device having an SOI MIS transistor with a body contact according to a first embodiment of the present invention, wherein FIG.
(B) is AA sectional drawing of (a).

As shown in FIG. 1, the SOI MIS transistor with a body contact according to the first embodiment is
An SOI substrate 100 composed of a support substrate 1 made of a semiconductor substrate, an insulating layer 2 made of a silicon oxide film formed on the support substrate 1, and a semiconductor layer 3 made of silicon formed on the insulating layer 2 The supporting substrate 1 and the semiconductor layer 3 are electrically insulated from each other by the insulating layer 2.

The n-type high-concentration source / drain diffusion layer 5 and the p-type channel sandwiched between the high-concentration source / drain diffusion layers 5 are provided in the semiconductor layer 3 region surrounded by the element isolation insulating film 4. Region 6, p-type body lead-out region 7 connected to channel region 6, and body lead-out region 7
And a p-type high concentration body contact region 8 connected thereto.

The gate electrode 9 includes a first gate electrode portion 9 a located above the body leading region 7, a second gate electrode portion 9 b located above the channel region 6, and an upper portion of the element isolation insulating film 4. And the third gate electrode 9c located at the same position. On the channel region 6, a gate insulating film 10 made of a silicon oxide film or a silicon oxynitride film having a predetermined thickness is formed between the second gate electrode portion 9b and the second gate electrode portion 9b. In addition, an insulating film 20 made of a silicon oxide film or a silicon oxynitride film having a thickness larger than that of the gate insulating film 10 is formed between the body extraction region 7 and the first gate electrode portion 9a.
A side wall insulating film 11 is formed on the side wall of the gate electrode 9, and an interlayer insulating film 12 is formed on the substrate on which the gate electrode 9 is formed.

The third gate electrode portion 9c of the gate electrode 9 located on the element isolation insulating film 4 has an interlayer insulating film 12
Is connected to the wiring 14a through a contact 13a provided in the high-concentration body contact region 8, and the high-concentration body contact region 8 is connected to the wiring 14b through the contact 13b.
Further, a contact 13c is provided on the high concentration source / drain diffusion layer 5 and is connected to a wiring (not shown). FIG. 1A shows the wiring 1
Illustration of 4a and 14b is omitted.

FIGS. 2A to 2D show the first embodiment of the present invention.
SOI MIS with body contact according to the embodiment of the present invention
FIG. 4 is a cross-sectional view illustrating a manufacturing process of a semiconductor device having a transistor.

First, in the step shown in FIG. 2A, the SOI substrate 100 includes a support substrate 1 made of a semiconductor substrate, an insulating layer 2 made of a silicon oxide film having a thickness of 100 nm formed on the support substrate 1, and Thickness 150 formed on insulating layer 2
and an SOI structure in which the supporting substrate 1 and the silicon semiconductor layer 3 are electrically insulated from each other by the insulating layer 2. An element isolation insulating film 4 reaching the insulating layer 2 is formed in an element isolation region of the semiconductor layer 3 of the SOI substrate 100. Thereafter, an insulating film having a thickness of 7.5 nm is formed on the semiconductor layer 3, a resist 21 covering at least the body leading-out region 7a is formed, and then the channel region 6a and the source / drain region are formed using the resist 21 as a mask. The insulating film (not shown) is removed by etching to form an insulating film 20x. Note that the insulating film 20x may be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a stacked film thereof so that the film thickness is larger than that of the gate insulating film.

Next, in the step shown in FIG. 2B, after removing the resist 21, a gate insulating film 10x having a thickness smaller than the insulating film 20x and a thickness of 3.5 nm is formed. A polycrystalline silicon film 9x serving as a gate electrode is formed on the film 10x.

Next, in the step shown in FIG. 2C, after a resist (not shown) for forming a gate electrode is formed on the polycrystalline silicon film 9x, the polycrystalline silicon film 9x is formed using the resist as a mask. The gate insulating film 10x and the insulating film 20x are etched to form the gate electrode 9, the gate insulating film 10, and the insulating film 20. At this time, the gate electrode 9 is formed over the body leading region 7a, the channel region 6a, and the upper portion of the element isolation insulating film 4, and the polycrystalline silicon film 9x on the body contact region 8a is removed. .

After that, the resist is removed. Next, a extension implantation resist (not shown) performs extension implantation resist and the gate electrode 9 to the ion implantation of arsenic into the mask energy 10 keV, a dose of 4 × 10 ¹⁴ / cm ^2, the source-drain An n-type high-concentration extension diffusion layer (not shown) is selectively formed in the region. After that, the extension injection resist is removed.

Thereafter, after depositing an insulating film on the entire surface, the insulating film is etched by anisotropic etching to form a sidewall insulating film 11 on the sidewall of the gate electrode 9. Thereafter, a source / drain injection resist (not shown) is formed, and the source / drain injection resist and the gate electrode 9 are formed.
Using the sidewall insulating film 11 as a mask and arsenic ion implantation at an energy of 20 keV and a dose of 3 × 10 ¹⁴ / cm ² , an n-type high-concentration source / drain diffusion layer 5 is selectively formed in the source / drain regions. . The high concentration source / drain diffusion layer 5 is shown only in FIG.
Thereafter, the source / drain implantation resist is removed.
Next, after forming a body contact implantation resist 22 having an opening 23 on the body contact region 8a, boron ion implantation is performed using the resist 22 as a mask at an energy of 5 keV and a dose of 2 × 10 ¹⁵ / cm ^2. The high concentration body contact region 8 is formed. As a result, the p-layer sandwiched between the high-concentration source / drain diffusion layers 5
The structure is such that the p-type channel region 6 is connected to the p-type high-concentration body contact region 8 via the p-type body extraction region 7.

Next, in the step shown in FIG. 2D, after removing the resist 22 and forming the interlayer insulating film 12 on the entire surface, the gate electrode 9, the high concentration source / drain diffusion layer 5, and the high concentration body contact are formed. A contact window is formed on the region 8. Thereafter, a metal film is buried in the contact window to form contacts 13a, 13b, and 13c, respectively. The contact 13c is shown only in FIG. After that, wirings 14a and 14b connected to the contacts 13a and 13b are formed. At this time, contact 1
The wiring connected to 3c is formed at the same time. Thereby, SOI type M with body contact as shown in FIG.
A semiconductor device having an IS transistor can be formed.

As described above, according to the semiconductor device and the method for fabricating the same according to the first embodiment of the present invention, the insulating film 20 formed between the body extraction region 7 and the first gate electrode portion 9a It is formed thicker than the gate insulating film 10 formed between the gate insulating film 9 and the second gate electrode portion 9b. Therefore, the threshold value in the body lead-out region 7 below the first gate electrode portion 9a becomes deeper than the threshold value in the channel region 6 below the second gate electrode portion 9b which becomes an effective channel region (the threshold value). Since the absolute value becomes higher), the gate capacitance in the body lead-out region 7 is reduced as compared with the conventional structure as shown in FIG. 9, and the operation speed of the transistor is improved, so that a high-performance semiconductor device can be obtained.

(Second Embodiment) First, a semiconductor device having an SOI MIS transistor with a body contact according to a second embodiment of the present invention and a method for manufacturing the same will be described. 3A and 3B show an example of an SOI MIS transistor with a body contact according to a second embodiment of the present invention. FIG. 3A is a plan view, and FIG. 3B is a BB cross-sectional view of FIG.

As shown in FIG. 3, the SOI MIS transistor with a body contact according to the second embodiment is
An SOI substrate 100 composed of a support substrate 1 made of a semiconductor substrate, an insulating layer 2 made of a silicon oxide film formed on the support substrate 1, and a semiconductor layer 3 made of silicon formed on the insulating layer 2 The supporting substrate 1 and the semiconductor layer 3 are electrically insulated from each other by the insulating layer 2.

In the region of the semiconductor layer 3 surrounded by the element isolation insulating film 4, an n-type high concentration source / drain diffusion layer 5 and a p-type channel sandwiched between the high concentration source / drain diffusion layers 5 are formed. Region 6, p-type body lead-out region 7 connected to channel region 6, and body lead-out region 7
And a p-type high concentration body contact region 8 connected thereto.

The gate electrode 25 is formed via the gate insulating film 26 over the body extraction region 7, the channel region 6 and the upper part of the element isolation insulating film 4, and is located above the body extraction region 7. It is composed of a first gate electrode part 25a, a second gate electrode part 25b located above the channel region 6, and a third gate electrode 25c located above the element isolation insulating film 4. Of the gate electrode 25, the second gate electrode portion 25b and the third gate electrode portion 25c are provided with n such as arsenic (As) or phosphorus (P).
Type impurities have been introduced. On the other hand, the first gate electrode portion 2
5a has a material having a larger work function than the second gate electrode portion 25b and the third gate electrode portion 25c, for example, Ti,
Hf, Zr, V, Cr, Mo, Ta, W, Ni, Co,
At least one impurity of Pt, Pd and Rh is introduced. The side wall insulating film 11 is formed on the side wall of the gate electrode 25, and the interlayer insulating film 12 is formed on the substrate on which the gate electrode 25 is formed.

A third gate electrode portion 25c of the gate electrode 25 located on the element isolation insulating film 4 is connected to a wiring 14a via a contact 13a provided on the interlayer insulating film 12.
The high-concentration body contact region 8 is connected to a wiring 14b via a contact 13b. Further, a contact 13c is provided on the high concentration source / drain diffusion layer 5 and is connected to a wiring (not shown). In FIG. 3A, the illustration of the wirings 14a and 14b is omitted.

FIGS. 4A to 4D show the second embodiment of the present invention.
SOI MIS with body contact according to the embodiment of the present invention
FIG. 4 is a cross-sectional view illustrating a manufacturing process of a semiconductor device having a transistor.

First, in the step shown in FIG. 4A, the SOI substrate 100 includes a support substrate 1 made of a semiconductor substrate, an insulating layer 2 made of a silicon oxide film having a thickness of 100 nm formed on the support substrate 1, and Thickness 150 formed on insulating layer 2
and an SOI structure in which the supporting substrate 1 and the silicon semiconductor layer 3 are electrically insulated from each other by the insulating layer 2. An element isolation insulating film 4 reaching the insulating layer 2 is formed in an element isolation region of the semiconductor layer 3 of the SOI substrate 100. Next, after a gate insulating film 26x made of a silicon oxide film is formed, a polycrystalline silicon film 25x to be a gate electrode is formed on the gate insulating film 26x. Thereafter, a material film having a large work function, for example, T
An i film is formed with a thickness of about 30 nm. Next, after forming a resist (not shown) covering at least the body lead-out region 7a, the resist is used as a mask to form Ti on the channel region 6a and the source / drain regions (not shown).
The film is removed by etching to form a Ti film 27. Thereafter, the polycrystalline silicon film 25x and the Ti film 27 are removed by performing a heat treatment after removing the resist on the Ti film 27.
To form a titanium-containing polycrystalline silicon film (titanium silicide film) 25y. The material films having a large work function include Ti, Hf, Zr, V, Cr, M
A material film containing at least one impurity of o, Ta, W, Ni, Co, Pt, Pd, and Rh may be used.

Next, in the step shown in FIG. 4B, after the Ti film 27 remaining on the titanium-containing polycrystalline silicon film 25y is removed, the polycrystalline silicon film 25x and the titanium-containing polycrystalline silicon film 25y are removed. Resist 2 for forming gate electrode
8 is formed. Thereafter, using the resist 28 as a mask, the polycrystalline silicon film 25x, the titanium-containing polycrystalline silicon film 2
The gate electrode 25 and the gate insulating film 26 composed of the first gate electrode portion 25a, the second gate electrode portion 25b, and the third gate electrode portion 25c are formed by etching the gate electrode 5y and the gate insulating film 26x. At this time, the gate electrode 25
The titanium-containing polycrystalline silicon film 25y formed over the body leading region 7a, the channel region 6a, and the upper portion of the element isolation insulating film 4 is removed from the body contact region 8a. Note that the titanium-containing polycrystalline silicon film 25y may be completely a titanium silicide film.

After that, the resist 28 is removed. next,
A resist for extension injection (not shown) is formed, and a resist for extension injection and a gate electrode 2 are formed.
5 is used as a mask to perform arsenic ion implantation to selectively form an n-type high-concentration extension diffusion layer (not shown) in the source / drain regions. After that, the extension injection resist is removed.

Next, in the step shown in FIG. 4C, after depositing an insulating film on the entire surface, the insulating film is etched by anisotropic etching to form a sidewall insulating film 11 on the sidewall of the gate electrode 25. . Thereafter, a source / drain implantation resist (not shown) is formed, and arsenic ions are ion-implanted using the source / drain implantation resist, the gate electrode 25 and the side wall insulating film 11 as a mask, and selectively into the source / drain regions. N-type high concentration source / drain diffusion layer 5
To form The high concentration source / drain diffusion layer 5 is shown only in FIG. Thereafter, the source / drain implantation resist is removed. Next, after forming a body contact implantation resist 30 having an opening 29 on the body contact region 8a, a high concentration body contact region 8 is formed by ion-implanting a p-type impurity using the resist 30 as a mask. I do. As a result, a structure is obtained in which the p-type channel region 6 sandwiched between the high-concentration source / drain diffusion layers 5 is connected to the p-type high-concentration body contact region 8 via the p-type body lead-out region 7.

Next, in a step shown in FIG. 4D, the resist 22 is removed and the interlayer insulating film 12 is formed on the entire surface, and then the gate electrode 25, the high concentration source / drain diffusion layer 5, and the high concentration body contact are formed. A contact window is formed on the region 8. Thereafter, a metal film is buried in the contact window to form contacts 13a, 13b, and 13c, respectively. The contact 13c is shown only in FIG. After that, wirings 14a and 14b connected to the contacts 13a and 13b are formed. At this time, contact 1
The wiring connected to 3c is formed at the same time. Thereby, SOI type M with body contact as shown in FIG.
A semiconductor device having an IS transistor can be formed.

As described above, according to the semiconductor device and the method of manufacturing the same according to the second embodiment of the present invention, the second gate electrode portion 2 formed on the channel region 6 and the element isolation insulating film 4
Arsenic ions are simultaneously implanted into the 5b and third gate electrode portions 25c when the high-concentration extension diffusion layer and the high-concentration source / drain diffusion layer 5 are formed, thereby lowering the resistance. Also, the first region formed on the body leading region 7
The gate electrode portion 25a contains titanium whose work function is larger than those of the second gate electrode portion 25b and the third gate electrode portion 25c into which arsenic is introduced. in this way,
The first gate electrode portion 25a on the body extraction region 7
Since the second gate electrode portion 25b on the channel region 6 contains an impurity having a higher work function than that of the second gate electrode portion 25b, the first gate electrode portion 2b
The work function difference between 5a and the base body extraction region 7 is
The work function difference between the second gate electrode portion 25b and the underlying channel region 6 is larger. That is, the threshold value in the body lead-out region 7 below the first gate electrode portion 25a is deeper than the threshold value in the channel region 6 below the second gate electrode portion 25b which is an effective channel region (the threshold value). Since the absolute value becomes higher), the gate capacitance in the body lead-out region 7 is reduced as compared with the conventional structure as shown in FIG. 9, and the operation speed of the transistor is improved, so that a high-performance semiconductor device can be obtained.

Third Embodiment First, a semiconductor device having an SOI MIS transistor with a body contact according to a third embodiment of the present invention and a method of manufacturing the same will be described. 5A and 5B show an example of an SOI MIS transistor with a body contact according to the third embodiment of the present invention, wherein FIG. 5A is a plan view and FIG. 5B is a cross-sectional view taken along the line CC of FIG.

As shown in FIG. 5, the SOI MIS transistor with body contact according to the third embodiment is
An SOI substrate 100 composed of a support substrate 1 made of a semiconductor substrate, an insulating layer 2 made of a silicon oxide film formed on the support substrate 1, and a semiconductor layer 3 made of silicon formed on the insulating layer 2 The supporting substrate 1 and the semiconductor layer 3 are electrically insulated from each other by the insulating layer 2.

In the region of the semiconductor layer 3 surrounded by the element isolation insulating film 4, an n-type high concentration source / drain diffusion layer 5 and a p-type channel sandwiched between the high concentration source / drain diffusion layers 5 are formed. Region 6, p-type body lead-out region 7 connected to channel region 6, and body lead-out region 7
And a p-type high concentration body contact region 8 connected thereto.

The gate electrode 31 is formed via the gate insulating film 32 over the body lead region 7, the channel region 6, and the upper part of the element isolation insulating film 4, and is located above the body lead region 7. The first gate electrode portion 31a, the second gate electrode portion 31b located above the channel region 6, and the third gate electrode 31c located above the isolation insulating film 4 are formed. In the gate electrode 31, the n-type impurity concentration of the first gate electrode portion 31a is formed lower than the n-type impurity concentration of the second gate electrode portion 31b and the third gate electrode portion 31c. The side wall insulating film 11 is formed on the side wall of the gate electrode 31.
Is formed, and the interlayer insulating film 12 is formed on the substrate on which the gate electrode 31 is formed.

A third gate electrode portion 31c of the gate electrode 31 located on the element isolation insulating film 4 is connected to a wiring 14a via a contact 13a provided on the interlayer insulating film 12.
The high-concentration body contact region 8 is connected to a wiring 14b via a contact 13b. Further, a contact 13c is provided on the high concentration source / drain diffusion layer 5 and is connected to a wiring (not shown). In FIG. 5A, the illustration of the wirings 14a and 14b is omitted.

FIGS. 6A to 6D show the third embodiment of the present invention.
SOI MIS with body contact according to the embodiment of the present invention
FIG. 4 is a cross-sectional view illustrating a manufacturing process of a semiconductor device having a transistor.

First, in the step shown in FIG. 6A, the SOI substrate 100 includes a support substrate 1 made of a semiconductor substrate, an insulating layer 2 made of a silicon oxide film having a thickness of 100 nm formed on the support substrate 1, and Thickness 150 formed on insulating layer 2
and an SOI structure in which the supporting substrate 1 and the silicon semiconductor layer 3 are electrically insulated from each other by the insulating layer 2. An element isolation insulating film 4 reaching the insulating layer 2 is formed in an element isolation region of the semiconductor layer 3 of the SOI substrate 100. Next, after forming a gate insulating film 32x made of a silicon oxide film, a polycrystalline silicon film 31x to be a gate electrode is formed on the gate insulating film 32x.

Next, in the step shown in FIG. 6B, a resist 33 for forming a gate electrode is formed on the polycrystalline silicon film 31x. After that, using the resist 33 as a mask, the polycrystalline silicon film 31x and the gate insulating film 32x are etched to form the gate electrode 31 and the gate insulating film 32. At this time, the gate electrode 31 is formed over the body leading region 7a, the channel region 6a, and the upper portion of the element isolation insulating film 4, and the polycrystalline silicon film 31x on the body contact region 8a is removed. .

Next, after removing the resist 33, a resist for extension implantation (not shown) is formed, and ion implantation of arsenic ions is performed at an energy of 10 ke using the mask for extension implantation and the gate electrode 31 as a mask.
V, at a dose of 4 × 10 ¹⁴ / cm ² , an n-type high-concentration extension diffusion layer (not shown) is selectively formed in the source / drain regions. After that, the extension injection resist is removed.

Next, in a step shown in FIG. 6C, after an insulating film is deposited on the entire surface, the insulating film is etched by anisotropic etching to form a side wall insulating film 11 on the side wall of the gate electrode 31. . Thereafter, a source / drain implantation resist (not shown) is formed, and arsenic ion implantation is performed at an energy of 20 keV using the source / drain implantation resist, the gate electrode 31 and the sidewall insulating film 11 as a mask.
The dose is set to 3 × 10 ¹⁴ / cm ² , and the n-type high-concentration source / drain diffusion layer 5 is selectively formed in the source / drain regions.
To form The high concentration source / drain diffusion layer 5 is shown only in FIG.

After that, the source / drain implantation resist is removed. Next, a body contact implantation resist 35 having an opening 34 formed on the body contact region 8a and the body leading region 7a is formed. Then, using the resist 35 as a mask, boron ion implantation is performed at an energy of 5 keV and a dose amount of 5 keV. This is performed at 2 × 10 ¹⁵ / cm ² to form a high-concentration body contact region 8. by this,
A p-type channel region 6 sandwiched between the high-concentration source / drain diffusion layers 5 is
The structure is connected to the high-concentration body contact region 8 of the mold.

Further, since the p-type impurity for forming the body contact region is introduced into the first gate electrode portion 31a on the body extraction region 7, the second gate electrode portion 31a on the channel region 6 is formed.
Since the n-type impurity (As) is canceled out as compared with the third gate electrode portion 31c on the gate electrode portion 31b and the element isolation insulating film 4, the impurity concentration becomes lower.

Next, in the step shown in FIG. 6D, after removing the resist 35 and forming the interlayer insulating film 12 on the entire surface, the gate electrode 31, the high concentration source / drain diffusion layer 5 and the high concentration body contact are formed. A contact window is formed on the region 8. Thereafter, a metal film is buried in the contact window to form contacts 13a, 13b, and 13c, respectively. The contact 13c is shown only in FIG. After that, wirings 14a and 14b connected to the contacts 13a and 13b are formed. At this time, contact 1
The wiring connected to 3c is formed at the same time. Thereby, SOI type M with body contact as shown in FIG.
A semiconductor device having an IS transistor can be formed.

As described above, according to the semiconductor device and the method of manufacturing the same according to the third embodiment of the present invention, the p-type impurity for forming the body contact region is introduced into the first gate electrode portion 31a on the body leading region 7. Therefore, compared to the second gate electrode portion 31 b and the third gate electrode portion 31 c formed on the channel region 6 and the element isolation insulating film 4, n
The impurity concentration of the mold impurity is reduced. That is, when forming the high-concentration extension diffusion layer and the high-concentration source / drain diffusion layer 5, of the arsenic ions implanted into the gate electrode 31, the arsenic ions in the first gate electrode portion 31a are used for forming the body contact region. This is offset by the introduction of the p-type impurity, so that the n-type impurity concentration decreases. As described above, since the first gate electrode portion 31a on the body extraction region 7 has a lower n-type impurity concentration than the second gate electrode portion 31b on the channel region 6, the first gate electrode portion 31a and the underlying body The work function difference between the lead region 7 and the work function difference between the second gate electrode portion 31b and the underlying channel region 6 becomes larger. That is, the threshold value in the body lead-out region 7 below the first gate electrode portion 31a is deeper than the threshold value in the channel region 6 below the second gate electrode portion 31b which is an effective channel region (the threshold value). Since the absolute value becomes higher), the gate capacitance in the body lead-out region 7 is reduced as compared with the conventional structure as shown in FIG. 9, and the operation speed of the transistor is improved, so that a high-performance semiconductor device can be obtained.

(Fourth Embodiment) First, a semiconductor device having an SOI MIS transistor with a body contact according to a fourth embodiment of the present invention and a method for manufacturing the same will be described. FIGS. 7A and 7B show an example of an SOI MIS transistor with a body contact according to the fourth embodiment of the present invention. FIG. 7A is a plan view, and FIG. 7B is a cross-sectional view taken along line DD of FIG.

As shown in FIG. 7, the SOI MIS transistor with a body contact according to the fourth embodiment is
An SOI substrate 100 composed of a support substrate 1 made of a semiconductor substrate, an insulating layer 2 made of a silicon oxide film formed on the support substrate 1, and a semiconductor layer 3 made of silicon formed on the insulating layer 2 The supporting substrate 1 and the semiconductor layer 3 are electrically insulated from each other by the insulating layer 2.

In the region of the semiconductor layer 3 surrounded by the element isolation insulating film 4, an n-type high concentration source / drain diffusion layer 5 and a p-type channel sandwiched between the high concentration source / drain diffusion layers 5 are formed. Region 16, body lead region 17 connected to channel region 16 and having a higher p-type impurity concentration than channel region 16, and p-type high concentration body contact region 1 connected to body lead region 17
8 are formed.

The gate electrode 36 is formed via the gate insulating film 37 over the body lead region 17, the channel region 16 and the upper part of the element isolation insulating film 4, and is located above the body lead region 17. It comprises a first gate electrode portion 36a, a second gate electrode portion 36b located above the channel region 16, and a third gate electrode 36c located above the element isolation insulating film 4. The side wall insulating film 11 is formed on the side wall of the gate electrode 36, and the interlayer insulating film 12 is formed on the substrate on which the gate electrode 36 is formed.

The third gate electrode portion 36c of the gate electrode 36 located on the element isolation insulating film 4 is connected to the wiring 14a via the contact 13a provided on the interlayer insulating film 12.
The high-concentration body contact region 18 is connected to a wiring 14b via a contact 13b. Further, a contact 13c is provided on the high concentration source / drain diffusion layer 5 and is connected to a wiring (not shown). In FIG. 7A, the illustration of the wirings 14a and 14b is omitted.

FIGS. 8A to 8D show the fourth embodiment of the present invention.
SOI MIS with body contact according to the embodiment of the present invention
FIG. 4 is a cross-sectional view illustrating a manufacturing process of a semiconductor device having a transistor.

First, in the step shown in FIG. 8A, the SOI substrate 100 includes a supporting substrate 1 made of a semiconductor substrate, an insulating layer 2 made of a silicon oxide film having a thickness of 100 nm formed on the supporting substrate 1, and Thickness 150 formed on insulating layer 2
and an SOI structure in which the supporting substrate 1 and the silicon semiconductor layer 3 are electrically insulated from each other by the insulating layer 2. An element isolation insulating film 4 reaching the insulating layer 2 is formed in an element isolation region of the semiconductor layer 3 of the SOI substrate 100. Next, after forming a resist (not shown) having openings on the body extraction region and the body contact region, boron ions are implanted with energy of 3 using the resist as a mask.
The process is performed at 0 keV and a dose of 1 to 2 × 10 ¹³ / cm ² to form a body lead-out region 17a and a body contact region 18a. At this time, the body drawing area 1
The channel region 16a is formed such that the p-type impurity concentration of 7a becomes high. In this embodiment, boron ions are implanted into both the body lead-out region 17a and the body contact region 18a.
What is necessary is just to implant a type impurity. Thereafter, the resist is removed, a gate insulating film 37x made of a silicon oxide film is formed, and then a polycrystalline silicon film 36x to be a gate electrode is formed on the gate insulating film 37x.

Next, in the step shown in FIG. 8B, a resist 38 for forming a gate electrode is formed on the polycrystalline silicon film 36x. Thereafter, the polycrystalline silicon film 36x and the gate insulating film 37x are etched using the resist 38 as a mask to form the gate electrode 36 and the gate insulating film 37. At this time, the gate electrode 36 is formed over the body leading region 17a, the channel region 16a, and the upper portion of the element isolation insulating film 4, and the polycrystalline silicon film 36x on the body contact region 18a is removed. .

Next, after removing the resist 38, an extension implantation resist (not shown) is formed, and arsenic ion implantation is performed at an energy of 10 keV and a dose of 4 × using the extension implantation resist and the gate electrode 36 as a mask. At 10 ¹⁴ / cm ² , an n-type high-concentration extension diffusion layer (not shown) is selectively formed in the source / drain regions. After that, the extension injection resist is removed.

Next, in the step shown in FIG. 8C, after an insulating film is deposited on the entire surface, the insulating film is etched by anisotropic etching to form the side wall insulating film 11 on the side wall of the gate electrode 36. . Thereafter, a source / drain implantation resist (not shown) is formed, and arsenic ion implantation is performed at an energy of 20 keV and a dose of 3 × 10 ¹⁴ / with the source / drain implantation resist, the gate electrode 36 and the sidewall insulating film 11 as a mask. performed in cm ^2, to form a high-concentration source-drain diffusion layer 5 of selectively n-type source and drain regions. The high-concentration source / drain diffusion layer 5 is shown in FIG.
It is shown only in (a).

After that, the source / drain implantation resist is removed. Next, after forming a body contact implantation resist 40 having an opening 39 on the body contact region 18a, boron ion implantation is performed using this resist 40 as a mask at an energy of 5 keV and a dose of 2 × 10 4.
^{At 15} / cm ² , a high concentration body contact region 18 is formed. As a result, the structure is such that the p-type channel region 16 sandwiched between the high-concentration source / drain diffusion layers 5 is connected to the p-type high-concentration body contact region 18 via the p-type body lead-out region 17. The impurity concentration of each region is, for example, 1 × 10 ¹⁸ / channel region 16.
cm ³ , body lead-out area 17 is 3 × 10 ¹⁸ / cm ³ ,
3 × 10 ²¹ / cm ³ high-concentration body contact region 18
It is.

Next, in the step shown in FIG. 8D, after removing the resist 40 and forming the interlayer insulating film 12 on the entire surface, the gate electrode 36, the high concentration source / drain diffusion layer 5, and the high concentration body contact are formed. A contact window is formed on the region 18. Thereafter, a metal film is buried in the contact window to form contacts 13a, 13b, and 13c, respectively. The contact 13c is shown only in FIG. After that, wirings 14a and 14b connected to the contacts 13a and 13b are formed. At this time, contact 1
The wiring connected to 3c is formed at the same time. Thereby, SOI type M with body contact as shown in FIG.
A semiconductor device having an IS transistor can be formed.

As described above, according to the semiconductor device and the method of manufacturing the same according to the fourth embodiment of the present invention, the p-type impurity concentration of the body lead region 17 is made higher than the p-type impurity concentration of the channel region 16. Body pull-out area 1
7 becomes larger than the work function of the channel region 16. Therefore, the work function difference between the first gate electrode portion 36a and the underlying body extraction region 17 is larger than the work function difference between the second gate electrode portion 31b and the underlying channel region 16. That is, the threshold value in the body lead-out region 17 below the first gate electrode portion 31a becomes deeper than the threshold value in the channel region 16 below the second gate electrode portion 31b which becomes an effective channel region (the threshold value). Since the absolute value increases), the gate capacitance in the body lead-out region 17 is reduced as compared with the conventional structure as shown in FIG. 9, and the operation speed of the transistor is improved, so that a high-performance semiconductor device can be obtained.

[0088]

As described above, according to the present invention, the work function difference between the first gate electrode portion and the underlying body lead region is smaller than the work function difference between the second gate electrode portion and the underlying channel region. It will be larger than that. Therefore, the threshold value in the body extraction region below the first gate electrode portion is deeper than the threshold value in the channel region below the second gate electrode portion, which is an effective channel region. The operation speed of the transistor is reduced and a high-performance semiconductor device can be obtained.

[Brief description of the drawings]

FIG. 1 is an example of a semiconductor device having an SOI MIS transistor with a body contact according to a first embodiment of the present invention, where (a) is a plan view and (b) is a cross-sectional view taken along line AA of (a).

FIGS. 2A to 2D are cross-sectional views illustrating manufacturing steps of a semiconductor device having an SOI MIS transistor with a body contact according to the first embodiment of the present invention;

3A and 3B are examples of a semiconductor device having an SOI MIS transistor with a body contact according to a second embodiment of the present invention, wherein FIG. 3A is a plan view and FIG.

FIGS. 4A to 4D are cross-sectional views illustrating manufacturing steps of a semiconductor device having an SOI MIS transistor with a body contact according to a second embodiment of the present invention.

FIG. 5 is an example of a semiconductor device having an SOI MIS transistor with a body contact according to a third embodiment of the present invention, wherein (a) is a plan view and (b) is a cross-sectional view taken along line CC of (a).

FIGS. 6A to 6D are cross-sectional views illustrating manufacturing steps of a semiconductor device having an SOI MIS transistor with a body contact according to a third embodiment of the present invention.

7A and 7B are examples of a semiconductor device having an SOI MIS transistor with a body contact according to a fourth embodiment of the present invention, wherein FIG. 7A is a plan view and FIG.

FIGS. 8A to 8D are cross-sectional views illustrating manufacturing steps of a semiconductor device having an SOI MIS transistor with a body contact according to a fourth embodiment of the present invention.

9A and 9B are an example of a semiconductor device having a conventional SOI MIS transistor with a body contact, in which FIG. 9A is a plan view and FIG. 9B is a cross-sectional view taken along line XX of FIG.

FIGS. 10A to 10D are cross-sectional views illustrating a manufacturing process of a semiconductor device having a conventional SOI MIS transistor with a body contact.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 support substrate 2 insulating layer 3 semiconductor layer 4 element isolation insulating film 5 high-concentration source / drain diffusion layer 6 channel region 7 body lead-out region 8 high-concentration body contact region 9 gate electrode 10 gate insulating film 11 sidewall insulating film 12 interlayer insulating film 13a, 13b, 13c Contact 100 SOI substrate

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 4M104 AA09 BB01 BB25 BB39 BB40 CC05 EE03 EE11 FF14 GG09 GG10 GG14 5F110 AA02 AA15 BB03 BB05 CC02 DD05 DD13 EE05 EE09 EE12 EE32 EE48 FF02 FF03 GG02 FF03 GG04 FF03 GG04 FF03 GG03 NN02 NN62

Claims (13)

[Claims] 1. A semiconductor device having an MIS transistor formed on an SOI substrate including a supporting substrate, an insulating layer formed on the supporting substrate, and a semiconductor layer formed on the insulating layer, The MIS transistor, an element isolation insulating film that reaches the insulating layer provided in an element isolation region of the semiconductor layer; a first conductivity type source / drain region surrounded by the element isolation insulating film; A second conductivity type channel region sandwiched between source / drain regions, a second conductivity type body lead region connected to the channel region, and a second conductivity type body contact region connected to the body lead region A first gate electrode portion formed above the body lead-out region; and a first gate electrode portion formed above the channel region. A gate electrode comprising a second gate electrode portion and a third gate electrode formed on the element isolation insulating film, wherein a threshold in the body lead-out region below the first gate electrode portion is an effective channel region. A semiconductor device which is deeper than a threshold value in the channel region below the second gate electrode portion. 2. The semiconductor device according to claim 1, wherein a work function difference between the first gate electrode portion and the underlying body extraction region is a work function between the second gate electrode portion and the underlying channel region. A semiconductor device characterized by being larger than the difference. 3. The semiconductor device according to claim 1, wherein an insulating film formed between said first gate electrode portion and said underlying body lead region is formed between said second gate electrode portion and said underlying channel region. A semiconductor device having a larger thickness than a gate insulating film formed between the semiconductor device and the semiconductor device. 4. The semiconductor device according to claim 1, wherein the first gate electrode portion contains a material having a work function larger than that of the second gate electrode portion. Semiconductor device. 5. The semiconductor device according to claim 1, wherein an impurity concentration of the first conductivity type of the first gate electrode portion is lower than an impurity concentration of the first conductivity type of the second gate electrode portion. A semiconductor device having a concentration. 6. The semiconductor device according to claim 1, wherein an impurity concentration of the second conductivity type in the body lead region is:
A semiconductor device, wherein the channel region has a higher impurity concentration than a second conductivity type impurity concentration. 7. An SOI substrate including a supporting substrate, an insulating layer formed on the supporting substrate, and a semiconductor layer formed on the insulating layer has a second conductivity type channel region formed on the second substrate. In a method of manufacturing a semiconductor device having an MIS transistor connected to a body contact region of a second conductivity type via a body lead region of a conductivity type, an element isolation insulating film reaching the insulating layer is provided in an element isolation region of the semiconductor layer. Forming (a), forming an insulating film at least on the body lead-out region (b), and forming a gate insulating film thinner than the insulating film on the channel region (c) A first gate electrode portion formed on the body lead region via the insulating film; and a second gate electrode formed on the channel region via the gate insulating film. Parts and, and forming a gate electrode and a third gate electrode portion formed on the element isolation insulating film (d), the source and introducing a first conductivity type impurity into said semiconductor layer
(E) forming a drain region. 8. An SOI substrate including a supporting substrate, an insulating layer formed on the supporting substrate, and a semiconductor layer formed on the insulating layer, wherein a second conductivity type channel region is formed on the SOI substrate. In a method of manufacturing a semiconductor device having an MIS transistor connected to a body contact region of a second conductivity type via a body lead region of a conductivity type, an element isolation insulating film reaching the insulating layer is formed in an element isolation region of the semiconductor layer. Forming (a), after the step (a), forming a gate insulating film on the semiconductor layer (b), and forming a gate insulating film on the body lead-out region via the gate insulating film. A gate comprising: one gate electrode portion; a second gate electrode portion formed on the channel region via the gate insulating film; and a third gate electrode portion formed on the element isolation insulating film. A step (c) of forming an electrode; a step (d) of introducing at least a first impurity into the second gate electrode section; (E) introducing a second impurity that increases in size, and introducing a first conductivity type impurity into the semiconductor layer to form a source
And (f) forming a drain region. 9. The method of manufacturing a semiconductor device according to claim 8, wherein said first impurity is at least one of arsenic and phosphorus.
And the second impurity is Ti, Hf, Zr, V, Cr, M
A method of manufacturing a semiconductor device, comprising: at least one impurity selected from the group consisting of o, Ta, W, Ni, Co, Pt, Pd, and Rh. 10. An SOI substrate including a supporting substrate, an insulating layer formed on the supporting substrate, and a semiconductor layer formed on the insulating layer has a second conductivity type channel region formed by a second conductive type channel region. In a method of manufacturing a semiconductor device having an MIS transistor connected to a body contact region of a second conductivity type via a body lead region of a conductivity type, an element isolation insulating film reaching the insulating layer is provided in an element isolation region of the semiconductor layer. Forming (a), after the step (a), forming a gate insulating film on the semiconductor layer (b), and forming a gate insulating film on the body lead-out region via the gate insulating film. A gate comprising: one gate electrode portion; a second gate electrode portion formed on the channel region via the gate insulating film; and a third gate electrode portion formed on the element isolation insulating film. (C) forming an electrode, and introducing a first conductivity type impurity into the semiconductor layer to form a source / electrode.
Forming a drain region; and (e) forming the first gate electrode portion to have a first conductive type impurity concentration lower than that of the second gate electrode portion. A method of manufacturing a semiconductor device. 11. The method for manufacturing a semiconductor device according to claim 10, wherein in the step (d), a first impurity of a first conductivity type is introduced into the first gate electrode portion and the second gate electrode portion. Then, a second impurity of a second conductivity type is introduced into the first gate electrode portion, and the first impurity contained in the first gate electrode portion is removed.
A method of manufacturing a semiconductor device, comprising: setting a conductivity type impurity concentration to be lower than the first conductivity type impurity concentration included in the second gate electrode portion. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the first gate electrode portion and the second gate electrode portion have a first gate electrode portion.
The step of introducing the first impurity of the conductivity type is performed simultaneously with the introduction of the first conductivity type impurity for forming the source / drain regions in the step (d), and the step of introducing the second conductivity type into the first gate electrode portion. The method of introducing a second impurity is performed simultaneously with the introduction of a second conductivity type impurity for forming the body contact region. 13. An SOI substrate including a supporting substrate, an insulating layer formed on the supporting substrate, and a semiconductor layer formed on the insulating layer, wherein a second conductivity type channel region is formed on the SOI substrate. In a method of manufacturing a semiconductor device having an MIS transistor connected to a body contact region of a second conductivity type via a body lead region of a conductivity type, an element isolation insulating film reaching the insulating layer is provided in an element isolation region of the semiconductor layer. Forming (a) and, after the step (a), introducing a second conductivity type impurity into the body lead region so as to be higher in concentration than the second conductivity type impurity in the channel region. (B)
(C) forming a gate insulating film on the semiconductor layer after the step (b); and a first gate electrode portion formed on the body lead-out region via the gate insulating film. Forming a gate electrode including a second gate electrode portion formed on the channel region via the gate insulating film and a third gate electrode portion formed on the element isolation insulating film; By introducing impurities of the first conductivity type into the semiconductor layer,
(E) forming a drain region.