JP2002231943A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having such a structure that by applying, from a peripheral part of a chip, a gate control signal to a gate interconnection disposed vertically through the chip from one side to the opposite side of the peripheral part of the chip, a switching element at the center of the chip can be switched nearly simultaneously with a switching element near the peripheral part of the chip. SOLUTION: The gate wiring of the semiconductor device comprises a peripheral wiring formed in the peripheral part of the chip, and vertical wiring formed in a plurality of columns from one side to the opposite side of the peripheral wiring so as to be nearly in parallel with each other. The width of each vertical wiring becomes larger as it comes closer to the center of the chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, switching a plurality of switching elements regularly arranged on the chip by applying a gate control signal from the chip periphery to the gate wiring arranged vertically from one side to the opposite side of the chip periphery. Accordingly, the present invention relates to a semiconductor device that conducts and blocks one signal as a whole chip.

[0002]

2. Description of the Related Art In a semiconductor device, a plurality of switching elements regularly arranged on a chip are connected to a gate wiring formed by vertically extending from one side of the chip periphery to the other side. In some chips, one signal is turned on and off as a whole by applying a control signal to perform switching.

FIG. 4 is a plan view showing an overall schematic configuration of a semiconductor device which controls a switching element on a chip by applying a gate control signal from a peripheral portion of the chip.

This semiconductor device has a gate composed of a chip peripheral wiring formed on a chip peripheral part, and a chip vertical part wiring formed in a plurality of substantially parallel rows extending from one side to the other side of the chip peripheral wiring. A wiring 1; a gate pad electrode 2 formed by enlarging a part of a chip peripheral wiring of the gate wiring 1 in order to apply a gate control signal to the gate wiring 1; And a cell unit 3 including a plurality of switching elements controlled by a gate control signal via the control unit 1.

[0005] As the switching element included in the cell section 3, various elements such as a MOS type switching element can be used. Here, an IGBT (Insulate) is used.
d Gate Bipolar Transistor).

FIG. 5 is an enlarged plan view showing a part of the structure of the cell portion of the mesh type gate wiring structure. In addition, FIG.
FIG. 5 is an enlarged plan view showing a portion corresponding to an enlarged portion 4 which is a part of the cell portion 3 in FIG. 4.

Cell structures 6 are arranged at a predetermined pitch between each of the gate wirings 1 formed in a plurality of substantially parallel rows extending from one side to the opposite side of the chip peripheral portion. A peripheral structure 5 is provided between the gate wirings 1 in the vicinity of the chip periphery.
Are formed.

In the cell portion of the mesh type gate wiring structure, the gate wiring 1 is also formed between the cell structures 6 substantially at right angles to the gate wiring 1 formed by vertically extending from one side of the chip peripheral portion to the opposite side. ing. Therefore, as shown in FIG. 5, the gate wiring 1 has a mesh type structure.

FIG. 6 shows an IGB as an example of the cell structure 6.
It is sectional drawing which showed the structure of T. FIG. 6 is a sectional view taken along line CC ′ in FIG.

The IGBT includes a gate oxide film 7 formed on the side and bottom surfaces in the trench on the surface of the semiconductor substrate, a gate wire 1 formed on the gate oxide film 7 so as to fill the trench, It comprises an emitter layer 8 formed near the surface of the base diffusion layer 9 on both sides, and a collector layer (not shown) at the bottom of the semiconductor substrate.

In the IGBT, when a gate control signal is applied to the gate wiring 1, a channel region 10 is formed along the side of the trench between the emitter layer 8 and the collector layer, and the channel region 10 is formed from the emitter layer 8 on the substrate surface side. The current flows to the collector layer on the back side of the substrate.

FIG. 7 is a plan view schematically showing a shape of a channel region 10 formed in an IGBT which is a cell structure 6 in a mesh-type gate wiring structure cell portion, as viewed from above.

In the cell portion of the mesh type gate wiring structure, a gate control signal is applied by the gate wiring 1 formed along the four sides of the cell structure 6, so that the channel region 10 is formed as shown in FIG. The cell structure 6 is formed in a rectangular shape along the periphery.

FIG. 8 is an enlarged plan view showing a part of the structure of the cell portion of the stripe type gate wiring structure. FIG.
5 is an enlarged plan view showing a portion corresponding to an enlarged portion 4 which is a part of the cell portion 3 in FIG.

A cell structure 6 is provided between each of the gate lines 1 formed in a plurality of substantially parallel rows extending from one side to the opposite side of the chip peripheral portion. In addition, a peripheral structure 5 is formed between the respective gate wirings 1 near the periphery of the chip.

The cell structure 6 in the stripe-shaped gate wiring structure cell portion includes a plurality of switching elements (cells) separated at predetermined pitches by its internal structure. Therefore, as shown in FIG.
Has a stripe type structure.

The IGBT shown in FIG. 6 can be used as a switching element included in the cell structure 6 in the cell portion of the stripe type gate wiring structure. Therefore, the cross-sectional view taken along line DD ′ in FIG. 8 is the same as that in FIG.

FIGS. 9A and 9B are plan views schematically showing examples of the structure of the IGBT included in the cell structure 6 in the stripe-shaped gate wiring structure cell portion, as viewed from above. It is.

The emitter layer 8 shown in FIGS. 9A and 9B
Is a top view of the emitter layer 8 in FIG. That is, as shown in FIGS. 9A and 9B, the cell structure 6 in the stripe-shaped gate wiring structure cell portion has a P
It has a structure including a plurality of IGBTs separated by the mold layer 11.

Then, when a gate control signal is applied to the gate wiring 1, as shown in FIGS.
A channel region 10 is formed along the side surface of the trench where the BT is formed, and the emitter layer 8 on the substrate surface side is formed.
Current flows from the collector layer to the collector layer on the back side of the substrate.

In both the conventional semiconductor device having the mesh-type gate wiring structure cell portion and the conventional semiconductor device having the stripe-type gate wiring structure cell portion, the gate wiring width W of the cell portion (see FIG. 6). As shown in FIGS. 5 and 8, W = a, and was always constant both in the vicinity of the periphery of the chip and in the center of the chip.

[0022]

However, in the conventional semiconductor device having the above-described structure, the gate wiring width W is always constant both in the vicinity of the chip periphery and in the center of the chip. The closer to the center of the chip, the greater the gate wiring resistance seen from the switching element.
The transmission of the gate control signal will be delayed.

Therefore, when the semiconductor device switches from the non-conductive state to the conductive state, the switching elements are sequentially switched to the conductive state from the chip peripheral part toward the chip central part.

As a result of the delay of the gate control signal, a current may flow in the switching element in the center of the chip before a sufficiently large channel region is formed, and the cell may be destroyed.

The present invention has been made in view of the above problems, and an object of the present invention is to apply a gate control signal from a chip peripheral portion to a gate wiring which is provided so as to extend from one side to the other side of the chip peripheral portion. It is another object of the present invention to provide a semiconductor device having a configuration in which a switching element in a central portion of a chip can be switched almost simultaneously with a switching element in a vicinity of a peripheral portion of the chip.

[0026]

According to the semiconductor device of the present invention, there is provided a chip peripheral wiring formed on a chip peripheral part, and a plurality of substantially parallel lines extending from one side to the opposite side of the chip peripheral wiring. A gate line formed of chip vertical section wiring formed in a column, wherein the width of each of the chip vertical section wirings increases from the chip peripheral portion toward the chip central portion, and a gate control signal is applied to the gate wiring. A cell including a gate pad electrode formed by expanding a part of the chip peripheral wiring and a plurality of switching elements provided on the chip and controlled by a gate control signal via the gate wiring And a unit.

According to this configuration, the gate wiring resistance as viewed from the switching elements near the chip center and the periphery of the chip becomes substantially uniform, so that a delay of the gate control signal at the chip center can be prevented, and the chip center can be prevented. The switching element near the peripheral portion of the chip and the periphery of the chip can be switched almost simultaneously. As a result, the conduction state of the entire chip can be made uniform, and destruction of the switching element at the center of the chip can be prevented.

In other words, it is preferable that the chip peripheral portion wiring has a first width near the chip peripheral portion and a second width larger than the first width near the chip central portion.

It is preferable that the ratio of the second width to the first width is determined so that the gate wiring resistance as viewed from the switching element in each part on the chip becomes substantially uniform.

The cell section includes a cell structure disposed at a predetermined pitch between the chip vertical section wirings and constituting a part of the switching element. Both ends of the cell section are located between the cell structures. It is preferable that a gate wiring between cell structures connected to the chip vertical section wiring is formed.

Alternatively, the cell section includes a cell structure disposed between the chip vertical section wirings and divided at predetermined pitches by an internal structure to constitute a part of the switching element. It is good to

The switching element is preferably a MOS type switching element. As an example, the switching element may be an IGBT.

It is preferable that the trench gate of the IGBT is the vertical wiring of the chip, and that the entire width of the trench gate from the top surface to the bottom surface increases from the periphery of the chip to the center of the chip.

Alternatively, it is preferable that the trench gate of the IGBT is the vertical wiring of the chip, and the width of the trench gate in the vicinity of the surface is increased from the periphery of the chip toward the center of the chip.

[0035]

Embodiments of a semiconductor device according to the present invention will be described below with reference to the drawings.

The overall configuration of the semiconductor device according to the present invention is the same as that of the semiconductor device shown in FIG. That is, in the semiconductor device according to the present invention, a plurality of switching elements regularly arranged on the chip are controlled by a gate wiring from the chip periphery to the gate wiring which is vertically arranged from one side to the opposite side of the chip periphery. This is a semiconductor device that conducts and cuts off one signal as a whole chip by applying a signal to perform switching.

Accordingly, the semiconductor device according to the present invention comprises a chip peripheral wiring formed on a chip peripheral part, and a chip longitudinally formed in a plurality of substantially parallel rows extending from one side of the chip peripheral part wiring to the opposite side. A gate wiring 1 composed of a partial wiring;
In order to apply a gate control signal to the gate wiring 1, a gate pad electrode 2 formed by extending a part of a chip peripheral wiring of the gate wiring 1 and a gate pad electrode 2 provided on a chip and via the gate wiring 1 A cell unit 3 including a plurality of switching elements controlled by a gate control signal.

However, the semiconductor device according to the present invention has the following features in the structure of the gate wiring formed in the cell portion.

FIG. 1 is an enlarged plan view showing a configuration of a part of a cell portion of a mesh type gate wiring structure of a semiconductor device according to a first embodiment of the present invention. FIG. 1 is an enlarged plan view showing a portion corresponding to the enlarged portion 4 which is a part of the cell portion 3 in FIG.

As shown in FIG. 1, the cell portion of the semiconductor device according to the first embodiment of the present invention has a mesh type gate wiring structure. Cell structures 6 are arranged at a predetermined pitch between each of the gate wirings 1 formed in a plurality of substantially parallel rows extending from one side to the opposite side of the chip peripheral portion. In addition, a peripheral structure 5 is formed between the respective gate wirings 1 near the periphery of the chip.

In the cell portion of the mesh-type gate wiring structure, the gate wiring 1 is also formed between the cell structures 6 at a substantially right angle to the gate wiring 1 formed by vertically extending from one side to the opposite side of the chip peripheral portion. ing. Therefore, as shown in FIG. 1, the gate wiring 1 has a mesh type structure.

In the semiconductor device according to the first embodiment of the present invention, in the chip peripheral wiring of the gate wiring 1, that is, when the gate wiring width W of the cell part is near the chip peripheral part, the first width a On the other hand, it is characterized in that the width gradually increases as approaching the central portion of the chip, and the second width b (b> a) is larger than the first width a at the central portion of the chip.

When the gate wiring width W in the central portion of the chip is made wider than that in the vicinity of the peripheral portion of the chip, the gate wiring resistance viewed from the switching element in the central portion of the chip is reduced. Therefore, by appropriately adjusting the ratio of the second width b to the first width a, the gate wiring resistance viewed from the switching element at the center of the chip can be reduced to the gate wiring resistance viewed from the switching element near the periphery of the chip. Can be almost equivalent to The ratio of the second width b to the first width a may be determined by simulation, experiment, or the like.

As described above, the gate wiring width W in the central portion of the chip is made wider than that in the vicinity of the peripheral portion of the chip, and the gate wiring resistance as viewed from the switching elements in the central portion of the chip and in the vicinity of the peripheral portion of the chip is made substantially uniform. It is possible to prevent the delay of the gate control signal at the center of the chip,
The switching elements near the chip central part and the chip peripheral part can be switched almost simultaneously. As a result, the conduction state of the entire chip can be made uniform, and destruction of the switching element at the center of the chip can be prevented.

As the switching element included in the cell section 3, various elements such as a MOS type switching element can be used. Here, it is assumed that an IGBT is used.

When an IGBT is used as the switching element, the cross-sectional structure taken along line AA ′ in FIG. 1 can be the same as that shown in FIG. However, in this case, the width of the trench formed on the substrate surface must be set to the first width a near the chip periphery and the second width b at the chip center. In addition, the following structure can be adopted as the structure of the IGBT in the semiconductor device according to the present invention.

FIG. 2 is a sectional view showing an example of the structure of the IGBT in the semiconductor device according to the present invention. FIG.
FIG. 2 is a sectional view taken along line AA ′ in FIG.

In the structure of the IGBT shown in FIG. 2, after a trench having a first width a is first formed, the width of the portion near the substrate surface gradually increases from the vicinity of the periphery of the chip toward the center of the chip. The pattern is etched to form a gate line width adjusting portion 12 having a first width a near the chip peripheral portion and a second width b near the chip center. Thereafter, according to a normal process, a gate oxide film 7 is formed on the side and bottom surfaces in the trench, and a gate wiring 1 is formed on the gate oxide film 7 so as to fill the trench. The gate wiring 1 is formed so as to completely bury the gate wiring width adjustment unit 12. In other respects, the configuration is the same as that of a normal IGBT, and includes an emitter layer 8 formed near the surface of the base diffusion layer 9 on both sides of the gate wiring 1 and a collector layer (not shown) on the bottom surface of the semiconductor substrate. Have been.

The IGBT includes a gate line width adjusting unit 12
The gate wiring resistance as viewed from the switching element is reduced in the portion where the width is wide. Therefore, the first width a
By appropriately adjusting the ratio of the second width b to
The gate wiring resistance can be made substantially uniform from the viewpoint of the switching element anywhere from the vicinity of the chip periphery to the center of the chip.

In this IGBT, similarly to a normal IGBT, when a gate control signal is applied to the gate wiring 1, a channel region 10 is formed along the trench side surface between the emitter layer 8 and the collector layer, and A current flows from the emitter layer 8 on the front surface side to the collector layer on the back surface side of the substrate.

FIG. 3 is an enlarged plan view showing a configuration of a part of a cell part of a stripe type gate wiring structure of a semiconductor device according to a second embodiment of the present invention. FIG. 3 is also an enlarged plan view showing a portion corresponding to the enlarged portion 4 which is a part of the cell portion 3 in FIG.

As shown in FIG. 3, the cell portion of the semiconductor device according to the second embodiment of the present invention has a stripe type gate wiring structure. A cell structure 6 is provided between each of the gate wirings 1 formed in a plurality of substantially parallel rows extending from one side to the opposite side of the chip peripheral portion. In addition, a peripheral structure 5 is formed between the respective gate wirings 1 near the periphery of the chip.

The cell structure 6 in the cell portion of the stripe type gate wiring structure includes a plurality of switching elements (cells) divided at predetermined intervals by its internal structure. Therefore, as shown in FIG.
Has a stripe type structure.

In the semiconductor device according to the second embodiment of the present invention, similarly to the first embodiment, the chip peripheral wiring of the gate wiring 1, that is, the gate wiring width W of the cell portion is used.
Has a first width a near the periphery of the chip, and gradually increases as approaching the center of the chip, and has a second width b (b> a) larger than the first width a at the center of the chip. The feature is that it is.

Therefore, the same effect as in the first embodiment can be obtained also in the semiconductor device according to the second embodiment of the present invention having the stripe type gate wiring structure.

As the switching element included in the cell section 3, various elements such as a MOS type switching element can be used. Here, it is assumed that an IGBT is used.

When an IGBT is used as the switching element, the cross-sectional structure taken along line BB ′ in FIG. 3 can be the same as that shown in FIG. 2 or FIG. However, when the IGBT having the structure shown in FIG.
As in the first embodiment, the width of the trench formed on the substrate surface must be set to the first width a near the periphery of the chip and to the second width b at the center of the chip.

[0058]

According to the semiconductor device of the present invention, the gate wiring width in the central portion of the chip is made wider than that in the vicinity of the peripheral portion of the chip, and the gate wiring resistance as viewed from the switching elements in each part on the chip is made substantially uniform. In addition, it is possible to prevent the delay of the gate control signal in the central portion of the chip, and to switch the switching elements near the central portion of the chip and the vicinity of the peripheral portion of the chip almost simultaneously. As a result, the conduction state of the entire chip can be made uniform, and destruction of the switching element at the center of the chip can be prevented.

[Brief description of the drawings]

FIG. 1 is an enlarged plan view showing a configuration of a part of a cell portion of a mesh-type gate wiring structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing an example of the structure of the IGBT in the semiconductor device according to the present invention.

FIG. 3 is an enlarged plan view illustrating a configuration of a part of a cell part of a stripe-type gate wiring structure of a semiconductor device according to a second embodiment of the present invention;

FIG. 4 is a plan view showing an overall schematic configuration of a semiconductor device that controls a switching element on a chip by applying a gate control signal from a peripheral portion of the chip.

FIG. 5 is an enlarged plan view showing a configuration of a part of a cell portion of a mesh-type gate wiring structure.

FIG. 6 is a cross-sectional view showing the structure of an IGBT as an example of the cell structure 6.

FIG. 7 shows a channel region 10 formed in an IGBT which is a cell structure 6 in a mesh-type gate wiring structure cell portion.
It is the top view which showed typically the shape seen from above.

FIG. 8 is an enlarged plan view showing a configuration of a part of a cell part of a stripe type gate wiring structure.

FIG. 9 is a plan view schematically showing an example of a structure of the IGBT included in the cell structure 6 in the stripe-shaped gate wiring structure cell portion as viewed from above.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Gate wiring 2 Gate pad electrode 3 Cell part 5 Peripheral structure 6 Cell structure 7 Gate oxide film 8 Emitter layer 9 Base diffusion layer 10 Channel region 11 P-type layer 12 Gate wiring width adjustment part

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 21/3205 H01L 21/88 A 29/417 J 29/50 BF Term (Reference) 4M104 CC05 EE09 FF11 FF27 GG06 GG09 GG10 GG14 GG15 HH16 HH20 5F033 MM01 MM21 MM29 MM30 UU03 VV06 XX00 XX08 XX27

Claims (9)

[Claims] 1. A chip peripheral portion wiring formed on a chip peripheral portion, and chip longitudinal section wirings formed in a plurality of substantially parallel rows extending from one side to the opposite side of the chip peripheral portion wiring. A gate wiring in which the width of the chip vertical portion wiring is increased from the chip peripheral portion toward the chip central portion, and a part of the chip peripheral portion wiring is expanded to apply a gate control signal to the gate wiring. A semiconductor device, comprising: a formed gate pad electrode; and a cell unit provided on a chip and including a plurality of switching elements controlled by a gate control signal via the gate wiring. . 2. The chip peripheral portion wiring has a first width near the chip peripheral portion and a second width larger than the first width near the chip central portion. 3. The semiconductor device according to claim 1. 3. A ratio of the second width to the first width is determined so that gate wiring resistance as viewed from the switching element in each part on the chip becomes substantially uniform. The semiconductor device according to claim 1. 4. The cell section includes a cell structure arranged at a predetermined pitch between the respective chip vertical section wirings and constituting a part of the switching element, respectively. 4. The semiconductor device according to claim 1, wherein a gate wiring between cell structures, both ends of which are connected to the chip vertical portion wiring, is formed. 5. The cell section includes a cell structure disposed between the chip vertical section wirings and divided at predetermined pitches by an internal structure to form a part of the switching element. 4. The method according to claim 1, wherein:
The semiconductor device according to any one of the above. 6. The semiconductor device according to claim 1, wherein said switching element is a MOS type switching element. 7. The switching device according to claim 1, wherein the switching element is an IGBT (Insu).
7. The semiconductor device according to claim 1, wherein the semiconductor device is a lated gate bipolar transistor. 8. The trench gate of the IGBT is a vertical wiring of the chip, and the trench gate has an overall width from a surface to a bottom which increases from a chip peripheral part to a chip central part. Claim 7
3. The semiconductor device according to claim 1. 9. The trench gate of the IGBT is the vertical wiring of the chip, and the width of the trench gate in the vicinity of the surface is increased from the periphery of the chip to the center of the chip. Item 8. The semiconductor device according to item 7.