JP2002229817A - Watchdog timer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a watchdog timer controllable without spending a resource such as an address space, a bit space or the like. SOLUTION: This watchdog timer is equipped with a CPU 1, a timer 2 for executing measuring operation by control from the CPU 1, and an initial value memory part 3 for memorizing a restriction value and a measurement start value to be set in the timer 2. First of all, the restriction value is set in the timer 2, and the measurement operation of the timer 2 is started from the restriction value, to thereby acquire a sufficient spare time until the measurement start value which is the most important value is set. Since the restriction value and the measurement start value can be set without losing the address space or the bit space, control of each watchdog timer can be executed without reducing decoding speed of an address or multiplexer speed of data even in a system incorporating many watchdog timers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a watchdog timer, and more particularly, to a watchdog timer control system.

[0002]

2. Description of the Related Art First, a limit value (time-up count value) of a watchdog timer is set by a CPU.
During the measurement operation toward this limit value, C
The PU clears the timer. This type of watchdog timer is used not only to prevent runaway of the CPU but also to prevent damage to solenoids, motors, and the like, and is often incorporated in control logic of the system.

[0003]

Some watchdog timers can change the limit value depending on the drive target and the drive state. Such a watchdog timer that can change the limit value often has a separate address for setting the limit value and an address for clearing the measured value. However, in this case, an additional address space of the main memory is required. In particular, when a large number of watchdog timers exist in the system, an address decoding circuit is required, which complicates the circuit configuration of the system.

On the other hand, instead of separately providing an address for setting a limit value and an address for clearing a measured value, some bits in a bit string accessible by one address are assigned for setting a limit value, and the remaining bits are set. A watchdog timer that allocates bits for clearing measurement values has also been proposed.

However, since it takes time to analyze the contents of the bit string, it may not be possible to quickly set the limit value and clear the measured value.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a watchdog timer that does not waste resources such as an address space and a bit space.

[0007]

In order to solve the above-mentioned problems, the present invention provides a limit value storing means for storing a limit value, a measuring means for performing a measuring operation toward the limit value,
A storage control unit that uses the limit value storage unit for a purpose other than the setting of the limit value before the measurement value of the measurement unit reaches the limit value.

According to the present invention, before the measured value of the measuring means reaches the limit value, the limit value storage means is used for purposes other than the setting of the limit value, so that the number of storage means can be reduced.

Here, the purpose other than the setting of the limit value is, for example, the setting of the measurement start value of the measuring means.

The limit value is, for example, the maximum value that can be measured by the measuring means.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a watchdog timer according to the present invention will be specifically described with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a watchdog timer according to the present invention. The watchdog timer of FIG. 1 is built in a printer, for example, and stores a CPU 1, a timer 2 that performs a measurement operation under the control of the CPU 1, a limit value for setting the timer 2, and a measurement start value. An initial value storage unit 3 is provided. The CPU 1 performs control for storing the limit value in the initial value storage unit 3.

FIG. 2 is a flowchart showing the processing procedure of the watchdog timer of FIG. First, the CPU 1 stores a limit value in the initial value storage unit 3 (step S1). Here, the limit value is the maximum value measured by the timer 2,
For example, 0xffff.

Next, the timer 2 starts a measurement operation with the limit value as an initial value (step S2). After the measurement value of the timer 2 is cleared when the first clock is input (step S3), the measurement value is counted up every time a clock is input (step S4).

Thereafter, at an appropriate timing, the CPU 1 stores the measurement start value in the initial value storage unit 3 (Step S).
5). Since the timer 2 is once cleared before performing the processing in step S5, it is not necessary to perform the processing in step S5 in a hurry. That is, there is sufficient time margin to set the measurement start value.

The measurement start value stored in the initial value storage unit 3 is set in the timer 2 (step S6), and the timer 2 restarts the measurement operation from this value (step S7).

Next, the measured value of the timer 2 is stored in the initial value storage unit 3.
It is determined whether or not the limit value stored in step S8 has been reached (step S8). If the limit value has not been reached, the determination process of step S8 is repeated while continuing the measurement operation of the timer 2 to reach the limit value. Then, the measured value is cleared at the next clock (step S9).

When the system is operating normally, the CPU
1 clears the measured value of the timer 2 while the timer 2 is performing the measuring operation.

As described above, in the present embodiment, the limit value and the measurement start value can be set without losing the address space or the bit space. Therefore, even if the system has many watchdog timers, Each watchdog timer can be controlled without reducing the address decoding speed or the data multiplexer speed.

Further, first, a limit value is set in the timer 2 and the measurement operation of the timer 2 is started from the limit value. Therefore, there is a sufficient time margin before the measurement start value which is the most important value is set. it can. Therefore, the CPU 1 can set the measurement start value with a margin, and the watchdog timer 2 can operate stably.

Even if the CPU 1 runs away between the time when the limit value is stored in the initial value storage unit 3 and the time when the measurement start value is stored in the initial value storage unit 3, the timer 2 sets the limit value as the initial value. Because it operates normally, it is not affected by runaway of CPU1,
It can function normally as the watchdog timer 2.

Further, when the CPU 1 returns thereafter, the limit value itself is valid, and the measurement operation can be normally resumed from the measurement start value newly set in the timer 2.

In this embodiment, the measurement start value is set after setting the limit value in the timer 2 first, and the timer 2 is accessed twice, but in general, the access to the watchdog timer 2 is Since the access is performed at intervals of several hundred ms or more, the number of accesses to the timer 2 from one to two is only a time loss of about 0.0001%. Therefore, there is almost no difference in the processing speed as compared with the conventional case where the limit value and the measurement start value are set at different addresses.

The number of watchdog timers 2 provided in the printer is not always one. A separate watchdog timer may be used to control each part of the printer. In such a case, the CP
U1 may control each watchdog timer according to the processing procedure of FIG. 2, or may control other watchdog timers 2b to 2n by controlling the main watchdog timer 2a as shown in FIG. Good.

The set value of the watchdog timer 2 may be used for various purposes. For example, in FIG. 4, when the set value of the watchdog timer 2 is 0xfff0 to 0xfff6, the watchdog timer 2 for the ports 0 to 6 is cleared, respectively, and when the set value of the watchdog timer 2 is 0xfff8 to 0xfffb, 0xfffe, the time units of the plunger control are different. An example of changing to a value is shown.

When the value of the watchdog timer 2 becomes 0xfffe, the clock for driving the plunger and the watchdog timer 2 is made extremely fast. This is to test and simulate the ASICs rationally instead of using them under normal operating conditions. That is, when the value of the watchdog timer 2 becomes 0xfffe, the clock frequency of the system increases, so that the ASIC test and the like can be performed at high speed.

In the embodiment described above, the watchdog timer 2 built in the printer has been described, but the present invention is applicable to various electric devices other than the printer.

[0028]

As described above in detail, according to the present invention, the limit value storage means is used for another purpose before the measured value of the measuring means reaches the limit value. It is not necessary to separately provide the storage means, and the storage area can be reduced, that is, unnecessary consumption of resources can be prevented. In particular, in the case of the present invention, both the limit value and the measurement start value can be stored in the limit value storage means, and the number of storage means can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a watchdog timer according to the present invention.

FIG. 2 is a flowchart showing a processing procedure of a watchdog timer in FIG. 1;

FIG. 3 is a block diagram showing an example in which another watchdog timer is controlled by controlling a main watchdog timer.

FIG. 4 is a diagram showing an example in which a set value of a watchdog timer is used for various purposes.

[Explanation of symbols]

 1 CPU 2 timer 3 initial value storage

Claims (5)

[Claims] A limit value storing means for storing a limit value; a measuring means for performing a measuring operation toward the limit value; and a limit value storing means before a measured value of the measuring means reaches the limit value. And a storage control unit that uses the limit value for purposes other than the setting of the limit value. 2. The watchdog timer according to claim 1, wherein said measuring means starts a measuring operation from the limit value stored in said limit value storing means. 3. The storage control means stores a measurement start value of the measurement means in the limit value storage means before the measurement value of the measurement means reaches the limit value, wherein the measurement means The watchdog timer according to claim 2, wherein the measurement operation is restarted from a start value, and the measurement value is reset when the limit value is reached. 4. The watchdog timer according to claim 1, wherein said limit value storage means stores a maximum value measurable by said measurement means as said limit value. 5. When the measured value of said measuring means reaches a predetermined value,
5. The watchdog timer according to claim 1, wherein a frequency of a reference clock of said measuring means is increased.