JP2002218249A - Image processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To set a matrix corresponding to an image by using a simple constitution in order to perform matching for smoothing processing. SOLUTION: A printer image processing circuit 11 is provided with a register 13 for valid/invalid matrix stetting besides a matching pattern RAM 12, and a matrix for which validity/invalidity is set beforehand for each pixel is stored in the register 13. Source image data stored in a line memory 15 and a matching pattern read from the matching pattern RAM 12 are compared with a comparator 18 for a valid pixel stored in the register 13 and matching is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing circuit for comparing pixel data of a matching pattern with image data of an image for smoothing processing.

[0002]

2. Description of the Related Art Generally, there is a process called smoothing as one of image processing. For the original image, increase the print resolution (for example, 200 dpi → 400 dpi)
i) This is a method of interpolating pixels to make an image look smoother. In this process, pixels around the pixel of interest,
For example, there is a method in which a 3 × 3 matrix is cut out and pattern matching is performed on eight pixels surrounding the central pixel as a target pixel. Then, it outputs pixel data that has been subjected to resolution conversion for the matched pattern.

[0003]

In the above-mentioned conventional image processing circuit, the effect of the smoothing depends on how the surrounding pixels are taken. Therefore, if it is possible to arbitrarily change the method of obtaining peripheral pixels for performing matching, (1) according to the original image to be printed
You can select the optimal matrix. (2) Even after the circuit [hardware] is determined, it can be changed by software, so that the degree of freedom in design increases. There are merits such as.

The present invention has been made in view of this point, and has an image processing circuit capable of setting a matrix corresponding to an image with a simple configuration and capable of performing processing according to an image. It is intended to provide.

[0005]

An image processing apparatus according to claim 1 of the present application is an image processing circuit that performs smoothing processing on image data by comparing each pixel data of the image with pixel data of a matching pattern. Means are provided for setting whether or not to perform comparison for pixels in the pattern to be matched.

An image processing circuit according to a second aspect of the present invention includes a first memory storing a matching pattern, a comparing circuit comparing pixel data of an image with the matching pattern stored in the first memory, There is provided a second memory for outputting pixel data based on a matching result based on a comparison result of the comparison circuit, and a third memory for setting validity / invalidity of each pixel to be compared by the comparison circuit.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail with reference to embodiments.

FIG. 1 is a block diagram showing a schematic configuration of a multifunction device having a copy function and a facsimile function provided with the image forming apparatus according to the embodiment. This composite device is C
PU (control unit) 1, NCU 2, modem 3, scanner 4,
Operation unit 5, ROM 6, RAM 7, image memory (DRA
M) 8, CODEC 9, DMAC (Direct Memory Access Controller) 10, RAM 12 for matching pattern, and register 1 for valid / invalid matrix
3, a printer image processing circuit (image data processing unit) 11 having a smoothed image data memory 14, a line memory (FIFO) 15, a DMAC 16, and a printer (image forming unit) 17. Each of these elements is the system bus 1
9 and the image bus 20.

[0009] The CPU 1 controls each unit constituting the apparatus.

The NCU 2 controls a connection with a telephone line (not shown), and has a function of transmitting a dial signal corresponding to a destination telephone number (including a FAX number) and a function of detecting an incoming call. Have. Modem 3 uses IT
U (International Telecommunication Union) -T Recommendation 30 based on a facsimile transmission control procedure according to V.30. 17, V.I. 27
ter. Modulation of the transmission data and demodulation of the reception data according to 29 or the like.

The scanner 4 reads image data of a document when performing fax transmission and copying. The operation unit 5 is for the user to instruct facsimile transmission / reception, printing, and the like when using the facsimile function and the copy function.

The ROM 6 stores a program for controlling this device. The RAM 7 temporarily stores data and the like. The image memory 8 temporarily stores received image data and image data read by the scanner 4 in a compressed state. The CODEC 9 encodes (reads) the read image data by MH, MR, MMR or the like in order to transmit the decoded image data, and decodes (decodes) the received image data. D
The MAC 10 is for transferring image data stored in the image memory 8 to the CODEC 9 and is started by the CPU 1.

The printer image processing circuit 11 performs a smoothing process together with a resolution conversion on the input pixel data and supplies it to a printer 17. Matching pattern R
The AM 12 stores a plurality of patterns of data for comparison with the original image data and matching. The register 13 stores setting data for determining whether the matching result of each pixel between the original image data for performing the smoothing and the matching pattern is valid or invalid. The smoothed image data memory 14 stores the output smoothed image data after the matching process. The matching pattern RAM 12, the register 13, and the smoothing image data memory 14 will be further described later.

The DMAC 16 transfers the image data decoded into the bit image by the CODEC 9 to the printer image processing circuit 11 and is started by the CPU 1. The printer 17 is a printer image processing circuit 1
The image data supplied from 1 is printed on recording paper.

FIG. 2 is a block diagram showing the configuration of the printer image processing circuit 11. Printer image processing circuit 11
Has a matching pattern RAM 12, a register 13 for storing a valid / invalid matrix, an address counter 15a for a line memory 15, a comparator 18, and an image data memory 14.

In the printer image processing circuit 11, when pixel data of an image to be subjected to smoothing processing is fetched into the line memory 15, the pixel data designated by the address counter 15a is read out, and the matching pattern RA is read.
The matching pattern is read from M12, and the valid / invalid data for each pixel is also input from the register 13 to the comparator 18. The original pixel data is compared with the matching pattern and valid / invalid data by the comparator 18. When the original pixel data and the matching pattern match in all the valid pixels, the matching data is output as data that identifies the matched pattern. The image data memory 14 stores the image data subjected to resolution conversion and smoothing corresponding to the matched pattern, and outputs the image data after smoothing to the printer 17.

FIG. 3 shows the comparator (comparison circuit) shown in FIG.
18 shows the configuration of the logic circuit 18 more specifically. Since FIG. 3 is equivalent to one pattern, usually there are a plurality of such circuits. FIG. 4 shows image data input to the comparator 18. FIG. 4A shows pixel data in three rows and three columns in the original image data, and shows a central target pixel and surrounding pixel data A, B,... FIG. 4B shows a matching pattern of 3 rows and 3 columns.
FIG. 4C also shows a valid / invalid matrix of 3 rows and 3 columns. Here, 0 = invalid and 1 = valid.

The comparator 18 has eight XOs here.
R circuit (Exclusive OR circuit: However, output is negated)
, 21h, NOT circuit 22a,
, 22h, eight OR circuits (OR circuits) 23a, 23b, ..., 23h, and one AN
And a D circuit (logical product circuit). XOR circuit 21
The pixel A of the original image data and the pixel a of the matching pattern are input to the input of a, and the input of the XOR circuit 21b is
The pixel B of the original image data and the pixel b of the matching pattern are input, and similarly, XOR circuits 21c,.
The inputs of h include pixels C and c,..., pixels H and h, respectively.
Is entered.

The input of the OR circuit 23a has an XOR
The output of the circuit 21a and the pixel Sa of the valid / invalid matrix inverted by the NOT circuit 22a are input, and the OR circuit 2
3b, the output of the XOR circuit 21b and the pixel Sb of the valid / invalid matrix inverted by the NOT circuit 22b
, And similarly the OR circuits 23c,..., 23h
Are the output of the XOR circuit 21c and the NOT, respectively.
Pixel Sc inverted by circuit 22c,..., XOR circuit 2
The output of 1h and the pixel Sh inverted by the NOT circuit 23h are input. Also, OR circuits 23a, 23b,...
, 23h are applied to the input of the AND circuit 24.

In the circuit of this embodiment, assuming that the data shown in FIG. 5 are assumed as specific examples of the original image data, the matching pattern, and the valid / invalid matrix (note that the resolution conversion is assumed to be 200 dpi → 400 dpi). And pixel a both match at “1”,
The pixel Sa of the valid / invalid matrix is set to "0" and invalid. Therefore, the input of the XOR circuit 21a is "1", the logic is "1", the logic is identical, and the output is "1". However, the input of the OR circuit 23a is NO when the pixel Sa = "0" is NO.
Since it is inverted by the T circuit and is "1", the OR circuit 23a
Is "1" regardless of the output of the XOR circuit 21a, and the output "1" is applied to the input of the AND circuit 24. OR of other invalid signals Sc, Sf, Sh inverted by NOT circuits 22c, 22f, 22h
The circuits 23c, 23f, and 23h also output "1", and this is input to the AND circuit 24.

On the other hand, since the pixels Sb, Sd, Se, Sg are "1", that is, valid, the NOT circuits 22b, 22
"0" is inverted by d, 22e, and 22g and the OR circuit 23
b, 23d, 23e, and 23g, each of which is "1" like pixels D and d, pixels E and e, and pixels G and g.
Or "0", the OR circuits 23d, 23d
The outputs of e and 23g become "1", and "1" is inputted to the input of the AND circuit 24. On the other hand, pixel B is “1”
On the other hand, the pixel b is “0” and the XOR circuit 21
b becomes “0”, one input of the OR circuit 23b becomes “0”, the pixel Sb becomes “1” and the NOT circuit 2
It is inverted at 2b to be "0", and the output of the OR circuit 23b becomes "0". Therefore, "0" is input to the AND circuit 24.
Is input, in this case, the original image data and the matching pattern do not match.

In FIG. 5, if the pixel B of the original image data is "0", the output of the OR circuit 21b becomes "1",
Therefore, the output of the OR circuit 23b also becomes "1", which is added to the input of the AND circuit 24. Therefore, the inputs of the AND circuit 24 all become "1", and it can be confirmed that the original image data and the matching pattern completely match. In this case, b = “0”, d = “1”, e = “1”, g =
“1” is output as data for identifying a matched parameter, and image data for four pixels, which has been smoothed based on this and subjected to resolution conversion, is output from the memory 14.

In some cases, a match occurs for a plurality of matching patterns. In such a case, priorities are assigned to the matching patterns, and the matching pattern having the highest priority is assigned to four pixels whose resolution has been converted. The image data may be output from the memory 14.

In the above embodiment, the matching pattern and the like have been described as a 3 × 3 matrix. However, the present invention is not limited to this, and is applicable to a matrix of another number of matrices such as a 5 × 5 matrix. it can.

[0025]

According to the present invention, it is possible to set whether or not to perform comparison for pixels in a pattern to be matched, so that a matrix can be set in accordance with an image, and processing in accordance with an image can be performed. It can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a facsimile apparatus with a multifunction function according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a functional configuration of a printer image processing unit of the facsimile apparatus with a multifunction according to the embodiment.

FIG. 3 is a block diagram illustrating a logical circuit configuration of a comparator of the printer image processing unit.

FIG. 4 is a diagram illustrating original image data, a matching pattern, and a valid / invalid matrix in the printer image processing unit.

FIG. 5 shows original image data, matching patterns and valid /
FIG. 7 is a diagram illustrating an example of data of each pixel of an invalid matrix.

[Explanation of symbols]

 Reference Signs List 11 Printer image processing circuit 12 Matching pattern RAM 13 Register for valid / invalid matrix 14 Image data memory after smoothing 15 Line memory 18 Comparator

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2C062 AA24 AA37 5B057 AA11 CA02 CA06 CA12 CA16 CB02 CB06 CB12 CB16 CC01 CE05 CE06 CH07 CH08 5C077 LL19 MP04 PP02 PP20 PP48 PP55 PP68 PQ12 PQ23 RR19 SS02 TT02

Claims (3)

[Claims] An image processing circuit that performs smoothing processing on image data by comparing each pixel data of an image with pixel data of a matching pattern, and sets whether or not to perform comparison for pixels in the pattern to be matched. Image processing circuit comprising: 2. A first memory for storing a matching pattern, a comparison circuit for comparing pixel data of an image with the matching pattern stored in the first memory, and a matching result based on a comparison result of the comparison circuit. An image processing circuit, comprising: a second memory for outputting pixel data based on the second memory; and a third memory for setting validity / invalidity of each pixel to be compared by the comparison circuit. 3. The comparison circuit calculates an exclusive OR of each pixel of pixel data of an image and data of each pixel stored in the first memory. 3. The image processing circuit according to claim 2, wherein the logical product of the two is used to determine the matching of the pattern.