JP2002217858A - Amplitude correcting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an amplitude correcting device where the amplitude fluctuations of a received signal are corrected and are made to converge to a prescribed value in an OFDM reception device having the phase error correcting circuit of at least one stage. SOLUTION: An amplitude correcting device 10 is installed between a selector 6a and a phase error-detecting circuit 6b, in the primary phase error correcting part 6 of the OFDM reception device. The amplitude correcting device 10 is constituted of a received power calculating part 11, an amplitude correction coefficient generating part 12 and an amplitude correcting part 13. The received power calculating part 11 calculates the power level of the received signal from the output of the selector 6a and calculates the received power level signal. The amplitude correction coefficient generating part 12 outputs amplitude correction coefficients, corresponding to the power level of the received signal, in response to the received power level signal. The amplitude correcting part 13 multiples the reception signal by the amplitude correction coefficient, corrects the amplitude and outputs a signal, whose amplitude corrected to a prescribed value, to a phase error correction signal generating circuit 6c.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplitude correction device suitable for a wireless digital communication system, and more particularly to an OFDM (Orthogonal Frequency Division Multiplex) having at least one stage error correction device.
ing) The present invention relates to a device suitable for amplitude correction of a received signal in a receiving device.

[0002]

2. Description of the Related Art FIG. 5 shows an example of an OFDM receiver.
In the figure, 1 is a receiving antenna, 2 is a down converter, 3 is a quadrature demodulator, 4 is an A / D converter, 5 is a frequency error correction unit, 6 is a primary phase error correction unit, and 7 is a secondary phase error correction. Reference numeral 8 denotes an FFT operation circuit.

The OFDM signal received by the receiving antenna 1 is converted into an IF signal by a down converter 2, and a baseband signal of I and Q components is demodulated from the IF signal by a quadrature demodulator 3. This baseband signal is converted into a digital signal by the A / D converter 4 and input to the frequency error correction unit 5. For example, in the case of the OFDM signal format shown in FIG.
The selector 5a identifies the A and B field components of the preamble part, the C field and the data part (payload part) of the preamble part of the digitally converted OFDM signal. The A and B field components of the preamble portion are input to a timing detection circuit 5b, which detects an FFT timing signal. The frequency error detection circuit 5c detects a frequency error from the A and B field components. The FFT timing signal is input to the FFT operation circuit 8, and the frequency error correction signal generation circuit 5d generates a frequency error correction signal based on the frequency error. By performing complex multiplication on the field component and the data part,
Correct the frequency error.

[0004] The FFT operation circuit 8 performs an FFT operation on the data portion from the frequency error correction unit 5 based on the FFT timing signal and outputs the result to the primary phase error correction unit 6. The primary phase error correction unit 6 corrects the phase error caused by the timing shift of the FFT operation. In the case of FIG. 6, for example, the selector 6a outputs the C field component of the preamble unit from the output of the FFT operation circuit 8 The data portion is extracted, and the phase error detection circuit 6b detects a phase error based on the C field component, and the phase error correction signal generation circuit 6c generates a phase error correction signal based on the phase error. The phase error correction signal is subjected to complex multiplication by the complex multiplication circuit 6d to the data section to correct the phase error.

[0005] The secondary phase error correction unit 7 is provided to correct a phase error based on a relative error between the transmission clock and the reception clock. The secondary phase error correction unit 7 corrects a phase error remaining due to a relative error between the transmission side clock and the reception side clock. The selector 7a converts the output of the primary phase error correction unit 6 into a data part. The I and Q components including the pilot signal are separated. The above components are input to a pilot signal extraction section 7b, whereby pilot signals between symbols in the data section are extracted. Since the error of the pilot signal from the theoretical value has a phase corresponding to the phase error remaining due to the relative error between the clocks, the conjugate signal of the pilot signal is converted by the phase error correction signal generation circuit 7c. Generated as a phase error correction signal. This conjugate signal is subjected to complex multiplication of the pilot signal in the data section by the complex multiplication circuit 7d to correct the phase error.

For details of the above-mentioned OFDM receiver, refer to Japanese Patent Application No.
000-400943. Further, as an example of an OFDM apparatus having a function different from the above-described example as the secondary phase error correction apparatus, for example, Japanese Patent Application No.
000-70186.

As described above, in the OFDM receiving apparatus, to correct the phase error due to various causes, the primary,
A phase error correction circuit of the second order or the like is used. As a method of correcting the phase error, as described above, the reception OFDM
In order to cancel the phase fluctuation of the signal, a method of giving an opposite phase rotation is adopted. Therefore, for example, a method such as a conjugate operation is used as a simple method. In the conjugate operation, a correction signal can be obtained by a simple operation of code conversion of a real part or an imaginary part of a received OFDM signal, and thus is often used for the purpose of reducing the circuit scale and the operation time.

[0008]

At this time, the problem is that the correction signal only needs to give the received signal a phase rotation only, and it is desired that the amplitude of the correction signal does not give an error. Since the correction signal is generated from the received signal, if the amplitude of the received signal fluctuates, the amplitude fluctuation remains as it is and affects the signal after the phase correction. For example, if the amplitude of the received input signal is １ ／, when the signal passes through the one-stage phase error correction device, the amplitude of the signal corrected by the complex multiplication becomes １ ／. If two types of correction are performed, the amplitude becomes 1/16 times. In order to cope with such amplitude fluctuation (attenuation), an operation such as division is required when generating a correction signal. However, if this operation is performed as it is, an enormous number of significant digits and an operation amount are required. The circuit scale or calculation time must be increased, which is not practical.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an amplitude correction device capable of holding the amplitude of an error correction signal at a constant value in a receiving device in a wireless digital communication system such as an OFDM receiving device.

[0010]

In order to achieve the above object, an amplitude correction apparatus according to the present invention provides a receiving apparatus in a wireless digital communication system, which calculates a power level of a received signal and outputs a received power level signal. Calculating means, amplitude correction coefficient generating means for outputting a predetermined amplitude correction coefficient corresponding to the power level of the received signal in response to the received power level signal, and multiplying the received signal by the amplitude correction coefficient to calculate the received signal. The gist of the present invention is to provide an amplitude correcting means for correcting the amplitude.

In the apparatus of the present invention, the amplitude correction coefficient generating means may be configured so that the amplitude correction coefficient is set and held in an amplitude correction table in advance corresponding to the power level of the received signal. Good.

Further, in the apparatus according to the present invention, the amplitude correction means includes: a bit shift means for receiving a signal; a control means for extracting an output signal having a shift amount corresponding to the amplitude correction coefficient from the bit shift means; And an adding unit for adding the output signal.

Further, in the apparatus according to the present invention, the receiving apparatus is an OFDM receiving apparatus having a frequency correcting apparatus and at least one phase correcting apparatus.
An amplitude correction circuit including the reception power calculation unit, the amplitude correction coefficient generation unit, and the amplitude correction unit may be provided.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The amplitude correction apparatus of the present invention can maintain the amplitude of an error correction signal at a constant level. Therefore, the error correction is performed several times on the receiving apparatus by complex multiplication of the error correction signal and the received signal. However, the amplitude of the signal at the time of reception can be kept constant.

In principle, this amplitude correction can be realized by finding the inverse characteristic of the received signal and multiplying the amplitude of the original signal by the numerical value of the inverse characteristic. However, according to this principle, since it is necessary to incorporate a multiplication and division circuit as an amplitude correction circuit, problems such as an increase in circuit scale or an increase in operation time occur.

Therefore, in the amplitude correction apparatus of the present invention, as described above, the power level of the received signal is calculated, and the amplitude of the received signal is corrected by correcting the amplitude of the received signal with an amplitude correction coefficient corresponding to the power level. Correct so that it becomes a constant value.

FIG. 1 shows an amplitude correction apparatus 10 according to the present invention, and FIG.
A first-order phase error correction section 6 of the OFDM receiver as shown in FIG.
1 shows an embodiment incorporated therein. In the figure, the amplitude of the signal (field portion, data portion) extracted by the selector 6a is corrected, but the pilot signal of the C field portion and the data portion is originally the same unless the amplitude of each subcarrier is equal. Instead, amplitude correction is also performed for each subcarrier.

FIG. 2 shows the basic configuration of the amplitude correction device of the present invention. In FIG. 2, reference numeral 11 denotes a reception power calculation unit, 12 denotes an amplitude correction coefficient generation unit, and 13 denotes an amplitude correction unit. The reception power calculator 11 calculates the power level of the reception signal from the output of the selector 6a, and calculates the reception power level signal.
The amplitude correction coefficient generator 12 outputs an amplitude correction coefficient corresponding to the power level of the received signal in response to the received power level signal. The amplitude correction unit 13 corrects the amplitude by multiplying the received signal by the above-described amplitude correction coefficient by the simple method of the present invention, and outputs a signal whose amplitude has been corrected to a constant value to the phase error correction signal generation circuit 6c. I do.

FIG. 3 is a conceptual diagram of a specific configuration for executing the operation of the amplitude correction device 10. In FIG.
a is a power calculation circuit, 11b is a sensor, and constitutes the reception power calculation unit 11. Reference numeral 12a denotes a memory in which a table of amplitude correction coefficients is stored, which constitutes the amplitude correction coefficient generator 12. 13a is a shift register, 13b is a selector, 13
c is an adder, 13d is a control circuit, and constitutes the amplitude correction unit 13.

The amplitude correction unit 13 performs simple multiplication for amplitude correction as described above. In order to simplify the multiplication, a configuration is adopted in which the multiplication can be realized only by bit shift and addition. , And the amplitude correction coefficient is set by a combination of powers of two. That is, the output signal of the selector 6a is, for example, quadrupled by the shift register 13a,
Generate, hold, multiply, multiply by 1, multiply by 1/2, and multiply by 1/4. These signals can be obtained only by bit-shifting the output signals, so that the amount of calculation is small as compared with a general multiplication method.

On the other hand, the power calculation circuit 11a calculates the sum of squares of the I and Q components of the output signal, and the sensor 11b senses the power level of the received signal from the sum of squares to calculate the received power level signal. At this time, the digitization of the power level is performed in accordance with the sensing accuracy of the sensor 11b. For example, the lower bits are discarded, leaving the upper b bits of the power level (sum of squares). The sensor 11b searches a table in the memory 12a according to the value of the power level of the received power level signal, extracts an amplitude correction coefficient corresponding to the value of the power level, and provides it to the control circuit 13d.

The control circuit 13d turns on the corresponding switches SW1 to SW5 of the selector 13b in accordance with the amplitude correction coefficient,
Turn off. For example, if the amplitude correction coefficient is 1.25,
The switches SW3 and SW5 are turned on, and the others are turned off.
When the selected signals are added by the adder 13c, a signal whose amplitude is corrected to be substantially constant is output. Sensor 11b
The convergence is enhanced as the sensing accuracy of is better.

The amplitude correction table 12a is obtained in advance by setting an amplitude correction coefficient corresponding to the power level by an experiment. Also, the table can be automatically created if the bit length of the correction signal and the sensitivity of the sensor unit 11b are determined. In order to facilitate the multiplication as the amplitude correction operation, the amplitude correction coefficient is set to a numerical value that can be realized only by bit shift and addition.

The target vector of the signal (I, Q components) after the amplitude correction is ^2a (a is the number of bits of the input signal, and the actual maximum value is ^2a- 1 due to the relationship of the significant digits). After amplitude correction, this signal and amplitude do not cause overflow,
The amplitude correction coefficient is determined so as to be as close as possible to the target value. However, if all bits of the preamble or pilot signal of the OFDM signal to be an input signal are used as effective digits, the capacity of the table, the operation speed, the operation capacity, and the like increase, so that the effective digits of the input signal are limited to some extent.

FIG. 4 shows the effect of generating an amplitude correction signal according to the present invention. In the figure, S1 represents an input signal, S2 represents a corrected output signal, and S3 represents an arc having a radius corresponding to a target vector length of the input signal when there is no amplitude fluctuation. From the figure, it can be seen that the signal after the amplitude correction is close to the target vector length, and has a small error and high convergence.

The present invention is not limited to an OFDM receiver,
The present invention can be applied to a receiving device in another wireless digital communication system.

[0027]

As described above, according to the present invention, the amplitude correction of an input digital signal can be easily performed without requiring a huge number of significant digits and a large amount of calculation, and the corrected amplitude value has high convergence. Shows that the circuit scale or the operation time of the entire receiver can be greatly reduced.
This is particularly effective when the receiving apparatus uses several stages of phase error correction units.

[Brief description of the drawings]

FIG. 1 shows an OFDM receiver as an amplitude correction device according to the present invention.
FIG. 7 is a block diagram showing an embodiment incorporated in a next phase correction unit.

FIG. 2 is a block diagram illustrating a basic configuration of an amplitude correction device according to the present invention.

FIG. 3 is a conceptual diagram of a specific configuration for executing an operation of the amplitude correction device.

FIG. 4 is a diagram illustrating the effect of amplitude correction of the present invention.

FIG. 5 is a block diagram illustrating an example of an OFDM receiver.

FIG. 6 is a diagram showing a format of an OFDM signal.

[Explanation of symbols]

 Reference Signs List 10 amplitude correction device 11 reception power calculation unit 12 amplitude correction coefficient generation unit 13 amplitude correction unit 11a power calculation circuit 11b sensor 12a amplitude correction coefficient table memory 13a shift register 13b selection unit 13c adder 13d control circuit

Continued on the front page (72) Inventor Roh Feng 6-27-8 Jingumae, Shibuya-ku, Tokyo Inside Kyocera DDI Future Communication Research Laboratories (72) Inventor Toru Sunaga 6-27-8 Jingumae, Shibuya-ku, Tokyo In the Kyocera DDI Future Communication Research Laboratory (72) Hiromasa Takada 6-27-8 Jingumae, Shibuya-ku, Tokyo Inside the Kyocera DDI Future Communication Research Laboratories (72) Toshiyuki Maeyama 6-27 Jingumae, Shibuya-ku, Tokyo -8 F-term in Kyocera DDI Future Communication Research Laboratories (reference) 5K022 DD01 DD13 DD19 DD33 DD34

Claims (4)

[Claims] 1. A receiving apparatus in a wireless digital communication system, comprising: a receiving power calculating means for calculating a power level of a received signal and outputting a received power level signal; Amplitude correction coefficient generating means for outputting a corresponding predetermined amplitude correction coefficient; and amplitude correction means for multiplying the received signal by the amplitude correction coefficient to correct the amplitude of the received signal. apparatus. 2. The amplitude correction coefficient generating means according to claim 1, wherein said amplitude correction coefficient is set in advance in an amplitude correction table corresponding to a power level of a received signal and held. Amplitude correction device. 3. The amplitude correction means adds a received signal bit shift means, a control means for extracting an output signal of a shift amount corresponding to the amplitude correction coefficient from the bit shift means, and the extracted output signal. 2. The amplitude correction device according to claim 1, further comprising an adding unit. 4. The receiving apparatus is an OFDM receiving apparatus having a frequency correcting apparatus and at least one phase correcting apparatus, wherein the received power calculating means, the amplitude correcting coefficient generating means, and the amplitude correcting means are provided in the phase correcting apparatus. The amplitude correction device according to claim 1, further comprising an amplitude correction circuit comprising: