JP2006157589A - Method for correcting received sample clock timing and digital signal receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for correcting received sample clock timing by which proper correction of the received sample clock timing can be executed by accurately measuring an error between the received sample clock timing and ideal received sample clock timing, and to provide a digital signal receiver. <P>SOLUTION: An A/D converter 2 executes digital conversion to an in-phase signal (an I signal) and an orthogonal signal (a Q signal) output from an orthogonal detector 1. A sample clock timing error measuring part 4 calculates the error direction and the error amount of a sample point by comparing the received IQ signals when ideally receiving known transmission preamble data with the IQ signals output by the A/D converter 2, and sets a phase correction value for correcting the calculated error to a phase shifter 5. The phase shifter 5 corrects timing of a clock from a clock generator on the basis of the phase correction value. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method and apparatus for measuring an error in sample clock timing from an A / D converted signal and correcting the sample clock timing to an appropriate sample clock timing.

  Conventionally, for example, a configuration disclosed in FIG. 1 of Patent Document 1 is known as A / D conversion sample clock timing correction of a received signal.

According to this configuration, the sample clock generation circuit generates the sample clock timing t0, the sample clock timing ta advanced by time τ, and the clock tb delayed by time τ, and samples data at each sample clock timing. The respective square sums Ra ² and Rb ² are calculated and compared. If Ra ² > Rb ² (Ra ² <Rb ² ), it is determined that the sample clock timing is advanced (delayed), and the sample clock timing is delayed (advanced) by a fixed time α. This repetition is performed, = sample clock timing if the Rb ² may be determined to be correct timing.
JP 2000-69100 A

  However, the conventional correction method described above can determine the direction of deviation in which the sample clock timing is early or late, but there is a problem in that an error in the accurate sample clock timing cannot be measured.

  In addition, since a comparison clock is required in addition to the sample clock, switching control frequently occurs, so there is a problem that the sample data for comparison affects the main signal system, which affects the main signal system. In order to avoid this, there is a problem in that an independent A / D circuit or the like for comparison sample data is required as shown in FIG.

  The present invention has been made in view of the above-described conventional circumstances, and is capable of accurately measuring an error between a reception sample clock timing and an ideal reception sample clock timing and capable of appropriately correcting the reception sample clock timing. An object of the present invention is to provide a sample clock timing correction method and a digital signal receiver.

  The reception sample clock timing correction method of the present invention includes a value of first sample data that is one of sample data when received in an ideal state, and the ideal state of sample data that is actually A / D converted. Calculating a first difference that is a difference from a value of the second sample corresponding to the first sampling data, and a timing error occurring with respect to the ideal state based on the first difference Determining the direction, based on a ratio of the first difference and a second difference that is a difference between the first sample data and the value of the preceding or succeeding data to the ideal state. A step of calculating an error amount of the generated timing, a step of calculating a phase correction value from the error direction and the error amount, and a step based on the phase correction value from the generated reference clock. And a step of shifting.

  By this method, it is possible to accurately measure the error between the reception sample clock timing and the ideal reception sample clock timing and correct the reception sample clock timing appropriately.

  Further, in the reception sample clock timing correction method of the present invention, the first sample data is different from a value of the first sample data and a sign of a value of the sample data before or after the first sample data, and the first sample data Among the points that satisfy the condition, the difference between the value of the point and the values of the front and rear sample data is the largest.

  By this method, since the difference between the first sample data and the values of the sample data before and after the first sample data is large, the error amount can be obtained more accurately.

  The digital signal receiver according to the present invention performs analog / digital conversion of received data at a predetermined sampling clock timing on an I signal, which is an in-phase signal obtained by quadrature detection of the received signal, and a Q signal, which is a quadrature component. / D converter, the value of the first sample data that is one of the sample data when received in the ideal state, and the first of the ideal state among the sample data output from the A / D converter Calculating a first difference, which is a difference from the value of the second sample corresponding to the sampling data, and determining an error direction of the timing generated with respect to the ideal state based on the first difference; , A tie generated for the ideal state based on a ratio between the first difference and a second difference which is a difference between the first sample data and the value of the preceding or succeeding data. Comprising seeking error amount of packaging, and the sample clock timing error measuring unit for calculating a phase correction value, a phase shifter for shifting the phase based on the generated reference clock to the phase correction value.

  With this configuration, it is possible to accurately measure the error between the reception sample clock timing and the ideal reception sample clock timing and correct the reception sample clock timing appropriately.

  According to the present invention, there is provided a reception sample clock timing correction method and a digital signal receiver capable of accurately measuring an error between a reception sample clock timing and an ideal reception sample clock timing and appropriately correcting the reception sample clock timing. can do.

  FIG. 1 is a block diagram showing a schematic configuration of a digital signal receiver according to an embodiment of the present invention.

  As shown in FIG. 1, the digital signal receiver according to the present embodiment converts, for example, an intermediate frequency band (hereinafter referred to as IF) received signal into an analog in-phase component signal and quadrature component signal (hereinafter referred to as I signal and Q signal). An orthogonal detector 1, an A / D converter 2 that digitally samples an analog IQ signal and converts it into digital IQ signal sample data, a baseband signal processing circuit 3 that performs demodulation processing from the digital IQ signal sample data, A sample clock timing error measurement unit 4 that obtains a sample clock timing error from IQ signal sample data, a phase shifter 5 that changes the phase of the sampling clock, and a clock oscillator 6 that generates the sampling clock are provided.

  First, the value of the oversampling point of the received symbol in the ideal state used for derivation of the sample clock timing error is derived by simulation calculation. Here, in order to simplify the explanation, a known symbol such as preamble data modulated by the BPSK (Binary Phase Shift Keying) method is used as an example, and explanation is made using the value of the I axis.

  FIG. 2 is a diagram showing an example of received sample points, and shows received sample points in an ideal state in which known symbols such as preamble data are oversampled four times. The symbol points are the sample points indicated by S0, S1, and S2, but among the received sample points, the sample point Sx is used for derivation of the sample error in this embodiment.

  This sample point Sx is different in sign of the value of the I axis of the front or rear sample point (that is, the central sample point lined up in the + to-direction or in the-to + direction), and such a point. Among them, the distance between the front and back samples is as large as possible.

  Assuming that the sample point immediately before Sx is Sy and the sample point immediately after Sx is Sz, values on the I axis of these Sy, Sx, and Sz are derived in advance by simulation calculation. An example is shown below.

Sy = 1.0017
Sx = 0.3396
Sz = −0.3497

  Next, the operation of the digital receiver according to the embodiment of the present invention will be described.

  When the reception IF signal is input to the digital receiver, the quadrature detector 1 performs quadrature detection and converts it to an analog IQ signal. The A / D converter 2 samples the analog IQ signal and converts it into digital IQ signal sample data. In this embodiment, the sampling is oversampling four times. The digital IQ signal is input to the baseband signal processing circuit 3, and the baseband signal processing circuit 3 performs demodulation processing and outputs a decoded signal. On the other hand, the digital IQ signal is input to the sample clock timing error measurement unit 4.

  Next, a reception sample clock timing correction method in the sample clock timing error measurement unit 4 will be described.

  For measurement of the sample clock timing error, among the sample points where the received signal is A / D converted by the A / D converter 2, Sa, which is an oversample point corresponding to Sx, is compared with Sx.

  If the values of Sa and Sx match, there is no error in sample timing.

  On the other hand, if Sx-Sa is negative, it can be seen that the sample clock timing is earlier than the appropriate timing, and further, it can be known how early the timing is from the ratio to Sy-Sx.

For example, if reception Sa = 0.47202,
Sx-Sa = 0.3966-0.47202 = 0.13242
Sy-Sx = 1.0017-0.3396 = 0.6621
0.13242 / 0.6621 = 0.2 (1)
Thus, it can be seen that the 1/5 sample clock timing is earlier, and that it is sufficient to delay the sample clock timing by 1/5 sample timing with respect to the phase shifter 5.

  Here, since Sx is selected to have a large difference from the values of the preceding and succeeding points Sy and Sz, the denominator in the above equation (1) becomes large, so a more accurate error amount can be obtained. It becomes.

  Similarly, accurate correction can be performed when the sample clock timing is later than the proper timing. In the present embodiment, the arrangement of Sy, Sx, and Sz is from the + direction to the-direction, but correction can be performed in the same way in the reverse case. In addition, it is expected that the influence of noise or the like can be reduced by performing averaging or the like using a plurality of sample points used for error derivation. The BPSK modulation method and the number of oversamples have been described as being four times, but the modulation method and the number of oversamples are arbitrary.

  The phase correction value obtained as described above is set in the phase shifter 5. In the phase shifter 5, the clock generated by the clock generator 6 is phase-shifted by the phase correction value and output, and supplied as a sample clock for the A / D converter 2.

  From the above, in this embodiment, it is not necessary to generate a clock other than the sample clock, the sample clock is not affected, and an independent A / D circuit for comparison and correction is not provided. Timing errors can be measured and sample clock timing can be accurately corrected.

  According to such an embodiment of the present invention, it is possible to appropriately correct the reception sample clock timing by accurately measuring the error between the reception sample clock timing and the ideal reception sample clock timing.

  Therefore, it is effective to prevent signal deterioration due to clock phase error between the transmitter and receiver without increasing the number of oversamples in the receiver, and to improve the reception performance. Also, it is not necessary to increase the number of oversamples more than necessary. Therefore, the present invention has an effect that it is not necessary to raise the operation clock of the circuit more than necessary, and is particularly useful for a digital transceiver that uses a multi-level modulation method such as 16QAM or 64QAM and requires accurate sample timing.

  The reception sample clock timing correction method and digital signal receiver according to the present invention have an effect of accurately measuring the error between the reception sample clock timing and the ideal reception sample clock timing and appropriately correcting the reception sample clock timing. However, it is useful for receivers of multilevel modulation schemes such as 16QAM and 64QAM.

1 is a block diagram showing a schematic configuration of a digital signal receiver according to an embodiment of the present invention. Diagram showing an example of received sample points

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Quadrature detector 2 A / D converter 3 Baseband signal processing circuit 4 Sample clock timing error measurement part 5 Phase shifter 6 Clock oscillator 7 Sample clock timing correction circuit

Claims (3)

The value of the first sample data, which is one of the sample data when received in the ideal state, and the second sample corresponding to the first sampling data in the ideal state among the sample data actually A / D converted Calculating a first difference that is a difference from the value of
Obtaining an error direction of timing occurring with respect to the ideal state based on the first difference;
Based on the ratio between the first difference and the second difference that is the difference between the first sample data and the previous or subsequent data, the timing of the occurrence of the ideal state Obtaining an error amount;
Calculating a phase correction value from the error direction and the error amount;
Shifting the phase based on the phase correction value from the generated reference clock; and a reception sample clock timing correction method. The reception sample clock timing correction method according to claim 1,
The first sample data has a value different from the value of the first sample data and the sign of the value of the sample data before or after the first sample data, and among the points satisfying the first condition, And a received sample clock timing correction method having the largest difference from the value of the subsequent sample data. An A / D converter that performs analog / digital conversion of received data at a predetermined sampling clock timing with respect to an I signal that is an in-phase signal obtained by quadrature detection of the received signal and a Q signal that is a quadrature component;
The value of the first sample data, which is one of the sample data when received in the ideal state, and the first sample data corresponding to the first sample data in the ideal state among the sample data output from the A / D converter. A first difference, which is a difference between two sample values, is calculated, and based on the first difference, an error direction of a timing occurring with respect to the ideal state is obtained, and the first difference is calculated. And an error amount of a timing generated with respect to the ideal state based on a ratio between the first sample data and a second difference that is a difference between values of the preceding data or the data before and after the first sample data. A sample clock timing error measuring unit for calculating a phase correction value;
A digital signal receiver comprising: a phase shifter that shifts a phase based on the phase correction value from a generated reference clock.

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