JP2002210192A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine in which a control state at power supply stoppage is surely restored when power supply is restarted. SOLUTION: In a processing to be executed when the power supply to this game machine is started, whether or not the data protective processing of a backup RAM area such as the addition of parity data is performed when the power supply of the previous time is stopped is confirmed. In the case that the power supply is stopped, the processing for protecting the data of the backup RAM area and the preservation processing of the execution address of a game control program are performed. In the case that the parity data are accurately preserved, a game state restoration processing is executed. In the game state restoration processing, the processing for restarting execution from the preserved execution address of the game control program is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gaming machine such as a pachinko gaming machine and a slot machine which allow a player to play a predetermined game.

2. Description of the Related Art As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a winning area such as a winning opening provided in the game area, a predetermined number of prize balls are obtained. Are paid out to players.
Further, a variable display device whose display state can be changed is provided, and when the display result of the variable display device becomes a predetermined specific display mode, a predetermined game value is provided to the player. is there.

[0002] The game value means that the state of the variable winning ball device provided in the game area of the gaming machine is in an advantageous state for a player who is likely to win a hit ball, or in an advantageous state for the player. For example, or a condition that facilitates the establishment of the prize ball payout condition.

[0003] In a pachinko gaming machine, when a display result of a variable display device for displaying a special symbol is a combination of a predetermined specific display mode, it is generally called a "big hit". When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the state shifts to a big hit game state in which a hit ball is easy to win. In each open period, a predetermined number (for example, 10
) Will be closed when there is a prize in the special winning opening.
The number of opening of the special winning opening is a predetermined number (for example, 16
Round). An opening time (for example, 29.5 seconds) is determined for each opening, and if the opening time elapses even if the number of winnings does not reach a predetermined number, the winning opening is closed. Further, at the time when the special winning opening is closed, predetermined conditions (for example, winning in the V zone provided in the special winning opening)
Is not established, the big hit gaming state ends.

In a gaming machine, a payout control means for controlling a prize ball payout in accordance with a winning is mounted on a payout control board different from a game control board on which a game control means for controlling the progress of a game is mounted. The game progress is controlled by the game control means mounted on the game control board,
The number of prize balls based on winning is determined by the game control means and transmitted to the payout control board. On the other hand, lending game media has nothing to do with the progress of the game, so in general,
It is controlled by the payout control means without going through the game control means. Hereinafter, the game control means and other control means for controlling various electric components provided in the gaming machine are referred to as electric component control means, and the board on which the electric component control means is mounted is referred to as an electric component control board. is there.

[0005]

Generally, each electric component control means includes a microcomputer.
That is, a program is stored in a ROM or the like, and data that temporarily occurs in control or data that changes as the control progresses is stored in the RAM. Then, when a power supply stop state due to a power failure or the like occurs in the gaming machine, data in the RAM is lost. For example, if a power supply stop state occurs during a jackpot game and data for control is lost, the player will not be able to enjoy the benefits based on the occurrence of the jackpot.

[0006] In order not to give such a disadvantage to the player, the game control is interrupted in response to a predetermined signal generated with a decrease in the power supply voltage value, and the game state at that time is changed to the game machine. There is a gaming machine that saves power in a power-backed-up RAM (backup storage means) even when power supply is stopped, and controls to wait until power supply is completely stopped. Such a gaming machine, when the power supply is resumed in a state where the gaming state is stored in the backup storage means,
Since the game is restarted based on the saved game state, it is possible to prevent the player from being disadvantaged. Then, when the power supply is restarted, the game can be restarted from the state at the time when the power supply was stopped, based on the stored data. However, in such a gaming machine, if the data in the backup storage means has changed for some reason in the power supply stopped state, the state cannot be restored to the state when the power supply was stopped, and the wrong game control There is a problem that the game may be restarted based on the state.

[0007] Even if the electric component control means restores the control state based on the held data, it may not be possible to completely restore the control state before the power supply is stopped. In that case, the game may be restarted from a gaming state that is disadvantageous to the player as compared to the gaming state before the power supply is stopped.

[0008] The present invention is to solve the above-mentioned problem, and appropriately sets the operation state of the electric component when the power supply to the game machine is stopped to save the appropriate game state. It is another object of the present invention to provide a gaming machine which can perform a power supply operation and can surely return to a control state when the power supply is stopped when the power supply is restarted.

[0009]

A gaming machine according to the present invention comprises:
A gaming machine in which a player can perform a predetermined game, wherein the electronic component control means controls an electrical component provided in the gaming machine by executing a control program, and varies according to the progress of the game. Fluctuation data storage means for storing the fluctuation data, and the stored contents are retained for a predetermined period even if the power supply to the gaming machine is stopped,
In the power supply stop processing executed when the power supply is stopped, data saving processing for storing data necessary for restoring the control state in the variable data storage means and checking based on the storage contents of the variable data storage means Generating data and storing the generated check data in the variable data storage means. The data stored in the variable data storage means in the data saving processing is at least a program address associated with the address of the control program that has been executed. Including the data, when the power supply is restored, the electric component control means determines whether the storage content stored in the variable data storage means is valid based on the check data stored in the variable data storage means. However, on the condition that the storage contents stored in the variation data storage means are determined to be valid. Performs state restoring processing to restore the control state based on the stored contents which is stored in the dynamic data storing means, and performs the process of resuming the execution of the control program based on the program address data.

[0010] The electrical component control means may be configured to perform an initialization process for initializing the control state when it is determined that the stored content stored in the variation data storage means is not valid.

The check data is, for example, data calculated by performing a predetermined logical operation based on the contents of at least a part of the variation data storage means.

[0012] The variable data storage means may include a work area in which a storage area is defined for each data, and the check data may be generated based on the contents of the work area.

It is preferable that the check data generated in the process at the time of power supply stop is stored in a work area.

The variable data storage means includes a stack area for saving data in accordance with satisfaction of a predetermined condition;
The program address data may be configured to be stored in a stack area.

The contents stored in the variable data storage means include stack address data indicating the address of the stack area, and when performing a state restoration process, the program address data is restored by restoring the stack address data. It may be configured as follows.

It is preferable that the contents of the register be saved in the stack area in the data saving processing.

The state restoring process may be configured to include a process of restoring the contents of the register.

The storage contents of the variable data storage means include interrupt state information indicating one of an interrupt inhibited state for inhibiting execution of a predetermined interrupt process and an interrupt permitted state for permitting execution. The state restoration process may be configured to include a restoration process of an interrupt prohibition state or an interruption permission state based on the interruption state information.

Power supply monitoring means for monitoring a state of a predetermined power supply and outputting a detection signal when the output of the power supply is reduced and a detection condition is satisfied, wherein the electric component control means receives the detection signal from the power supply monitoring means The power supply stop processing may be configured to be executed accordingly.

The electric part control means executes electric part control processing for controlling electric parts provided in the game machine based on the occurrence of a timer interrupt that occurs periodically, and controls electric part control. The processing for updating the counter used for the control of the game may be performed in the remaining time of the processing, and the interrupt may be set to be prohibited during the processing for updating the counter in the remaining time.

[0021]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. FIG. 1 is a front view of the pachinko gaming machine as viewed from the front, and FIG. 2 is a front view of the front of the gaming board with the glass door frame removed. In the following embodiments, a pachinko gaming machine will be described as an example, but the gaming machine according to the present invention is not limited to a pachinko gaming machine, and may be, for example, a slot machine. Further, the present invention can be applied to an image-type gaming machine.

The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be openable and closable. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape and provided in a game frame so as to be openable and closable. The game frame includes a front frame (not shown) installed to be freely openable and closable with respect to the outer frame, a mechanism plate to which mechanical components and the like are attached, and various components attached to them (excluding a game board described later). And a structure including:

As shown in FIG. 1, the pachinko gaming machine 1
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray (upper tray) 3. A surplus ball receiving tray 4 for storing game balls that cannot be accommodated in the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing a hitting ball are provided below the hitting ball supply tray 3. Glass door frame 2
A game board 6 is detachably attached to the back of the game board. The game board 6 is a structure that includes a plate-like body constituting the board and various components attached to the plate-like body. A game area 7 is formed on the front of the game board 6.

In the vicinity of the center of the game area 7, there is provided a variable display device (special symbol display device) 9 including a plurality of variable display portions each of which variably displays a symbol as identification information. The variable display device 9 includes, for example, “left”, “middle”,
There are three “right” variable display sections (symbol display areas).
Below the variable display device 9, a start winning port 14 is provided. The winning ball that has entered the start winning port 14 is guided to the back of the game board 6 and detected by the starting port switch 14a. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. Variable winning ball device 1
5 is opened by a solenoid 16.

Below the variable winning ball device 15, there is provided an opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state). Opening / closing plate 20
Is a means for opening and closing the special winning opening. One of the winning balls guided to the back of the game board 6 from the opening / closing plate 20 (V winning area)
The winning ball entered is detected by the V winning switch 22, and the winning ball from the opening / closing plate 20 is detected by the count switch 23. On the back of the game board 6, there is also provided a solenoid 21A for switching the route in the special winning opening. In addition, a start storage display 18 having four displays for displaying the number of effective winning balls in the start winning opening 14, that is, the number of start memories, is provided below the variable display device 9. In this example, the start storage display unit 18 increases the number of lit display units by one each time there is a valid start prize, with four as an upper limit. Then, each time the variable display of the variable display device 9 is started, the number of the lit display unit is reduced by one.

When a game ball wins at the gate 32, variable display of the display of the ordinary symbol display 10 by the 7-segment LED is started. When the stop symbol on the ordinary symbol display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined number of times and for a predetermined time. In the vicinity of the ordinary symbol display 10, an ordinary symbol start storage display 41 having four displays for displaying the number of winning balls entering the gate 32 is provided. In this example, each time there is a prize in the gate 32, the normal symbol start storage display 41 increases the number of lit display units one by one, with the upper limit being four. Then, each time the opening control of the variable winning ball device 15 is performed, the number of the lit display units is reduced by one.

The game board 6 has a plurality of winning ports 24, 29,
30 and 33 are provided, and the winning holes 24, 29 and 3 for the game balls are provided.
The prizes for 0 and 33 are determined by the prize opening switches 24a and 24a, respectively.
29a, 30a and 33a. At the left and right sides of the game area 7, there are provided decorative lamps 25 which are displayed blinking during the game, and at the lower part there is an out port 26 for absorbing hit balls which have not won. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides outside the game area 7. A ceiling lamp 28 is provided on the outer periphery of the game area 7.
a, a left frame lamp 28b and a right frame lamp 28c. Further, decorative LEDs are installed around each structure (such as a special winning opening) in the game area 7.

In this example, the prize ball lamp 51 is turned on when there is a remaining prize ball near the left frame lamp 28b.
Is provided, and near the top frame lamp 28a, a ball-out lamp 52 that is turned on when the supply ball has run out is provided.
Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming machine 1 and that allows a ball to be lent by inserting a prepaid card.

The card unit 50 has a usable indicator lamp 151 for indicating whether or not the card is usable. If there is a fraction (a number less than 100 yen) in the balance information recorded in the card, the fraction is displayed. Fraction display switch 1 for displaying on a frequency display LED provided near hit ball supply tray 3
52, a connecting stand direction indicator 15 indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to
3. Card insertion indicator 154 indicating that a card has been inserted into card unit 50, card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back of card insertion slot 155 A card unit lock 156 is provided to release the card unit 50 when checking the mechanism of the writer.

The game ball fired from the hitting ball launching device enters the game area 7 through the hitting ball rail, and then descends from the game area 7. When a hit ball enters the starting winning opening 14 and is detected by the starting opening switch 14a, the special display starts variable display (variation) on the variable display device 9 if the variable display of the symbol can be started. If it is not in a state where the variable display of the symbol can be started, the number of start storages is increased by one.

The variable display of the special symbol on the variable display device 9 stops when a certain time has elapsed. If the combination of the special symbols at the time of stopping is a combination of the big hit symbols, the game shifts to the big hit game state. That is, the opening and closing plate 20
Is released until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. Then, when a hit ball wins in the V winning area while the opening and closing plate 20 is open and is detected by the V winning switch 22, a continuation right is generated and the opening and closing plate 20 is opened again. Generation of the continuation right is permitted a predetermined number of times (for example, 15 rounds).

If the combination of special symbols in the variable display device 9 at the time of stoppage is a combination of big hit symbols with a probability variation, the probability of the next big hit increases. That is, a high probability state, which is more advantageous for the player, is obtained.

When the ball hits the gate 32, the display number as the normal symbol on the ordinary symbol display 10 changes continuously. Also, when the stop symbol in the ordinary symbol display 10 is a predetermined symbol (hit symbol),
The variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the ordinary symbol display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIGS. FIG. 3 is a back view of the gaming machine as viewed from the back. FIG. 4 is a rear view of the mechanism plate to which various members are attached as viewed from the rear side of the gaming machine.

As shown in FIG. 3, on the rear side of the gaming machine, a variable display control unit 49 including a symbol control board 80 for controlling the variable display device 9, a game control board (mainly a game control microcomputer) on which a game control microcomputer and the like are mounted. (Substrate) 31 is provided. In addition, a payout control board 37 on which a payout control microcomputer for performing ball payout control and the like is mounted. Furthermore, various decorations L provided on the game board 6
ED, special symbol start memory display 18, normal symbol start memory display 41, decorative lamp 25, top frame lamp 28a, left frame lamp 28b, right frame lamp 2 provided on the frame side
8c, a lamp control board 3 on which a lamp control means for controlling lighting of the prize ball lamp 51 and the ball out lamp 52 is mounted.
5. A sound control board 70 on which sound control means for controlling sound generation from the speaker 27 is also provided. Also, D
A power supply board 910 on which a power supply circuit for generating C30V, DC21V, DC12V and DC5V is mounted, and a launch control board 91 are provided.

A terminal board 160 having terminals for outputting various types of information to the outside of the gaming machine is provided above the gaming machine on the rear side. Terminal board 160
At least, a ball-out terminal for introducing and outputting the output of the ball-out detection switch, a prize-ball terminal for externally outputting the prize-ball number signal, and a ball-end number signal for externally outputting the ball lending number signal. A ball lending terminal is provided. In the vicinity of the center, an information terminal board 34 having terminals for outputting various information from the main board 31 to the outside of the gaming machine is provided.

Further, storage contents holding means (for example, a backup RA which can hold the contents even when the power supply is stopped) included in each board (the main board 31, the payout control board 37, etc.).
A switch board 190 provided with a clear switch 921 as an operation means for clearing the backup data stored in M) is provided. Switch board 1
The 90 is provided with a clear switch 921 and a connector 922 connected to another substrate such as the main substrate 31.

The game balls stored in the storage tank 38 pass through the guide rail 39 and, as shown in FIG.
Through 86, it reaches a ball dispensing device covered with a prize ball case 40A. At the top of the ball payout device, a ball out switch 187 as a game medium out detecting means is provided. When the ball-out switch 187 detects the ball-out, the payout operation of the ball payout device stops. The ball out switch 187 is a switch for detecting the presence or absence of a game ball in the game ball passage. The ball out switch 167 for detecting a shortage of replenishment balls in the storage tank 38 is also provided in the upstream portion (the storage tank 38) of the guide rail 39. (A part close to). When the ball-out detection switch 167 detects a shortage of game balls, the replenishment mechanism provided on the game machine installation island supplies the game machines with game balls.

The ball out switch 187 is locked at a position where it is possible to detect the presence of about 27 to 28 game balls in the payout ball passage leading to the ball payout device. That is, the out-of-ball switch 187 outputs the maximum payout amount of one unit of the prize ball (15 in this embodiment) and the maximum payout amount of one unit of the ball lending (100 yen: 25 in this embodiment).
) Is installed at a position where it can be confirmed that the above is secured.

The game balls paid out from the ball payout device are guided to the hitting plate 3 provided on the front face of the pachinko gaming machine 1 through the communication port 45. On the side of the communication port 45, an excess ball passage 46 communicating with the excess ball receiving tray 4 provided on the front of the pachinko gaming machine 1 is formed.

A large number of game balls as prizes based on winnings and game balls based on ball lending requests are paid out and the hitting ball supply tray 3 becomes full. Finally, after the game balls reach the contact 45, the game balls are further added. When paid out, the game balls are guided to the surplus ball tray 4 via the surplus ball passage 46. When the game balls are further paid out, the sensing lever 47 presses the full tank switch 48 as the storage state detecting means, and the full tank switch 48 as the storage state detecting means is turned on. In this state, the rotation of the payout motor in the ball payout device stops, the operation of the ball payout device stops, and the driving of the firing device also stops.

As shown in FIG. 4, on the side of the ball dispensing device, a ball removing passage 191 is formed from a curve gutter 186 to a discharge port 192 at a lower portion of the gaming machine. Ball-free passage 19
A ball-pulling lever 193 is provided at the upper part of the game ball 1, and when the ball-pulling lever 193 is operated by a game clerk or the like, a game ball path is formed from the guide rail 39 to the ball-pulling path 191, and is stored in the storage tank 38. The game ball that has been played is discharged from the discharge port 192 to the outside of the gaming machine.

FIG. 5 is an exploded perspective view showing a configuration example of the ball payout device 97. In this example, a ball payout device 97 is formed inside three cases 140, 141, and 142 as the prize ball case 40A. Holes 170 and 171 communicating with the ball passage below the ball cut switch 187 are provided in the upper portions of the cases 140 and 141, and the game balls are provided in the holes 170
From 171, the ball flows into the ball payout device 97.

The ball payout device 97 includes a payout motor (for example, a stepping motor) 289 serving as a driving source. The rotational force of the payout motor 289 is transmitted to the gear 290 fitted on the rotation shaft of the payout motor 289, and further transmitted to the gear 291 that meshes with the gear 290. A sprocket 292 having a recess is fitted on the central axis of the gear 291. The game balls flowing from the holes 170 and 171 are dropped one by one into the ball passage 293 below the sprocket 292 by the concave portion of the sprocket 292.

The ball passage 293 is provided with a distribution member 311 for switching the flow path of the game ball. The distributing member 311 is driven by the solenoid 310, and when the prize ball is paid out, the game ball falls down on one of the flow paths in the ball path 293, and when the ball is lent, the game ball flows on the other flow path in the ball path 293. To fall. The payout motor 289 and the solenoid 310 are controlled by a payout control CPU mounted on the payout control board 37. Further, the payout control CPU includes a main board 31.
The payout motor 289 and the solenoid 310 are controlled in accordance with a command from a game control CPU mounted on the CPU.

A prize ball sensor (prize ball count switch) 301A for detecting a game ball paid out by the ball payout device is provided below the down flow path selected at the time of paying out the prize ball.
A ball lending sensor (ball lending count switch) 301B for detecting game balls paid out by the ball payout device is provided below the down flow path selected at the time of ball lending. The detection signal of the prize ball count switch 301A and the detection signal of the ball lending count switch 301B are input to the payout control CPU of the payout control board 37. The payout control CPU counts the number of game balls actually paid out based on the detection signals.

FIG. 6 is a front view showing a portion of the switch board 190 provided on the game board 6. As shown in FIG. 6, on the switch board 190, a connector 922 for connecting the output of the clear switch 921 to another board such as the main board 31 via a cable is mounted.

FIG. 7 is a configuration diagram showing an example of the configuration of the clear switch 921 mounted on the switch board 190. FIG. 7A shows a clear switch 921 having a push button structure. When the clear switch 921 is pressed, a low level (on state) clear switch signal is output and transmitted to the main board 31 and the like via the connector 922. If the clear switch 921 is not pressed, a high-level (off-state) signal is output.

FIG. 7B is a configuration diagram showing another example of the configuration of the clear switch 921. The clear switch 921 illustrated in FIG. 7B has a switching operation unit 921a for performing selection switching of “OFF”, “ON”, and “clear”. When "OFF" is selected by the switching operation unit 921a, no signal is generated. "ON"
When is selected, a high-level signal is output.
Note that the clear switch 921 may also serve as a switch for turning on / off the power supply to the gaming machine 1. In this case, when "OFF" is selected, the gaming machine 1
Is stopped (the power of the gaming machine is turned off). When "ON" or "clear" is selected, a state is reached in which power is supplied to the gaming machine 1 (power of the gaming machine is on). When “clear” is selected, a low-level clear switch signal is output.

In this embodiment, the switch substrate 190 on which the clear switch 921 is mounted is provided separately from other substrates, but the clear switch 921 may be mounted on another substrate. For example, it may be mounted on the power supply board 910. The clear switch 921 is connected to the power supply board 910
In the case where the game board 6 is mounted, even if the power supply board 910 is used as it is for the game board 6 after replacement in the case of replacement of the game board 6, for example, the game state is restored on the game board 6 after replacement. Processing or the like can be performed.
That is, the power supply board 910 can be reused.

FIG. 8 is a block diagram showing an example of the circuit configuration of the main board 31. FIG. 8 also shows a payout control board 37, a lamp control board 35, a sound control board 70, a firing control board 91, and a symbol control board 80.
The pachinko machine 1 is provided on the main board 31 according to the program.
, A gate switch 32a, a starting port switch 14a, a V winning switch 22, a count switch 23, a winning port switches 24a, 29a, 30a,
33a, full tank switch 48, ball out switch 187,
Prize ball count switch 301A and clear switch 9
Switch circuit 5 for providing a signal from circuit 21 to basic circuit 53
8, a solenoid 16 for opening and closing the variable winning ball device 15,
A solenoid 21 for opening and closing the opening / closing plate 20 and a solenoid circuit 59 for driving a solenoid 21A for switching a path in the special winning opening in accordance with a command from the basic circuit 53 are mounted.

Although not shown in FIG. 8, the count switch short-circuit signal is also transmitted to the basic circuit 53 via the switch circuit 58. Further, the gate switch 32a, the starting port switch 14a, the V winning switch 22, the count switch 23, the winning port switches 24a, 29a, 30a,
33a, full tank switch 48, ball out switch 187,
Switches such as the award ball count switch 301A may be called sensors. That is, a game medium detecting means capable of detecting a game ball (in this example, a game ball detecting means)
If so, its name does not matter.

According to the data provided from the basic circuit 53, the jackpot information indicating the occurrence of a jackpot, the effective start information indicating the number of start winning balls used to start the variable display of the symbol on the variable display device 9, and the probability fluctuation are obtained. An information output circuit 64 for outputting an information output signal such as probability change information indicating occurrence to an external device such as a hall computer is mounted.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 as storage means (variable data storage means) used as a work data area (work area) and a stack area (evacuation area),
CPU 56 and I which perform a control operation according to a program
/ O port section 57 is included. In this embodiment, the ROM
The RAM 55 and the RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to have at least the RAM 55 therein, and the ROM 54 and the I / O port unit 57 may be external or internal.

A part or all of the RAM (may be a CPU built-in RAM) 55 is a backup RAM that is backed up by a backup power supply created on the power supply board 910. That is, even if the power supply to the gaming machine is stopped,
Some or all of the contents of 55 are saved.

A hit ball launching device that hits and fires a game ball is driven by a drive motor 94 controlled by a circuit on a launch control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

In this embodiment, the lamp control means mounted on the lamp control board 35 is provided with the start memory display 18, the ordinary symbol start memory display 41 and the decorative lamp 25 provided on the game board. While performing display control, display control of the top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, the award ball lamp 51, and the ball out lamp 52 provided on the frame side is performed. The display control of the variable display device 9 for variably displaying a special symbol and the ordinary symbol display 10 for variably displaying an ordinary symbol is controlled by a symbol control board 80.
This is performed by display control means mounted on the device.

FIG. 9 shows the circuit configuration in the symbol control board 80 by using an LCD (liquid crystal display) 82, an ordinary symbol display 10, and an output port (port 0) of the main board 31 as an example of the variable display device 9. , 2) are block diagrams shown together with 570, 572 and output buffer circuits 620, 62A.
Output port (output port 2) 572 outputs 8-bit data, and output port 570 outputs a 1-bit strobe signal (INT signal).

The display control CPU 101 controls the control data R
It operates according to the program stored in the OM 102, and receives an INT signal from the main board 31 via the noise filter 107 and the input buffer circuit 105B, and receives a display control command via the input buffer circuit 105A. As the input buffer circuits 105A and 105B, for example, 74HC540 and 74HC14, which are general-purpose ICs, can be used. When the display control CPU 101 does not include an I / O port, an I / O port is provided between the input buffer circuits 105A and 105B and the display control CPU 101.

Then, the display control CPU 101 controls display of a screen displayed on the LCD 82 according to the received display control command. Specifically, a command corresponding to the display control command is given to the VDP 103. VDP103
Reads necessary data from the character ROM 86. The VDP 103 controls the LCD 8 according to the input data.
2 to generate image data to be displayed on the LCD 2, and output R, G, B signals and a synchronization signal to the LCD 82.

FIG. 9 also shows a reset circuit 83 for resetting the VDP 103, an oscillation circuit 85 for supplying an operation clock to the VDP 103, and a character ROM 86 for storing frequently used image data. The frequently used image data stored in the character ROM 86 is, for example, a person, an animal, or an image composed of characters, figures, or symbols displayed on the LCD 82.

The input buffer circuits 105A and 105B
The signal can be passed only in the direction from the main board 31 to the display control board 80. Therefore, the display control board 8
There is no room for a signal to be transmitted from the 0 side to the main board 31 side. That is, the input buffer circuits 105A and 105B together with the input ports constitute irreversible information input means. Even if a circuit in the display control board 80 is tampered with, a signal output by the tampering is not transmitted to the main board 31 side.

Noise filter 10 for blocking high frequency signals
For example, a three-terminal capacitor or a ferrite bead is used as 7, but even if the display control command includes noise between the substrates due to the presence of the noise filter 107, the effect is eliminated. Also, a noise filter may be provided on the output side of the buffer circuits 620 and 62A of the main board 31.

FIG. 10 is a block diagram showing components related to payout, such as components of the payout control board 37 and the ball payout device 97. As shown in FIG. 10, a detection signal from the full tank switch 48 is input to the I / O port unit 57 of the main board 31 via the relay board 71. The detection signal from the ball cut switch 187 is also transmitted to the I / O port 5 of the main board 31 via the relay board 72 and the relay board 71.
7 is input.

The CPU 56 of the main board 31 determines whether the detection signal from the ball out switch 187 indicates that the ball is out.
Alternatively, when the detection signal from the full tank switch 48 indicates the full tank state, a payout control command indicating that the payout should be stopped is transmitted. When receiving the payout control command indicating that the payout should be stopped, the payout control CPU 371 of the payout control board 37 stops the ball payout process.

Further, the detection signal from the prize ball count switch 301A is input to the relay board 72 and the I / O port section 57 of the main board 31 via the relay board 71, and the payout control is performed via the relay board 72. It is input to the input port 372b of the substrate 37. Prize ball count switch 30
1A is provided in the payout mechanism portion of the ball payout device 97, and detects a prize ball payout ball actually paid out.

When there is a prize, the payout control board 37 has output ports (ports 0, 1) 570, 571 of the main board 31.
, A payout control command indicating the number of winning balls is input. The output port (output port 1) 571 outputs 8-bit data, and the output port 570 outputs a 1-bit INT signal. The payout control command indicating the number of winning balls is input to the I / O port 372a via the input buffer circuit 373A. The INT signal is input to the interrupt terminal of the payout control CPU 371 via the input buffer circuit 373B. The payout control CPU 371 includes an I / O port 372a.
A payout control command is input via the, and the ball payout device 97 is driven in accordance with the payout control command to perform the prize ball payout. In this embodiment, the payout control CPU 371
A one-chip microcomputer, at least RA
M is built-in.

In the main board 31, the output port 5
Buffer circuits 620 and 68A are provided outside 70 and 571. As the buffer circuits 620 and 68A, for example, 74HC250 and 7HC which are general-purpose CMOS-ICs
4HC14 is used. According to such a configuration, since a signal inputted from the outside to the inside of the main board 31 is blocked, a signal line to which a signal may be given from the payout control board 37 to the main board 31 is further reliably eliminated. be able to. Note that a noise filter may be provided on the output side of the buffer circuits 620 and 68A.

The payout control CPU 371 is connected to the output port 3
A ball lending number signal indicating the number of lending balls is output to the terminal board 160 via 72c. Further, the output port 37
An error signal is output to the error display LED 374 via 2d.

Further, the input port 3 of the payout control board 37
Detection signals from a ball lending count switch 301B and a payout motor position sensor for detecting the rotational position of the payout motor 289 are input to the relay board 72b via the relay board 72. The ball lending count switch 301B is provided in the payout mechanism portion of the ball payout device 97, and detects the actually paid lending balls. The drive signal from the payout control board 37 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72, and the drive signal to the distribution solenoid 310 is provided. Is transmitted to the distribution solenoid 310 in the dispensing mechanism of the ball dispensing device 97 via the output port 372e and the relay board 72. The output of the clear switch 921 is also input to the input port 372b.

The card unit 50 is provided with a microcomputer for controlling the card unit. Also,
The card unit 50 is provided with a fraction display switch 152, a connection board direction indicator 153, a card insertion indicator lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected to a frequency display LED, a ball lending switch, and a return switch provided near the hit ball supply tray 3.

From the balance display board 74 to the card unit 50
In response to the operation of the player, a ball lending switch signal and a return switch signal are given via the payout control board 37. In addition, the balance display board 74 is provided from the card unit 50.
, A card balance display signal indicating the balance of the prepaid card and a ball lending possible display signal are given via the payout control board 37. Between the card unit 50 and the payout control board 37, a connection signal (VL signal) and a unit operation signal (B
RDY signal), ball lending request signal (BRQ signal), ball lending completion signal (EXS signal) and pachinko machine operation signal (P
RDY signal) is input port 372b and output port 3
It is exchanged via 72e.

When the power of the pachinko gaming machine 1 is turned on,
The payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal. The payout control CPU 371 determines the connection state / non-connection state based on the input state of the VL signal. When the card is accepted in the card unit 50 and the ball lending switch is operated to input a ball lending switch signal, the microcomputer for controlling the card unit outputs a BRDY signal to the payout control board 37. When a predetermined delay time has elapsed from this point, the microcomputer for controlling the card unit outputs a BRQ signal to the payout control board 37.

The payout control board 37 of the payout control board 37
When the PU 371 raises the EXS signal to the card unit 50 and detects the fall of the BRQ signal from the card unit 50, it drives the payout motor 289 and pays out a predetermined number of loaned balls to the player. At this time, the distribution solenoid 310 is in a driving state. That is, the ball distribution member 311 is directed to the ball lending side. When the payout is completed, the payout control CPU 371 sets the card unit 5
The EXS signal for 0 falls. Thereafter, if the BRDY signal from the card unit 50 is not in the ON state,
The winning ball payout control is executed.

As described above, all signals from the card unit 50 are input to the payout control board 37. Therefore, regarding the ball lending control, the card unit 5
No signal is input from 0 to the main board 31, and there is no room for a signal to be incorrectly input from the card unit 50 side to the basic circuit 53 of the main board 31. The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37.

In this embodiment, a power-off signal is also input from the power supply board 910 to the payout control board 37. The power-off signal is input to the non-maskable interrupt (NMI) terminal of the payout control CPU 371. Further, the payout control board 3
7 is backed up by a backup power supply created on the power supply board 910. That is, even if the power supply to the gaming machine is stopped, at least a part of the contents of the RAM is stored for a predetermined period.

In this embodiment, the case where the card unit 50 is installed separately from the gaming machine and adjacent to the gaming machine will be described as an example, but the card unit 50 is integrated with the gaming machine. You may. Also, the present invention can be applied to a case where a game ball corresponding to the amount of money is lent out according to insertion of a coin.

FIG. 11 is a block diagram showing an example of the configuration of the power supply board 910. The power supply board 910 includes a main board 31,
Symbol control board 80, sound control board 70, lamp control board 3
5 and is installed independently of the electric component control boards such as the payout control board 37, and generates a voltage used by each electric component control board and mechanical components in the gaming machine. In this example, AC2
4V, VSL (DC + 30V), DC + 21V, DC + 1
Generate 2V and + 5V DC. The capacitor 916 serving as a backup power supply, that is, a storage power supply means, is charged from DC + 5V, that is, a power supply line for driving an IC or the like on each substrate. Note that VSL is generated in the rectifier circuit 912 by rectifying and boosting 24 VAC with a rectifier. VSL is a solenoid drive power supply.

The transformer 911 converts an AC voltage from an AC power supply to 24V. AC 24V voltage is applied to connector 9
15 is output. Further, the rectifier circuit 912 includes an AC24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. DC-D
C converter 913 includes one or more converters I
C922 (only one is shown in FIG. 11) and VSL
Then, + 21V, + 12V, and + 5V are generated based on the above and output to the connector 915. A relatively large-capacity capacitor 923 is connected to the input side of the converter IC 922. Therefore, when the power supply to the gaming machine from the outside is stopped, the DC voltage such as +30 V, +12 V, +5 V, etc., decreases relatively slowly. The connector 915 is connected to, for example, a relay board, and power of a voltage required for each electric component control board and a mechanical component is supplied from the relay board.

However, the power supply board 910 may be provided with each connector leading to each electric component control board, and the power supply board 910 may supply each voltage reaching each board without passing through the relay board. Also, FIG. 11 shows one connector 915 as a representative, but the connectors are provided for each electric component control board.

+5 V from DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 is a backup RAM of the electric component control board when the power supply to the gaming machine is stopped (RAM backed up by a power supply, that is, a backup storage unit that can be in a storage state even when the power supply is stopped).
Is a backup power supply that supplies power so that the storage state can be maintained. A backflow preventing diode 9 is provided between the + 5V line and the backup + 5V line.
17 is inserted. In this embodiment, +5 V for backup is applied to the main board 31 and the payout control board 3.
7 is supplied.

A power supply monitoring IC 902 as a power supply monitoring circuit is mounted on the power supply board 910. The power supply monitoring IC 902 detects the occurrence of a power supply stop to the gaming machine by introducing the VSL voltage and monitoring the VSL voltage. Specifically, the VSL voltage is a predetermined value (in this example, +
22V) or less, a power cutoff signal is output on the assumption that power supply has stopped. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is a voltage immediately after conversion from AC to DC, is used. Power supply monitoring IC
The power cut-off signal from 902 is supplied to the main board 31, the payout control board 37, and the like.

The predetermined value for the power supply monitoring IC 902 to detect the stop of power supply is lower than the normal voltage, but is a voltage at which the CPU on each electric component control board can operate for a while. The power supply monitoring IC 902 is a CPU
For driving circuit elements such as (+5 in this example)
V), and is configured to monitor the voltage immediately after conversion from AC to DC, so that the monitoring range can be extended for the voltage required by the CPU. Therefore, more precise monitoring can be performed. Further, when VSL (+30 V) is used as the monitoring voltage, the voltage supplied to various switches of the gaming machine is +12 V
Therefore, prevention of erroneous switch-on detection upon momentary power interruption can be expected. That is, by monitoring the voltage of the +30 V power supply, it is possible to detect a decrease in the voltage of +12 V generated after the generation of +30 V before the voltage starts to drop.

When the voltage of the +12 V power supply drops, the switch output comes to an on state. However, if the stop of the power supply is recognized by monitoring the +30 V power supply voltage that drops faster than +12 V, the switch output will turn on. It is possible to enter a state of waiting for power supply recovery before entering a state in which the switch output is not detected.

Further, since the power supply monitoring IC 902 is mounted on the power supply board 910 separate from the electric component control board, the power supply monitoring circuit can supply a power-off signal to the plurality of electric component control boards. No matter how many electrical component control boards require a power-off signal, it is sufficient that only one power supply monitoring means is provided. Therefore, even if each electrical component control means in each electrical component control board performs recovery control described later, However, the cost of gaming machines does not increase much.

In the configuration shown in FIG. 11, the detection signal (power-off signal) of the power supply monitoring IC 902 is supplied to the respective electric component control boards (for example, the main board 31 and the payout control signal) via buffer circuits 918 and 919. Although the signal is transmitted to the board 37), for example, a configuration in which one detection signal is transmitted to the relay board and the same signal is distributed from the relay board to each electric component control board may be employed. Further, a buffer circuit may be provided according to the number of substrates that require a power-off signal. Further, the main board 31
The monitoring voltage of the power monitoring circuit that outputs the power-off signal may be different for the power-off signal output to the payout control board 37 and the power-off signal.

FIG. 12 shows the CPU 56 on the main board 31.
It is a block diagram which shows the example of a surrounding structure. As shown in FIG. 12, a power-off signal from a power supply monitoring circuit (power supply monitoring means; first power supply monitoring means) of a power supply
It is connected to 56 non-maskable interrupt terminals (XNMI terminals). Therefore, the CPU 56 sets the non-maskable interrupt (NM
I) It is possible to confirm the occurrence of the stop of the power supply to the gaming machine by the processing.

FIG. 12 also shows a system reset circuit 65. When the power is turned on, the reset IC 651
The output is set to the low level for a predetermined time determined by the capacity of the external capacitor, and the output is set to the high level after the predetermined time has elapsed. That is, the reset signal is raised to a high level to make the CPU 56 operable. The reset IC 651 monitors the power supply voltage VSL, which is the same power supply voltage as the power supply voltage monitored by the power supply monitoring circuit, and determines that the voltage value is a predetermined value (lower than the power supply voltage value at which the power supply monitoring circuit outputs a power-off signal). Value), the output goes low. Therefore, the CPU 56 performs a predetermined power supply stop processing in response to a power-off signal from the power supply monitoring circuit, and then performs a system reset.

As shown in FIG. 12, the reset IC 651
Is input to the NAND circuit 947 and also to the clear terminal of the counter IC 941 via the inverting circuit (NOT circuit) 944. When the input to the clear terminal goes low, the counter IC 941 counts the clock signal from the oscillator 943.
The Q5 output of the counter IC 941 is output to the NOT circuit 9
45, 946 and input to the NAND circuit 947. The Q6 output of the counter IC 941 is input to a clock terminal of a flip-flop (FF) 942.
The D input of the flip-flop 942 is fixed at a high level, and the Q output is input to an OR circuit (OR circuit) 949. The other input of the OR circuit 949 is connected to the NAND circuit 9.
The output of 47 is introduced via NOT circuit 948. The output of the OR circuit 949 is connected to the reset terminal of the CPU 56. According to such a configuration, two reset signals (low-level signals) are supplied to the reset terminal of the CPU 56 when the power is turned on.
Starts operation reliably.

For example, the detection voltage of the power supply monitoring circuit (the voltage at which the power supply cutoff signal is output) is set to +22 V, and the detection voltage for setting the reset signal to low level is set to +9 V. In such a configuration, the power supply monitoring circuit and the system reset circuit 65 are connected to the same power supply VSL.
, The difference between the timing at which the voltage monitoring circuit outputs the power-off signal and the timing at which the system reset circuit 65 outputs the system reset signal can be reliably set to a desired predetermined period. The desired predetermined period is a period from the start of the power supply stop processing in response to the power supply cutoff signal from the power supply monitoring circuit until the power supply stop processing is completely completed.

The power supply voltage monitored by the power supply monitoring circuit and the power supply voltage monitored by the system reset circuit 65 may be different.
Further, the system reset circuit 65 corresponds to a second power supply monitoring unit.

While power is not supplied from the + 5V power supply which is the driving power supply of the CPU 56 and the like, at least a part of the RAM is backed up by the backup power supply supplied from the power supply board, and even if the power supply to the gaming machine is stopped. The contents are saved. Then, when the + 5V power supply is restored, a reset signal is issued from the system reset circuit 65, so that the CPU 56 returns to the normal operation state. At that time, since the necessary data is stored in the backup RAM, it is possible to restore the gaming state at the time of occurrence of the power failure or the like at the time of recovery from the power failure or the like.

In the configuration shown in FIG. 12, two reset signals (low-level signals) are applied to the reset terminal of the CPU 56 when the power is turned on. When using the CPU to be released, reference numerals 941 to 949
The circuit element indicated by is not required. In that case, the output of the reset IC 651 is directly connected to the reset terminal of the CPU 56.

CPU 56 used in this embodiment
Incorporates an I / O port (PIO) and a timer / counter circuit (CTC). PIO is PB0-PB
It has a port of 3 4 bits and 1 byte of PA0 to PA7. The ports PB0 to PB3 and PA0 to PA7 can be set for both input and output.

FIGS. 13 and 14 are explanatory diagrams showing the assignment of output ports in this embodiment. Figure 1
As shown in FIG. 3, the output port 0 is an output port for an INT signal of a control command sent to each electric component control board. Also, 8-bit data of the payout control command sent to the payout control board 37 is output from the output port 1,
The 8-bit data of the display control command sent to the symbol control board 80 is output from the output port 2, and the 8-bit data of the lamp control command sent to the lamp control board 35 is output from the output port 3. And FIG.
8, the 8-bit data of the sound control command sent to the sound control board 70 is output from the output port 4.

The output port 5 is connected to the information output circuit 6
4, various information output signals reaching the information terminal board 34 and the terminal board 160, that is, output data of information related to control are output. From the output port 6, a solenoid 16 for opening and closing the variable winning ball device 15, a solenoid 21 for opening and closing the opening and closing plate 2 of the special winning opening, and a solenoid 21 for switching a path in the special winning opening.
A drive signal for A is output.

As shown in FIG. 14, the payout control board 37,
An output port for outputting each INT signal (payout control signal INT, display control signal INT, lamp control signal INT, and voice control signal INT) output to the symbol control board 80, the lamp control board 35, and the sound control board 70. Output port 0) is different from output ports (output ports 1 to 4) for outputting payout control signals CD0 to CD7, display control signals CD0 to CD7, lamp control signals CD0 to CD7, and audio control signals CD0 to CD7. It is.

Therefore, when outputting the INT signal, the payout control signals CD0 to CD7 and the display control signals CD0
The possibility of changing the CD7, the ramp control signals CD0 to CD7, and the audio control signals CD0 to CD7 is reduced. When outputting the payout control signals CD0 to CD7, the display control signals CD0 to CD7, the lamp control signals CD0 to CD7, or the audio control signals CD0 to CD7,
The possibility of changing the NT signal is reduced. As a result, the command from the game control means of the main board 31 to each electric component control board is more reliably transmitted. Further, all the INT signals are configured to be output from the output port 0.
The burden of NT signal output processing is reduced.

FIG. 15 is an explanatory diagram showing bit assignment of an input port in this embodiment. As shown in FIG. 15, winning ports switches 33a, 24a, 29a, 30a,
The detection signals of the starting port switch 14a, the count switch 23, the V winning switch 22, and the gate switch 32a are input. The detection signals of the prize ball count switch 301A, the full tank switch 48, the ball out switch 187, the count switch short-circuit signal, and the clear switch 921 are input to bits 0 to 4 of the input port 1, respectively. The detection signal from each switch is logically inverted in the switch circuit 58. As described above, the detection signal of the clear switch 921, that is, the operation signal of the operation means is the input port (8-bit input section) to which the detection signal of the switch for detecting the game ball is input.
Bit at the same input port as (input port circuit)
Has been entered. The fact that the detection signal of the clear switch 921 indicates the switch operation state corresponds to the output of the operation signal.

Next, the operation of the gaming machine will be described. Figure 1
6 is a flowchart showing a main process executed by the game control means (CPU 56 and peripheral circuits such as ROM and RAM) on the main board 31. When the power is turned on to the gaming machine and the input level of the reset terminal becomes high level, the CPU 56 starts the main processing after step S1. In the main process, the CPU 56 first
Make the necessary initial settings.

In the initial setting process, the CPU 56 first sets interrupt prohibition (step S1). Next, the interrupt mode is set to the interrupt mode 2 (step S2), and a stack pointer designated address is set to the stack pointer (step S3). Then, the internal device registers are initialized (step S4). After initializing a built-in device (built-in peripheral circuit) CTC (counter / timer) and PIO (parallel input / output port) (step S5), the RAM is set to an accessible state (step S6).

CPU 56 used in this embodiment
Incorporates an I / O port (PIO) and a timer / counter circuit (CTC). Also, CTC has two external clock / timer trigger inputs CLK / TRG2, 3
And two timer outputs ZC / TO0,1.

CPU 5 used in this embodiment
6, the following three modes are prepared as maskable interrupt modes. When an interrupt that can be masked occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter on the stack.

Interrupt mode 0: The built-in device that has issued the interrupt request receives an RST instruction (1 byte) or a CALL instruction (3 bytes).
Byte) on the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. Upon reset, CPU 56 automatically switches to interrupt mode 0
become. Therefore, when it is desired to set the mode to the interrupt mode 1 or the interrupt mode 2, it is necessary to perform a process for setting the mode to the interrupt mode 1 or the interrupt mode 2 in the initial setting process.

Interrupt mode 1: When an interrupt is accepted,
In this mode, the camera always jumps to the address 0038 (h).

Interrupt mode 2: The address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is the interrupt address. Mode. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary (albeit skipped) even address. Each built-in device has a function of sending an interrupt vector when making an interrupt request.

Therefore, when the interrupt mode 2 is set, it is possible to easily process an interrupt request from each built-in device, and it is possible to set an interrupt process at an arbitrary position in a program. Will be possible. Further, unlike the interrupt mode 1, it is easy to prepare an interrupt process for each interrupt occurrence factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

Next, the CPU 56 checks the state of the output signal of the clear switch 921 inputted via the input port 1 only once (step S7). If ON is detected in the confirmation, the CPU 56 executes a normal initialization process (steps S11 to S1).
5). When the clear switch 921 is on (when pressed), a low-level clear switch signal is output. In the input port 1, the ON state of the clear switch signal is at a high level (see FIG. 15). Also, for example, the game store clerk can use the clear switch 92.
By starting the power supply to the gaming machine while turning 1 on, the initialization process can be easily executed. That is, the RAM can be cleared.

When the clear switch 921 is not on, when the power supply to the gaming machine is stopped, data protection processing for the backup RAM area (for example, processing for stopping power supply such as addition of parity data) is performed. It is confirmed whether or not it has been performed (step S8). In this embodiment, when the power supply is stopped, a process for protecting the data in the backup RAM area is performed. The case where such protection processing has been performed is regarded as backup. After confirming that such a protection process has not been performed, the CPU 56 executes an initialization process.

In this embodiment, the backup RAM
Whether or not there is backup data in the area is confirmed by the state of the backup flag set in the backup RAM area in the power supply stop processing. In this example, as shown in FIG. 17, if "55H" is set in the backup flag area, it means that there is a backup (on state), and if a value other than "55H" is set, there is no backup (off). State).

After confirming that there is a backup, the CPU 5
No. 6 performs data check (parity check in this example) of the backup RAM area (step S9). In this embodiment, clear data (00) is set in a checksum data area, and a checksum calculation start address is set in a pointer. In addition, the number of checksum calculations corresponding to the number of data to be checked is set. Then, an exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the value of the pointer is increased by one, and the value of the number of checksum calculations is decremented by one. The above process is repeated until the value of the number of checksum calculations becomes zero. When the number of checksum calculation times becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area,
The inverted data is used as a checksum.

In the power supply stop processing, a checksum is calculated by the same processing as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. If power is restored after an unexpected power outage or other power outage, backup RA
Since the data in the M area should be stored, the check result (comparison result) becomes normal (match). If the check result is not normal, it means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state at the time of stopping the power supply, the initialization processing executed at the time of turning on the power other than the recovery from the stop of the power supply is executed.

If the check result is normal, the CPU 56
Performs a game state restoration process for returning the internal state of the game control means and the control state of the electric component control means such as the display control means to the state at the time of stopping the power supply (step S10). Then, the saved value of the PC (program counter) stored in the backup RAM area is set in the PC, and the program returns to that address.

As described above, the backup RA and the check data such as the checksum are used for the backup RA.
By confirming whether or not the data in the M area is stored, the gaming state can be accurately returned to the state at the time of stopping the power supply. That is, the reliability of the state restoration processing based on the data in the backup RAM area is improved. In this embodiment, whether or not the data in the backup RAM area is stored is confirmed by using both the backup flag and the check data. However, only one of them may be used. That is, one of the backup flag and the check data may be used as a trigger for executing the state restoration processing.

In the initialization process, the CPU 56 first sets R
An AM clear process is performed (step S11). In addition, a predetermined work area (for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer,
Special symbol process flag, payout command storage pointer,
A work area setting process for setting an initial value to a flag for performing a process selectively according to a control state such as a winning ball flag, a ball out flag, and a payout stop flag is performed (step S1).
2). Further, a process of transmitting a payout permission state designation command (hereinafter, referred to as a payout possible state designation command) indicating that the payout from the ball payout device 97 is possible is performed to the payout control board 37 (step S13). . Also,
Other sub-boards (lamp control board 35, sound control board 70,
A process of transmitting an initialization command for initializing the symbol control board 80) to each sub-board is executed (step S1).
4). As the initialization command, a command indicating the initial symbol displayed on the variable display device 9 (for the symbol control board 80) and a command for instructing the prize ball lamp 51 and the ball out lamp 52 to be turned off (for the lamp control board 35) And).

In the initialization processing, a payout possible state designation command is always transmitted to the payout control board 37. what if,
Even if the state of the gaming machine is a state in which the payout from the ball payout device 97 is not possible, in the game control processing executed immediately thereafter, the fact is detected, and the payout indicating that the payout is not possible is performed. Prohibition status specification command (hereinafter,
This command is called a payout stop state designation command. ) Is sent, so there is no problem. In the process of transmitting the payout possible state designation command and the initialization command to other sub-boards, for example, a table (R
The address of the OM area may be set in the pointer, and a processing routine such as a command setting process (see FIG. 37) described later may be called.

Then, the register of the CTC provided in the CPU 56 is set so that the timer is interrupted periodically every 2 ms (step S15). That is,
A value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value.

Execution of initialization processing (steps S11 to S1)
When 5) is completed, the display random number updating process (step S17) and the initial value random number updating process (step S18) are repeatedly executed in the main process. When the display random number update process and the initial value random number update process are executed, the interrupt is prohibited (step S16), and when the display random number update process and the initial value random number update process are completed, the interrupt is enabled. Is performed (step S19). The display random number is a random number for determining a symbol to be displayed on the variable display device 9, and the display random number update process is a process of updating the count value of a counter for generating the display random number. . The initial value random number updating process is a process of updating the count value of a counter for generating an initial value random number. The initial value random number is a random number for determining an initial value of a count value of a counter for generating a random number for determining whether or not to make a big hit (a random number generation counter for big hit determination). In the game control process described later, when the count value of the big hit determination random number generation counter makes one round, an initial value is set in the counter.

When the display random number updating process is executed, the interrupt is prohibited because the display random number updating process is also executed in the timer interrupt process described later. This is to avoid competing with. That is, if a timer interrupt occurs during the process of step S17 and the count value of the counter for generating the display random number is updated during the timer interrupt process, the continuity of the count value is lost. There are cases. However, such an inconvenience does not occur if the interrupt is prohibited during the processing in step S17.

FIG. 18 is a flowchart showing an example of the game state restoring process. In the game state restoration process, C
The PU 56 first performs a stack pointer return process (Step S81). The value of the stack pointer is saved in a predetermined RAM area (a stack pointer save buffer in a power-backed work area) in a power supply stop process described later in detail. Therefore,
In step S81, the process returns by setting the value of the RAM area in the stack pointer. The register value and the value of the program counter (PC) when the power supply is stopped are saved in the area pointed to by the restored stack pointer (that is, the stack area).

Next, the CPU 56 checks whether or not the payout has been stopped (step S82). Whether or not the dispensing is stopped is determined by the RAM backed up by the power supply.
A predetermined work area stored in the area (for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a special symbol process flag,
This is confirmed by the payout stop flag as the payout state data in the payout command storage pointer, the winning ball flag, the ball out flag, the payout stop flag, and the like. If it is in the payout stop state, a payout control command (payout stop state designation command) for instructing stop of payout is transmitted to the payout control means mounted on the payout control board 37 (step S83). If it is not in the payout stop state, a payout control command (payout possible state designation command) for instructing that payout is possible is sent to the payout control means (step S84). As described later, the payout stop flag is set when a payout stop state designation command is received, and is reset when a payout possible state designation command is received. Among the state designation commands, data corresponding to the last command transmitted by the game control means before the power supply is stopped is set.

Since the payout control means cannot recognize the shortage of the supply balls or the fullness of the surplus ball tray 4, the game control means does not notify it. There is a possibility that the payout process of the game ball may be started in spite of the tongue. However, in this embodiment, in the game state restoring process, a payout control command instructing stop of payout or a payout control command instructing that payout is possible is transmitted. Even if the surplus ball receiving tray 4 is full, the payout processing of the game balls does not start.

Here, if the payout state determining means (part of the game control means) which determines whether or not the payout of the game medium is possible detects that the payout is not possible, regardless of the cause, Although one type of payout stop state designation command is transmitted, it may be transmitted separately for each cause (in this example, a command indicating a shortage of supply balls and a command indicating a lower plate full). . Further, when the payout of the game ball is not possible, a command for prohibiting the firing of the game ball may be transmitted to the payout control board 37 in order to prohibit the continuation of the game. Dispensing control board 3
When receiving the command instructing prohibition of the launch of the game ball, the payout control unit mounted on 7 stops driving of the hit ball launching device. Further, when the payout of the game balls is not possible, the game control means may directly give a signal for instructing the firing control means to prohibit the firing of the game balls. Further, the payout control means may stop driving the hit ball firing device when receiving the payout stop state designation command.

Next, the CPU 56 checks whether or not the special symbol is being changed on the variable display device 9 when the power supply is stopped (step S85). Whether or not the special symbol is changing when the power supply is stopped can be confirmed by, for example, the value of the special symbol process flag stored in the RAM area where the power is backed up. If the special symbol is being changed, a special symbol power failure recovery command and a display control command for designating the left and right symbols are transmitted to the display control means mounted on the symbol control board 80 (step S86, S8
7). Here, the left and right symbols specified by the display control command are symbols that should have been stopped and displayed due to the special symbol change that was performed when the power supply was stopped.

When the display control means receives the special symbol power failure restoration command, it performs a predetermined notification process. For example, the variable display device 9 displays that a power failure has occurred. The game state returns to the state before the power supply was stopped based on the various information that was backed up by the power supply. After that, when the fluctuation period of the special symbol ends, the game control unit issues a determination command to the display control unit. Send. The display control means includes:
Based on the reception of the confirmation command, the next special symbol can be changed.

When the special symbol is not changing, the CP
U56 performs a process of transmitting a display control command for designating a left and right middle symbol, a confirmation command, and a customer waiting demonstration command to the display control means (steps S88 to S9).
0). The left and right symbols specified by the display control command are
It is a symbol displayed on the variable display device 9 when the power supply is stopped.

Upon receiving the confirmation command, the display control means controls the variable display device 9 to display the special symbol designated by the display control command for designating the left and right middle symbols. Further, upon receiving the customer waiting demonstration command, control is performed to change the display state such as the background of the variable display device 9 to the display state of the standby state.

Thereafter, the CPU 56 clears the backup flag (step S91), that is, resets a flag indicating that a predetermined storage protection process was executed when the power supply was stopped last time. Also, the saved values of various registers are read from the stack area, and various registers (IX
Register, HL register, DE register, BC register) (step S92). That is, register restoration processing is performed. Note that the value of the stack pointer is reduced each time each register is restored. That is, the value of the stack pointer is updated so as to point to the address immediately before the stack area. If the parity flag is not turned on, the interrupt is permitted (steps S93 and S94). Finally, the AF register (accumulator and flag register) is restored from the stack area (step S95).

Then, the RET instruction is executed. RET
When the instruction is executed, the CPU 56 implements the return operation of the program by setting the data stored in the area pointed to by the stack pointer in the program counter. However, the return destination here is not the part that called the game state restoration processing. This is because the stack pointer is restored in step S81, and after the register restoration process is completed in step S92, the stack pointer pointing to the stack area becomes NM.
This indicates an area where the address of the program executed when the power supply stop processing by I is started is saved. That is, the return address stored in the stack area pointed to by the returned stack pointer is
This is the address where the NMI occurred when the power supply was stopped last time in the program. Therefore, the RET instruction following step S95 returns to the address where the NMI occurred when the power supply was stopped. That is, recovery control is executed based on the address data (program address data) saved in the stack area.

When a timer interrupt occurs, the CPU 56
After performing the register save processing (step S20), the game control processing of steps S21 to S32 shown in FIG. 19 is executed. In the game control process, the CPU 56 first
Through the switch circuit 58, detection signals of switches such as the gate switch 32a, the starting port switch 14a, the count switch 23, and the winning port switches 33a, 24a, 29a, 30a are input, and their states are determined (switch processing: Step S21).

Next, various abnormality diagnosis processes are performed by the self-diagnosis function provided in the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S22).

Next, a process of updating the count value of each counter for generating each judgment random number such as a big hit judgment random number used in the game control is performed (step S23).
The CPU 56 further performs a process of updating the count value of the counter for generating the display random number and the initial value random number (steps S24 and S25).

Further, the CPU 56 performs a special symbol process (step S26). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Further, a normal symbol process is performed (step S27). In the normal symbol process process, a corresponding process is selected and executed according to a normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. And the value of the normal symbol process flag is
It is updated during each process according to the game state.

Next, the CPU 56 sets a display control command relating to the special symbol in a predetermined area of the RAM 55 and transmits the display control command (special symbol command control process: step S28). Further, a process of setting a display control command relating to a normal symbol in a predetermined area of the RAM 55 and transmitting the display control command is performed (ordinary symbol command control process: step S29).

Further, the CPU 56 performs an information output process of outputting data such as big hit information, start information, and probability variation information supplied to the hall management computer (step S30).

Further, the CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is satisfied (step S31). The solenoid circuit 59 drives the solenoids 16, 21 and 21A in response to a drive command in order to open or close the variable winning prize ball device 15 or the opening / closing plate 20 and to switch the game ball passage in the special winning opening. I do.

Then, the CPU 56 sets the winning opening switch 3
A prize ball process for setting the number of prize balls based on the detection signals of 3a, 24a, 29a, and 30a is executed (step S32). Specifically, the winning opening switches 33a, 24
A payout control command indicating the number of prize balls is output to the payout control board 37 in response to the winning detection based on the fact that a, 29a and 30a are turned on. The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 according to a payout control command indicating the number of winning balls. afterwards,
The contents of the register are restored (step S33), and the interrupt permission state is set (step S34).

By the above control, in this embodiment, the game control process is started every 2 ms.
In this embodiment, the game control process is executed in the timer interrupt process, but in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set.
The game control process may be executed in the main process.

FIGS. 20 and 21 are flowcharts showing an example of a non-maskable interrupt process (power supply stop process) executed in response to a power-off signal from the power supply board 910. When the non-maskable interrupt occurs, the interrupt control mechanism built in the CPU 56 stores the address of the program being executed at the time of the occurrence of the non-maskable interrupt (specifically, the next address after the execution is completed) into the stack pointer. Is saved in the stack area indicated by, and the value of the stack pointer is increased. That is, the value of the stack pointer is updated so as to point to the next address of the stack area.

In the power supply stop processing, the CPU 56
Saves the AF register (accumulator and flag register) to the stack area indicated by the stack pointer (step S51). At this time, the value of the stack pointer is updated so as to point to the next address in the stack area. Further, the interrupt flag is copied to the parity flag (step S52). Parity flag is backup R
It is formed in the AM area. The interrupt flag is a flag indicating whether the interrupt is enabled or disabled, and is in a control register built in the CPU 56. The ON state of the interrupt flag indicates that the interrupt is prohibited.
As described above, the parity flag is referred to in the game state restoration processing. Then, in the game state restoring process, if the parity flag is in the ON state, the interrupt state is not set.

The BC register, DE register, HL
The register and the IX register are saved in the stack area indicated by the stack pointer (steps S54 to S57). At this stage, the address of the program that was being executed when the non-maskable interrupt occurred, the BC register,
This means that the values of the DE register, the HL register, and the IX register are sequentially stored. Each time a register is saved, the value of the stack pointer is updated to point to the next address in the stack area. Further, the value of the stack pointer is saved in a predetermined area (stack pointer save buffer) in the work area (step S5).
8).

Next, the backup specified value (in this example, “55H”) is stored in the backup flag. The backup flag is formed in the backup RAM area. Next, parity data is created (steps S60 to S67). That is, first, clear data (0
0) is set in the checksum data area (step S60), and the checksum calculation start address is set in the pointer (step S61). Further, the number of checksum calculations is set (step S62).

Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S63). The calculation result is stored in the checksum data area (step S6).
4) The value of the pointer is incremented by 1 (step S65), and the value of the checksum calculation count is decremented by 1 (step S6).
6). The processing of steps S63 to S66 is repeated until the value of the number of checksum calculation times becomes 0 (step S63).
67).

When the value of the number of checksum calculations becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area (step S68). And
The inverted data is stored in the checksum data area (step S69). This data is the parity data that is checked when the power is turned on. Next, an access prohibition value is set in the RAM access register (step S70). Thereafter, the internal RAM 55 cannot be accessed. Therefore, even if the program runs away due to the voltage drop, the stored contents of the RAM are not destroyed.

Further, the CPU 56 sets the clear data (0
0) is set in an appropriate register (step S71),
The number of processes ("7" in this example) is set in another register (step S72). Further, the address of the output port 0 is set in the IO pointer (step S73). Yet another register is used as the IO pointer.

Then, the clear data is set at the address pointed to by the IO pointer (step S74).
The value of the IO pointer is incremented by 1 (step S75), and the value of the number of processes is decremented by 1 (step S77). Step S7
The processes from 4 to S76 are repeated until the value of the number of processes becomes zero. As a result, clear data is set in all output ports 0 to 6 (see FIGS. 13 and 14). FIG.
As shown in FIG. 14 and FIG. 14, in this example, "1" is on, and "00", which is clear data, is set to each output port, so that all output ports are off.

Therefore, after the processing for saving the gaming state (in this example, the generation of the checksum and the prevention of the RAM access) is executed, each output port is immediately turned off. In this embodiment, the RAM area in which data used in the game control process is stored is all backed up by power. Therefore, a process of generating a checksum indicating whether or not the content is correctly stored, and an R for preventing the content from being rewritten.
The AM access prevention process corresponds to a process for saving a gaming state.

Since each output port is immediately turned off after the processing for storing the game state is executed, it is possible to reliably prevent a situation in which the game state does not match the stored game state. That is, in a gaming machine having a variable winning ball device such as a pachinko gaming machine, in terms of mounting,
The position of the variable winning opening in the variable winning ball device and the installation position of the winning opening switch for detecting a winning must be separated to some extent. If the output port, in particular, the output port for outputting a signal for opening the variable winning ball device is not turned off immediately, when the power supply is stopped, the power supply is stopped despite the winning in the variable winning opening. A situation may occur where the execution of the process is started and the winning opening switch is not detected. In this case, the fact that the variable winning opening has been won is not saved. That is, the game state that actually occurs (the winning is achieved) does not match the saved game state.
However, in this embodiment, since the output port is cleared and the variable winning prize ball device is closed, it is possible to reliably prevent a situation in which the game state does not match the saved game state.

Further, at the time of the power supply stop processing executed before the driving of the electric components is disabled, the output port can be cleared. Each electric component controlled by the game control means can be brought into an appropriate operation stop state before the game control means. For example, the operation of the electric component is stopped after the operation of the electric component is stopped, for example, by closing the open big winning opening and closing the open variable winning ball device 15 being opened. be able to. Therefore, it is possible to wait for restoration of power supply in an appropriate stop state. And
When the clear processing for the output port is completed, the CPU 5
6 enters a standby state (loop state). Therefore, nothing is done until the system is reset.

In this embodiment, the power supply stop processing is executed according to the NMI.
It may be connected to the maskable terminal of the PU 56 to execute the power supply stop processing by the maskable interrupt processing. Alternatively, the power-off signal may be input to the input port, and the power supply stop processing may be executed according to the check result of the input port.

FIG. 22 shows a RAM according to the present embodiment.
FIG. 4 is an explanatory diagram showing an address map of an area. As shown in FIG. 22, the head of the RAM area is allocated to a backup flag area. The area of the checksum buffer is allocated to the last part. The area from the backup flag to the checksum buffer corresponds to the work area, and the stack area is set in the area after the checksum buffer. In this embodiment, the entire RAM area is backed up by a power supply.

FIG. 23 is an explanatory diagram for explaining an example of a checksum creation method. However, in the example shown in FIG. 23, the size of the data in the backup RAM area is 3 bytes for simplicity. In the process at the time of stopping power supply based on the power supply voltage drop, as shown in FIG. 23, initial data (in this example, 00
(H)) is set. Next, “00 (H)” and “F0
(H) "is exclusive-ORed, and the result and" 16 "
(H) ". Further, an exclusive OR of the result and “DF (H)” is obtained. And
As a result, a value (“C6 (H)” in this example) obtained by logically inverting the result (“39 (H)” in this example) is set in the checksum buffer.

FIG. 23 shows a state in which data "39 (H)" before logical inversion is stored in the checksum buffer for ease of explanation. In addition,
Although 00 (H) as the initial data is a value corresponding to the clear data for the checksum data set in step S60, actually, the exclusive OR with 00 (H) is obtained before and after the operation. Since the value does not change, it is not necessary to perform an exclusive OR operation with 00 (H).

In this embodiment, the checksum buffer is provided in the backup RAM area (variable data storage means).
Is stored at the last address. So, for example,
When checking whether there is any error in the program of the checksum generation method, the check can be easily performed.
This is because it is sufficient to confirm whether the value of the last address of the RAM area is correct. Further, in this embodiment, the checksum calculation start address is the address where the backup flag is set, and the checksum calculation end address is the last address of the prize ball control flag buffer (see FIG. 22). . Therefore, if the last address of the backup RAM area is set as the checksum buffer area after the prize ball control flag buffer, the RA
No waste occurs in the M area.

The first address of the backup RAM area may be a checksum buffer area in consideration of easy confirmation and prevention of waste of the RAM area.

When the power supply to the gaming machine is started, it is determined whether or not the parity check is OK (step S9 in FIG. 16). S7
1 to S77), and if the processing result, that is, the operation result matches the contents of the checksum buffer, it is determined that the parity check is OK.

Here, the last or first address of the backup RAM area is used as the checksum buffer area, but the checksum buffer area may be allocated to an intermediate area of the backup RAM area. In this embodiment, the checksum is generated based on the data in the work area. However, the checksum may be generated including the data in the stack area.

Further, in this embodiment, at the start of power supply, a checksum is generated by the same processing as that in the power supply stop processing, and the generated checksum and the checksum stored in the backup RAM are compared. Although compared, other methods may be used. For example, using the checksum stored in the backup RAM as an initial value, an operation is performed on each of the data to be calculated in the power supply stop processing, and if the calculation result matches a predetermined value (eg, 00 (H)), the parity It may be determined that the check is OK. Also, the check data for the parity check is not limited to the checksum, and other check data may be used as long as it can determine whether the contents of the backup RAM are properly stored.

FIG. 24 is a timing chart showing the state of the power supply voltage drop and the NMI signal (= power-off signal: power-supply stop signal) when the power supply to the gaming machine is stopped. When the power supply to the gaming machine is stopped, the voltage value of VSL, which is the highest DC power supply voltage, gradually decreases. Then, in this example, when the voltage drops to +22 V, a power supply cutoff signal is output from the power supply monitoring IC 902 mounted on the power supply board 910 (to a low level).

The power-off signal is supplied to the electric component control board (the main board 31 and the payout control board 37 in this embodiment).
Input to MI terminal. CPU 56 and payout control C
The PU 371 executes a predetermined power supply stop process by the NMI process.

When the voltage value of VSL further decreases to a predetermined value (+9 V in this example), the output of the system reset circuit mounted on the main board 31 or the dispensing control board 37 goes low, and the CPU 56 And the payout control CPU 371 enters a system reset state. Note that C
The PU 56 and the payout control CPU 371 have completed the power supply stop processing before the system reset state.

When the voltage value of VSL further decreases and falls below a voltage capable of generating Vcc (+5 V for driving various circuits), each circuit cannot operate on each substrate. However, at least in the main board 31 and the payout control board 37, the power supply stop processing is executed,
56 and the payout control CPU 371 are in a system reset state.

As described above, in this embodiment, the power supply monitoring circuit monitors the highest voltage of the power supply VSL among the DC voltages used in the gaming machine, and the voltage of the power supply falls below the predetermined value. Then, a voltage drop signal (power cutoff detection signal) is generated. As shown in FIG. 24, at the timing when the power-off signal is output, the IC drive voltage is still a voltage value that can sufficiently drive various circuit elements. Therefore, the operation time for the CPU 56 of the main board 31 operating at the IC drive voltage to perform the predetermined power supply stop processing is secured.

Here, the power supply monitoring circuit monitors the highest voltage of the power supply VSL among the DC voltages used in the gaming machine.
If the timing is such that the operation time for the electric component control means operating at the C drive voltage to perform the predetermined power supply stop processing is secured, the monitored voltage is the highest power supply V
The voltage need not be SL voltage. That is, if at least a voltage higher than the IC drive voltage is monitored, the power-off signal can be generated at a timing such that the operation time for the electric component control means to perform the predetermined power supply stop processing is secured. .

In this case, as described above, it is preferable that the voltage to be monitored is a voltage that can be expected to prevent erroneous switch-on detection when power supply is stopped. That is, the voltage (switch voltage) supplied to various switches of the gaming machine is +1
Since the voltage is 2 V, it is preferable that the voltage drop can be detected before the +12 V power supply voltage starts to drop. Therefore, it is preferable to monitor at least a voltage higher than the switch voltage.

Next, a specific example of the switch processing (step S21) in the main processing will be described. In this embodiment, when the ON state of the detection signal of each switch continues for a predetermined time, it is determined that the switch has been turned on, and the processing corresponding to the switch-on is started. A switch timer is used to measure a predetermined time. The switch timer is a 1-byte counter formed in the backup RAM area, and is incremented by 1 every 2 ms when the detection signal indicates the ON state. As shown in FIG. 25, the switch timers are provided by the number N of the detection signals (excluding the detection signal of the clear switch 921). In this embodiment, N = 12. In the RAM 55, the addresses of the switch timers are arranged in the same order as the bit arrangement order of the input ports (the order from the top to the bottom shown in FIG. 15).

FIG. 26 is a flowchart showing an example of the switch process in step S21 in the game control process. The switch process is first executed in the game control process as shown in FIG. In the switch processing, the CPU 56 first inputs data input to the input port 0 (step S101). Then
"8" is set as the number of processes (step S102), and the address of the switch timer for the winning opening switch 33a is set in the pointer (step S103). Then, a switch check processing subroutine is called (step S104).

FIG. 27 is a flowchart showing a switch check processing subroutine. In the switch check processing subroutine, the CPU 56 sets the port input data, in this case, the input data from the input port 0 as a “comparison value” (step S121). Also, clear data (00) is set (step S1).
22). Then, the switch timer indicated by the pointer (the address of the switch timer is set) is loaded (step S123), and the comparison value is shifted to the right (from the upper bit to the lower bit) (step S123).
124). The data of the input port 0 is set as the comparison value. In this case, the detection signal of the winning opening switch 33a is pushed out by the carry flag.

If the value of the carry flag is "1" (step S125), that is, if the detection signal of the winning opening switch 33a is on, the value of the switch timer is incremented by 1 (step S127). If the value after the addition is not 0, the added value is returned to the switch timer (step S128,
S129). When the value after the addition becomes 0, the added value is not returned to the switch timer. That is, if the value of the switch timer has already reached the maximum value (255), the value is not increased further.

If the value of the carry flag is "0", that is, if the detection signal of the winning opening switch 33a is in an OFF state, clear data is set in the switch timer (step S126). That is, if the switch is off, the value of the switch timer returns to zero.

Thereafter, the CPU 56 adds 1 to the pointer (address of the switch timer) (step S130), and subtracts 1 from the number of processes (step S13).
1). If the number of processes is not 0, step S122
Return to Then, the processing of steps S122 to S132 is repeated.

The processes of steps S122 to S132 are repeated for the number of processes, that is, eight times. In the meantime, the detection signals of the switches input to the 8 bits of the input port 0 are sequentially turned on or off. A check process is performed, and if it is in the ON state, the value of the corresponding switch timer is incremented by one.

The CPU 56 executes the switch processing in step S
At 105, the data input to the input port 1 is input. Next, "4" is set as the number of processes (step S106), and the address of the switch timer for the winning ball count switch 301A is set in the pointer (step S107). Then, a switch check processing subroutine is called (step S108).

In the switch check processing subroutine,
Since the processing described above is performed, steps S122 to S
The process of step 132 is repeated for the number of processes, that is, four times. During that time, the detection signal of the switch input to the 4 bits of the input port 1 is sequentially checked to determine whether it is on or off, If it is in the ON state, the value of the corresponding switch timer is increased by one.

In this embodiment, since the game control process is started every 2 ms, the switch process is also executed once every 2 ms. Therefore, the switch timer is incremented by 1 every 2 ms.

FIGS. 28 to 30 are flowcharts showing an example of the prize ball processing in step S31 in the game control processing. In this embodiment, in the prize ball processing, prize port switches 33a, 24a, 29a,
30a, count switch 23 and starting port switch 1
It is determined whether or not 4a has been reliably turned on, and if turned on, control is performed so that a payout control command indicating the number of winning balls is sent to the payout control board 37. It is determined whether or not the switch has been securely turned on, and if turned on, processing such as controlling a predetermined payout control command to be sent to the payout control board 37 is performed.

In the prize ball processing, the CPU 56 sets “1” as an offset of the input determination value table (step S150), and sets “9” as an offset of the address of the switch timer (step S151). The offset “1” in the input determination value table (see FIG. 32) is
This means that the second data “50” in the input judgment value table is used. Each switch timer is shown in FIG.
Since the input ports are arranged in the same order as the bit order of the input ports shown in (1), the offset “9” of the address of the switch timer means that the switch timer corresponding to the full switch 48 is designated. Then, the switch-on check routine is called (step S152).

The input judgment value table is an RO in which a judgment value is set for each switch so that the number of consecutive ONs is detected and the switch is definitely judged to be turned ON.
This is the M area. FIG. 32 shows a configuration example of the input determination value table. As shown in FIG. 32, in the input determination value table, “2”, “50”, “250”, “30”,
Determination values of “250” and “1” are set. Also,
In the switch-on check routine, the judgment value set at the address determined by the start address of the input judgment value table and the offset value is compared with the value of the switch timer determined by the start address of the switch timer and the offset value. If so, for example, a switch-on flag is set.

One example of the switch-on check routine is shown in FIG. In the switch-on check routine, if the value of the switch timer corresponding to the full tank switch 48 matches the full tank switch-on determination value "50", the switch-on flag is set (step S153). (Step S
154). Although not explicitly shown in FIG. 28, when the value of the switch timer corresponding to the full tank switch 48 becomes 0, the full tank flag is reset.

The CPU 56 sets “2” as the offset of the input judgment value table (step S15).
6), “0A (H)” is set as the offset of the address of the switch timer (step S157). The offset “2” in the input determination value table means that the third data “250” in the input determination value table is used. Further, since each switch timer is arranged in the same order as the bit order of the input port shown in FIG. 15, the offset “0A (H)” of the address of the switch timer is designated by the switch timer corresponding to the out-of-ball switch 187. Means to be done. Then, the switch-on check routine is called (step S158).

In the switch-on check routine,
If the value of the switch timer corresponding to the out-of-ball switch 187 matches the out-of-ball switch-on determination value "250", the switch-on flag is set (step S1).
59), a ball out flag is set (step S16)
0). Although not explicitly shown in FIG. 28, a switch-off timer corresponding to the out-of-ball switch 187 is prepared, and when its value reaches 50, the out-of-ball flag is reset.

Then, the CPU 56 checks whether or not the payout is stopped (step S201). The dispensing stop state is a state after a dispensing stop state designation command, which is a dispensing control command for instructing the dispensing control board 37 to stop dispensing, is sent out. Is a state in which the payout stop flag is set. If it is not the payout stop state, it is checked whether the above-mentioned ball out-of-ball state flag or the full tank flag is turned on (step S202).

When either of them changes to the ON state,
Set the payout stop state flag (step S
203), a command transmission table relating to the payout stop state designation command is set (step S204), and a command set process is called (step S205). In step S204, the command transmission table (R
OM) is set as the address of the command transmission table. In the command transmission table relating to the payout stop state designation command, INT data to be described later, data of the first byte of the payout control command, and data of the second byte of the payout control command are set. In step S202, when one of the flags is already in the ON state and the other flag is in the ON state, the processing of steps S203 to S205 is not performed.

If the payout is stopped, it is checked whether both the out-of-ball state flag and the full tank flag have been turned off (step S206). When both are turned off, the payout stop flag is reset (step S207), and a command transmission table relating to the payable state designation command is set (step S207).
208), a command set process is called (step S209). In step S208, the head address of the command transmission table (ROM) storing the payout control command of the payable state designation command is set as the address of the command transmission table. In the command transmission table relating to the payout possible state designation command, INT data to be described later, data of the first byte of the payout control command, and data of the second byte of the payout control command are set.

Further, the CPU 56 sets "0" as an offset of the input judgment value table (step S22).
1), “0” is set as the offset of the address of the switch timer (step S222). The offset “0” of the input judgment value table means that the first data of the input judgment value table is used. Also, since the switch timers are arranged in the same order as the bit order of the input port shown in FIG. 15, the offset “0” of the address of the switch timer specifies the switch timer corresponding to the winning opening switch 33a. Means Also, “4” is set as the number of repetitions (step S223).
Then, the switch-on check routine is called (step S224).

In the switch-on check routine,
The CPU 56 sets the start address of the input determination value table (see FIG. 32) (Step S281). And
An offset is added to the address (step S28)
2) The switch-on determination value is loaded from the address after the addition (step S283).

Next, the CPU 56 sets the start address of the switch timer (step S284), adds an offset to the address (step S285), and loads the value of the switch timer from the address after the addition (step S286). Since each switch timer is arranged in the same order as the bit order of the input port shown in FIG. 15, the value of the switch timer corresponding to the switch is loaded.

Then, the CPU 56 compares the value of the loaded switch timer with the switch-on determination value (step S287). If they match, a switch-on flag is set (step 128).

In this case, in the switch-on check routine, if the value of the switch timer corresponding to the winning opening switch 33a matches the switch-on determination value "2", the switch-on flag is set (step S2).
25). The switch check-on routine is executed for the number of repetitions initially set (Steps S228 and S229) while the offset of the address of the switch timer is updated (Step S230).
After all, the winning opening switches 33a, 24a, 29a, 30a
, The value of the corresponding switch timer is compared with the switch-on determination value “2”.

When the switch-on flag is set, "10" is set in the ring buffer as the number of award balls to be paid out (step S226). Then, 10 is added to the value stored in the total prize ball storage buffer (step S22).
7). When data is written to the ring buffer, the write pointer is incremented. When data is written to the last area of the ring buffer, the write pointer is updated to point to the first area of the ring buffer.

The total prize ball number storage buffer is a buffer for storing the cumulative value of the prize ball number instructed to the payout control means (however, it is subtracted when the payout is made).
It is formed in the backup RAM. In this embodiment, when data is written to the ring buffer, addition processing is performed on the stored value of the total prize balls storage buffer, but a payout control command indicating the number of prize balls to be paid out is output to the output port. At the time of output, the process of adding the number of prize balls corresponding to the payout control command to be output to the value stored in the total prize ball storage buffer may be performed.

Next, the CPU 56 sets "0" as an offset of the input judgment value table (step S23).
1), "4" is set as the offset of the address of the switch timer (step S232). The offset “0” of the input judgment value table means that the first data of the input judgment value table is used. Further, since each switch timer is arranged in the same order as the bit order of the input port shown in FIG. 15, the offset “4” of the address of the switch timer indicates that the switch timer corresponding to the starting port switch 14a is designated. Means Then, the switch-on check routine is called (step S).
233).

In the switch-on check routine,
If the value of the switch timer corresponding to the starting port switch 14a matches the switch-on determination value "2", the switch-on flag is set (step S234). When the switch-on flag is set, "6" is set as the number of award balls to be paid out in the ring buffer (step S235). The value stored in the total prize balls storage buffer is 6
Is added (step S236).

Next, the CPU 56 sets "0" as an offset of the input judgment value table (step S24).
1), “5” is set as the offset of the address of the switch timer (step S242). The offset “0” of the input judgment value table means that the first data of the input judgment value table is used. Further, since each switch timer is arranged in the same order as the bit order of the input port shown in FIG. 15, the offset “5” of the address of the switch timer indicates that the switch timer corresponding to the count switch 23 is designated. means. Then, the switch-on check routine is called (step S).
243).

In the switch-on check routine,
If the value of the switch timer corresponding to the count switch 23 matches the switch-on determination value “2”, the switch-on flag is set (step S244). When the switch-on flag is set, "15" as the number of award balls to be paid out is set in the ring buffer (step S245). Also, 15 is added to the value stored in the total prize ball storage buffer (step S246).

If data exists in the ring buffer (step S247), the contents of the ring buffer indicated by the read pointer are set in the transmission buffer (step S248), and the value of the read pointer is updated (step S248). It is updated to point to the next area) (step S249), a command transmission table for the number of winning balls is set (step S250), and a command set process is called (step S251). The operation of the command set processing will be described later in detail.

In step S250, the head address of the command transmission table (ROM) in which the payout control command relating to the number of winning balls is stored is set as the address of the command transmission table. The command transmission table relating to the number of winning balls includes INT data (01
(H)), the first byte data (F
0 (H)) and the second byte of the payout control command. However, “80 (H)” is set as the data of the second byte.

As described above, when trying to output a payout control command instructing the number of winning balls from the game control means to the payout control board 37, the address setting of the command transmission table relating to the number of winning balls and the setting of the transmission buffer are performed. Is performed. Then, a payout control command is transmitted to the payout control board 37 based on the command transmission table relating to the number of winning balls and the setting contents of the transmission buffer by the command set processing. In step S247, it is possible to confirm whether or not there is data based on the difference between the write pointer and the read pointer. It may be confirmed whether or not.

Then, the content of the total prize balls storage buffer is 0.
If not, that is, if there is still a prize ball remaining, C
The PU 56 turns on the award ball payout flag (step S
252, S253).

When the award ball paying flag is on (step S254), the CPU 56 monitors the number of award balls actually paid out from the ball payout device 97 and stores the total number of award ball storage buffers. A winning ball number subtraction process of subtracting the value is performed (step S255). When the award ball paying flag changes from on to off, the lamp control board 3
5, a lamp control command instructing lighting of the prize ball lamp 51 is transmitted.

In this embodiment, even if the payout is stopped (steps S201 and S206), step S221 is performed.
To S251 are executed. That is, the game control means can send out a payout control command for instructing the number of winning balls even in the payout stop state. In other words, a command for instructing the number of winning balls is transmitted to the payout control means even in the payout stop state, and when the payout stop state is released, the payout ball payout can be started earlier. Further, the game control means does not require a large storage area for storing the number of winning balls based on winnings in the payout stop state.

Next, a method of transmitting a control command from the game control means to each electric component control means will be described. When an attempt is made to output a control command from the game control means to another electric component control board (sub board), the start address of a command transmission table is set. FIG.
FIG. 3A is an explanatory diagram illustrating a configuration example of a command transmission table. One command transmission table is composed of three bytes, and INT data is set in the first byte.
In the command data 1 of the second byte, MODE data of the first byte of the control command is set. Then, in the command data 2 of the third byte, EXT data of the second byte of the control command is set.

Although the EXT data itself may be set in the command data 2 area, the command data 2
May be set to data for specifying an address of a table in which EXT data is stored. For example, if bit 7 (work area reference bit) of command data 2 is 0, EX
Indicates that the T data itself is set. Such EXT data is data in which bit 7 is 0.
In this embodiment, if the work area reference bit is 1, it indicates that the contents of the transmission buffer are used as EXT data. If the work area reference bit is 1, the other 7 bits may be configured to indicate that it is an offset for specifying the address of the table in which the EXT data is stored.

FIG. 33B is an explanatory diagram showing an example of the configuration of the INT data. Bit 0 in the INT data is
Indicates whether or not a payout control command should be sent to the payout control board 37. If bit 0 is "1", it indicates that a payout control command should be sent. Therefore, the CPU 56
Sets "01 (H)" in the INT data in, for example, the prize ball processing (step S31 of the main processing). Bit 1 in the INT data indicates whether a display control command should be sent to the symbol display control board 80 or not. If bit 1 is "1", it indicates that a display control command should be sent. Therefore, the CPU 56 performs, for example, a special symbol command control process (step S27 of the main process).
, "02 (H)" is set in the INT data.

Bits 2 and 3 of the INT data are bits indicating whether or not a lamp control command and a sound control command are to be sent, respectively. The INT data, the command data 1 and the command data 2 are set in the command transmission table pointed to by the pointer in the symbol processing or the like. When these commands are transmitted, the corresponding bit of the INT data is set to “1”, and MOD is added to command data 1 and command data 2.
E data and EXT data are set.

In this embodiment, a ring buffer and a transmission buffer are prepared for the payout control command as shown in FIG. Then, in the prize ball processing, when the prize ball payout condition is satisfied, the number of prize balls according to the satisfied condition is sequentially set in the ring buffer. When sending out a payout control command relating to the number of winning balls,
One piece of data is transferred from the ring buffer to the transmission buffer. In the example shown in FIG. 33C, data corresponding to 12 payout control commands can be stored in the ring buffer. That is, there are 12 buffers. The number of buffers in the ring buffer may be a number corresponding to the number of winning ports for generating prize balls. This is because even in the case of simultaneous winning, data of a payout control command based on each winning can be stored.

FIG. 34 is an explanatory diagram showing an example of a command form of a control command sent from the main board 31 to another electric component control board. In this embodiment, the control command has a 2-byte configuration, the first byte represents MODE (classification of command), and the second byte represents EXT (type of command). The first bit (bit 7) of MODE data is always "1", and the first bit (bit 7) of EXT data is always "0". As described above, the control command, which is a command to the electric component control board, is composed of a plurality of data, and is in a form in which each can be distinguished by the first bit. The command form shown in FIG. 34 is an example, and another command form may be used. For example, a control command composed of one byte or three or more bytes may be used. FIG. 34 illustrates a payout control command sent to the payout control board 37,
Control commands sent to other electrical component control boards have the same configuration.

FIG. 35 shows 8-bit control signals CD0 to CD constituting a control command for each electric component control means.
FIG. 7 is a timing chart showing a relationship between the signal No. 7 and an INT signal. As shown in FIG. 35, when the period indicated by A elapses after the MODE or EXT data is output to the output port (any one of the output ports 1 to 4), the CPU 56 outputs the data output. INT which is a signal indicating
Set the signal to high level (ON data). When the period indicated by B elapses therefrom, the INT signal is set to low level (off data). Further, when there is data to be transmitted next, that is, after the MODE data is transmitted, the data of the second byte is transmitted to the output port after a period indicated by C. Regarding the data of the second byte, the periods of A and B are the same as the case of the first byte.
Thus, the capture signal is output for each of the MODE and EXT data.

The period A is a period for the CPU 56 to prepare for sending a command, that is, a period required for processing to set a sending command in the buffer, and a period for stabilizing data on the control signal line. That is, after the control signals CD0 to CD7 are output on the control signal line, an INT signal is output as a capture signal after a lapse of a predetermined period (period A: a part of the off output period). Also,
The period B (ON output period) is a period for stabilizing the INT signal. The period C (a part of the off-output period) is a period set so that the electric component control means can reliably take in data. In periods B and C,
The data on the signal line does not change. That is, the data output is maintained until the periods B and C elapse.

In this embodiment, the payout control command to the payout control board 37, the display control command to the symbol control board 80, the lamp control command to the lamp control board 35, and the sound control command to the sound control board 70 are: It is transmitted using the same command transmission processing routine (common module). Therefore, the period of B and C, that is, the period from the rise of the INT signal relating to the first byte to the start of transmission of the second byte of data, is longer than the reception processing time of the electric component control means which takes the longest time for command reception processing. Is also set to be longer.

Each electric component control means detects that the INT signal has risen, and starts a process of fetching 1-byte data by, for example, an interrupt process.

Since the periods B and C are longer than the reception processing time of the electric component control means which takes the longest time for the command reception processing, the game control means controls the command transmission processing for each electric component control means by the common module. However, any of the electric component control means can reliably receive the control command from the game control means.

When a predetermined period elapses after the execution of the INT signal output processing, the CPU 56 is ready to transmit the next data. During the predetermined period (B and C periods),
It is longer than the period (period A) from sending the data before the T signal output process to starting to output the INT signal. As described above, the period A is a stabilization period in the command signal line, and the periods B and C are periods for securing the time required for the receiving side to capture data. Therefore, by making the period A shorter than the periods B and C, it is possible to obtain an effect that the receiving-side electric component control means can reliably receive a command, and complete the transmission of one command. This also has the effect of shortening the time required.

FIG. 36 is an explanatory diagram showing an example of the content of the payout control command. In the example shown in FIG.
Command F of ODE = FF (H) and EXT = 00 (H)
F00 (H) is a payout control command (payout possible state designation command) indicating that payout is possible. M
Command F of ODE = FF (H) and EXT = 01 (H)
F01 (H) is a payout control command (payout stop state designation command) indicating that the payout should be stopped.
It is. Also, the command F0X of MODE = F0 (H)
X (H) is a payout control command for specifying the number of winning balls. "XX" which is EXT indicates the number of payouts.

When the payout control means receives the payout control command of FF01 (H) from the game control means of the main board 31, the payout control means stops the prize ball payout and the ball lending.
When the payout control command of (H) is received, it becomes possible to pay out prize balls and lend a ball. Further, when a payout control command specifying the number of winning balls is received, prize ball payout control according to the number specified by the received command is performed.

Note that the payout control command is sent only once so that the payout control means can recognize it. Recognizable means that the level of the INT signal changes in this example, and sent only once so as to be recognizable means that in this example the first and second bytes of the payout control signal Accordingly, the INT signal is output only once in a pulse form (rectangular wave form).

Control commands to each electric component control board are
When outputting to the corresponding output port (output ports 1 to 4), any one of the bits 0 to 3 of the output port 0 becomes "1" (high level) for a predetermined period. Correspond to the bit arrangement at the output port 0. Therefore, when sending a control command to each electric component control board, it is possible to easily output an INT signal based on the INT data.

FIG. 37 is a flowchart showing an example of the command setting process (steps S205, S209, S251). The command set process is a process including a command output process and an INT signal output process. In the command set processing, the CPU 56 first saves the address of the command transmission table (the contents of the pointer as the transmission signal instruction means) in a stack or the like (step S3).
31). Then, the INT data of the command transmission table pointed to by the pointer is loaded into the argument 1 (step S332). Argument 1 is input information for a command transmission process described later. Further, the address indicating the command transmission table is incremented by 1 (step S333). Therefore,
The address indicating the command transmission table matches the address of the command data 1.

Then, the CPU 56 sets the command data 1
Is read and set as argument 2 (step S334).
The argument 2 also becomes input information for a command transmission process described later. Then, a command transmission processing routine is called (step S335).

FIG. 38 is a flowchart showing a command transmission processing routine. In the command transmission processing routine, the CPU 56 first sets the data set in the argument 1, ie, the INT data, in the work area determined as the comparison value (step S351).
Next, the number of transmissions = 4 is set in the work area determined as the number of processes (step S352). Then, the address of the port 1 for outputting the payout control signal is set to the IO address (step S353). In this embodiment, the address of port 1 is the address of an output port for outputting a payout control signal. The addresses of ports 2 to 4 are the addresses of output ports for outputting display control signals, lamp control signals, and audio control signals.

Next, the CPU 56 shifts the comparison value one bit to the right (step S354). It is determined whether or not the carry bit has become 1 as a result of the shift processing (step S355). The fact that the carry bit has become 1 means that the rightmost bit in the INT data is “1”.
It means that it was. In this embodiment, four shift processes are performed. For example, when it is specified that a payout control command should be sent, the carry bit becomes 1 in the first shift process.

When the carry bit becomes 1, the data set in the argument 2, that is, the command data 1 (that is, MODE data) is output to the address set as the IO address (step S3
56). When the first shift process is performed, the port 1 address is set in the IO address. At this time, the MODE data of the payout control command is
Is output to

Next, the CPU 56 sets the IO address to 1
While adding (step S357), 1 is subtracted from the number of processes (step S358). If the port 1 is indicated before the addition, the IO address is set to the address of the port 2 by the addition processing for the IO address. Port 2 is a port for outputting a display control command. Then, the CPU 56 checks the value of the number of processes (step S359), and if the value is not 0,
It returns to step S354. The shift process is performed again in step S354.

In the second shift processing, the value of bit 1 in the INT data is pushed out, and the carry flag becomes "1" or "0" according to the value of bit 1. Therefore,
A check is made as to whether it is specified that a display control command should be sent. Similarly, by the third and fourth shift processes, it is checked whether or not it is specified that the lamp control command and the sound control command should be transmitted. As described above, when each shift process is performed, the IO address corresponding to the control command (payout control command, display control command, lamp control command, sound control command) checked by the shift process is included in the IO address. Is set.

Therefore, when the carry flag becomes "1", the corresponding output port (port 1 to port 4)
Is sent to the control command. That is, a single common module can perform a process of transmitting a control command to each electric component control unit.

As described above, since it is determined which electrical component control means should output the control command only by the shift processing, it is determined which electrical component control means should output the control command. Processing has been simplified.

Next, the CPU 56 reads the contents of the argument 1 storing the INT data before the start of the shift processing (step S360), and outputs the read data to the port 0 (step S361). In this embodiment,
The port 0 address is a port for outputting an INT signal for each control signal.
To 4 are a payout control INT signal and a display control IN, respectively.
A port for outputting a T signal, a lamp control INT signal, and a sound control INT signal. In the INT data, the bit corresponding to the output bit of the INT signal corresponding to the control command (payout control command, display control command, lamp control command, sound control command) output in the processing of steps S351 to S359 becomes “1”. Has become. Therefore,
The INT signal corresponding to the control command (payout control command, display control command, lamp control command, sound control command) output to any of the ports 1 to 4 becomes high level.

Next, the CPU 56 sets a predetermined value in the weight counter (step S362), and decrements by one until the value becomes 0 (steps S363 and S36).
4). This process is a process for setting the period B shown in FIG. When the value of the wait counter becomes 0, clear data (00) is set (step S36).
5), and outputs the data to port 0 (step S3)
66). Therefore, the INT signal becomes low level. Then, a predetermined value is set in the weight counter (step S3).
62), and decrement by 1 until the value becomes 0 (steps S368, S369). This process is a process for setting the period C shown in FIG. However, the actual period of C is the time created in steps S367 to S369, and the subsequent processing time (if MODE data is output at this time, the time required for control required until EXT data is output). ) Is added. Thus, by setting the period of C,
Even when commands are continuously transmitted, a predetermined period is set between the completion of output of one command and the start of transmission of the next command. Can easily identify the breaks in successive commands, and each command is reliably received.

Therefore, the value set in the wait counter in step S367 is such that the period of C is a period long enough for all the electric component control means to receive the control command to reliably execute the command receiving process. Value. The value set in the wait counter is such that the period of C is
This value is longer than the time required for the processing in steps S357 to S359 (corresponding to the period A). Note that A
If it is desired to make the period A longer, a wait process for creating the period A (for example, a process of setting a predetermined value in the weight counter and performing subtraction until the value of the weight counter becomes 0) is performed.

As described above, the MODE data of the first byte of the control command is transmitted. Therefore, CPU5
No. 6 adds 1 to the value indicating the command transmission table in step S336 shown in FIG. Therefore, the area of the command data 2 in the third byte is specified. The CPU 56
The contents of the indicated command data 2 are loaded into the argument 2 (step S337). Further, it is determined whether the value of bit 7 (work area reference bit) of the command data 2 is “0” (step S339). If it is not 0, the contents of the transmission buffer are loaded into argument 2 (step S341). If the extended data is used when the value of the work area reference bit is "1", the start address of the command extended data address table is set in the pointer, and the command data is stored in the pointer. The address is calculated by adding the values of bit 6 to bit 0 of 2. Then, the data of the area indicated by the address is loaded into the argument 2.

Since data that can specify the number of winning balls is set in the transmission buffer, the data is set in argument 2. If the extended data is used when the value of the work area reference bit is “1”, the command extended data address table contains
EXT data that can be sent to the electric component control means is sequentially set. Therefore, if the value of the work area reference bit is “1”, the EXT data in the command extension data address table corresponding to the contents of the command data 2 is loaded into the argument 2.

Next, the CPU 56 calls a command transmission processing routine (step S342). Therefore, M
EXT at the same timing as when sending ODE data
Data is sent.

As described above, the 2-byte control command (dispensing control command, display control command, lamp control command, sound control command) is transmitted to the corresponding electric component control means. When the electric component control means detects the rise of the INT signal, the control command fetch process is started. In any of the electric component control devices, a new signal from the game control means is output before the fetch process is completed. There is no output on the line. That is, a reliable command receiving process is performed in each electric component control unit. In addition, each electric component control means is IN
The control command capturing process may be started at the falling edge of the T signal. Also, the polarity of the INT signal may be reversed from that shown in FIG.

In this embodiment, in the prize ball processing, when the prize ball payout condition is satisfied, data capable of specifying the number of prize balls is stored in a ring buffer capable of storing a plurality of data at the same time. Is sent, the data in the ring buffer area pointed to by the read pointer is transferred to the transmission buffer. Therefore, even if a plurality of prize ball payout conditions are satisfied at the same time, the data that can specify the number of prize balls based on the satisfaction of these conditions is stored in the ring buffer, so that the command output processing based on the satisfaction of each condition does not cause any problem. Be executed.

Further, in this embodiment, both a payout stop state designation command or a payout possible state designation command and a command indicating the number of winning balls can be transmitted in one winning ball processing. That is, 1 which is activated every 2 ms
A plurality of commands can be transmitted within one control period. In this embodiment, a plurality of ring buffers are prepared for each control command (display control command, lamp control command, sound control command, and payout control command) to each control means. When data capable of specifying a control command is set in the ring buffer of the control command, the lamp control command, and the sound control command, a plurality of display control commands, lamp control commands, and sound control commands are processed in one command control process. Can also be configured to be transmitted. That is, a plurality of control commands can be sent out simultaneously (meaning in the start cycle of the game control process, that is, the 2 ms timer interrupt process). Since such control commands are transmitted at the same time during the progress of the game effect, it is convenient to have such a configuration. However, since the payout control command is generated independently of the progress of the game effect, the display control command,
It is not sent simultaneously with the lamp control command and the sound control command.

FIG. 39 is a flowchart showing an example of the prize ball number subtraction processing. In the prize ball number subtraction process, C
The PU 56 first loads the value stored in the total prize balls storage buffer (step S381). Then, it is determined whether or not the stored value is 0 (step S382). If it is 0, the process ends.

If it is not 0, the switch timer for the prize ball count switch is loaded (step S383), and the loaded value is compared with the ON determination value (in this case, "2") (step S384). If they match (step S38)
5) Assuming that the prize ball count switch 301A has certainly turned on, that is, one game ball has surely
7, the value stored in the total prize balls storage buffer is decremented by one (step S386).

Also, the value of the award ball information counter is incremented by 1 (step S387). If the value of the prize ball information counter is 10 or more (step S388), the value of the prize ball information output counter is incremented by one (step S38).
9), the value of the prize ball information counter is reduced by -10 (step S)
390). The value of the prize ball information output counter is shown in FIG.
Is referred to in the information output process (step S29) in the game control process shown in (1), and if the value is 1 or more, 1 as a prize ball signal (bit 7 of output port 5: see FIG. 14)
A pulse is output. Therefore, in this embodiment, 1
Each time 0 game balls are paid out as prize balls, one prize ball signal is output outside the gaming machine.

When the value stored in the total prize ball storage buffer becomes 0 (step S391), the flag for paying out prize balls is cleared (step S392), and in order to notify that there is no remaining prize ball, After setting command data indicating the turning off of the prize ball lamp 51 in the command transmission table for the lamp control command (step S393), a lamp control command transmission process is executed (step S394).

Next, payout control means will be described as an example of electric component control means other than the game control means.

FIG. 40 is a block diagram showing an example of a configuration around the payout control CPU 371. As shown in FIG. As shown in FIG. 40, the power-off signal from the power supply monitoring circuit (power supply monitoring means) of the power supply board 910 is connected to the non-maskable interrupt terminal (XNMI terminal) of the payout control CPU 371 via the buffer circuit 960. I have. Therefore, the payout control CPU 37
1 can confirm that power supply to the gaming machine has stopped due to the non-maskable interrupt process.

CLK / TRG of payout control CPU 371
The INT signal from the main board 31 is connected to the two terminals. When a clock signal is input to the CLK / TRG2 terminal, the value of the timer counter register CLK / TRG2 incorporated in the payout control CPU 371 is counted down. When the register value becomes 0, an interrupt occurs. Therefore, the timer counter register CLK / TRG
If the initial value of 2 is set to "1", an interrupt occurs in response to the input of the INT signal.

The payout control board 37 is also equipped with a system reset circuit 975. In this embodiment,
Reset IC 97 in system reset circuit 975
Reference numeral 6 indicates that when the power is turned on, the output is set to the low level for a predetermined time determined by the capacity of the external capacitor, and the output is set to the high level after the predetermined time has elapsed. Also, reset IC 9
The monitor 76 monitors the power supply voltage of VSL, and sets the output to a low level when the voltage value falls below a predetermined value (for example, +9 V). Therefore, when the power supply to the gaming machine is stopped, the reset IC 9
When the signal from 76 goes low, the payout control CPU 371 is reset.

The predetermined value for the reset IC 976 to detect the stop of the power supply is lower than the normal voltage, but is a voltage at which the payout control CPU 371 can operate for a while. Further, the reset IC 976 is connected to the payout control CPU 3.
Since it is configured to monitor a voltage higher than the voltage required by 71 (+5 V in this example), the monitoring range for the voltage required by the payout control CPU 371 can be expanded. Therefore, more precise monitoring can be performed. Note that the system reset circuit 975 corresponds to a second power supply monitoring unit.

While power is not being supplied from the + 5V power supply, at least a part of the built-in RAM of the payout control CPU 371 is backed up by connecting a backup power supply supplied from the power supply board to the backup terminal, so that power supply or the like can be prevented. The contents are preserved even if the power supply to the gaming machine is stopped. Then, when the + 5V power supply is restored, a reset signal is issued from the system reset circuit 975, so that the payout control CPU 371 returns to the normal operation state. At that time, since the necessary data is backed up, it is possible to restore the dispensing control state at the time of the power failure at the time of recovery from a power failure or the like.

In the configuration shown in FIG. 40, when power is turned on, system reset circuit 975 outputs a low level for a period determined by the capacitance of the capacitor, and then outputs a high level. That is, the reset release timing is only once. However, as in the case of the main substrate 31 shown in FIG. 9, a circuit configuration in which a plurality of reset release timings occur may be used.

FIG. 41 is an explanatory diagram showing the assignment of output ports in this embodiment. As shown in FIG. 41, the output port C (address 00H) is
An output port for driving signals and the like output to 89. The output port D (address 01H) is an output port for a display control signal output to the error display LED 374, which is a 7-segment LED. And the output port E
(Address 02H) is a drive signal output to the distribution solenoid 310 and EX to the card unit 50.
This is an output port for outputting the S signal and the PRDY signal.

FIG. 42 is an explanatory diagram showing bit assignment of input ports in this embodiment. As shown in FIG. 42, the input port A (address 06H) is an input port for receiving an 8-bit payout control signal of the payout control command sent from the main board 31. The detection signals of the prize ball count switch 301A and the ball lending count switch 301B are input to bits 0 to 1 of the input port B (address 07H), respectively. Bits 2 to 5 include a BRDY signal, a BRQ signal, a VL signal, and a clear switch 921 from the card unit 50.
Is input.

FIG. 43 shows the payout control means (payout control CP).
It is a flowchart which shows main processing of U371 and peripheral circuits, such as ROM and RAM. In the main process, the payout control CPU 371 first makes necessary initial settings. That is, the payout control CPU 371 first sets interrupt prohibition (step S701). Next, the interrupt mode is set to the interrupt mode 2 (step S702), and a stack pointer designated address is set to the stack pointer (step S703). The payout control CPU 37
1 initializes a built-in device register (step S704), and initializes CTC and PIO (step S704).
After performing step 705), the RAM is set in an accessible state (step S706).

In this embodiment, one channel of the built-in CTC is used in the timer mode. Therefore,
In the internal device register setting process in step S704 and the process in step S705, a register setting for setting a channel to be used to the timer mode, a register setting for permitting interrupt generation, and a register for setting an interrupt vector The settings are made. Then, the interruption by the channel is used as a timer interruption. When it is desired to generate a timer interrupt every 2 ms, for example, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value.

The interrupt vector set for the channel set in the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt processing. Specifically, the start address of the timer interrupt processing is specified by the value set in the I register and the interrupt vector.
In the timer interrupt process, a payout control process is executed.

Another one of the built-in CTCs (channel 2 in this embodiment) is used as an interrupt generation channel for receiving a payout control command from the game control means. Is used in the counter mode. Therefore, in the setting processing of the internal device register in step S704 and the processing in step S705, the register setting for setting the channel to be used to the counter mode, the register setting for permitting the interrupt generation, and the interrupt vector setting are performed. Is set.

The interrupt vector set for the channel (channel 2) set in the counter mode corresponds to the head address of the command reception interrupt process described later.
Specifically, the start address of the command reception interrupt process is specified by the value set in the I register and the interrupt vector.

In this embodiment, the payout control CPU 3
At 71, the interrupt mode 2 is set. Therefore, the built-in CT
An interrupt process based on the count-up of C can be used. Further, it is possible to set an interrupt processing start address according to the interrupt vector transmitted by the CTC.

The interrupt based on the count up of the channel 2 (CH2) of the CTC is an interrupt generated when the value of the timer counter register CLK / TRG2 becomes "0". Therefore, for example, in step S705, the timer counter register C as a specific register
The initial value “1” is set in LK / TRG2. further,
The count value of the timer counter register CLK / TRG2 as a specific register is decremented by -1 at the rise or fall of the signal input to the CLK / TRG2 terminal. You can make a selection. In this embodiment, at the rising edge of the signal input to the CLK / TRG2 terminal, the timer / counter register CLK / TRG
A setting is made so that the count value of 2 is decremented by one.

The interrupt based on the count up of channel 3 (CH3) of the CTC is an interrupt generated when the internal clock (system clock) of the CPU is counted down and the register value becomes "0", and will be described later. 2m to do
Used as s timer interrupt. Specifically, the CPU 3
A clock obtained by dividing the operation clock of 71 is supplied to the CTC, and the value of the register is subtracted by the input of the clock. When the value of the register becomes 0, a timer interrupt occurs.
For example, the register value of CH3 is 1 / system clock.
It is subtracted in 256 cycles. Since the subtraction is performed based on the divided clock, the initial value of the register does not increase. In step S705, a value corresponding to 2 ms is set as an initial value in the register of CH3.

The priority of the CTC interrupt based on the count-up of CH2 is higher than the priority of the interrupt based on the count-up of CH3. Therefore, when the count-up occurs at the same time, an interrupt based on the count-up of CH2,
That is, the interrupt that triggers the execution of the command reception interrupt process has priority.

Next, the payout control CPU 371 checks the state of the output signal of the clear switch 921 inputted via the input port B (see FIG. 42) only once (step S707). In the case where the ON is detected in the confirmation, the payout control CPU 371 executes a normal initialization process (steps S711 to S713). When the clear switch 921 is on (when pressed), a low-level clear switch signal is output. In the input port 372, the ON state of the clear switch signal is at a high level. Further, the payout control means does not have to perform the determination in step S707.

In the same manner as the CPU 56 of the main board 31, the payout control CPU 371, when performing the ON determination of the switch detection signal, has at least two ON states, for example.
ms (when the detection signal is turned on immediately before the detection in the first processing of the processing started every 2 ms), the switch is not considered to be turned on unless it is continued. However, when the clear switch 921 is detected to be turned on, one switch is performed. ON / OFF is determined by the ON determination. That is, it is determined whether or not the clear switch 921 as the operating means is in a predetermined operation state.
The initialization request detection determination period for determination by U371 is
The period is different from the game medium detection determination period for determining that the prize ball count switch or the like as the game medium detection means has detected the game medium.

If the clear switch 921 is not on, the payout control CPU 371 checks whether backup data exists in the payout control backup RAM area (step S708). For example, similarly to the processing of the CPU 56 of the main board 31, it is confirmed whether or not backup data exists by determining whether or not a backup flag that is set when power supply to the gaming machine is stopped is set. If the backup flag is set, it is determined that there is backup data.

After confirming that there is a backup, the payout control CPU 371 checks the data in the backup RAM area (parity check in this example). When the power supply is restored after the power supply is stopped due to an unexpected power failure or the like, the data in the backup RAM area should have been saved, and the check result becomes normal. If the check result is not normal, the internal state cannot be returned to the state at the time of stopping the power supply. Therefore, an initialization process executed at the time of power-on, not at the time of recovery from a shortage of power failure or the like, is executed.

If the check result is normal (step S
709), the payout control CPU 371 performs a payout state restoring process for returning the internal state to the state at the time of stopping power supply (step S710). Then, the process returns to the address indicated by the PC (program counter) stored in the backup RAM area.

In the initialization processing, the payout control CPU 371
Performs RAM clear processing first (step S71).
1). A CTC provided in the payout control CPU 371 so that a timer interrupt is periodically performed every 2 ms.
Are set (step S712). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value. Since the interrupt is prohibited in step S701 of the initial setting process, the interrupt is permitted before the initialization process is completed (step S713).

In this embodiment, the payout control CPU 3
The built-in CTC 71 is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is 2
ms. And when a timer interrupt occurs,
As shown in FIG. 44, a timer interrupt flag indicating that a timer interrupt has occurred is set (step S772).
Then, when it is detected in the main processing that the timer interrupt flag is set (step S714), the timer interrupt flag is reset (step S714).
751), payout control processing (steps S751 to S76)
0) is executed.

In the timer interrupt, as shown in FIG. 44, the interrupt is initially set to the permission state (step S77).
1). Therefore, during the timer interrupt process, the interrupt is permitted, and the payout control command receiving process based on the input of the INT signal can be executed with priority.

In the payout control processing, the payout control CPU
Reference numeral 371 denotes a prize ball count switch 301A or a ball lending count switch 3 input to the input port 372b.
It is determined whether a switch such as 01B has been turned on (switch processing: step S752).

Next, the payout control CPU 371 sets the payout stop state when the payout stop state designation command is received from the main board 31, and releases the payout stop state when the payout possible state designation command is received. (Payout stop state setting processing: step S753). Further, it analyzes the received payout control command and executes a process according to the analysis result (command analysis execution process: step S754). Further, a prepaid card unit control process is performed (step S755).

Next, the payout control CPU 371 performs control to pay out the lent ball in response to the ball lending request (step S756). At this time, the payout control CPU 371 sets the ball distribution member 311 to the ball lending side by the distribution solenoid 310.

Furthermore, the payout control CPU 371 performs a prize ball control process of paying out the prize balls of the number stored in the total number storage (step S757). At this time, the payout control CPU 371 sets the ball distribution member 311 to the winning ball side by the distribution solenoid 310. And output port 3
A drive signal is output to the payout motor 289 in the payout mechanism of the ball payout device 97 via the relay board 72c and the relay board 72, and a payout motor control process for rotating the payout motor 289 by a predetermined number of revolutions is performed (step S758). .

In this embodiment, the delivery motor 2
A stepping motor is used as 89, and a 1-2 phase excitation method is used to control them. Therefore,
Specifically, in the payout motor control processing, eight types of excitation pattern data are repeatedly output to the payout motor 289. In this embodiment, each excitation pattern data is output for 4 ms.

Next, error detection processing is performed, and a predetermined display is made on the error display LED 374 according to the result (error processing: step S759). In addition, processing such as outputting a ball lending number signal output to the outside of the gaming machine is performed (output processing: step S760).

The output port C shown in FIG. 41 is connected to the payout motor control processing (step S75) in the payout control processing.
8) is accessed. The output port D is accessed in an error process (step S759) in the payout control process. The output port E is accessed in the ball lending control process (step S756) and the prize ball control process (step S757) in the payout control process.

FIG. 45 is a flowchart showing an example of the payout state restoring process in step S710. In the payout state restoring process, the payout control CPU 371 first performs a stack pointer return process (step S73).
1). The value of the stack pointer is saved in a predetermined RAM area (power is backed up) in a power supply stop process described later. Therefore, step S7
At 31, the value is restored by setting the value of the RAM area to the stack pointer. The register value and the value of the program counter (PC) when the power supply is stopped are saved in the area pointed to by the restored stack pointer (that is, the stack area).

Next, the payout control CPU 371 clears the backup flag (step S732), that is, resets a flag indicating that a predetermined memory protection process was executed when the power supply was stopped last time. Further, the saved values of the various registers are read from the stack area and set in the various registers (step S733). That is,
Performs register restoration processing. If the parity flag is not turned on, the interrupt is permitted (step S
732, S735). Finally, the AF register (accumulator and flag register) is restored from the stack area (step S736).

Then, the RET instruction is executed, but the return destination here is not the part that called the payout state restoration processing. This is because the stack pointer is restored in step S731, and the return address stored in the stack area pointed to by the restored stack pointer is the address where the NMI occurred when the power supply was stopped last time in the program. Therefore, the RET instruction following step S736 returns to the address where the NMI occurred when the power supply was stopped. That is, restoration control is performed based on the address saved in the stack area.

FIGS. 46 and 47 are flow charts showing an example of the non-maskable interrupt processing (NMI processing: power supply stop processing) executed in response to a power-off signal from the power supply board 910.

In the power supply stop processing, the payout control CPU 371 stores the AF register in the predetermined backup R
Save to the AM area (step S801). Further, the interrupt flag is copied to the parity flag (step S80).
2). The parity flag is formed in the backup RAM area. The interrupt flag is a flag indicating whether the interrupt is enabled or disabled, and is in a control register incorporated in the payout control CPU 371. The ON state of the interrupt flag indicates that the interrupt is prohibited. As described above, the parity flag is referred to in the game state restoration processing. Then, in the payout state restoration processing, if the parity flag is in the ON state, the interrupt permission state is not set.

Also, BC register, DE register, HL
The registers, the IX register, and the stack pointer are saved in the backup RAM area (Steps S804 to S804)
08).

Next, the backup specified value (in this example, “55H”) is stored in the backup flag. The backup flag is formed in the backup RAM area. Next, the same processing as the processing of the CPU 56 of the main board 31 is performed to create parity data, and the backup R
The data is stored in the AM area (steps S810 to S819).
Then, an access prohibition value is set in the RAM access register (step S820). Thereafter, the internal RAM cannot be accessed.

Further, the payout control CPU 371 sets the clear data (00) in an appropriate register (step S821), and sets the number of processes ("3" in this example) in another register (step S822). Further, the address of the output port C (“00H” in this example) is set in the IO pointer (step S823). Yet another register is used as the IO pointer.

Then, clear data is set at the address pointed to by the IO pointer (step S82).
4), increment the value of the IO pointer by 1 (step S82)
5), the value of the number of processes is subtracted by 1 (step S827).
If the value of the number of processes is 0 in the processes of steps S824 to S826,
Repeat until. As a result, clear data is set to all output ports CE (see FIG. 41). As shown in FIG. 41, in this example, "1" is on, and "00", which is clear data, is set for each output port, so that all output ports are off.

Therefore, after the processing for saving the control state (in this example, generation of the checksum and prevention of RAM access) is performed, each output port is immediately turned off. Therefore, the process of generating a checksum indicating whether or not the content is correctly stored and the process of preventing RAM access for preventing the content from being rewritten correspond to the process for storing the payout control state.

Since the output ports are turned off immediately after the processing for saving the control state is executed, it is possible to reliably prevent a situation in which the game state does not match the saved game state. In addition, since the output port can be cleared during the power supply stop processing before the driving of the electric component is disabled, the control is performed by the payout control unit before the driving of the electric component is disabled. Each electrical component,
An appropriate operation stop state can be achieved. For example, after the operation of the electric components is stopped, such as by stopping the operation of the payout motor 289 in the driving state, the driving of the electric components can be disabled. Therefore, it is possible to wait for restoration of power supply in an appropriate stop state.

Upon completion of the clearing process for the output port, the payout control CPU 371 enters a standby state (loop state). Therefore, nothing is done until the system is reset.

FIG. 48 is an explanatory diagram showing an example of use of the RAM incorporated in the payout control CPU 371. In this example,
In the backup RAM area, a total number storage (for example, 2 bytes) and a rental ball number storage are respectively formed.
The total number storage stores the total number of awarded ball payouts instructed from the main board 31 side. The rental ball number storage stores the number of unpaid ball rentals. In addition,
R storing data used in the payout control process
All the AM areas may be backed up by power.

When the payout control CPU 371 receives a payout control command indicating the number of prize balls from the game control means in, for example, the prize ball control process (step S757), the payout control CPU 371 stores the specified number in the total number storage. Increase. In the ball lending control process (step S756), the content is increased in the lending ball number storage by one unit (for example, 25) each time a ball lending request signal is received from the card unit 50. Further, the payout control CPU 3
71 is a prize ball count switch 3 in the prize ball control processing.
When 01A detects one prize ball payout, the value of the total number storage is reduced by one, and when the ball lending count switch 301B detects one lending ball payment in the ball lending control processing, the value of the lending ball number storage is reduced by one.

Therefore, the number of unpaid prize balls and the number of loaned balls are equal to the number of backup RAs that can hold the contents for a predetermined period.
It will be stored in the M area. Therefore, even if an unexpected power supply stop such as a power failure occurs, if the power supply is restored within a predetermined period, the prize ball processing and the ball lending processing can be restarted based on the contents stored in the backup RAM area. That is, even if the power supply to the gaming machine is stopped, if the power supply is resumed, the payout is performed based on the number of unpaid prize balls and the number of loaned balls at the time of the power supply stop, and is given to the player. The disadvantage can be reduced.

FIG. 49 is an explanatory diagram showing an example of the configuration of a receiving buffer for storing the payout control command received from the main board 31. In this example, a ring buffer type receiving buffer capable of storing six payout control commands having a 2-byte configuration is used. Accordingly, the reception buffer is configured by a 12-byte area of the reception command buffers 1 to 12. Then, a command reception number counter indicating in which area the received command is stored is used. The command reception number counter takes a value from 0 to 11.

FIG. 50 is a flowchart showing a payout control command receiving process by the interrupt process. An INT signal for payout control from the main board 31 is supplied to a payout control CPU 371.
Are input to the CLK / TRG2 terminal. Therefore, when the INT signal from the main board 31 rises, the payout control CPU 371 is interrupted, and the processing of receiving the payout control command shown in FIG. 50 is started. The payout control CP
U371 is a CPU having a structure in which, when an interrupt occurs, a maskable interrupt does not further occur unless the interrupt is permitted by software.

Here, the command reception processing of the payout control means will be described, but the same command reception processing is executed in the display control means, the lamp control means and the sound control means. In this embodiment, CLK /
The initialization was performed such that the value of the timer counter register CLK / TRG2 is decremented by 1 when the input of the TRG2 terminal rises, that is, the initialization was performed such that an interrupt occurs at the rise of the INT signal. CLK / TRG
When the input of two terminals falls, the timer counter register C
Initial setting may be performed such that the value of LK / TRG2 is set to −1. In other words, initialization may be performed such that an interrupt occurs at the falling edge of the INT signal.

That is, if an interrupt is generated at the level change timing (edge) of the pulse (rectangular wave) INT signal as the capture signal, the edge may be a rising edge or a falling edge. There may be. In any case, the configuration is such that an interrupt occurs at the level change timing (edge) of the pulse (rectangular wave) INT signal as the capture signal. By doing so, it becomes possible to receive a command as soon as possible when the command fetch is instructed. In addition, period A (FIG. 3)
Since the output of the INT signal is on standby until 5) elapses, the output state of the command data on the lines of the control signals CD0 to CD7 is stable when the INT signal is output.
Therefore, the payout control command is favorably received by the payout control means.

In the receiving process of the payout control command, the payout control CPU 371 first saves each register in the stack (step S850). Next, the input port 3 assigned to the input of the payout control command data
Data is read from 72a (see FIG. 10) (step S851). Then, it is confirmed whether or not this is the first byte of the payout control command having the 2-byte structure (step S).
852). Whether it is the first byte or not is confirmed by whether or not the first bit of the received command is “1”. The first bit should be “1” in the MODE byte (first byte) of the payout control command having a 2-byte configuration (see FIG. 34). Therefore, if the first bit is “1”, the payout control CPU 371 determines that a valid first byte has been received, and stores the received command in the reception command buffer indicated by the command reception number counter in the reception buffer area (step). S85
3).

If it is not the first byte of the payout control command, it is confirmed whether or not the first byte has already been received (step S854). Whether or not the data has already been received is confirmed based on whether or not valid data is set in the reception buffer (reception command buffer).

When the first byte has already been received,
It is checked whether the first bit of the received 1 byte is “0”. And if the first bit is “0”,
Assuming that the valid second byte has been received, the received command is stored in the reception command buffer indicated by the command reception number counter + 1 in the reception buffer area (step S855). The first bit should be “0” in the EXT byte (second byte) of the payout control command having the 2-byte structure (see FIG. 34). If it is determined in step S854 that the first byte has already been received, the process ends if the first bit of the data received as the second byte is not “0”. If "N" is determined in step S854, the process of step S856 is not performed, and the next received command is stored in the buffer area where the command received this time should have been stored. You.

In step S855, when the command data of the second byte is stored, 2 is added to the command reception number counter (step S856). Then, it is checked whether or not the command reception counter is 12 or more (step S857), and if it is 12, the command reception number counter is cleared (step S858). After that, the saved register is restored (step S859),
Finally, interrupt permission is set (step S859).

[0296] During the command reception interrupt process, the interrupt is prohibited. As described above, the interrupt is permitted during the 2 ms timer interrupt process. Therefore, if a command reception interrupt occurs during the 2 ms timer interrupt, the command reception interrupt process is executed with priority. You. Further, even if a 2 ms timer interrupt occurs during the command reception interrupt process, the interrupt process is kept waiting. As described above, in this embodiment, the processing priority of the command reception processing from the main board 31 is high. Further, since no other interrupt processing is executed during the command reception processing, the maximum time required for the command reception processing is determined. It is difficult to estimate the longest time required for the command receiving process if the configuration is such that another interrupt process can be executed during the command receiving process. Since the maximum time required for the command receiving process is determined, a period C in the command sending process of the game control means (see FIG. 35).
Can be accurately determined.

[0297] The payout control command has a 2-byte structure, and the first byte (MODE) and the second byte (EX)
T) is configured to be immediately distinguishable on the receiving side.
In other words, the receiving side can immediately detect whether the data as MODE or the data as EXT has been received by the first bit. Therefore, as described above, it can be easily determined whether or not appropriate data has been received.

In this embodiment, in the command reception interrupt processing, control for storing the received command in the reception buffer is performed. However, a payout stop state setting processing (see FIG. 52) described later and a command analysis execution processing (See Fig. 53)
May be executed in the command reception interrupt processing. As described above, when the command determination processing for determining the command in the reception buffer is also executed in the command reception interrupt processing, the determination of the command is also quickly performed.

FIG. 51 is a flowchart showing an example of the switch processing in step S751. In the switch processing, the payout control CPU 371 checks whether or not the award ball count switch 301A indicates the ON state (step S751a). If it indicates the ON state, the payout control CPU 371 increments the winning ball count switch ON counter by one (step S751b). The prize ball count switch on counter includes the prize ball count switch 30.
This is a counter for counting the number of times the 1A ON state is detected.

Then, the value of the prize ball count switch on counter is checked (step S751c). If the value is 2, it is determined that one prize ball has been paid out. When determining that one prize ball has been paid out, the payout control CPU 371 decrements the prize ball non-payout counter (the number of prize balls stored in the total number storage) (step S751d).

If it is determined in step S751a that the prize ball count switch 301A is not on, the payout control CPU 371 clears the prize ball count switch on counter (step S751e). In this embodiment, the ball rental count switch 3
It is checked whether 01B indicates the ON state (step S751f). If it indicates the ON state, the payout control CPU 371 increments the ball lending count switch ON counter by one (step S751g). The ball rental count switch on counter is a ball rental count switch 301
This is a counter for counting the number of times the ON state of B is detected.

Then, the value of the ball lending count switch on counter is checked (step S751h). If the value is 2, it is determined that one lending ball has been paid out. If it is determined that one loaned ball has been paid out, the payout control CPU 371 determines the number-of-lent-ball-unpaid-number counter (number of loaned balls stored in the number-of-lent-ball storage).
Is decremented by 1 (step S751i).

If it is confirmed in step S751f that the ball lending count switch 301B is not on, the payout control CPU 371 clears the ball lending count switch on counter (step S751j).

FIG. 52 is a flowchart showing an example of the payout stop state setting processing in step S753. In the payout stop state setting process, the payout control CPU 371
It is checked whether there is a reception command in the reception buffer (step S753a). If there is a reception command in the reception buffer, it is checked whether or not the received payout control command is a payout stop state designation command (step S).
753b). If the command is the payout stop state designation command, the payout control CPU 371 sets the payout stop state (step S753c).

If it is determined in step S753b that the received command is not a payout stop state designation command, it is checked whether the received payout control command is a payout possible state designation command (step S753d). If the command is a payable state designation command, the payout stop state is released (step S753e).

FIG. 53 is a flowchart showing an example of the command analysis execution processing in step S754. In the command analysis execution processing, the payout control CPU 371
It is determined whether or not there is a reception command in the reception buffer (step S754a). If there is a received command, it is confirmed whether or not the received payout control command is a payout control command for specifying the number of winning balls (step S7).
54b). Note that the payout control CPU 371 makes a determination in step S754b on the reception command stored at the address in the reception buffer indicated by the read pointer as the command instructing means. After the determination, the value of the read pointer is incremented by one. If the address pointed to by the read pointer exceeds the address of the receive command buffer 12 (see FIG. 49), the value of the read pointer is updated to point to the receive command buffer 1.

If the received payout control command is a payout control command for designating the number of winning balls, the number specified by the payout control command is added to the total number storage (step S754c). That is, the payout control CPU 371
Stores the number of winning balls included in the payout control command sent from the CPU 56 of the main board 31 in the backup RAM area (total number storage).

Note that the payout control CPU 371 performs a command reception number counter subtraction and a reception command shift process in the reception buffer, if necessary. Further, the payout stop state setting process and the command analysis execution process may be configured to be repeated until the value of the read pointer matches the latest command storage position in the reception buffer. For example, if the difference between the value of the read pointer and the latest command storage position in the reception buffer is "3", there are three unprocessed received commands. , There are no unprocessed received commands. That is, the received commands stored in the reception buffer are all read out and processed in one process.

FIG. 54 is a flowchart showing an example of the prepaid card unit control processing in step S755. In the prepaid card unit control process, the payout control CPU 371 checks whether or not the VL signal input from the card unit control microcomputer has been detected (step S755a). If the VL signal has not been detected, the VL signal non-detection counter is incremented by 1 (step S755b). The payout control CPU 37
1 checks whether the value of the VL signal non-detection counter is 125 in this example (step S755c). If the value of the VL signal non-detection counter is 125, the payout control CP
U371 stops the emission control signal output to the emission control board 91 and stops the drive motor 94 (step S7).
55d).

By the above processing, 125 times (2 ms ×
(125 = 250 ms) If the OFF of the VL signal is detected continuously, the state is set to the ball firing prohibited state.

If the VL signal has been detected in step S755a, the payout control CPU 371 clears the VL signal non-detection counter (step S755e). If the output of the firing control signal has been stopped (step S755f), the payout control CPU 371 starts outputting the firing control signal to the firing control board 91 to make the drive motor 94 operable (step S755g). .

FIGS. 55 and 56 show steps S756.
It is a flowchart which shows an example of the ball lending control process.
In this embodiment, the maximum value of the number of consecutive payouts is one unit of the lending ball (for example, 25), but the maximum value of the number of consecutive payouts may be another number.

In the ball lending control process, the payout control CP
The U371 confirms whether or not the lending ball is being paid out (step S511). If the lending ball is being paid out, the process shifts to a ball lending process shown in FIG. Whether or not the ball is being paid out is determined based on the state of a ball lending process flag described later. If the ball is not being paid out, it is confirmed whether or not the prize ball is being paid out (step S512). Whether or not a prize ball is being paid out is determined by the state of a prize ball processing flag described later.

If neither a loaned ball is being paid out nor a prize ball is being paid out, the payout control CPU 371 checks whether or not a ball lending request has been issued from the card unit 50 (step S5).
13). If there is a request, the ball lending process flag is turned on (step S514), and 25 (the number of ball lending units: 100 yen here) is set in the lending ball number storage in the backup RAM area (step S515). Then, the payout control CPU 371 turns on the EXS signal (step S516). Further, the distributing solenoid 310 is driven to set the ball distributing member 311 below the ball dispensing device 97 to the ball lending side (step S517). Further, the payout motor 289 is turned on (step S51).
8) The process proceeds to the ball lending process shown in FIG.

The turning on of the payout motor 289 is performed by
Strictly speaking, the BRQ signal is turned off to indicate that the card unit 50 has recognized the reception. The ball lending processing flag is set in the backup RAM area.

FIG. 56 is a flowchart showing processing during lending a ball in the payout control processing by the payout control CPU 371. In the ball lending process, if the payout motor 289 is not on, it is turned on. In this embodiment,
In the switch processing of step S751, it is checked whether or not the payout of the game ball has been performed based on the detection signal of the ball lending count switch 301B. Therefore, in the ball lending control processing, the subtraction of the storage of the number of lending balls is not performed.

In the ball lending control process, the payout control CP
U371 confirms whether it is during the lending ball passage waiting time or not (step S519). If it is not during the waiting time for passing a rental ball, the rental ball is paid out (step S520),
It is determined whether or not the driving of the payout motor 289 should be finished (whether one unit of the payout operation has been finished) (step S52).
1). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts has been completed. When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 stops driving the payout motor 289 (step S522),
The waiting time for passing a rental ball is set (step S52).
3).

If it is determined in step S519 that the waiting time for passing a ball is being passed, the payout control CPU 371 confirms whether or not the waiting time for passing a ball is completed (step S52).
4). The lending ball passing waiting time is the time from when the last payout ball is paid out by the payout motor 289 to when it passes through the ball lending count switch 301B. When confirming the end of the waiting time for passing a lending ball, since all lending balls for lending have been paid out, it is necessary to indicate to the card unit 50 that the next lending ball lending request can be accepted. The EXS signal is turned off (step S525). In addition, the distribution solenoid is turned off (step S5).
26), the ball lending processing flag is turned off (step S5)
27). If the last payout ball has not passed through the ball lending count switch 301B before the passage of the ball lending wait time, a ball lending path error is determined. Also,
In this embodiment, the prize ball and the ball lending are performed by the same payout device.

After the EXS signal indicating acceptance of the ball lending request is turned off and the BRQ signal which is the ball lending request signal is turned on again within a predetermined period, the ball lending without turning off the sorting solenoid and the payout motor is performed. The processing may be continued. That is, a predetermined unit (100 yen unit in this example)
Instead of performing the ball lending process every time, the ball lending process may be performed continuously.

[0320] The content of the stored number of lent balls is retained by the backup power supply of the power supply board 910 for a predetermined period even if the power supply to the gaming machine is stopped. Therefore, when the power supply is restored during the predetermined period, the payout control CPU 371 can continue the ball lending process based on the contents of the lending ball number storage.

FIGS. 57 and 58 show steps S757.
It is a flowchart which shows an example of the award ball control processing. In this example, the maximum value of the number of continuous payouts is the same as one unit of the lending ball (for example, 25), but the maximum value of the number of continuous payouts may be another number.

In the prize ball control processing, the payout control CPU
The 371 checks whether or not the rental ball is being paid out (step S531). Whether or not the ball is being paid out is determined based on the state of the ball lending process flag. If the ball is not being paid out, it is confirmed whether or not the prize ball is being paid out (step S).
532) If the prize ball is being paid out, the processing shifts to the processing during the prize ball shown in FIG. Whether or not a prize ball is being paid out is determined by a state of a prize ball processing flag described later.

If neither a loaned ball is being paid out nor a prize ball is being paid out, the payout control CPU 371 checks whether there is a ball lending preparation request from the card unit 50 (step S).
533). Whether or not there is a ball lending preparation request is performed by confirming whether the BRDY signal input from the card unit 50 is on (requested) or off (no request).

[0324] If there is no ball lending preparation request from the card unit 50, the payout control CPU 371 checks whether or not the number of awarded balls (the number of unpaid awarded balls) stored in the total number storage is not zero (0). Step S534). If the number of award balls stored in the total number storage is not 0, the award ball control CPU 371 turns on the award ball processing flag (step S535), and determines whether the value of the total number storage is 25 or more. Confirm (step S536). The award ball processing flag is set in the backup RAM area.

If the number of prize balls stored in the total number storage is 25 or more, the payout control CPU 371 instructs the payout motor 289 to rotate the payout motor 289 until 25 game balls are paid out. In order to output a drive signal, a 25-piece payout operation is set (step S53).
7). If the number of prize balls stored in the total number storage is not 25 or more, the payout control CPU 371 drives the payout motor 289 to rotate the payout motor 289 until all game balls stored in the total number storage are paid out. Is set to output the total number payout operation (step S53).
8). Next, the payout motor 289 is turned on (step S538). Since the distribution solenoid is off, the ball distribution member below the ball payout device 97 is set to the winning ball side. Then, the processing shifts to a processing during payout of the winning ball in the winning ball control processing shown in FIG.

FIG. 58 is a flowchart showing an example of processing during a prize ball in the payout control processing by the payout control CPU 371. In the prize ball control processing, the payout motor 289
Turn on if is not on. In this embodiment, it is determined whether or not a game ball has been paid out based on the detection signal of the prize ball count switch 301A in the switch processing of step S751, so that the total number storage is subtracted in the prize ball control processing. Is not done.

In the processing during the prize ball, the payout control CPU
The step 371 confirms whether or not the award ball passing waiting time is in progress (step S540). If it is not during the waiting time for passing a prize ball, a prize ball is paid out (step S541), and whether or not the driving of the payout motor 289 should be terminated (whether 25 or a predetermined number of less than 25 payout operations have been completed) is determined. Is confirmed (step S542). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts has been completed. When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 stops driving the payout motor 289 (step S543), and sets a prize ball passing waiting time (step S544). The prize ball passing waiting time is a time from when the last payout ball is paid out by the payout motor 289 to when it passes through the prize ball count switch 301A.

If it is determined in step S540 that the waiting time for passing a prize ball is in progress, the payout control CPU 371 checks whether or not the waiting time for passing a prize ball has ended (step S545).
The time point when the waiting time for passing the prize ball ends is determined in step S537.
Alternatively, all the prize balls set in step S538 have been paid out. Therefore, the payout control CPU 371
Turns off the award ball processing flag if the award ball passage waiting time has expired (step S546). If the last payout ball has not passed through the prize ball count switch 301A before the prize ball passage waiting time has elapsed, it is determined that a prize ball path error has occurred.

Note that, in this embodiment, step S5
11. Although the ball lending is given priority over the prize ball processing by the determination in step S531, the prize ball processing may be given priority over the ball lending.

The contents of the storage of the total number and the storage of the number of lent balls are retained by the backup power supply of the power supply board 910 for a predetermined period even if the power supply to the gaming machine is stopped. Therefore, when the power supply is restored during the predetermined period, the payout control C
The PU 371 can continue the payout process based on the contents of the total number storage.

The payout control CPU 371 manages the number of prize balls instructed from the main board 31 as the total number in the prize ball number storage, but for each prize ball number (for example, 15, 10 or 6).
). For example, a number counter corresponding to each prize ball number is provided, and when a payout number designation command is received, the number counter corresponding to the number designated by the command is incremented by one. When the prize ball payout corresponding to the number counter is performed, the number counter is decremented by one (in this case, the subtraction processing is performed in the payout control processing).
Also in this case, each number counter is formed in the backup RAM area. Therefore, even if the power supply to the gaming machine is stopped, if the power is restored during the predetermined period, the payout control CP
U371 can continue the prize ball payout process based on the content of each number counter.

In this embodiment, the payout control means detects that the INT signal relating to the payout control signal has risen, and starts a process of fetching 1-byte data by, for example, an interrupt process. Since a receiving ring buffer (a receiving buffer in this example) capable of storing a plurality of payout control commands is provided, after the payout control command is received, the next payout control command is issued before control based on the command is started. Does not mean that the command is not received by the payout control means.

As shown in the flow charts of FIGS. 28 to 30, the game control means is configured to be able to execute the command set process of step S251 even in the payout stop state (step S201). Have been.
Therefore, even when the payout is stopped, a payout control command indicating the number of payouts is transmitted to the payout control means when a prize is detected.

[0334] In the payout control means, the interruption process is started even when the payout is stopped, so that the payout control means can receive the payout control command even when the payout is stopped. And while the payout is stopped, the payout process according to the received payout control command is stopped, but since the receiving ring buffer capable of storing a plurality of payout control commands is provided, the payout control command is transmitted from the game control means. The paid-out control command does not disappear in the payout control means.

In the payout control means, a command reception number counter is used as address indicating means for indicating in which area in the receiving ring buffer the sending command is stored. Therefore, it is easy to determine which area should be used.

In the above embodiment, the case where the RAM is used as the variable data storage means has been described. However, as the variable data storage means, any other electrically rewritable storage means other than the RAM can be used. May be used.

Further, like the RAMs of the game control means and the payout control means, the RAMs of the sound control means, the lamp control means and the display control means may have a portion to be backed up.

Furthermore, in the above embodiment, the power supply monitoring means is provided on the power supply board 910 and the circuit for generating a signal for system reset is provided on the electric component control board. It may be provided on a substrate.

As described above, the game control means and the payout control means as the electric component control means are the variable data storage means which is backed up by the backup power supply as the memory holding power supply means in the power supply stop processing. A parity check is performed on an area (for example, a RAM), parity data is stored as check data, and when power supply is restarted, a state restoration process is performed if the parity data is correctly stored. Then, when the power supply is restarted, the parity check is performed again, the check result is compared with the stored parity data, and if they match, the state restoration processing is performed. If the storage contents of the variable data storage unit backed up by the backup power supply change while the power supply is stopped, the result of the parity check again does not match the stored parity data. Therefore, it is prevented that the state restoration processing is executed based on the erroneous storage contents.

In the power supply stop processing, the electric component control means sets a parity flag indicating that the power supply stop processing has been performed, and according to the state of the parity flag when the power supply is restarted. Since it is determined whether to perform the state restoration processing or the initialization processing, it is possible to reliably determine whether to perform the state restoration processing by a simple method. As a result, it is possible to reliably utilize the control state saved by the power supply stop processing.

In the game state restoring process, the game control means sets a payout possible state designation command for designating prohibition of game ball payout from the ball payout device 97 or a payout stop for designating permission of payout. Since the control for outputting the state designation command to the payout control means is performed, the state information (payout information, ball lending information, prize ball information,
It is possible to avoid the occurrence of a discrepancy in recognition regarding launch information. As a result, a malfunction by the payout control means can be prevented.

In the above embodiment, at the time of starting the power supply, the game control means transmits the payout stop state designation command or the payout possible state designation command to the payout control means. Good. For example, whether or not a hit ball can be fired by the hit ball operation handle 5 and information on an error and error cancellation are notified. With such a configuration, it is possible to avoid occurrence of a discrepancy in recognition of the current situation between the game control unit and the payout control unit after the start of power supply. As a result, appropriate game control can be performed.

In the above embodiment, when the payout control means receives the payout stop state designation command, both the ball lending and the prize ball payout are stopped, and both the ball lending and the prize ball payout are performed according to the payable state designation command. Both are returned to the possible state, but the payout stop instruction for the prize ball and the payout stop instruction for the ball lending are set as different commands, and the payout stop release instruction for the prize ball and the payout stop release instruction for the ball lending may be set as different commands. . In the case of such a configuration, there is a discrepancy between the game control means and the payout control means in the recognition of the current state of stopping / releasing the prize ball and stopping / releasing the ball after the power supply is started. Can be avoided.

In the above-described embodiment, the payout means is configured to execute both ball lending and prize ball payout. However, even if the mechanism for lending balls and the mechanism for paying out prize balls are independent. The present invention can be applied. In that case, even if the mechanism for lending the ball and the mechanism for paying out the prize ball are independent, if the payout control means is configured to control both mechanisms, as in the above-described embodiment, 1 It can be configured to instruct stop / cancel stop of both ball lending and prize ball payout with one command.

Further, when the power supply is started, even if the control state saved in the power supply stop processing remains, the electric component control means restores the state when the operation means is operated. Execute the initialization process without executing the process. Therefore, a game clerk or the like can easily clear the storage state.

When the state restoration processing is completed, the microcomputer in the electric component control means returns to the address stored in the stack area when the power supply stop processing is executed, and resumes the execution of the program.
Therefore, it is possible to easily return to the control state that was being executed when the power supply was stopped, and to reliably return to the control state that was being executed when the power supply was stopped.

[0347] Further, in the processing at the time of stopping the power supply, the output ports are immediately set to the off state after the processing for saving the gaming state is executed. As a result, it is possible to reliably prevent a situation that does not match the saved game state.

The pachinko gaming machine 1 according to each of the above-described embodiments mainly provides a predetermined game when a stop symbol of a special symbol variably displayed on the variable display device 9 based on a winning start is a predetermined symbol combination. Although it was a first-class pachinko gaming machine in which a value can be given to a player, a predetermined game value can be given to a player when there is a prize in a predetermined area of an electric accessory that is opened based on a starting prize. A second type of pachinko gaming machine, or a predetermined right is generated or continued when there is a prize to a predetermined electric accessory which is opened when a stop symbol of a symbol variably displayed based on a winning prize is a predetermined symbol combination. The present invention can be applied to a third-type pachinko gaming machine.

Further, the present invention is not limited to the pachinko game machine in which the game medium is a game ball, and the present invention can be applied to a slot machine or the like if an electric component for paying out the game medium is provided.

[0350]

According to the first aspect of the present invention, when the power supply is restored, the electric component control means stores the gaming machine in the fluctuation data storage means by using the check data stored in the fluctuation data storage means. It is determined whether the stored content was valid or not, and the stored content stored in the variable data storage unit is determined on the condition that the stored content stored in the variable data storage unit is determined to be valid. Based on the state restoration process to restore the control state based on
Since the processing for restarting the execution of the control program is performed based on the program address data, if the storage content of the variable data storage means has changed, the state recovery processing is not executed and the storage including the error is not performed. It is possible to prevent the control state from being restored based on the contents, and it is possible to reliably continue the control from the control state before the power supply was stopped by a simple method.

In the invention according to claim 2, the electric component control means performs an initialization process for initializing the control state when the storage contents stored in the variation data storage means are determined to be invalid. Therefore, if the stored contents have changed, the control state can be returned to the initial state by executing the initialization processing.

According to the third aspect of the present invention, the check data is data calculated by performing a predetermined logical operation based on at least a part of the contents of the variation data storage means. And it can be generated in a short time.

In the present invention, the variable data storage means includes a work area in which a storage area is defined for each data, and the check data is generated based on the contents of the work area. Therefore, it is possible to narrow an area for which check data is generated, and to generate check data in a short time.

According to the fifth aspect of the present invention, the check data generated in the power supply stop processing is configured to be stored in the work area. Therefore, when the power supply is started, the check data is stored. Check data can be easily read.

According to the invention of claim 6, since the program address data is configured to be stored in the stack area, it becomes easy to restore the program address data when power supply is started.

According to the seventh aspect of the present invention, the storage contents of the variable data storage means include the stack address data indicating the address of the stack area, and when the state recovery processing is performed, the stack address data is recovered. Therefore, the processing for restoring the program address data related to the address of the control program can be easily realized.

According to the eighth aspect of the present invention, the contents of the registers are stored in the stack area in the data saving processing, so that the contents of the registers are stored in the same area as the program address data, thereby facilitating data management.

According to the ninth aspect of the present invention, since the state restoring process is configured to include the process of restoring the contents of the register, the contents of the register are restored by the state restoring process, so that an accurate state is restored. Recovery takes place.

According to the tenth aspect of the present invention, the contents stored in the variable data storage means include any one of an interrupt inhibited state in which execution of a predetermined interrupt processing is inhibited and an interrupt permitted state in which execution is permitted. Since the state restoration processing includes the interruption state information indicating the state and the state restoration processing includes the restoration processing of the interruption prohibition state or the interruption permission state based on the interruption state information, the interruption prohibition or interruption is performed. Accurate state recovery including the permission state is performed.

According to the eleventh aspect of the present invention, there is provided a power supply monitoring means for monitoring a state of a predetermined power supply and outputting a detection signal when the output of the power supply is reduced and a detection condition is satisfied, and Since the power supply stop processing is configured to be performed in response to a detection signal from the power supply monitoring unit, even if an unexpected power supply stop due to a power failure or the like occurs, it is possible to detect that. .

According to the twelfth aspect of the present invention, the electric part control means controls the electric parts provided in the game machine based on the occurrence of a timer interrupt which occurs periodically. In addition to executing the process of updating the counter used for controlling the game with the remaining time of the time required for the electric component control process, and setting the interrupt prohibition during the process of updating the counter with the remaining time With this configuration, it is possible to prevent a situation in which an interrupt is generated while the counter is being updated in a surplus time and a failure occurs in updating the counter.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is a front view showing the front of the game board with the glass door frame removed.

FIG. 3 is a rear view of the gaming machine as viewed from the rear.

FIG. 4 is a rear view of the mechanism plate to which various members are attached, as viewed from the rear side of the gaming machine.

FIG. 5 is an exploded perspective view showing a configuration example of a ball payout device.

FIG. 6 is a front view showing a portion of a switch board installed on the game board.

FIG. 7 is a configuration diagram illustrating an example of a configuration of a clear switch.

FIG. 8 is a block diagram showing a circuit configuration example of a game control board (main board).

FIG. 9 is a block diagram illustrating a circuit configuration example of a symbol control board.

FIG. 10 is a block diagram illustrating a circuit configuration example of a payout control board.

FIG. 11 is a block diagram illustrating a circuit configuration example of a power supply board.

FIG. 12 is a block diagram illustrating a configuration example around a CPU for power supply monitoring and power supply backup.

FIG. 13 is an explanatory diagram showing an example of bit assignment of an output port.

FIG. 14 is an explanatory diagram showing an example of bit assignment of an output port.

FIG. 15 is an explanatory diagram showing an example of bit assignment of an input port.

FIG. 16 is a flowchart showing a main process executed by a CPU on a main board.

FIG. 17 is an explanatory diagram showing an example of a relationship between a backup flag and whether or not to execute a game state restoration process.

FIG. 18 is a flowchart showing a game state restoration process.

FIG. 19 is a flowchart showing a 2 ms timer interrupt process.

FIG. 20 is a flowchart illustrating a non-maskable interrupt process (process at the time of stopping power supply).

FIG. 21 is a flowchart showing a non-maskable interrupt process (process at the time of stopping power supply).

FIG. 22 is an explanatory diagram showing an address map of a RAM.

FIG. 23 is an explanatory diagram illustrating an example of a checksum creation method.

FIG. 24 is a diagram showing a case where the power supply to the game machine is stopped and the power supply is reduced or N
FIG. 4 is a timing chart showing a state of an MI signal.

FIG. 25 is an explanatory diagram showing an example of forming a switch timer in a RAM.

FIG. 26 is a flowchart illustrating an example of a switch process.

FIG. 27 is a flowchart illustrating an example of a switch check process.

FIG. 28 is a flowchart illustrating an example of a prize ball process.

FIG. 29 is a flowchart illustrating an example of a prize ball process.

FIG. 30 is a flowchart illustrating an example of a prize ball process.

FIG. 31 is a flowchart showing a switch-on check process.

FIG. 32 is an explanatory diagram showing a configuration example of an input determination value table.

FIG. 33 is an explanatory diagram showing a configuration example of a command transmission table and the like.

FIG. 34 is an explanatory diagram illustrating an example of a command form of a control command.

FIG. 35 is a timing chart showing the relationship between an 8-bit control signal constituting a control command and an INT signal.

FIG. 36 is an explanatory diagram showing an example of the content of a payout control command.

FIG. 37 is a flowchart illustrating an example of a command set process.

FIG. 38 is a flowchart showing a command transmission processing routine.

FIG. 39 is a flowchart showing an example of a winning ball number subtraction process.

FIG. 40 is a block diagram showing a configuration example around a payout control CPU for power supply monitoring and power supply backup.

FIG. 41 is an explanatory diagram showing an example of bit assignment of an output port.

FIG. 42 is an explanatory diagram illustrating an example of bit assignment of an input port.

FIG. 43 is a flowchart showing a main process executed by the CPU in the payout control board.

FIG. 44 is a flowchart showing a 2 ms timer interrupt process.

FIG. 45 is a flowchart showing a payout state restoration process.

FIG. 46 is a flowchart showing a non-maskable interrupt process (process at the time of stopping power supply).

FIG. 47 is a flowchart showing non-maskable interrupt processing (processing at the time of power supply stop).

FIG. 48 is an explanatory diagram showing a configuration example of a RAM in the payout control means.

FIG. 49 is an explanatory diagram illustrating a configuration example of a reception command buffer.

FIG. 50 is a flowchart illustrating an example of a command receiving process of the payout control CPU.

FIG. 51 is a flowchart illustrating an example of a switch process.

FIG. 52 is a flowchart illustrating an example of a payout stop state setting process.

FIG. 53 is a flowchart illustrating an example of a command analysis execution process.

FIG. 54 is a flowchart showing an example of a prepaid card unit control process.

FIG. 55 is a flowchart illustrating an example of a ball lending control process.

FIG. 56 is a flowchart showing an example of a ball lending control process.

FIG. 57 is a flowchart illustrating an example of a winning ball control process.

FIG. 58 is a flowchart illustrating an example of a winning ball control process.

[Explanation of symbols]

 1 Pachinko gaming machine 31 Main board 37 Payout control board 53 Basic circuit 55 RAM (variable data storage means) 56 CPU 371 Payout control CPU 910 Power supply board 916 Capacitor (Storage holding power supply means)

Claims (12)

[Claims] 1. A game machine in which a player can play a predetermined game, an electric component control means for controlling an electric component provided in the game machine by executing a control program, and a progress of the game. And fluctuating data storage means for storing fluctuating data which fluctuates in accordance with the condition, and storing the stored data for a predetermined period even if the power supply to the gaming machine is stopped. A data saving process for storing data necessary for restoring a control state in the variable data storage unit in a power supply stop process executed when the power supply is stopped; Generating the check data and storing the generated check data in the variable data storage means. At least includes a program address data associated with the address of the control program which has been executed, the electrical component control unit, when electric power supply is restored,
Based on the check data stored in the fluctuation data storage unit, it is determined whether the storage content stored in the fluctuation data storage unit is valid, and the storage content stored in the fluctuation data storage unit is determined to be valid. Under the condition that it is determined that the control data is restored, a state restoring process for restoring the control state based on the stored contents stored in the fluctuation data storage means is performed, and the execution of the control program is performed based on the program address data. A gaming machine characterized by performing a process of restarting. 2. The gaming machine according to claim 1, wherein the electric component control means performs an initialization process for initializing a control state when the storage content stored in the variation data storage means is determined to be invalid. . 3. The gaming machine according to claim 1, wherein the check data is data calculated by performing a predetermined logical operation based on at least a part of the contents of the change data storage means. 4. The gaming machine according to claim 1, wherein the variation data storage means includes a work area in which a storage area is defined for each data, and the check data is generated based on the contents of the work area. . 5. The gaming machine according to claim 4, wherein the check data generated in the power supply stop processing is stored in a work area. 6. The variable data storage means according to claim 1, further comprising a stack area for saving data according to a predetermined condition being satisfied, wherein program address data is stored in said stack area. Gaming machine. 7. The storage contents of the variable data storage means include stack address data indicating an address of a stack area, and when performing a state restoring process, the program address data is restored by restoring the stack address data. 7. The gaming machine according to claim 6, wherein the game is restored. 8. The gaming machine according to claim 6, wherein the contents of the register are stored in a stack area in the data saving process. 9. The gaming machine according to claim 8, wherein the state restoring process includes a process of restoring the contents of the register. 10. The storage contents of the variation data storage means include:
The interrupt status information includes one of an interrupt prohibition state for prohibiting execution of a predetermined interrupt process and an interrupt permission state for permitting execution, and the status recovery process includes the interrupt status information. 10. The gaming machine according to claim 1, further comprising a process for restoring an interrupt prohibition state or an interruption permission state based on the processing. 11. A power supply monitoring means for monitoring a state of a predetermined power supply, and outputting a detection signal when an output of the power supply is reduced and a detection condition is satisfied, wherein an electric component control means receives the power supply monitoring means from the power supply monitoring means. The gaming machine according to claim 1, wherein the power supply stop processing is executed in accordance with the detection signal of (i). 12. The electric component control means executes an electric component control process for controlling an electric component provided in the gaming machine based on the occurrence of a timer interrupt which occurs periodically, and A process for updating a counter used for control of a game with a surplus time required for the electric component control process, and setting an interrupt prohibition during the process for updating the counter with the surplus time. 10. The gaming machine according to 10.