JP2002208570A - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the sameInfo
- Publication number
- JP2002208570A JP2002208570A JP2001004688A JP2001004688A JP2002208570A JP 2002208570 A JP2002208570 A JP 2002208570A JP 2001004688 A JP2001004688 A JP 2001004688A JP 2001004688 A JP2001004688 A JP 2001004688A JP 2002208570 A JP2002208570 A JP 2002208570A
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- Japan
- Prior art keywords
- semiconductor
- semiconductor element
- semiconductor device
- semiconductor wafer
- back surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子の電極
形成面の裏面に接着材により補強部材を接合して成る半
導体装置および半導体装置の製造方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a reinforcing member is bonded to the back surface of an electrode forming surface of a semiconductor element with an adhesive, and a method of manufacturing the semiconductor device.
【０００２】[0002]
【従来の技術】電子機器の基板などに実装される半導体
装置は、ウェハ状態で回路パターン形成が行われた半導
体素子にリードフレームのピンや金属バンプなどを接続
するとともに樹脂などで封止するパッケージング工程を
経て製造されている。最近の電子機器の小型化に伴って
半導体装置の小型化も進み、中でも半導体素子を薄くす
る取り組みが活発に行われている。2. Description of the Related Art A semiconductor device mounted on a substrate or the like of an electronic device is a package in which a semiconductor element having a circuit pattern formed in a wafer state is connected with a lead frame pin or a metal bump and sealed with a resin or the like. It is manufactured through a aging process. With the recent miniaturization of electronic devices, miniaturization of semiconductor devices has progressed, and in particular, efforts have been actively made to make semiconductor elements thinner.
【０００３】薄化された半導体素子は外力に対する強度
が弱くハンドリング時のダメージを受けやすいことか
ら、従来より薄化された半導体素子を用いた半導体装置
は、半導体素子を補強のための樹脂層で封止する構造が
一般的である。Since a thinned semiconductor element has low strength against external force and is easily damaged during handling, a semiconductor device using a thinned semiconductor element in the related art has a resin layer for reinforcing the semiconductor element. A structure for sealing is common.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、薄い半
導体素子の表面に樹脂層を形成する工程においては、樹
脂層形成時の硬化収縮による半導体素子の反りや割れな
どの不具合が発生しやすいものであった。この問題は半
導体素子が薄化するほど顕著となり、１００μｍ以下の
極薄の半導体素子では樹脂封止することすら困難な状況
となる。However, in the process of forming a resin layer on the surface of a thin semiconductor element, defects such as warping and cracking of the semiconductor element due to curing shrinkage during the formation of the resin layer are likely to occur. Was. This problem becomes more conspicuous as the semiconductor element becomes thinner, and it becomes difficult to seal the semiconductor element even with a very thin semiconductor element having a thickness of 100 μm or less.
【０００５】そこで本発明は、薄化された半導体素子の
取り扱いが簡単な半導体装置および半導体装置の製造方
法を提供することを目的とする。Accordingly, an object of the present invention is to provide a semiconductor device in which a thinned semiconductor element can be easily handled and a method of manufacturing the semiconductor device.
【０００６】[0006]
【課題を解決するための手段】請求項１記載の半導体装
置は、外部接続用の電極が形成された電極形成面を有す
る半導体素子と、前記電極形成面の裏面に低弾性係数の
樹脂接着材を介して接合され前記半導体素子と同材質の
補強部材とを備えた。According to a first aspect of the present invention, there is provided a semiconductor device having a semiconductor element having an electrode forming surface on which electrodes for external connection are formed, and a resin adhesive having a low elastic coefficient on a back surface of the electrode forming surface. And a reinforcing member made of the same material as the semiconductor element.
【０００７】請求項２記載の半導体装置は、外部接続用
の電極が形成された電極形成面を有する第１の半導体素
子と、この第１の半導体素子の電極形成面の裏面に低弾
性係数の樹脂接着材を介して接合された第２の半導体素
子とを備えた。According to a second aspect of the present invention, there is provided a semiconductor device having a first semiconductor element having an electrode forming surface on which an electrode for external connection is formed, and a low elasticity coefficient on a back surface of the electrode forming surface of the first semiconductor element. A second semiconductor element joined via a resin adhesive.
【０００８】請求項３記載の半導体装置の製造方法は、
半導体素子の外部接続用の電極が形成された電極形成面
の裏面に低弾性係数の樹脂接着材を介して補強部材を接
合して成る半導体装置を製造する半導体装置の製造方法
であって、複数の半導体素子が形成された半導体ウェハ
の電極形成面の裏面を削る薄化工程と、薄化工程後の前
記半導体ウェハの裏面に前記半導体素子と同材質の補強
部材を低弾性係数の樹脂接着材を介して接合する接合工
程と、半導体ウェハを前記補強部材と共に半導体素子毎
に切断することにより個片の半導体装置に分離する分離
工程とを含む。According to a third aspect of the invention, there is provided a method of manufacturing a semiconductor device.
A method of manufacturing a semiconductor device for manufacturing a semiconductor device in which a reinforcing member is joined to a back surface of an electrode forming surface on which an electrode for external connection of a semiconductor element is formed via a resin adhesive having a low elastic modulus, A thinning step of shaving the back surface of the electrode forming surface of the semiconductor wafer on which the semiconductor element is formed, and a reinforcing member made of the same material as the semiconductor element on the back surface of the semiconductor wafer after the thinning step with a resin adhesive having a low elastic modulus. And a separation step of cutting the semiconductor wafer together with the reinforcing member for each semiconductor element to separate the semiconductor device into individual semiconductor devices.
【０００９】請求項４記載の半導体装置の製造方法は、
第１の半導体素子の外部接続用の電極が形成された電極
形成面の裏面に低弾性係数の樹脂接着材を介して第２の
半導体素子を接合して成る半導体装置を製造する半導体
装置の製造方法であって、複数の第１の半導体素子が形
成された第１の半導体ウェハの電極形成面の裏面を削る
薄化工程と、薄化工程後の前記第１の半導体ウェハの裏
面に第１の半導体素子と対応して複数の第２の半導体素
子が形成された第２の半導体ウェハを低弾性係数の樹脂
接着材を介して接合する接合工程と、第１の半導体ウェ
ハを第２の半導体ウェハと共に半導体素子毎に切断する
ことにより個片の半導体装置に分離する分離工程とを含
む。According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
Manufacturing of a semiconductor device in which a second semiconductor element is joined to a back surface of an electrode forming surface of a first semiconductor element on which an electrode for external connection is formed via a resin adhesive having a low elastic coefficient. A thinning step of shaving a back surface of an electrode forming surface of a first semiconductor wafer on which a plurality of first semiconductor elements are formed, and a first thinning process on the back surface of the first semiconductor wafer after the thinning step. Bonding a second semiconductor wafer, on which a plurality of second semiconductor elements are formed in correspondence with the first semiconductor element, via a resin adhesive having a low elastic modulus, and bonding the first semiconductor wafer to the second semiconductor wafer. Separating the semiconductor device into individual semiconductor devices by cutting the semiconductor device together with the wafer.
【００１０】本発明によれば、半導体素子の外部接続用
電極が形成された電極形成面の裏面に低弾性係数の樹脂
接着材を介して半導体素子と同材質の補強部材を接合す
ることにより、熱変形による半導体ウェハの反りを防止
することができる。According to the present invention, a reinforcing member made of the same material as that of the semiconductor element is joined to the back surface of the electrode forming surface of the semiconductor element on which the external connection electrodes are formed, via a resin adhesive having a low elastic modulus. Warpage of the semiconductor wafer due to thermal deformation can be prevented.
【００１１】[0011]
【発明の実施の形態】（実施の形態１）図１、図２は本
発明の実施の形態１の半導体装置の製造方法の工程説明
図、図３は本発明の実施の形態１の半導体装置の斜視
図、図４は本発明の実施の形態１の半導体装置の実装方
法の説明図である。なお、図１、図２は半導体装置の製
造方法を工程順に示している。(Embodiment 1) FIGS. 1 and 2 are process explanatory views of a method for manufacturing a semiconductor device according to Embodiment 1 of the present invention, and FIG. 3 is a semiconductor device according to Embodiment 1 of the present invention. FIG. 4 is an explanatory view of a method of mounting the semiconductor device according to the first embodiment of the present invention. 1 and 2 show a method of manufacturing a semiconductor device in the order of steps.
【００１２】図１（ａ）において、１は複数の半導体素
子が形成された半導体ウェハである。半導体ウェハ１の
上面には、外部接続用の電極であるバンプ２が形成され
ている。図１（ｂ）に示すように、半導体ウェハ１の上
面のバンプ形成面（電極形成面）にはシート３が貼着さ
れ、シート３によって補強された状態で電極形成面の裏
面の薄化加工が行われる（薄化工程）。薄化加工手段と
しては、砥石を用いた研磨装置や、ドライエッチング装
置によるエッチング、さらには薬液の化学反応を利用し
てエッチングを行うものがある。これにより、半導体ウ
ェハ１は約５０μｍの厚さまで薄化される。具体的な薄
化加工方法としては、まず砥石を用いた研磨装置で半導
体ウェハ１の裏面の粗加工を行い、ドライエッチングや
ウェットエッチングで仕上げ加工を行う。この仕上げ加
工では、粗加工によって半導体ウェハの裏面に生じたマ
イクロクラックを除去するので、抗折強度に優れた極薄
の半導体ウェハ１を得ることができる。In FIG. 1A, reference numeral 1 denotes a semiconductor wafer on which a plurality of semiconductor elements are formed. On an upper surface of the semiconductor wafer 1, bumps 2 which are electrodes for external connection are formed. As shown in FIG. 1B, a sheet 3 is adhered to a bump forming surface (electrode forming surface) on the upper surface of the semiconductor wafer 1, and the back surface of the electrode forming surface is thinned while being reinforced by the sheet 3. Is performed (thinning step). As the thinning means, there is a polishing apparatus using a grindstone, an etching using a dry etching apparatus, and an etching using a chemical reaction of a chemical solution. Thereby, the semiconductor wafer 1 is thinned to a thickness of about 50 μm. As a specific thinning method, first, the back surface of the semiconductor wafer 1 is roughly processed by a polishing device using a grindstone, and finish processing is performed by dry etching or wet etching. In this finishing process, microcracks generated on the back surface of the semiconductor wafer by the roughing process are removed, so that an extremely thin semiconductor wafer 1 excellent in bending strength can be obtained.
【００１３】次に、薄化された半導体ウェハ１の下面へ
のバンパ板４の貼着が行われる。図１（ｃ）に示すよう
に、半導体素子と同材質のシリコンを板状に形成したバ
ンパ板４の上面には接着材５が塗布される。ここで、接
着材５は低弾性係数の樹脂接着材であり、エラストマー
など接合状態における弾性係数が小さく、小さな外力で
容易に伸縮する材質が用いられる。バンパ板４の材質と
して半導体ウェハ１を構成する半導体素子１’と同材質
のシリコンを用いることにより、接着材５の硬化時に熱
膨張率差による反り変形が生じにくいという効果を得
る。Next, the bumper plate 4 is attached to the lower surface of the thinned semiconductor wafer 1. As shown in FIG. 1C, an adhesive 5 is applied to an upper surface of a bumper plate 4 in which silicon of the same material as the semiconductor element is formed in a plate shape. Here, the adhesive 5 is a resin adhesive having a low elastic modulus, and a material such as an elastomer having a small elastic coefficient in a joined state and easily expanding and contracting with a small external force is used. By using silicon of the same material as the semiconductor element 1 ′ constituting the semiconductor wafer 1 as a material of the bumper plate 4, an effect is obtained that warpage due to a difference in coefficient of thermal expansion hardly occurs when the adhesive 5 is cured.
【００１４】次にこの接着材５の塗布面に対して、薄化
された半導体ウェハ１を貼着し、半導体ウェハ１とバン
パ板４とを接合する（接合工程）。このバンパ板４は、
各半導体素子毎に切り分けられて半導体装置を形成した
状態で、半導体装置のハンドリング用の保持部として機
能すると共に、半導体素子を外力や衝撃から保護する補
強部材としての役割をも有するものである。このためバ
ンパ板４は、半導体素子の曲げ剛性よりも大きな曲げ剛
性を有する充分な厚さとなっている。この後、図１
（ｄ）に示すように、半導体ウェハ１を貼着後のバンパ
板４の下面には、ダイシング工程における保持用のシー
ト６が貼着され、シート３が電極形成面から剥離され
る。Next, the thinned semiconductor wafer 1 is attached to the surface to which the adhesive 5 is applied, and the semiconductor wafer 1 and the bumper plate 4 are joined (joining step). This bumper plate 4
In a state where the semiconductor device is formed by being divided for each semiconductor element, the semiconductor device functions as a holding portion for handling the semiconductor device and also has a role as a reinforcing member for protecting the semiconductor element from external force and impact. For this reason, the bumper plate 4 has a sufficient thickness having a bending rigidity larger than the bending rigidity of the semiconductor element. After this, FIG.
As shown in (d), the holding sheet 6 in the dicing step is attached to the lower surface of the bumper plate 4 after the semiconductor wafer 1 is attached, and the sheet 3 is separated from the electrode forming surface.
【００１５】次いで、シート６によって保持されたバン
パ板４および半導体ウェハ１はダイシング工程に送られ
る。ここでは、図２（ａ）に示すようにバンパ板４と半
導体ウェハ１とを異なるダイシング幅で切り分ける２段
ダイシングが行われる。すなわち半導体ウェハ１はダイ
シング幅ｂ１で切り分けられて個片の半導体素子１’に
分割され、バンパ板４はｂ１よりも狭いダイシング幅ｂ
２で切り分けられて個片のバンパ部材４’となる（分離
工程）。このダイシング工程において、半導体ウェハ１
とバンパ板４とは同材質であるため、ダイシング条件の
設定が容易であり、半導体素子１’へのダメージを減少
させるとともにダイシングを効率よく行うことができ
る。Next, the bumper plate 4 and the semiconductor wafer 1 held by the sheet 6 are sent to a dicing process. Here, as shown in FIG. 2A, two-stage dicing is performed in which the bumper plate 4 and the semiconductor wafer 1 are cut at different dicing widths. That is, the semiconductor wafer 1 is cut at a dicing width b1 and divided into individual semiconductor elements 1 ', and the bumper plate 4 has a dicing width b smaller than b1.
The individual bumper members 4 'are cut out at 2 (separation step). In this dicing step, the semiconductor wafer 1
Since the bumper plate 4 and the bumper plate 4 are made of the same material, dicing conditions can be easily set, and damage to the semiconductor element 1 'can be reduced and dicing can be performed efficiently.
【００１６】そして、接着材５によって半導体素子１’
と接着されたバンパ部材４’をシート６から剥離するこ
とにより、図２（ｂ）に示すように個片の半導体装置７
が完成する。この半導体装置７は、外部接続用の電極で
あるバンプ２が形成された半導体素子１’と、この半導
体素子１’の電極形成面の裏面に接着材５により接合さ
れた補強部材としてのバンパ部材４’とを備えた構成と
なっており、バンパ部材４’のサイズＢ２は半導体素子
１’のサイズＢ１よりも大きく、その外周端は、半導体
素子１’の外周端よりも外側に突出している。バンパ部
材４’は半導体素子１’と接着材５によって接合された
構造となっている。接着材５は低弾性係数の樹脂接着材
であるので、半導体素子１’の変形を許容する状態で、
この半導体素子１’をバンパ部材４’に接合している。Then, the semiconductor element 1 ′ is bonded by the adhesive 5.
By peeling the bumper member 4 ′ adhered to the sheet 6 from the sheet 6, as shown in FIG.
Is completed. The semiconductor device 7 includes a semiconductor element 1 ′ on which a bump 2 serving as an electrode for external connection is formed, and a bumper member as a reinforcing member joined to the back surface of the electrode forming surface of the semiconductor element 1 ′ by an adhesive 5. 4 ', the size B2 of the bumper member 4' is larger than the size B1 of the semiconductor element 1 ', and the outer peripheral end of the bumper member 4' projects outward from the outer peripheral end of the semiconductor element 1 '. . The bumper member 4 ′ has a structure in which the semiconductor element 1 ′ and the adhesive 5 are joined. Since the adhesive 5 is a resin adhesive having a low modulus of elasticity, the semiconductor element 1 ′ is allowed to be deformed.
This semiconductor element 1 'is joined to a bumper member 4'.
【００１７】図３に示すように、バンパ部材４’の上面
には、従来の樹脂封止型の電子部品の上面と同様に、識
別情報としての部品コード８が印字されており、コーナ
部には実装時の方向を特定する極性マーク９が形成され
ている。すなわち、バンパ部材４’の半導体素子１’と
の接合面の裏面は、識別情報の印加面となっている。こ
の後、個片の半導体装置７を上下反転してバンパ部材
４’を上面側にし、電子部品供給用のテープに収容する
テーピング処理を行う。これにより、半導体装置７は、
電子部品実装装置による実装が可能な状態となる。As shown in FIG. 3, a component code 8 as identification information is printed on the upper surface of the bumper member 4 'similarly to the upper surface of a conventional resin-encapsulated electronic component. Is formed with a polarity mark 9 for specifying a mounting direction. That is, the back surface of the bonding surface of the bumper member 4 'with the semiconductor element 1' is a surface to which the identification information is applied. Thereafter, a taping process is performed in which the individual semiconductor devices 7 are turned upside down so that the bumper member 4 ′ is placed on the upper surface side and housed in a tape for supplying electronic components. As a result, the semiconductor device 7
The electronic component mounting apparatus is ready for mounting.
【００１８】この半導体装置７の実装について図４を参
照して説明する。図４（ａ）に示すように、半導体装置
７はバンパ部材４’の上面を実装ヘッド１０によって吸
着して保持され、実装ヘッド１０を移動させることによ
り、基板１１の上方に位置する。そして半導体装置７の
バンプ２を基板１１の電極１２に位置合わせした状態
で、実装ヘッド１０を下降させて半導体素子１’のバン
プ２を基板１１の電極１２の上に着地させる。The mounting of the semiconductor device 7 will be described with reference to FIG. As shown in FIG. 4A, the upper surface of the bumper member 4 'is sucked and held by the mounting head 10, and the semiconductor device 7 is located above the substrate 11 by moving the mounting head 10. Then, with the bumps 2 of the semiconductor device 7 aligned with the electrodes 12 of the substrate 11, the mounting head 10 is lowered to land the bumps 2 of the semiconductor element 1 ′ on the electrodes 12 of the substrate 11.
【００１９】その後基板１１を加熱することにより、バ
ンプ２を電極１２に半田接合する。すなわち、半導体装
置７を基板１１へ搭載する際のハンドリングにおいて、
実装ヘッド１０によって、保持部であるバンパ部材４’
を保持する。なおバンプ２の電極１２との接合に、導電
性樹脂接着材による接合方法を用いてもよい。Thereafter, the bumps 2 are soldered to the electrodes 12 by heating the substrate 11. That is, in handling when the semiconductor device 7 is mounted on the substrate 11,
The mounting head 10 allows the bumper member 4 ′ as a holding unit to be held.
Hold. Note that the bumps 2 may be bonded to the electrodes 12 by a bonding method using a conductive resin adhesive.
【００２０】この半導体装置７を基板１１に実装して成
る実装構造は、半導体装置７の電極であるバンプ２をワ
ークである基板１１の電極１２に接合することにより半
導体装置７が基板１１に固定される形態となっている。
図４（ｃ）に示すように、実装後に基板１１に何らかの
外力により、撓み変形が発生した場合には、半導体素子
１’は薄くて撓みやすいくしかも接着材５は低弾性係数
の変形しやすい材質を用いていることから、基板１１の
撓み変形に対して半導体素子１’と接着材５の接着層の
みが追従して変形する。The mounting structure in which the semiconductor device 7 is mounted on the substrate 11 is such that the semiconductor device 7 is fixed to the substrate 11 by bonding the bumps 2 as electrodes of the semiconductor device 7 to the electrodes 12 of the substrate 11 as works. It is a form to be done.
As shown in FIG. 4C, when the substrate 11 undergoes bending deformation due to some external force after mounting, the semiconductor element 1 ′ is thin and easily bent, and the adhesive 5 is easily deformed with a low elastic coefficient. Since the material is used, only the adhesive layer of the semiconductor element 1 ′ and the adhesive 5 follows the bending deformation of the substrate 11 and deforms.
【００２１】これにより、実装後にアンダーフィル樹脂
を充填するなどの補強処理を必要とすることなく接合部
の応力が緩和され、単に半導体素子１’とバンパ部材
４’とを接着材５により接合するという簡易な形態のパ
ッケージ構造で、実装後の信頼性を確保が実現される。As a result, the stress at the joint is reduced without requiring a reinforcing process such as filling an underfill resin after mounting, and the semiconductor element 1 'and the bumper member 4' are simply joined by the adhesive material 5. With this simple package structure, reliability after mounting is realized.
【００２２】（実施の形態２）図５は本発明の実施の形
態２の半導体装置の側面図である。本実施の形態２は、
実施の形態１において単に半導体素子を補強する補強部
材としての機能を果たしていたバンパ部材を、半導体素
子と同様の機能を有する半導体素子に置き換えたもので
ある。(Embodiment 2) FIG. 5 is a side view of a semiconductor device according to Embodiment 2 of the present invention. In the second embodiment,
In the present embodiment, a bumper member which merely functions as a reinforcing member for reinforcing a semiconductor element in Embodiment 1 is replaced with a semiconductor element having the same function as the semiconductor element.
【００２３】図５において、半導体装置１７は、半導体
素子１’（第１の半導体素子）の電極形成面の裏面に、
実施の形態１に示す接着材５を介して半導体素子２２
（第２の半導体素子）を接合した構成となっている。半
導体素子２２には半導体素子１’と同様に回路が形成さ
れており、実装状態においては、半導体素子１’は実施
の形態１と同様にバンプ２によって基板２１の電極２１
ａに接合され、半導体素子２２は上面に形成された接続
用の電極２２ａをワイヤボンディングなどの方法で基板
２１の回路電極２１ｂとつなぐことにより電気的に接続
される。In FIG. 5, a semiconductor device 17 is provided on the back surface of the electrode forming surface of the semiconductor element 1 '(first semiconductor element).
Semiconductor element 22 via adhesive 5 described in the first embodiment.
(A second semiconductor element). A circuit is formed on the semiconductor element 22 in the same manner as the semiconductor element 1 ′. In the mounted state, the semiconductor element 1 ′ is mounted on the electrode 21 of the substrate 21 by the bump 2 as in the first embodiment.
a, and the semiconductor element 22 is electrically connected by connecting the connection electrode 22a formed on the upper surface to the circuit electrode 21b of the substrate 21 by a method such as wire bonding.
【００２４】この半導体装置１７の製造過程において
は、実施の形態１と同様の薄化工程によって薄化加工さ
れた半導体ウェハ（第１の半導体ウェハ）の裏面に、半
導体素子１’に対応して半導体素子２２が形成された半
導体ウェハ（第２の半導体ウェハ）が、実施の形態１に
示す接合工程と同様にして接合される。そしてこの後、
第１の半導体ウェハと第２の半導体ウェハの接合体を実
施の形態１と同様にダイシング加工することにより、個
片の半導体装置１７が得られる。In the manufacturing process of the semiconductor device 17, a semiconductor wafer (first semiconductor wafer) thinned by the same thinning process as in the first embodiment is provided on the back surface corresponding to the semiconductor element 1 '. The semiconductor wafer (second semiconductor wafer) on which the semiconductor elements 22 are formed is joined in the same manner as in the joining step described in the first embodiment. And after this,
By dicing the joined body of the first semiconductor wafer and the second semiconductor wafer in the same manner as in the first embodiment, individual semiconductor devices 17 can be obtained.
【００２５】このような構成を採用することにより、半
導体素子２２は半導体素子１’を補強する補強部材とし
ての機能を果たすとともに独自の電子回路を有してお
り、基板２１上での同一占有面積あたりの実装密度を向
上させることができる。By adopting such a configuration, the semiconductor element 22 functions as a reinforcing member for reinforcing the semiconductor element 1 ′ and has its own electronic circuit, and has the same occupied area on the substrate 21. Per package can be improved.
【００２６】[0026]
【発明の効果】本発明によれば、半導体素子の外部接続
用電極が形成された電極形成面の裏面に低弾性係数の樹
脂接着材を介して半導体素子と同材質の補強部材を接合
するようにしたので、半導体素子と補強部材との熱膨張
率の差が存在せず、熱変形による半導体ウェハの反りを
防止することができる。According to the present invention, a reinforcing member of the same material as that of the semiconductor element is joined to the back surface of the electrode forming surface of the semiconductor element on which the external connection electrodes are formed, via a resin adhesive having a low elastic modulus. Therefore, there is no difference in the coefficient of thermal expansion between the semiconductor element and the reinforcing member, and warpage of the semiconductor wafer due to thermal deformation can be prevented.
【図１】本発明の実施の形態１の半導体装置の製造方法
の工程説明図FIG. 1 is a process explanatory view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention;
【図２】本発明の実施の形態１の半導体装置の製造方法
の工程説明図FIG. 2 is a process explanatory view of the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
【図３】本発明の実施の形態１の半導体装置の斜視図FIG. 3 is a perspective view of the semiconductor device according to the first embodiment of the present invention;
【図４】本発明の実施の形態１の半導体装置の実装方法
の説明図FIG. 4 is a diagram illustrating a method for mounting the semiconductor device according to the first embodiment of the present invention;
【図５】本発明の実施の形態２の半導体装置の側面図FIG. 5 is a side view of the semiconductor device according to the second embodiment of the present invention;
１ 半導体ウェハ １’、２２ 半導体素子 ２ バンプ ３ シート ４ バンパ板 ４’ バンパ部材 ５ 接着材 ６ シート DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 1 ', 22 Semiconductor element 2 Bump 3 Sheet 4 Bumper board 4' Bumper member 5 Adhesive 6 Sheet
Claims (4)
を有する半導体素子と、前記電極形成面の裏面に低弾性
係数の樹脂接着材を介して接合され前記半導体素子と同
材質の補強部材とを備えたことを特徴とする半導体装
置。1. A semiconductor element having an electrode forming surface on which an electrode for external connection is formed, and a reinforcing member of the same material as the semiconductor element, which is joined to a back surface of the electrode forming surface via a resin adhesive having a low elastic coefficient. And a member.
を有する第１の半導体素子と、この第１の半導体素子の
電極形成面の裏面に低弾性係数の樹脂接着材を介して接
合された第２の半導体素子とを備えたことを特徴とする
半導体装置。2. A first semiconductor element having an electrode forming surface on which an electrode for external connection is formed, and joined to a back surface of the electrode forming surface of the first semiconductor element via a resin adhesive having a low elastic modulus. And a second semiconductor element.
た電極形成面の裏面に低弾性係数の樹脂接着材を介して
補強部材を接合して成る半導体装置を製造する半導体装
置の製造方法であって、複数の半導体素子が形成された
半導体ウェハの電極形成面の裏面を削る薄化工程と、薄
化工程後の前記半導体ウェハの裏面に前記半導体素子と
同材質の補強部材を低弾性係数の樹脂接着材を介して接
合する接合工程と、半導体ウェハを前記補強部材と共に
半導体素子毎に切断することにより個片の半導体装置に
分離する分離工程とを含むことを特徴とする半導体装置
の製造方法。3. A semiconductor device manufacturing method for manufacturing a semiconductor device in which a reinforcing member is joined to a back surface of an electrode forming surface on which an electrode for external connection of a semiconductor element is formed via a resin adhesive having a low elastic coefficient. A thinning step of shaving the back surface of the electrode forming surface of the semiconductor wafer on which a plurality of semiconductor elements are formed, and a low-elasticity reinforcing member of the same material as the semiconductor element on the back surface of the semiconductor wafer after the thinning step. A bonding step of bonding via a resin adhesive having a coefficient, and a separating step of separating the semiconductor wafer into individual semiconductor devices by cutting the semiconductor wafer together with the reinforcing member for each semiconductor element. Production method.
成された電極形成面の裏面に低弾性係数の樹脂接着材を
介して第２の半導体素子を接合して成る半導体装置を製
造する半導体装置の製造方法であって、複数の第１の半
導体素子が形成された第１の半導体ウェハの電極形成面
の裏面を削る薄化工程と、薄化工程後の前記第１の半導
体ウェハの裏面に第１の半導体素子と対応して複数の第
２の半導体素子が形成された第２の半導体ウェハを低弾
性係数の樹脂接着材を介して接合する接合工程と、第１
の半導体ウェハを第２の半導体ウェハと共に半導体素子
毎に切断することにより個片の半導体装置に分離する分
離工程とを含むことを特徴とする半導体装置の製造方
法。4. A semiconductor device in which a second semiconductor element is joined to a back surface of an electrode forming surface of a first semiconductor element on which an electrode for external connection is formed via a resin adhesive having a low elastic coefficient. A thinning step of shaving a back surface of an electrode forming surface of a first semiconductor wafer having a plurality of first semiconductor elements formed thereon, and the first semiconductor wafer after the thinning step Bonding a second semiconductor wafer having a plurality of second semiconductor elements formed on the back surface thereof in correspondence with the first semiconductor elements via a resin adhesive having a low elastic modulus;
Separating the semiconductor wafer into individual semiconductor devices by cutting the semiconductor wafer together with the second semiconductor wafer into individual semiconductor elements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001004688A JP4043720B2 (en) | 2001-01-12 | 2001-01-12 | Semiconductor device and manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001004688A JP4043720B2 (en) | 2001-01-12 | 2001-01-12 | Semiconductor device and manufacturing method of semiconductor device |
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| Publication Number | Publication Date |
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| JP4043720B2 JP4043720B2 (en) | 2008-02-06 |
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ID=18872845
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007115770A (en) * | 2005-10-18 | 2007-05-10 | Seiko Epson Corp | Manufacturing method of semiconductor device |
| JP2015060928A (en) * | 2013-09-18 | 2015-03-30 | 株式会社ディスコ | Wafer processing method |
-
2001
- 2001-01-12 JP JP2001004688A patent/JP4043720B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007115770A (en) * | 2005-10-18 | 2007-05-10 | Seiko Epson Corp | Manufacturing method of semiconductor device |
| JP2015060928A (en) * | 2013-09-18 | 2015-03-30 | 株式会社ディスコ | Wafer processing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4043720B2 (en) | 2008-02-06 |
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