JP2002203969A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device where the freedom in the structure of a gate electrode or a channel part increases by making the gate electrode which specifies the channel region of a MISFIT into a new structure which enables in its turn the reduction of the surface area of the board occupied by single MISFIT, or the increase of the drain current of the MISFIT, and the control of a multivalent digital signal with a single MISFIT. SOLUTION: This semiconductor device possesses the gate electrode G of a MOSFET whose one part at least is buried in the semiconductor substrate 300, a gate insulating film 308 which covers the surface of the gate electrode within the semiconductor substrate, the channel regions 306 of the MOSFET which are made in contact with the gate insulating film within the semiconductor substrate and lie along both flanks of the gate electrode within the semiconductor substrate, and the source region S and the drain region D of the MOSFET which range from the channel region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a MIS field-effect transistor (MISFET) having a buried gate electrode structure, which is used for a large-scale integrated circuit (LSI).

[0002]

2. Description of the Related Art FIG. 23 shows a conventional LSI.
1 shows the structure of a MOSFET.

In this MOSFET, a source region 101, a channel region 102, and a drain region 103 are arranged adjacent to the surface of a semiconductor substrate 100, and a gate electrode 105 is formed on a semiconductor surface immediately above the channel region 102 via a gate insulating film 104. Have a planar structure in which they are in planar contact.

In such a planar structure, it is necessary to reduce the area of each of the source, drain and channel regions in order to miniaturize the device.

[0005] However, the speed of miniaturization required for MOSFETs is becoming difficult to follow with the speed of progress of actual fine processing technology. With the current miniaturization technology, it is becoming increasingly difficult to follow the schedule of the miniaturization request for the length of the channel portion where the miniaturization is strictly required or the length of the gate electrode disposed immediately above.

[0006] Further, with the miniaturization of elements, the width of the channel has been narrowed, and the driving force of the current itself has been decreasing, so that the drain current has been reduced.
Therefore, with the current planar structure, MOSFET
There is a limit to the miniaturization of.

As one of practical solutions to these problems, it is conceivable to change the structure of the MOSFET to reduce the area of the device or increase the channel width.

On the other hand, currently used digital circuits
MOSFETs are driven by the magnitude of the voltage applied to the gate electrode.
There are two operating states: a state where the drain current flows and a state where the drain current does not flow. The current digital circuit signal is "0" or "
Since there are only two values of 1 "(ON or OFF), the MOSFET has only one threshold voltage as it is now.

However, it is considered that a multi-valued digital circuit that handles signals of three or more values (multi-valued signal) will be adopted in the future. In order to increase the degree of integration of LSI, it is desirable that a single device itself controls multi-level signals instead of handling multi-level signals by a circuit composed of current MOSFETs. A MOSFET having the above operation state is required.

In order to overcome the limitations of the current MOSFETs listed above, it is necessary to change the structure of the MOSFET, especially the structure of the channel (or gate electrode) for controlling the current in the device.

[0011]

SUMMARY OF THE INVENTION As described above, the conventional
The structure of the MOSFET is becoming increasingly difficult to keep up with the schedule of miniaturization requirements, and there is a problem that it is difficult to apply it to multivalued digital circuits.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the degree of freedom of the structure of the gate electrode or the channel portion is greatly increased by adopting a novel structure for the gate electrode defining the channel region of the MISFET. And a single MI
It is an object of the present invention to provide a semiconductor device capable of reducing the substrate surface area occupied by the SFET, increasing the drain current of the MISFET, and controlling a multi-level digital signal with a single MISFET.

[0013]

A first semiconductor device according to the present invention comprises a semiconductor substrate, a gate electrode of a MISFET at least partially embedded in the semiconductor substrate, and a surface of the gate electrode in the semiconductor substrate. A gate insulating film to cover and a MISFET formed in contact with the gate insulating film in the semiconductor substrate
And a source region and a drain region of the MISFET formed on the semiconductor substrate and connected to the channel region, wherein the channel region extends along the outer peripheral surface of the gate electrode in a channel width direction of the MISFET. Thus, the gate insulating film is formed so as to spread also in the thickness direction of the gate insulating film.

According to a second semiconductor device of the present invention, a first insulating film formed on an inner surface of a first groove provided in a semiconductor substrate, and a first insulating film embedded in the first groove are formed. A semiconductor layer, a second insulating film formed on an inner surface of a second groove provided in the first semiconductor layer, and a second semiconductor layer embedded in the second groove. A source region of the MISFET formed so as to be continuous with the first semiconductor layer at the bottom of the first groove, and a channel of the MISFET sequentially formed vertically on the source region inside the second groove; A region and a drain region, a gate insulating film of a MISFET formed on an inner surface of a third groove penetrating the drain region and provided at least at a depth close to the source region, and via the gate insulating film. Of the MISFET embedded substantially vertically inside the third groove. Comprising an electrode, wherein the semiconductor substrate, wherein the trench capacitor is formed by the first insulating film and first semiconductor layer.

According to a third semiconductor device of the present invention, there is provided a semiconductor substrate, a source region and a drain region of a MISFET formed in the semiconductor substrate, at least a part of which is buried in the semiconductor substrate, and one end of which is connected to the source substrate. A first gate electrode of the MISFET formed close to the region, a second gate electrode of the MISFET at least partially embedded in the semiconductor substrate and having one end formed close to the drain region; A gate insulating film formed so as to cover the surface of each gate electrode in the semiconductor substrate, wherein a first channel region formed when a gate voltage is applied to the first gate electrode is A second channel region connected to the source region and formed when a gate voltage is applied to the second gate electrode, connected to the drain region;
The first channel region and the second channel region are connected in series between the source region and the drain region.

In a fourth semiconductor device according to the present invention, a semiconductor substrate, a source region and a drain region of a MISFET formed in the semiconductor substrate, at least a part of which is buried in the semiconductor substrate, and one end of which is connected to the source substrate. A first gate electrode of the MISFET formed in close proximity to the region, a second gate electrode of the MISFET at least partially embedded in the semiconductor substrate and having one end formed near the drain region; At least a portion is embedded in the semiconductor substrate,
One end is close to the first gate electrode and the other end is the second gate electrode.
A third gate electrode of the MISFET formed in close proximity to the gate electrode of the MISFET, and a gate insulating film formed to respectively cover the surface of each gate electrode in the semiconductor substrate,
A first channel region formed when a gate voltage is applied to the first gate electrode is continuous with the source region, and a second channel formed when a gate voltage is applied to the second gate electrode A region connected to the drain region; a third channel region formed when a gate voltage is applied to the third gate electrode connected to the first channel region and the second channel region;
The third channel region, the third channel region and the second channel region are connected in series between the source region and the drain region.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

<First Embodiment> FIGS. 1A to 4
(C) shows a cross-sectional structure of a semiconductor device according to the first embodiment of the present invention, for explaining a manufacturing process of a MOSFET in which a gate electrode is embedded in a substrate.

First, as shown in FIG. 1A, the surface of a semiconductor substrate 200 is oxidized to form an oxide film 201, and a resist pattern by photolithography and reactive ion etching (RIE) are used. Then, a trench 202 for a buried gate electrode is dug in the substrate surface.

Next, as shown in FIG. 1B, the inner wall of the groove 202 is oxidized to form an oxide film 203 for a gate insulating film.
Further, after a polysilicon layer 204 is deposited on the entire surface, a part of the polysilicon layer 204 and the oxide film 201 on the substrate surface other than the inner wall of the groove 202 are removed by chemical mechanical polishing (CMP). Exposing a part of the substrate surface.

Next, as shown in FIG. 1C, after an oxide film 206 for a gate insulating film is formed on the entire surface, a portion (MO) of the oxide film 206 is formed using a resist pattern and RIE.
Except for the portion that becomes the gate insulating film of the SFET), a portion 205 of the substrate surface is exposed.

Next, as shown in FIG. 1D, a single-crystal silicon layer 207 is grown from the exposed portion 205 on the substrate surface.
At this time, if the surface of the portion to be the gate insulating film 206 is not too large, a single-crystal silicon layer 207 is grown on the entire surface so as to cover it. If the surface of the portion to be the gate insulating film 206 is too wide to cover the single crystal silicon layer 207, polycrystalline silicon or amorphous silicon is deposited and heated.

Next, as shown in FIG. 1E, the polysilicon layer 204 is formed by using a resist pattern 230 and RIE.
Is formed in the single-crystal silicon layer 207 and the oxide film 206.

Next, after the resist pattern 230 is stripped, an oxide film 209 for a gate insulating film is formed on the entire surface including the inner surface of the hole 208 as shown in FIG.
The oxide film on the surface of the single crystal silicon layer 207 is removed using P 2.

Next, as shown in FIG. 2B, a polysilicon layer 210 is deposited on the entire surface.

Next, as shown in FIG. 2C, the polysilicon layer 204 is formed by using a resist pattern 231 and RIE so as not to damage the oxide film 209 on the inner surface of the hole 208.
Drill holes 211 to reach.

Next, after the resist pattern 231 is peeled off, as shown in FIG. 2D, the excess oxide film 209 around the bottom surface of the hole 211 is receded by wet etching. A groove 212 is formed in this recessed portion.

Next, as shown in FIG. 3A, a single crystal silicon layer 213 is grown on the entire surface. Next, as shown in FIG. 3B, the single crystal silicon layer 207 is formed using CMP.
Planarization is performed to expose the surface, and then FIG.
As shown in (c), after the entire surface is oxidized to form an oxide film 215 for a gate insulating film, a part of the flattened substrate surface is exposed, and a single crystal is formed from the exposed portion (not shown). A silicon layer 216 is grown over the entire surface.

Next, as shown in FIG. 3D, using the resist pattern 232 and RIE, the single crystal silicon layer 21 is formed.
Out of 6, the source forming region 217 and the drain forming region 218
, The other region and the oxide film 215 thereunder are removed.

Next, after the resist pattern 232 is peeled off, as shown in FIG.
Is grown over the entire surface.

Next, as shown in FIG. 4B, a hole for a gate extraction electrode is formed in a part of the surface of the single crystal silicon layer 219.
Form 220.

Next, as shown in FIG. 4C, after the entire surface is oxidized to form a surface oxide film 221, a single crystal silicon layer is formed.
219, an element isolation region (not shown) is formed,
A source region (S) 222 and a drain region (D) 223 are formed by impurity ion implantation, respectively, and are covered with the source region 222, the drain region 223 and the oxide films 203, 206, 209 and 215 for the gate insulating film. A source wiring (not shown), a drain wiring (not shown), and a gate wiring (not shown) are formed so as to be in contact with the gate electrodes G respectively.

According to the MOSFET having the above structure, the gate electrode G is buried in the semiconductor substrate, so that the degree of freedom of the structure of the gate electrode G can be increased as compared with the conventional planar type MOSFET. Therefore, the source region S, the drain region D, and the gate electrode G can be arranged at free positions as if they were independent elements.

The channel region is formed along the upper surface, the side surface and the lower surface of the gate electrode G in the substrate and in contact with the gate insulating film. The length in the channel width direction is the outer peripheral surface of the polysilicon layers 204 and 210. Along the thickness direction of the oxide film 206 (the depth direction of the substrate) and the thickness direction of the oxide film 209 (the in-plane direction of the substrate). At this time, the drain current
Id flows mainly in the shortest distance between the source region S and the drain region D, for example, as indicated by the path indicated by the arrow in the drawing.

<Second Embodiment> FIGS. 5A to 7
(C) illustrates a process for manufacturing a MOSFET in which a gate width (channel width) of a gate electrode is buried in a substrate of a semiconductor device according to a second embodiment of the present invention so as to be perpendicular to a substrate surface. Therefore, a sectional structure or a planar pattern is shown.

First, as shown in FIG. 5A, after forming a deep element isolation region (for example, STI) 301 in a semiconductor substrate 300, the surface of the substrate is thinly oxidized to form a sacrificial oxide film 302.

Next, the cross section shown in FIG.
As shown in the upper surface of FIG. 3C, a well region 303, a source region 304, a drain region 305, and a channel region 306 are formed by impurity ion implantation. In this case, a source region 304 and a drain region 305 are located on both ends in the well region 303, and a channel region 306 is located between the source region 304 and the drain region 305.

Next, as shown in FIG. 6A, a hole 307 for embedding a gate electrode is dug in a part of the source region 304, the drain region 305, and the channel region 306 by using a resist pattern 320 and RIE.

Next, after removing the resist pattern 320, the inner wall of the hole 307 is oxidized to oxidize the inner wall of the hole 307 as shown in the cross section shown in FIG. 6B and the upper surface shown in FIG. 6C. An oxide film 308 is formed.

Next, as shown in FIG.
A polysilicon layer 309 is deposited on the entire surface including the inside of FIG.

Next, as shown in FIG. 7B, a part of the polysilicon layer 309 and the oxide film 308 are exposed by CMP so that the upper surfaces of the source region 304 and the drain region 305 are exposed. And a part of the sacrificial oxide film 302 is removed.

Next, as shown in FIG. 7C, after introducing impurity ions to make the polysilicon layer 309 a gate electrode G, the source region (S) 304, the drain region (D) 305 and A source wiring (not shown), a drain wiring (not shown), and a gate wiring (not shown) are formed so as to be in contact with the gate electrode G, respectively. And
A protective film 310 is formed on the entire surface.

According to the MOSFET having the above structure, the gate electrode G is buried in the deep hole 307 for burying the gate electrode, and the channel width corresponds to the depth of the hole 307. In other words, in the conventional MOSFET having a planar structure, when the channel width is increased, the pattern area (element area) on the substrate surface is correspondingly increased. The channel width can be increased by changing the depth of the hole without increasing the area. In addition, since the channel region is formed on both sides (flat surface) of the gate electrode G in the thickness direction of the oxide film 308 (in-plane direction of the substrate) and the channel width is increased, the pattern area on the substrate surface is increased. Without having to effectively double the channel width.

<Modification of Second Embodiment> FIG.
15 shows a main part of a plane pattern of a MOSFET structure according to a modification of the embodiment.

In the second embodiment, one gate electrode G is formed between the source region S and the drain region D. However, as shown in FIG. 8, a plurality of holes for embedding the gate electrode are formed. A plurality of gate electrodes G may be formed in parallel by opening them in parallel and embedding the gate electrodes G in each. In FIG. 8, reference numeral 311 denotes an element isolation region, and the same portions as those in FIG. 7C are denoted by the same reference numerals.

According to the MOSFET having the above structure, basically the same effects as those of the MOSFET of the second embodiment can be obtained, and furthermore, by applying the same gate voltage to the plurality of gate electrodes G, the effective effect can be obtained. The width of the channel can be increased, and the number of current paths can be increased.

In this case, when a gate voltage is independently applied to the plurality of gate electrodes G, one MOSFET can have the same function as a conventional circuit in which a plurality of MOSFETs are arranged in parallel. . Further, the drain current can be controlled in a stepwise manner in proportion to the number of gates turned on, even though the MOSFET is a single MOSFET. Therefore, the amount of current can be controlled according to the multi-valued digital signal.

Further, the distance between the gate electrode at one end or both ends of the array of the plurality of gate electrodes G and the element isolation region 311 around the MOSFET is reduced (the gate electrode G
And the element isolation region 311 are brought close to each other),
As with the licon on insulator (SOI), the effect of realizing the depletion element can be expected.

<Third Embodiment> FIGS. 9A to 11
9 shows a cross-sectional structure for explaining a manufacturing process of a MOSFET in which a gate electrode is buried in a substrate in a semiconductor device according to a third embodiment of the present invention so as to be parallel to a substrate surface.

First, as shown in FIG. 9A, after the surface of the semiconductor substrate 400 is oxidized to form an oxide film 401 for a gate insulating film, the well region 402 in the semiconductor substrate 400 and the inside thereof are removed. Impurity ions are implanted into the channel region 403.

Next, as shown in FIG. 9B, a polysilicon layer 404 is deposited on the entire surface.

Next, as shown in FIG. 9C, the polysilicon layer 404 and the oxide film 401 are patterned into the shape of the gate electrode G by using a resist pattern 420 and RIE by photolithography.

Next, after the resist pattern 420 is peeled off, as shown in FIG. 9D, the entire surface is oxidized to form an oxide film 405 for a gate insulating film, and then the resist pattern and RIE are used. Then, the oxide film other than the surface of the gate electrode is removed.

Next, as shown in FIG. 9E, a single crystal silicon layer 406 is grown. At this time, the gate electrode G
If the surface of the oxide film 405 on the surface is not very wide, a single-crystal silicon layer 406 is grown over the entire surface so as to cover the surface.
If the surface of the oxide film 405 on the surface of the gate electrode G is too wide to cover the single crystal silicon layer 406, polycrystalline silicon or amorphous silicon is deposited and heated. After this, the single-crystal silicon layer is
406 is flattened.

Next, as shown in FIG. 10A, after the surface of the single crystal silicon layer 406 is oxidized to form an oxide film 407, impurities are added to the well region 408 and the channel region 409 therein. Implant ions.

Next, as shown in FIG. 10B, the oxide film 407 and the single crystal silicon layer 406 other than those above the gate electrode G are removed by using the resist pattern 421 and RIE.

Next, after the resist pattern 421 is removed, as shown in FIG.
Grow 0

Next, as shown in FIG. 11, an element isolation region (not shown) is formed in the single crystal silicon layer 410, and a well region 411, a source region (S) 412, and a drain region (D) are formed. 413 are respectively formed by impurity ion implantation, and a source wiring (not shown), a drain wiring (not shown), and a gate wiring (not shown) are formed so as to be in contact with the source region S, the drain region D and the gate electrode G, respectively. (Not shown).

According to the MOSFET having the above structure, the gate electrode G
A semiconductor layer 406 is deposited on the
409. That is, since the channel region is formed on the upper and lower surfaces of the gate electrode G in the thickness direction of the oxide films 401 and 405 (in the depth direction of the substrate) and the channel width is increased, the pattern area on the substrate surface is increased. Instead, the channel width can be effectively doubled.

<Modification of Third Embodiment> FIG. 12 shows a main part of a sectional structure of a MOSFET according to a modification of the third embodiment.

In the third embodiment, one gate electrode G is provided between a source region S and a drain region D in a semiconductor substrate 400.
Is shown, but a plurality of gate electrodes G may be formed in parallel as shown in FIG. 12, the same parts as those in FIG. 11 are denoted by the same reference numerals.

According to the MOSFET having the above-described structure, basically the same effects as those of the MOSFET of the third embodiment can be obtained, and furthermore, by applying the same gate voltage to a plurality of gate electrodes G, the effective effect can be obtained. The width of the channel can be increased, and the number of current paths can be increased.

In this case, when a gate voltage is independently applied to the plurality of gate electrodes G, one MOSFET can have the same function as a conventional circuit in which a plurality of MOSFETs are arranged in parallel. . Further, the drain current can be controlled in a stepwise manner in proportion to the number of gates turned on, even though the MOSFET is a single MOSFET.

Further, the upper surface of the gate electrode G determines the threshold value for forming the inversion layer and the lower surface side independently determines the threshold value for forming the inversion layer, and each gate electrode G independently determines the threshold value for forming the inversion layer. It is possible to control the drain current stepwise in accordance with the number of gates that are turned on in accordance with the magnitude of the voltage applied to the gate electrode G, even though it is a single MOSFET. is there.

<Fourth Embodiment> FIGS. 13 (a) to 1
FIG. 7C shows a cross-sectional structure or a plane pattern for describing a manufacturing process of a MOSFET in which a source, a channel, and a drain are arranged in a substrate in a vertical direction in a semiconductor device according to a fourth embodiment of the present invention. I have.

First, as shown in FIG. 13A, after the surface of the semiconductor substrate 500 is oxidized to form an oxide film 501, a resist pattern 530 by photolithography and a deep first hole 502 using RIE. Dig.

Next, as shown in FIG.
After oxidizing the inner wall of the oxide film 503 to form an oxide film 503, a hole 502 in the oxide film 503 is formed using a resist pattern and RIE.
Other portions are removed except for the inner wall of the hole and the periphery of the hole 502.

Next, as shown in FIG. 13C, a single-crystal silicon layer 504 is grown on the entire surface. At this time, the hole 50
If the surface of the oxide film 503 on the inner wall of No. 2 is not very wide, a single-crystal silicon layer 504 is grown on the entire surface so as to cover the surface. If the surface of the oxide film 503 on the inner wall of the hole 502 is too large to cover the single crystal silicon layer 504, polycrystalline silicon or amorphous silicon is deposited and heated.

Next, as shown in FIG. 14A, the substrate is flattened using CMP so that the substrate surface is exposed.

Next, as shown in FIG. 14B, a single-crystal silicon layer 504 is formed by using a resist pattern 531 and RIE.
Drill a hole 505 inside.

Next, after the resist pattern 531 is peeled off, as shown in FIG. 14C, a highly fluid insulating material (for example, TEOS) 506 is deposited on the entire surface to fill the hole 505.

Next, as shown in FIG. 15A, a resist pattern 532 and RIE are used to form the single-crystal silicon layer.
A second hole 50 shallow in said insulating material 506 so as to reach 504;
Open 7.

Next, after the resist pattern 532 is stripped, a single-crystal silicon layer 508 is grown on the entire surface as shown in FIG.

Next, as shown in FIG. 15C, the surface of the insulating material 506 is flattened using CMP so as to be exposed.

Next, as shown in FIG. 16A, a well region 509 is formed in the single crystal silicon layer 508, and a source region (S) 510, a channel region 512, and a drain region (D) 511 are formed therein. Are sequentially implanted in the vertical direction.

Next, as shown in FIG. 16B, using the resist pattern 533 and RIE, a hole 513 for embedding a gate electrode that penetrates through the drain region D and reaches at least the vicinity of the source region S is formed. Open. The hole 513 for embedding the gate electrode can be formed through the channel region 512 to the oxide film 503.

Next, after removing the resist pattern 533, as shown in FIG. 17A, a hole 51 for a gate electrode is formed.
3 is oxidized to form an oxide film 514.

Next, after a polycrystalline silicon layer 515 is deposited over the entire surface as shown in the cross section shown in FIG.
Then, the surface is planarized using CMP so as to leave the polycrystalline silicon layer 515 inside the hole 513 as a gate electrode G as shown in a plane pattern in FIG.

Further, a drain wiring (not shown) and a gate wiring (not shown) are formed so as to be in contact with the drain region D and the gate electrode G, respectively.

The structure of the MOSFET thus obtained is
As shown in the top view of FIG.
7 (for example, a circle), a gate electrode G is buried in a gate electrode hole 513 (for example, a circle) of the well region 509 via an oxide film (gate insulating film) 514 on the inner wall. Further, the source region S is located below the bottom surface of the hole 513.
And a drain region D exists in the opening of the hole 513,
A hole 513 is formed between the drain region D and the source region S.
A channel region 512 exists along the inner surface of the oxide film 514, and its channel width extends 360 ° in the plane parallel to the substrate, similarly to the thickness direction of the oxide film 514. In this case, since the source region S, the channel region 512, and the drain region D of the MOSFET are arranged in the vertical direction, the area of the element is reduced.

Further, a capacitor having a structure in which the oxide film 503 on the inner wall of the deep first hole 502 is sandwiched between the substrate 500 and the single crystal silicon layer 504 is formed, and the single crystal silicon layer 504 is formed in the source region of the MOSFET. Since these capacitors are connected to S, these capacitors and MOSFETs can be used as DRAM memory cells. In this case, since the MOSFET exists inside the capacitor, the space can be saved.

Further, since the trench capacitor itself can be formed large along the inner surface of the deep first hole 502, a large capacitance can be realized. In this case, since the source region and one electrode of the capacitor are directly connected, quick charging and discharging of the capacitor can be performed.

<Fifth Embodiment> FIG. 18 shows a semiconductor device according to a fifth embodiment of the present invention in which a plurality of (two in this example) are provided between a source region S and a drain region D in a substrate.
MOSFETs with embedded gate electrodes G arranged in series
2 shows a plane or cross section of the structure of FIG.

In the figure, S is a source region, D is a drain region, G1 is a first gate electrode, and G2 is a second gate electrode. Each of the gate electrodes G1 and G2 has, for example, a plate shape, and has a surface covered with a gate insulating film (not shown).

Here, one end of the first gate electrode G 1 is connected to the source region S so that an inversion layer (first channel region) 601 formed when a gate voltage is applied is connected to the source region S. It is located close to a part.

Similarly, one end of the second gate electrode G 2 is connected to the drain region D such that the inversion layer (second channel region) 602 formed when a gate voltage is applied is connected to the drain region D. It is located close to a part.

Then, the gate electrodes G1 and G2
Is a distance such that the first channel region 601 and the second channel region 602 are continuous when a predetermined gate voltage is applied (a distance less than twice the inversion layer width). ).

Therefore, according to the structure of the MOSFET,
A simulated AND logic circuit that, when a single element having a small area, receives two gate inputs of a predetermined voltage respectively, connects between the source region S and the drain region D in two channel regions and turns on. Has formed.

The manufacture of this MOSFET can be realized by steps according to the other embodiments described above.

<Sixth Embodiment> FIG. 19 shows a semiconductor device according to a sixth embodiment of the present invention in which a plurality (4 in this example) is formed between a source region S and a drain region D in a substrate.
2) shows a plane or cross section of a MOSFET structure in which embedded gate electrodes G are arranged in series and in parallel.

In the figure, S is a source region, D is a drain region, G1 is a first gate electrode, G2 is a second gate electrode, G3 is a third gate electrode, and G4 is a fourth gate electrode. Each of the gate electrodes G1 to G4 has, for example, a plate shape, and has a surface covered with a gate insulating film (not shown).

Here, the first gate electrode G 1 and the fourth gate electrode G 1
Are opposed in parallel, and one end thereof is arranged close to a part of the source region S. With this arrangement, the first gate electrode G1 is formed by an inversion layer (first channel region) 711 formed when a gate voltage is applied.
Are connected to the source region S. Similarly, the fourth gate electrode G
4 also, the inversion layer (fourth channel region) 714 formed when the gate voltage is applied continues to the source region S.

The second gate electrode G2 is disposed on an extension of the fourth gate electrode G4, and is an inversion layer (second channel region) 712 formed when a gate voltage is applied.
One end is arranged close to a part of the drain region D so that is connected to the drain region D.

One end of the third gate electrode G3 is
The first gate electrode G1 and the fourth gate electrode G4 are arranged so as to approach each other in parallel to each other. The other end of the third gate electrode G3 is disposed so as to approach and be parallel to the other end of the fourth gate electrode G4.

According to such an arrangement, the third gate electrode G3 is formed such that the inversion layer (third channel region) 713 formed when a gate voltage is applied is directly connected to the source region S and the drain region D. Are not connected, but are connected to the source region S via the first channel region 711 or the fourth channel region 714 and connected to the drain region D via the second channel region 712.

Therefore, according to the MOSFET having the above structure,
A gate input of a predetermined voltage is applied to each of the second gate electrode G2 and the third gate electrode G3, and a gate input of a predetermined voltage is applied to either the first gate electrode G1 or the fourth gate electrode G4. Then, the region between the source region S and the drain region D is connected to the channel region and turned on. That is, a composite circuit of pseudo OR logic and AND logic is formed, and a plurality of inputs can be determined and output.

It should be noted that the manufacture of this MOSFET can be realized by steps according to the other embodiments described above.

<Seventh Embodiment> FIG. 20 shows a main part of a cross-sectional structure of a MOSFET according to a seventh embodiment.

In this MOSFET, the semiconductor layer 81 on the upper surface side of one gate electrode G horizontally embedded in the substrate surface between element isolation regions 80 in the semiconductor substrate has a first conductivity type (for example, P type). Source region S and drain region D are formed,
A source region S and a drain region D of the second conductivity type (for example, N type) are formed in the semiconductor layer 82 on the lower surface side.

According to the MOSFET having the above structure, as described above, the MOSFET having the structure in which the gate electrode G is buried in the horizontal direction.
Basically, the same effect can be obtained, and the P-type MOSFET and the N-type MOSFET can be commonly controlled by the voltage applied to one gate electrode G.

By using such a structure, it is possible to configure a CMOS inverter circuit using MOSFETs in a relatively narrow region of the substrate.

<Modification of First Embodiment> FIG. 21 schematically shows a cross-sectional structure or a planar pattern of a MOSFET according to a modification of the first embodiment.

In this MOSFET, the gate electrode G is arranged in a bent shape in the semiconductor substrate, and the source region S, the channel region and the drain region D are not arranged on a straight line. According to such a structure, the positions of the source, the drain and the gate can be freely determined.

<Modification of Sixth Embodiment> FIG. 22 schematically shows a cross-sectional structure or a planar pattern of a MOSFET according to a modification of the sixth embodiment of the present invention.

In this MOSFET, a plurality of buried gate electrodes G formed in an arbitrary shape such as a flat plate, a T shape, an E shape, and an L shape are formed between a source region S and a drain region D in a semiconductor substrate. 1 schematically illustrates a cross-sectional structure or a planar pattern arranged in series and in parallel.

[0106]

As described above, according to the semiconductor device of the present invention, the gate electrode for defining the channel region of the MISFET has a novel structure, thereby greatly increasing the degree of freedom in the structure of the gate electrode or the channel portion. Augmented and thus a single MISFET
Can reduce the substrate surface area occupied by the MISFET, increase the drain current of the MISFET, and control a multi-valued digital signal with a single MISFET.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a part of a manufacturing process of a MOSFET in which a gate electrode is embedded in a substrate in a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view shown to explain a step that follows the step of FIG. 1;

FIG. 3 is a sectional view shown to explain a step that follows the step of FIG. 2;

FIG. 4 is a sectional view illustrating a step that follows the step of FIG. 3;

FIG. 5 shows a part of a manufacturing process of a MOSFET in which a gate width (channel width) of a gate electrode is buried in a substrate of a semiconductor device according to a second embodiment of the present invention so as to be perpendicular to a substrate surface. 3A and 3B are a cross-sectional view and a plane pattern diagram shown for explanation.

6A and 6B are a cross-sectional view and a plan pattern diagram illustrating a step that follows the step of FIG. 5;

FIG. 7 is a sectional view shown to explain a step that follows the step of FIG. 6;

FIG. 8 is a view showing a main part of a plane pattern of a MOSFET according to a modification of the second embodiment.

FIG. 9 is a sectional view illustrating a part of the manufacturing process of the MOSFET in which the gate electrode is buried in the substrate in the semiconductor device according to the third embodiment of the present invention so as to be parallel to the substrate surface; .

10 is a sectional view shown for explaining a step that follows the step of FIG. 9;

FIG. 11 is a sectional view shown for explaining a step that follows the step of FIG. 10;

FIG. 12 shows a MOSF according to a modification of the third embodiment of the present invention.
Sectional drawing which shows the principal part of the structure of ET.

FIG. 13 is a sectional view illustrating a part of the manufacturing process of the MOSFET in which the source, the channel, and the drain are vertically arranged in the substrate in the semiconductor device according to the fourth embodiment of the present invention;

FIG. 14 is a sectional view illustrating a step that follows the step of FIG. 13;

FIG. 15 is a sectional view shown to explain a step that follows the step of FIG. 14;

16 is a sectional view shown for explaining a step that follows the step of FIG. 15;

FIG. 17 is a cross-sectional view and a plan pattern diagram illustrating a step that follows the step of FIG. 16;

FIG. 18 is a diagram showing a semiconductor device according to a fifth embodiment of the present invention.
FIG. 4 is a plan view or a cross-sectional view illustrating a structure of a MOSFET in which embedded gate electrodes are arranged in series.

FIG. 19 is a diagram illustrating a semiconductor device according to a sixth embodiment of the present invention.
FIG. 4 is a plan view or a cross-sectional view illustrating a structure of a MOSFET in which a plurality of embedded gate electrodes are arranged in series and in parallel.

FIG. 20 is a sectional view schematically showing a main part of a sectional structure of a MOSFET according to a seventh embodiment of the present invention.

FIG. 21 shows a MOSF according to a modification of the first embodiment of the present invention.
FIG. 2 is a cross-sectional view schematically showing a cross-sectional structure or a plane pattern of the ET.

FIG. 22 shows a MOSF according to a modification of the sixth embodiment of the present invention.
The figure which shows the cross-section or planar pattern of ET schematically.

FIG. 23 is a sectional view showing the structure of a MOSFET formed in a conventional LSI.

[Explanation of symbols]

200: semiconductor substrate, 201: oxide film, 202: groove for buried gate electrode, 203: oxide film (gate insulating film), 204: gate electrode material (polysilicon), 205: exposed substrate surface, 206: oxide film (Gate insulating film), 207: deposited crystalline silicon, 208: hole for gate electrode, 209: oxide film (gate insulating film), 210: polysilicon of gate electrode material, 211: remove unnecessary oxide film in the electrode Holes for forming 212, a groove formed by retreating an oxide film by wet etching, 213, a single-crystal silicon layer, 215, an oxide film, 216, a single-crystal silicon layer, 219, a single-crystal silicon layer, 220, a hole, 221 …Oxide film. 222 ... source region (S), 223 ... drain region (D),

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 27/108 H01L 27/10 625A 21/8242 29/60 29/423 29/78 301V 29/78 301G 653 301X 617N 626A F-term (reference) 4M104 AA01 BB01 CC05 DD75 DD78 DD88 DD91 EE03 EE14 FF01 GG08 GG09 GG10 GG14 HH20 5F040 DA21 DB03 DC01 EA09 EC03 EC04 EC07 EC16 EC18 EC19 EC20 EC21 FC05 EE04 EA01 AC02 BB05 BB19 BD02 BD05 BD07 BD09 BE08 5F083 AD04 AD17 AD19 GA09 JA02 ZA21 5F110 AA04 AA07 BB04 BB06 CC08 CC09 DD05 DD13 EE08 EE09 EE12 EE22 EE24 EE28 EE29 EE45 EE48 FF02 FF23 GG22 HJ13Q19

Claims (15)

[Claims] 1. A semiconductor substrate, and a MISF at least partially embedded in the semiconductor substrate.
A gate electrode of ET, a gate insulating film covering a surface of the gate electrode in the semiconductor substrate, a channel region of a MISFET formed in contact with the gate insulating film in the semiconductor substrate, and formed on the semiconductor substrate; Connect to channel area
A source region and a drain region of the MISFET, wherein the channel region is formed so as to extend in the thickness direction of the gate insulating film along the outer peripheral surface of the gate electrode in the channel width direction of the MISFET. A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein the gate electrode is arranged in a bent shape in the semiconductor substrate, and the source region, the channel region, and the drain region are not arranged on a straight line. Semiconductor device. 3. The semiconductor device according to claim 2, wherein the gate electrode has a flat plate shape, is embedded substantially vertically in the semiconductor substrate, and has a channel width set in a depth direction of the semiconductor substrate. Item 2. The semiconductor device according to item 1. 4. The semiconductor device according to claim 3, wherein a plurality of gate electrodes each having a flat plate shape are buried substantially in parallel, and the same voltage is applied to each of the plurality of gate electrodes. 5. The semiconductor device according to claim 3, wherein a plurality of gate electrodes each having a plate-like shape are buried substantially in parallel, and a voltage is independently applied to each of the plurality of gate electrodes. 6. The semiconductor device according to claim 1, wherein the gate electrode has a plate shape, is embedded in the semiconductor substrate in a substantially horizontal state, and has a channel width set in a width direction of the gate electrode. 2. The semiconductor device according to 1. 7. The semiconductor device according to claim 6, wherein a plurality of gate electrodes each having a flat plate shape are buried substantially in parallel, and the same voltage is applied to each of the plurality of gate electrodes. 8. The semiconductor device according to claim 6, wherein a plurality of gate electrodes each having a plate-like shape are buried substantially in parallel, and a voltage is independently applied to each of the plurality of gate electrodes. 9. The channel region formed corresponding to each flat plate surface of the gate electrode, wherein at least a part of each threshold voltage differs from each other. Semiconductor device. 10. The semiconductor device according to claim 1, wherein the gate electrode is embedded substantially vertically in the semiconductor substrate, and the drain region and the source region are arranged above and below the gate electrode in the semiconductor substrate. 2. The semiconductor device according to claim 1, wherein 11. A first insulating film formed on an inner surface of a first groove provided in a semiconductor substrate; a first semiconductor layer embedded in the first groove; A second insulating film formed on an inner surface of a second groove provided in the semiconductor layer, a second semiconductor layer embedded in the second groove, and a bottom of the first groove. A source region of the MISFET formed so as to be continuous with the first semiconductor layer; a channel region and a drain region of the MISFET sequentially formed in the second groove on the source region in the vertical direction; A gate insulating film of a MISFET formed on an inner surface of a third groove provided through the region and provided at least at a depth close to the source region, and an inside of the third groove via the gate insulating film. And a MISFET gate electrode buried in a substantially vertical state. Semiconductor substrate, wherein a trench type capacitor is formed by the first insulating film and first semiconductor layer. 12. The semiconductor device according to claim 11, wherein the MISFET and the trench-type capacitor form a DRAM memory cell. 13. A semiconductor substrate, a source region and a drain region of a MISFET formed in the semiconductor substrate, and at least a part embedded in the semiconductor substrate and one end formed near the source region. A first gate electrode of the MISFET, and a second gate electrode of the MISFET at least partially embedded in the semiconductor substrate and having one end formed near the drain region.
And a gate insulating film formed so as to respectively cover the surface of each gate electrode in the semiconductor substrate, wherein a first gate electrode is formed when a gate voltage is applied to the first gate electrode. Channel region is connected to the source region, and the second
A second channel region formed when a gate voltage is applied to the gate electrode of the second electrode region is continuous with the drain region, and the first channel region and the second channel region are connected in series between the source region and the drain region. A semiconductor device characterized by being connected. 14. A semiconductor substrate, a source region and a drain region of a MISFET formed in the semiconductor substrate, and at least a part embedded in the semiconductor substrate, and one end formed in close proximity to the source region. The first of MISFET
A second MISFET having at least a part embedded in the semiconductor substrate and one end formed near the drain region;
And a third electrode of the MISFET formed at least partially in the semiconductor substrate, one end of which is close to the first gate electrode, and the other end of which is formed close to the second gate electrode. A first gate electrode, comprising: a gate electrode; and a gate insulating film formed so as to cover a surface of each gate electrode in the semiconductor substrate, wherein a first gate electrode is formed when a gate voltage is applied to the first gate electrode. A channel region is continuous with the source region;
A second channel region formed when a gate voltage is applied to the gate electrode of the second line is connected to the drain region, and a third channel region formed when a gate voltage is applied to the third gate electrode is formed as the third region. A first channel region and a second channel region connected to each other, wherein the first channel region, the third channel region, and the second channel region are connected in series between the source region and the drain region; Semiconductor device. 15. At least a part is buried in the semiconductor substrate, one end is formed near the source region, and the other end is formed near the third gate electrode.
A fourth gate electrode of the MISFET; and a gate insulating film formed so as to cover a surface of the fourth gate electrode in the semiconductor substrate.
A fourth channel region formed when a gate voltage is applied to the gate electrode of the third channel region is connected to the source region and the third channel region.
15. The semiconductor device according to claim 14, wherein the channel region and the second channel region are connected in series between the source region and the drain region.