JP3611445B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a nonvolatile memory cell having a floating gate electrode and a control gate electrode, and a method for manufacturing the same.
[0002]
[Prior art]
In recent years, with the price reduction of system equipment and the shortening of product cycles, there is a strong demand for cost reduction and shortening of the development period for semiconductor devices. In particular, the future of semiconductor devices (flash-embedded logic LSIs) that integrate flash memory and state-of-the-art logic circuits together as a device that can reduce development costs as well as reduce costs by using a single chip. Is promising.
[0003]
Here, in order to integrate different types of devices such as flash memory and DRAM / logic into one chip, it is indispensable to improve the element density, and in order to improve the element density, miniaturization of processing dimensions is an essential condition. As important factors for miniaturizing the processing dimension, there are fidelity of the formation pattern with respect to the mask pattern and flatness in the substrate at the time of pattern formation by lithography.
[0004]
For miniaturization of processing accuracy, a technique for forming element isolation for insulating and isolating each element is important. As this element isolation formation method, a selective oxidation method (LOCOS method) has been conventionally used. However, this method has a problem that a pattern shift is caused by bird's beak, that is, the fidelity of a formation pattern with respect to a mask pattern is deteriorated. In order to improve the device density, the limit is almost approached. Therefore, recently, in the memory cell region, a trench isolation method in which no bird's beak is generated is used instead of the LOCOS method. As a conventional example of a flash memory using trench isolation, there is a technique disclosed in, for example, Japanese Patent Laid-Open No. 3-295276.
[0005]
FIG. 17 is a cross-sectional view showing the structure of the semiconductor device disclosed in the above publication. As shown in the figure, a P-type silicon substrate 201 is provided with a memory cell region Rmemo and a peripheral circuit region Rperi. Here, FIG. 17 shows a structure in a cross section perpendicular to the gate length direction in the memory cell region Rmemo, and a structure in a cross section parallel to the gate length direction in the peripheral circuit region Rperi. In the memory cell region Rmemo, a tunnel oxide film 213a, a floating gate electrode 214, a gate insulating film 215, a control gate electrode 216a, a silicide layer 220a, a source are formed in an active region surrounded by the trench type element isolation 218. A nonvolatile memory cell having an impurity layer (not shown) to be a drain region is provided. On the other hand, in the peripheral circuit region Rperi, a field effect having a gate oxide film 213b, a gate electrode 216b, a silicide layer 220b, and an impurity layer 223 serving as a source / drain region in an active region surrounded by the LOCOS film 212. A transistor is provided. An interlayer insulating film 222 is deposited on the substrate, and a bit line 224 is formed thereon. This conventional semiconductor device is formed by the following procedure, for example.
[0006]
First, after the LOCOS film 212 is formed in the peripheral circuit region Rperi, the tunnel oxide film 213a and the gate oxide film 213b are formed in the memory cell region Rmemo and the peripheral circuit region Rperi, respectively. Next, the floating gate electrode 214 and the gate insulating film 215 are selectively formed in the memory cell region Rmemo.
[0007]
Then, after depositing a gate electrode film on the entire surface of the substrate, it is patterned by lithography and etching to form a control gate electrode 216a in the memory cell region Rmemo and a gate electrode 216b in the peripheral circuit region Rperi.
[0008]
Further, a trench for element isolation surrounding the active region is formed in the memory cell region Rmemo by lithography and etching, and an insulating film is deposited on the entire surface of the substrate and then flattened, so that the insulating film is embedded in the trench and the groove is formed. A mold element isolation 218 is formed.
[0009]
Thereafter, silicide layers 220a and 220b are formed on the control gate electrode 216a and the gate electrode 216b, respectively, an interlayer insulating film 222 is deposited on the substrate, and a bit line 224 is formed thereon.
[0010]
Thus, by forming the groove type element isolation 218 in the memory cell region Rmemo, the fidelity of the formation pattern with respect to the mask pattern is improved, and the density of the memory cell region is increased. Further, by forming the trench type element isolation 218 on the floating gate electrode 213a in a self-aligning manner, the cell area is reduced.
[0011]
A process is also employed in which the floating gate electrode of the nonvolatile memory cell and the control gate electrode of the field effect transistor are formed of a common conductor film.
[0012]
[Problems to be solved by the invention]
However, the above conventional techniques have the following problems.
[0013]
Although the conventional technology can improve the device density in the memory cell region, in order to increase the density of the entire semiconductor device, not only the memory cell region but also the peripheral circuit region can be reduced. It is necessary to do it together. Thus, it is conceivable that the element isolation in the peripheral circuit region is also formed by the trench isolation method instead of the conventional LOCOS method. However, the conventional technique has a problem that the overall flatness cannot be kept good. That is, when an element isolation having a trench isolation structure is simultaneously formed in the memory cell region Rmemo and the peripheral circuit region Rperi, the presence of the floating gate 214 in the memory cell region Rmemo causes the control gate electrode 216a in the memory cell region Rmemo and the peripheral circuit to be formed. There will be a difference in height between the gate electrode 216b in the region Rperi and the flatness of the entire substrate will be deteriorated.
[0014]
That is, it is difficult to simultaneously realize the fidelity of the formation pattern with respect to the mask pattern and the flatness of the substrate, and it is difficult to realize a single chip such as a flash-embedded logic LSI.
[0015]
The present invention has been made in view of the above points, and an object of the present invention is to improve a device density of both the memory cell region and the peripheral circuit region by a simple method and to maintain a good flatness. The manufacturing method is provided.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, the basic means taken by the present invention is that, as a semiconductor device and a manufacturing method thereof, the upper surface of the semiconductor substrate in the active region of the peripheral circuit region is higher than the upper surface of the semiconductor substrate in the memory cell region. And the upper surface of the floating gateSame asIt is to have the same height.
[0028]
According to a first method of manufacturing a semiconductor device of the present invention, a nonvolatile memory cell having a tunnel insulating film, a floating gate electrode, a gate insulating film, and a control gate electrode is formed on a first active region of a memory cell region of a semiconductor substrate. On the other hand, a method of manufacturing a semiconductor device for forming a field effect transistor having a gate insulating film and a gate electrode on a second active region in a peripheral circuit region of a semiconductor substrate, the semiconductor substrate in the memory cell region A first step of forming a height difference between the upper surfaces of the peripheral circuit region so that the height position of the upper surface of the semiconductor substrate is lower than the height position of the upper surface of the semiconductor substrate in the peripheral circuit region; A tunnel insulating film and a first conductor film are sequentially formed on the upper surface of the semiconductor substrate, and the height position of the upper surface of the first conductor film is set in the peripheral circuit region. After the second step, which is the same as the height position of the upper surface of the conductor substrate, and the second step, the first and second active regions are respectively formed on the semiconductor substrate in the memory cell region and the peripheral circuit region. A third step of forming a surrounding element isolation groove and a fourth step of filling the groove with an insulating film to form a trench type element isolation;The first step includes a step of partially removing the semiconductor substrate in the memory cell region to a certain depth by etching using a mask member having an opening on the memory cell region.
[0029]
By this method, in the second step, the first conductor film in the memory cell region and the upper surface of the semiconductor substrate in the peripheral circuit region are planarized, and in the third and fourth steps, an element having a trench isolation structure is formed. Since the separation is formed, it is possible to form a semiconductor device having good flatness and having elements at high density throughout.
[0030]
UpIn the first method of manufacturing a semiconductor device, after the fourth step, a step of sequentially forming an insulating film for a gate insulating film, a second conductor film, and a conductor protective film on the substrate, and formation of a control gate electrode The conductor protective film and the second conductor film are selectively removed by etching using a mask member covering the region and the gate electrode formation region, and the control gate electrode and the upper layer are formed in the first active region. And forming the gate electrode in the second active region, and removing the mask member and then using the mask member covering the peripheral circuit region and the electrode protective film as a mask. A step of selectively removing the gate insulating film insulating film and the first conductive film by etching to form a floating gate electrode in the first active region.AndThus, since the gate insulating film and floating gate electrode in the memory cell region and the gate insulating film and gate electrode in the peripheral circuit region are formed by a common member, it is possible to form a high-density semiconductor device inexpensively and easily. It becomes possible. Further, since the floating gate electrode is formed by etching using the control gate electrode as a mask, a mask alignment margin is not required, and the memory cell region can be densified.
[0031]
UpIn the first method of manufacturing a semiconductor device, after the fourth step, a step of sequentially forming an insulating film for a gate insulating film and a second conductor film on the substrate, and the memory cell region and the gate electrode formation region And a step of selectively removing the second conductive film by etching using a mask member covering the first active region to form a gate electrode in the second active region; The second conductor film, the gate insulating film insulating film, and the first conductor film are selectively removed sequentially by etching using a mask member that covers the circuit region and the control gate electrode formation region, Forming a control gate electrode and a floating gate electrode in the first active region.AndFurther, since the gate insulating film and floating gate electrode in the memory cell region and the gate insulating film and gate electrode in the peripheral circuit region are formed by common members, a high-density semiconductor device can be formed easily and inexpensively. It becomes possible. Further, since the floating gate electrode and the control gate electrode are formed by etching using a common mask member, a mask alignment margin is not required, and the memory cell region can be densified.
[0032]
UpIn the first method of manufacturing a semiconductor device, the first conductor film is selectively formed by etching using a mask member covering the peripheral circuit region and the floating gate electrode formation region after the fourth step. Removing and forming a floating gate electrode in the first active region; and after removing the mask member, sequentially forming a gate insulating film insulating film and a second conductor film on the substrate; The first conductor film, the gate insulating film insulating film, and the second conductor film are selectively removed by etching using a mask member that covers the control gate electrode forming region and the gate electrode forming region, Forming a control gate electrode extending from the floating gate electrode to the semiconductor substrate in the first active region and a gate electrode in the second active region.AndThus, a semiconductor device having a high-density split gate type nonvolatile memory cell is formed.
[0033]
UpIn the first method of manufacturing a semiconductor device, the gate insulating film insulating film is formed such that the thickness of the gate insulating film insulating film in the memory cell region is larger than the thickness in the peripheral circuit region. ThisAndThus, a non-volatile memory cell and a field effect having different appropriate thicknesses in the gate insulating film functioning as a capacitive insulating film between the floating gate electrode and the control gate electrode of the non-volatile memory cell and the gate insulating film of the field effect transistor, respectively. A semiconductor device including a transistor is formed.
[0041]
The second method for manufacturing a semiconductor device of the present invention is as follows.HalfA non-volatile memory cell having a tunnel insulating film, a floating gate electrode, a gate insulating film and a control gate electrode is formed on the first active region of the memory cell region of the conductor substrate, while the second of the peripheral circuit region of the semiconductor substrate is formed. A method of manufacturing a semiconductor device for forming a field effect transistor having a gate insulating film and a gate electrode on an active region, wherein the memory cell region is exposed while the semiconductor substrate is exposed in the peripheral circuit region. A first step of forming a tunnel insulating film, a first conductor film on the tunnel insulating film, and a conductor protective film on the first conductor film; Height position of the upper surface of the first conductor film in the regionSame asA second step of forming the same semiconductor crystal film, a third step of removing the first conductor protective film on the first conductor film, and the memory cell region and the peripheral circuit region A fourth step of forming a trench for element isolation surrounding the first and second active regions, and a fifth step of filling the trench with an insulating film to form a trench type isolation.
[0042]
By this method, when the first step is completed, a height difference is formed between the upper surface of the semiconductor substrate in the memory cell region and the upper surface of the semiconductor substrate in the peripheral circuit region, and the floating of the nonvolatile memory cell is performed. The upper surface of the first conductor film constituting the gate electrode and the upper surface of the semiconductor substrate in the peripheral circuit region are planarized. Therefore, as in the first method for manufacturing a semiconductor device, a highly dense semiconductor device with good flatness can be easily formed.
[0043]
In the second method for manufacturing a semiconductor device, the first step can be easily realized by the following steps.
[0044]
UpIn the second method of manufacturing a semiconductor device, the first step includes a step of sequentially forming a tunnel insulating film, a first conductor film, and a conductor protective film on the semiconductor substrate, and a memory cell region. A step of sequentially removing the conductor protective film, the first conductor film, and the tunnel insulating film in the peripheral circuit region by etching using a mask member for covering can be included.
[0045]
UpIn the second method of manufacturing a semiconductor device, the first step uses a step of sequentially forming a tunnel insulating film and a first conductor film on the semiconductor substrate, and a mask member covering the memory cell region. Removing the first conductor film and the tunnel insulating film in the peripheral circuit region by etching, and removing the mask member, and then removing the first conductor film and the peripheral circuit region in the memory cell region. A step of forming a first conductor protective film on the semiconductor substrate so as to be thicker on the first conductor film than on the semiconductor substrate; and etching back in the memory cell region. A step of removing the first conductor protective film in the peripheral circuit region under a condition that the first conductor protective film on the first conductor film remains.
[0046]
UpIn the second method of manufacturing a semiconductor device, in the first step, a step of sequentially forming a tunnel insulating film, a first conductor film, and a first conductor protective film on the semiconductor substrate, and the memory A step of removing the first conductor protective film, the first conductor film, and the tunnel insulating film in the peripheral circuit region by etching using a mask member covering the cell region; and after removing the mask member, And forming a second conductor protective film on the side surface of the first conductor film on the condition that the first conductor protective film on the first conductor film remains by etching back. A step of removing the second conductor protective film while leaving the conductor protective film.
[0047]
UpIn the second method of manufacturing a semiconductor device, after the fifth step, a step of forming an insulating film for a gate insulating film, a second conductor film, and a protective film on the substrate, a control gate electrode formation region, and a gate The protective film and the second conductor film are selectively removed by etching using a mask member covering the electrode forming region, and the control gate electrode and the electrode protective film thereon are provided in the first active region. Forming a gate electrode in each of the second active regions, and removing the mask member and then etching using the mask member covering the peripheral circuit region and the electrode protective film as a mask. A step of selectively removing the gate insulating film insulating film and the first conductor film to form a floating gate electrode in the first active region.
[0048]
UpIn the second semiconductor device manufacturing method, after the fifth step, a step of sequentially forming an insulating film for a gate insulating film and a second conductor film on the substrate, and the memory cell region and the gate electrode forming region And a step of selectively removing the second conductive film by etching using a mask member covering the first active region to form a gate electrode in the second active region; The second conductor film, the gate insulating film insulating film, and the first conductor film are selectively removed sequentially by etching using a mask member that covers the circuit region and the control gate electrode formation region, Forming a control gate electrode and a floating gate electrode in the first active region.
[0049]
UpIn the second method of manufacturing a semiconductor device, after the fifth step, the first conductor film is selectively formed by etching using a mask member that covers the peripheral circuit region and the floating gate electrode formation region. Removing and forming a floating gate electrode in the first active region; and after removing the mask member, sequentially forming a gate insulating film insulating film and a second conductor film on the substrate; The first conductor film, the gate insulating film insulating film, and the second conductor film are selectively removed by etching using a mask member that covers the control gate electrode forming region and the gate electrode forming region, Forming a control gate electrode extending from the floating gate electrode in the first active region to the semiconductor substrate in the memory cell region, and a gate electrode in the peripheral circuit region. Can.
[0050]
UpIn the second method for manufacturing a semiconductor device, the gate insulating film insulating film is formed such that the thickness of the gate insulating film insulating film in the memory cell region is larger than the thickness in the peripheral circuit region. It is preferable.
[0051]
The third method for manufacturing a semiconductor device of the present invention is as follows.HalfA nonvolatile memory cell having a tunnel insulating film, a floating gate electrode, a gate insulating film, and a control gate electrode is formed on at least a first active region of the memory cell region of the conductor substrate, while at least a first peripheral circuit region of the semiconductor substrate is formed. A method of manufacturing a semiconductor device for forming a field effect transistor having a gate insulating film and a gate electrode on two active regions, wherein the height position of the upper surface of the semiconductor substrate in the memory cell region is the peripheral circuit region A first step of forming a height difference between the upper surfaces of the semiconductor substrate so as to be lower than a height position of the upper surface of the semiconductor substrate, and a tunnel insulating film and a second layer on the upper surface of the semiconductor substrate in the memory cell region. 1 conductor film is formed in sequence, and the height position of the upper surface of the first conductor film is set to the height of the upper surface of the semiconductor substrate in the peripheral circuit region. PositionSame asThe second step ofAfter the third step of forming the gate insulating film insulating film and the second conductor film on the substrate, and after the third step,Element isolation trenches are formed in the semiconductor substrate in the memory cell region and the peripheral circuit region to surround the first and second active regions, respectively.4thAnd a fifth step of filling the trench with an insulating film to form trench type element isolation.
[0052]
According to this method, it is possible to form a semiconductor device in which a field effect transistor having a gate electrode made of two conductor films is arranged in the peripheral circuit region and can exhibit the above-described effects.
[0053]
BookA fourth method of manufacturing a semiconductor device of the invention isHalfA non-volatile memory cell having a tunnel insulating film, a floating gate electrode, a gate insulating film and a control gate electrode is formed on the first active region of the memory cell region of the conductor substrate, while the second of the peripheral circuit region of the semiconductor substrate is formed. A method of manufacturing a semiconductor device for forming a field effect transistor having a gate insulating film and a gate electrode on an active region, wherein the memory cell region is exposed while the semiconductor substrate is exposed in the peripheral circuit region. A first step of forming a tunnel insulating film, a first conductor film on the tunnel insulating film, and a conductor protective film on the first conductor film; and the semiconductor substrate in the peripheral circuit region A semiconductor crystal is grown thereon, and the height position of the upper surface is the height position of the upper surface of the first conductor film in the memory cell region.Same asA second step of forming the same semiconductor crystal film, a third step of removing the first conductor protective film on the first conductor film, a gate insulating film insulating film and a second step on the substrate A fourth step of forming a second conductor film, a fifth step of forming an element isolation groove surrounding the first and second active regions in the memory cell region and the peripheral circuit region, and the groove Is embedded with an insulating film to form a trench type element isolation.
[0054]
By this method, a semiconductor device is formed in which a field effect transistor having a semiconductor substrate in a peripheral circuit formed by epitaxial growth and having a gate electrode made of two conductor films is arranged in the peripheral circuit region.The
[0055]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
First, a semiconductor device and a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. 1, 2 a to 2 f and FIGS. 3 a to 3 e.
[0056]
FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. In the figure, 10 is a semiconductor substrate, 111 is a control gate electrode in the memory cell region Rmemo, 112 is a floating gate electrode, 113 is a gate electrode in the peripheral circuit region Rperi, 102 is a buried insulating film constituting element isolation, and 121 is an interlayer An insulating film, 122 is a connection hole, and 123 is a metal wiring.
[0057]
2a to 2f and FIGS. 3a to 3e are cross-sectional views illustrating manufacturing steps of the semiconductor device according to the first embodiment. However, both are cross-sectional views taken along the line 9A-9A shown in FIG. In other words, in the memory cell region Rmemo and the peripheral circuit region Rperi, cross-sectional views of the memory cell and the MOSFET in a cross section parallel to the gate length direction and a cross section orthogonal to the gate length direction are shown.
[0058]
First, in the step shown in FIG. 2a, the surface of the semiconductor substrate 10 is oxidized to form a pad oxide film 21 having a thickness of about 10 nm, and a silicon nitride film 22 having a thickness of about 150 nm is deposited thereon. Thereafter, a resist film 51 having an opening is formed on the memory cell region Rmemo, and the silicon nitride film 22 in the memory cell region is removed by etching using the resist film 51 as a mask.
[0059]
Next, in the step shown in FIG. 2b, after removing the resist film 51, the entire surface of the substrate is oxidized to further thicken the pad oxide film 21 whose surface is exposed in the memory cell region Rmemo, and the thickness is about 200 nm. The field oxide film 103 is formed.
[0060]
Next, in the step shown in FIG. 2c, the silicon nitride film 22, the pad oxide film 21 and the field oxide film 103 on the semiconductor substrate 10 are all removed.
[0061]
Next, in the step shown in FIG. 2d, the entire surface of the semiconductor substrate 10 is oxidized to form a tunnel oxide film 31 having a thickness of about 10 nm, and a polycrystalline silicon film having a thickness of about 100 nm, which is a first conductor film. 32 is deposited.
[0062]
Next, in the step shown in FIG. 2e, CMP (chemical mechanical polishing) using the tunnel oxide film 31 as a stopper is performed to remove the polycrystalline silicon film 32 in the peripheral circuit region Rperi and planarize the entire substrate. At this time, the polycrystalline silicon film 32 is exposed in the memory cell region Rmemo, and the tunnel oxide film 31 is exposed in the peripheral circuit region Rperi. Thereafter, only the tunnel oxide film 31 exposed in the peripheral circuit region Rperi is removed by selective etching.
[0063]
Next, in the step shown in FIG. 2f, after the pad oxide film 23 and the silicon nitride film 24 are formed on the entire surface of the substrate, a resist film 52 having openings in regions where element isolation is to be formed is formed. Then, the silicon nitride film 24, the pad oxide film 23, the polycrystalline silicon film 32, the tunnel oxide film 31, and a part of the semiconductor substrate 10 are selectively sequentially formed by etching using the resist film 52 as a mask. By removing, a trench 101 for element isolation is formed.
[0064]
Next, in the step shown in FIG. 3A, a silicon oxide film is deposited by CVD and planarized by CMP to form a buried insulating film 102 in the element isolation trench 101.
[0065]
Next, in the step shown in FIG. 3B, the silicon nitride film 24 and the pad oxide film 23 are removed by selective etching (for example, wet etching) to make the upper surface of the substrate substantially flat. At this time, the surface of the polycrystalline silicon film 32 is exposed in the memory cell region Rmemo, while the surface of the semiconductor substrate 10 is exposed in the peripheral circuit region Rperi.
[0066]
Next, in the step shown in FIG. 3c, a gate oxide film 33 with a thickness of about 10 nm, a polycrystalline silicon film 34 as a second conductor film with a thickness of about 150 nm, and a conductor protective film are formed on the entire surface of the substrate. A silicon oxide film 35 having a thickness of about 150 nm is formed.
[0067]
Next, in a step shown in FIG. 3d, a resist film 53 is formed to cover a region in the memory cell region Rmemo where the control gate electrode is to be formed and a region in which the gate electrode in the peripheral circuit region Rperi is to be formed. The silicon oxide film 35 and the polycrystalline silicon film 34 are selectively removed by etching using the resist film 53 as a mask to form a control gate electrode 111 in the memory cell region Rmemo, and a gate electrode in the peripheral circuit region Rperi. 113 is formed. In any region, the electrode protection film is constituted by the patterned silicon oxide film 35.
[0068]
Next, in the step shown in FIG. 3e, after the resist film 53 is removed, a resist film 51 having an opening in the memory cell region Rmemo is formed, and the gate oxidation of the memory cell region Rmemo is performed by etching using the resist film 51 as a mask. The floating gate electrode 112 is formed in the memory cell region Rmemo by selectively removing the film 33 and the polycrystalline silicon film 32.
[0069]
Although the illustration of the subsequent steps is omitted, after removing the resist film 51, an interlayer insulating film, a contact hole, a wiring layer, etc. are formed, and a nonvolatile memory cell is formed in the memory cell region Rmemo. In the peripheral circuit region Rperi, a field effect transistor arranged in a memory cell driving circuit and a field effect transistor arranged in a logic circuit are formed.
[0070]
According to this embodiment, first, in the steps shown in FIGS. 2a to 2c, the thickness of the floating gate electrode and the tunnel oxide film between the upper surface of the semiconductor substrate in the memory cell region and the upper surface of the semiconductor substrate in the peripheral circuit region. By forming a height difference that anticipates the above, the subsequent steps can be easily and accurately performed, and the following effects can be obtained.
[0071]
In the memory cell region Rmemo of the semiconductor device formed by the above manufacturing process, the embedded insulating film 102 constituting element isolation in the cross section orthogonal to the gate length direction is compared with the floating gate electrode 112, and the floating gate electrode 112 is Since each control gate electrode 111 is formed in a self-aligned manner, a margin for mask alignment for forming each member becomes unnecessary, and the memory cell region Rmemo can be further densified.
[0072]
In addition, since the upper surface of the substrate is flattened in the step immediately before forming the trench isolation (the step shown in FIG. 2e), the photolithography step when forming the resist film 52 for element isolation formation is performed with high accuracy. In addition to being easy to perform, the insulating film can be embedded in the element isolation trench 101 and then flattened without any restrictions. As a result, the trench isolation of both the memory cell region Rmemo and the peripheral circuit region Rperi can be finely formed by a simple process in a single trench isolation formation process. In both the peripheral circuit region Rperi and the memory cell region Rmemo, element isolation is formed by trench isolation instead of the LOCOS film, so that the density of the entire semiconductor device can be increased.
[0073]
Further, in the manufacturing process of the present embodiment, in the process of forming the control gate electrode 111 and the gate electrode 113 (see FIG. 3d), there is almost no difference in height between the memory cell region Rmemo and the peripheral circuit region Rperi, and it is almost flat. Therefore, a photolithography process for forming the resist film 53 for forming the gate electrode can be easily performed with high accuracy, and the control gate electrode 111 in the memory cell region Rmemo and the gate electrode 113 in the peripheral circuit region Rperi Since the upper surface positions of the two are the same, the subsequent metal wiring pattern can be easily formed.
[0074]
Therefore, the flash memory and the heterogeneous device such as DRAM / logic can be made into one chip at a production cost that can be put into practical use.
[0075]
(Second Embodiment)
Next, a second embodiment will be described with reference to FIGS. Also in the present embodiment, the structure of the semiconductor device is the same as that in the first embodiment. 4A to 4E are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the second embodiment. However, both are cross-sectional views taken along the line 9A-9A shown in FIG.
[0076]
Also in the present embodiment, the same processing as that shown in FIGS. 2A to 2F is performed as in the first embodiment. Description of these processes is omitted.
[0077]
Next, in the step shown in FIG. 4A, a silicon oxide film is deposited by CVD and flattened by CMP to form a buried insulating film 102 in the trench.
[0078]
Next, in the step shown in FIG. 4B, the silicon nitride film 24 and the pad oxide film 23 are removed. At this time, the surface of the polycrystalline silicon film 32 is exposed in the memory cell region Rmemo, while the surface of the semiconductor substrate 10 is exposed in the peripheral circuit region Rperi.
[0079]
Next, in the step shown in FIG. 4c, a gate oxide film 33 having a thickness of about 10 nm and a polycrystalline silicon film 34 as a second conductor film having a thickness of about 150 nm are formed on the entire surface of the substrate.
[0080]
Next, in the step shown in FIG. 4d, a resist film 54 covering the entire memory cell region Rmemo and the region where the gate electrode of the peripheral circuit region Rperi is to be formed is formed, and etching using this resist film 54 as a mask is performed. The polycrystalline silicon film 34 is selectively removed, and a gate electrode 113 is formed in the peripheral circuit region Rperi.
[0081]
Next, in the step shown in FIG. 4e, after removing the resist film 54, a resist film 55 is formed to cover the entire peripheral circuit region Rperi and the region where the control gate electrode of the memory cell region Rmemo is to be formed. By etching using the film 55 as a mask, the polycrystalline silicon film 34, the gate oxide film 33 and the polycrystalline silicon film 32 in the memory cell region Rmemo are selectively removed, and the control gate electrode 111 and the floating gate are formed in the memory cell region Rmemo. An electrode 112 is formed.
[0082]
Although illustration of the subsequent steps is omitted, after removing the resist film 55, an interlayer insulating film, a contact hole, a wiring layer, etc. are formed, and a nonvolatile memory cell is formed in the memory cell region Rmemo. In the peripheral circuit region Rperi, a field effect transistor arranged in a memory cell driving circuit and a field effect transistor arranged in a logic circuit are formed.
[0083]
According to the present embodiment, in the memory cell region Rmemo, the buried insulating film 102 constituting the element isolation in the cross section orthogonal to the gate length direction is the floating gate electrode 112, and the floating gate electrode 112 is the control gate electrode 111. On the other hand, since they are formed in a self-aligned manner, the memory cell region Rmemo can be further densified as in the first embodiment.
[0084]
In addition, since the upper surface of the substrate is flattened in the step immediately before forming the trench isolation (the step shown in FIG. 2e), the trench isolation forming step can be easily performed in the same manner as in the first embodiment. The trench isolation of both the memory cell region Rmemo and the peripheral circuit region Rperi can be finely formed by a simple process. In both the peripheral circuit region Rperi and the memory cell region Rmemo, element isolation is formed by trench isolation instead of the LOCOS film, so that the density of the entire semiconductor device can be increased.
[0085]
Further, in the process immediately before the formation of the control gate electrode 111 and the gate electrode 113 (see FIG. 4c), there is almost no difference in height between the memory cell region Rmemo and the peripheral circuit region Rperi. Since the top surface positions of the control gate electrode 111 of Rmemo and the gate electrode 113 of the peripheral circuit region Rperi are the same, the subsequent metal wiring pattern can be easily formed.
[0086]
Therefore, according to the manufacturing method of the present embodiment, as in the first embodiment, different devices such as a flash memory and a DRAM / logic can be integrated into one chip at a practical manufacturing cost. .
[0087]
In particular, according to the manufacturing method of the semiconductor device of this embodiment, it is not necessary to provide a conductor protective film made of a silicon oxide film or the like on the polycrystalline silicon film 34 as compared with the manufacturing method of the first embodiment. The process can be simplified by as much.
[0088]
In the present embodiment, the gate electrode 113 in the peripheral circuit region Rperi is formed first and then the control gate electrode 111 and the floating gate electrode 112 in the memory cell region Rmemo are formed. However, the control gate electrode in the memory cell region Rmemo is first formed. After forming 111 and the floating gate electrode 112, the gate electrode 113 in the peripheral circuit region Rperi may be formed.
[0089]
(Third embodiment)
Next, a third embodiment will be described with reference to FIGS. 5a to 5e are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the third embodiment. However, both are cross-sectional views taken along the line 9A-9A shown in FIG. In other words, in the memory cell region Rmemo and the peripheral circuit region Rperi, cross-sectional views of the memory cell and the MOSFET in a cross section parallel to the gate length direction and a cross section orthogonal to the gate length direction are shown.
[0090]
Also in the present embodiment, the same processing as that shown in FIGS. 2A to 2F is performed as in the first embodiment. Description of these processes is omitted.
[0091]
Next, in the step shown in FIG. 5a, a silicon oxide film is deposited by CVD and flattened by CMP to form a buried insulating film 102 in the trench.
[0092]
Next, in the step shown in FIG. 5B, the silicon nitride film 24 and the pad oxide film 23 are removed. At this time, the surface of the polycrystalline silicon film 32 is exposed in the memory cell region Rmemo, while the surface of the semiconductor substrate 10 is exposed in the peripheral circuit region Rperi.
[0093]
Next, in the step shown in FIG. 5C, a resist film 56 is formed to cover the entire peripheral circuit region Rperi and the region where the floating gate electrode of the memory cell region Rmemo is to be formed, and etching is performed using this resist film 56 as a mask. The floating gate electrode 112 is formed in the memory cell region Rmemo.
[0094]
Next, in the step shown in FIG. 5d, after removing the resist film 56, a gate oxide film 33 having a thickness of about 10 nm and a polycrystalline silicon film as a second conductor film having a thickness of about 150 nm are formed on the entire surface of the substrate. 34.
[0095]
Next, in the step shown in FIG. 5e, a resist film 53 is formed to cover the region where the control gate electrode of the memory cell region Rmemo is to be formed and the region where the gate electrode of the peripheral circuit region Rperi is to be formed. The polycrystalline silicon film 34 is selectively removed by etching using the film 53 as a mask to form the gate electrode 113 in the peripheral circuit region Rperi, while the floating gate is formed in the memory cell region Rmemo via the gate oxide film 33. A control gate electrode 111 extending from the electrode 112 to the semiconductor substrate 10 is formed.
[0096]
Although illustration of subsequent steps is omitted, after removing the resist film 53, an interlayer insulating film, contact holes, a wiring layer, etc. are formed, and a nonvolatile memory cell is formed in the memory cell region Rmemo. In the peripheral circuit region Rperi, a field effect transistor arranged in a memory cell driving circuit and a field effect transistor arranged in a logic circuit are formed.
[0097]
According to the manufacturing method of the present embodiment, the above-described first gate is also applied to the split gate type memory cell having better data retention characteristics than the stacked gate type memory cell as in the first and second embodiments. The same effects as those of the second embodiment can be exhibited.
[0098]
That is, in the memory cell region Rmemo, the buried insulating film 102 constituting the element isolation is formed in a self-aligned manner with respect to the floating gate electrode 112 in the cross section orthogonal to the gate length direction. Similarly to the above, the memory cell region Rmemo can be further densified.
[0099]
In addition, since the upper surface of the substrate is flattened in the step immediately before forming the trench isolation (the step shown in FIG. 2e), the trench isolation forming step can be easily performed in the same manner as in the first embodiment. The trench isolation of both the memory cell region Rmemo and the peripheral circuit region Rperi can be finely formed by a simple process. In both the peripheral circuit region Rperi and the memory cell region Rmemo, element isolation is formed by trench isolation instead of the LOCOS film, so that the density of the entire semiconductor device can be increased.
[0100]
Further, in the process immediately before the formation of the floating gate electrode 112 (see FIG. 5b), there is almost no difference in level between the memory cell region Rmemo and the peripheral circuit region Rperi, so that the subsequent photolithography process is smooth. The metal wiring pattern can be easily formed.
[0101]
Therefore, according to the manufacturing method of this embodiment, as in the first and second embodiments, different devices such as flash memory and DRAM / logic can be integrated into one chip at a practical manufacturing cost. It becomes.
[0102]
(Fourth embodiment)
Next, a fourth embodiment will be described with reference to FIGS. 6, 7 a to 7 g and FIGS. 8 a to 7 d. However, both are cross-sectional views taken along the line 9A-9A shown in FIG. In other words, in the memory cell region Rmemo and the peripheral circuit region Rperi, cross-sectional views of the memory cell and the MOSFET in a cross section parallel to the gate length direction and a cross section orthogonal to the gate length direction are shown.
[0103]
FIG. 6 is a cross-sectional view of the semiconductor device according to the fourth and fifth embodiments. In the figure, 10 is a semiconductor substrate, 111 is a control gate electrode in the memory cell region Rmemo, 112 is a floating gate electrode, 113 is a gate electrode in the peripheral circuit region Rperi, 102 is a buried insulating film constituting element isolation, and 121 is an interlayer An insulating film, 122 is a connection hole, and 123 is a metal wiring. The characteristics of the semiconductor device with respect to the structure of the semiconductor device according to the first to third embodiments is that the control gate electrode 111 in the memory cell region Rmemo and the gate electrode 113 in the peripheral circuit region Rperi are both multi-layered. The point is that it is composed of a crystalline silicon film.
[0104]
7a to 7g and FIGS. 8a to 8d are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the present embodiment.
[0105]
First, in the step shown in FIG. 7a, the semiconductor substrate 10 is oxidized to form a pad oxide film 21 having a thickness of about 10 nm, and a silicon nitride film 22 having a thickness of about 150 nm is deposited thereon. Thereafter, a resist film 51 having an opening in the memory cell region Rmemo is formed, and the silicon nitride film 22 in the memory cell region Rmemo is removed by etching using the resist film 51 as a mask.
[0106]
Next, in the step shown in FIG. 7B, after removing the resist film 51, the entire surface of the substrate is oxidized, and the pad oxide film 21 whose surface is exposed in the memory cell region Rmemo is further thickened. Form.
[0107]
Next, in the step shown in FIG. 7c, the silicon nitride film 22, the pad oxide film 21 and the field oxide film 103 on the semiconductor substrate 10 are all removed.
[0108]
Next, in the step shown in FIG. 7d, the entire surface of the semiconductor substrate 10 is oxidized to form a tunnel oxide film 31 having a thickness of about 10 nm, and a polycrystalline silicon film having a thickness of about 100 nm, which is a first conductor film. 32 is deposited.
[0109]
Next, in the step shown in FIG. 7e, CMP using the tunnel oxide film 31 as a stopper is performed to remove the polycrystalline silicon film 32 in the peripheral circuit region Rperi and planarize the entire substrate. At this time, the polycrystalline silicon film 32 is exposed in the memory cell region Rmemo, and the tunnel oxide film 31 is exposed in the peripheral circuit region Rperi. Thereafter, only the tunnel oxide film 31 exposed in the peripheral circuit region Rperi is removed by selective etching.
[0110]
Next, in the step shown in FIG. 7f, a gate oxide film 33 having a thickness of about 10 nm and a polycrystalline silicon film 34 having a thickness of about 150 nm are formed as a second conductor film on the entire surface of the substrate.
[0111]
Next, in the step shown in FIG. 7g, a resist film 52 having an opening in a region where element isolation is to be formed is formed. Then, by etching using the resist film 52 as a mask, the polycrystalline silicon film 34, the gate oxide film 33, the polycrystalline silicon film 32, the tunnel oxide film 31, and the substrate 10 are sequentially etched to form the element isolation trench 101. To do.
[0112]
Next, in the step shown in FIG. 8a, deposition of a silicon oxide film by CVD and planarization by CMP using the polycrystalline silicon film 34 as a stopper are performed to form a buried insulating film 102 in the trench 101 for element isolation. .
[0113]
Next, in the step shown in FIG. 8b, a polycrystalline silicon film 36 having a thickness of about 50 nm and a silicon oxide film 35 having a thickness of about 150 nm are formed as a third conductor film on the entire surface of the substrate. To do.
[0114]
Next, in a step shown in FIG. 8C, a resist film 53 is formed to cover a region where the control gate electrode of the memory cell region memo is to be formed and a region where the gate electrode of the peripheral circuit region Rperi is to be formed. The silicon oxide film 35, the polycrystalline silicon film 36, and the polycrystalline silicon film 34 are selectively removed by etching using the film 53 as a mask, and the control gate electrode 111 in the memory cell region Rmemo and the gate electrode in the peripheral circuit region Rperi 113.
[0115]
Next, in the step shown in FIG. 8D, after removing the resist film 53, a resist film 51 is formed to open the memory cell region Rmemo and cover the peripheral circuit region Rperi. The resist film 51, the control gate electrode 111, and the silicon oxide The gate oxide film 33 and the polycrystalline silicon film 32 in the memory cell region Rmemo are selectively removed by etching using the film 35 as a mask, and the floating gate electrode 112 is formed in the memory cell region Rmemo.
[0116]
Although the illustration of the subsequent steps is omitted, after removing the resist film 51, an interlayer insulating film, a contact hole, a wiring layer, etc. are formed, and a nonvolatile memory cell is formed in the memory cell region Rmemo. In the peripheral circuit region Rperi, a field effect transistor arranged in a memory cell driving circuit and a field effect transistor arranged in a logic circuit are formed.
[0117]
According to the present embodiment, in the memory cell region Rmemo, the buried insulating film 102 constituting the element isolation in the cross section orthogonal to the gate length direction is the floating gate electrode 112, and the floating gate electrode 112 is the control gate electrode 111. On the other hand, since they are formed in a self-aligned manner, the memory cell region Rmemo can be further densified as in the first to third embodiments.
[0118]
In addition, since the upper surface of the substrate is planarized in the process immediately before forming the trench isolation (the process shown in FIG. 7f), the trench isolation forming process is performed once as in the first to third embodiments. Thus, the trench isolation of both the memory cell region Rmemo and the peripheral circuit region Rperi can be finely formed by a simple process. In both the peripheral circuit region Rperi and the memory cell region Rmemo, element isolation is formed by trench isolation instead of the LOCOS film, so that the density of the entire semiconductor device can be increased.
[0119]
Further, in the process immediately before the formation of the control gate electrode 111 and the gate electrode 113 (see FIG. 8b), there is almost no difference in height between the memory cell region Rmemo and the peripheral circuit region Rperi. Since the top surface positions of the control gate electrode 111 of Rmemo and the gate electrode 113 of the peripheral circuit region Rperi are the same, the subsequent metal wiring pattern can be easily formed.
[0120]
Therefore, according to the manufacturing method of the present embodiment, as in the first embodiment, different devices such as a flash memory and a DRAM / logic can be integrated into one chip at a practical manufacturing cost. .
[0121]
In particular, according to the manufacturing method of the semiconductor device of the present embodiment, the gate electrode 113 in the peripheral circuit region Rperi is formed of two layers of polycrystalline silicon film, and the element isolation is self-aligned with the lower layer film 34 of the gate electrode 113 Since it is formed (see the right end portion in FIG. 8d), it is possible to suppress characteristic fluctuation due to electric field concentration from the side surface of the trench, which is a problem in normal trench isolation.
[0122]
(Fifth embodiment)
Next, a fifth embodiment will be described with reference to FIGS. 10a to 10d. 10a to 10d are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the fifth embodiment. However, both are cross-sectional views taken along the line 9A-9A shown in FIG. In other words, in the memory cell region Rmemo and the peripheral circuit region Rperi, cross-sectional views of the memory cell and the MOSFET in a cross section parallel to the gate length direction and a cross section orthogonal to the gate length direction are shown.
[0123]
Also in this embodiment, the same process as the process shown in FIGS. 7a to 7g described in the fourth embodiment is performed. Description of these processes is omitted.
[0124]
Next, in the step shown in FIG. 10A, a silicon oxide film is deposited by CVD and planarized by CMP using the polycrystalline silicon film 34 as a stopper to form a buried insulating film 102 in the element isolation trench 101. Next, as shown in FIG. .
[0125]
Next, in the step shown in FIG. 10b, a polycrystalline silicon film 36 having a thickness of about 50 nm is formed as a third conductor film on the entire surface of the substrate.
[0126]
Next, in the step shown in FIG. 10c, a resist film 54 is formed which covers the entire memory cell region memo and the region where the gate electrode of the peripheral circuit region Rperi is to be formed, and etching using this resist film 54 as a mask. The polycrystalline silicon film 36 and the polycrystalline silicon film 34 are selectively removed to form the gate electrode 113 in the peripheral circuit region Rperi.
[0127]
Next, in the step shown in FIG. 10d, after removing the resist film 54, a resist film 55 is formed to cover the region where the control gate electrode of the memory cell region Rmemo is to be formed and the entire peripheral circuit region Rperi. The polycrystalline silicon films 36 and 34, the gate oxide film 33 and the polycrystalline silicon film 32 in the memory cell region Rmemo are selectively removed by etching using the film 55 as a mask, and the control gate electrode 111 is formed in the memory cell region Rmemo. Then, the floating gate electrode 112 is formed.
[0128]
Although illustration of the subsequent steps is omitted, after removing the resist film 55, an interlayer insulating film, a contact hole, a wiring layer, etc. are formed, and a nonvolatile memory cell is formed in the memory cell region Rmemo. In the peripheral circuit region Rperi, a field effect transistor arranged in a memory cell driving circuit and a field effect transistor arranged in a logic circuit are formed.
[0129]
According to the present embodiment, in the memory cell region Rmemo, the buried insulating film 102 constituting the element isolation in the cross section orthogonal to the gate length direction is the floating gate electrode 112, and the floating gate electrode 112 is the control gate electrode 111. On the other hand, since they are formed in a self-aligned manner, the memory cell region Rmemo can be further densified as in the first to third embodiments.
[0130]
In addition, since the upper surface of the substrate is planarized in the process immediately before forming the trench isolation (the process shown in FIG. 7f), the trench isolation forming process is performed once as in the first to third embodiments. Thus, the trench isolation of both the memory cell region Rmemo and the peripheral circuit region Rperi can be finely formed by a simple process. In both the peripheral circuit region Rperi and the memory cell region Rmemo, element isolation is formed by trench isolation instead of the LOCOS film, so that the density of the entire semiconductor device can be increased.
[0131]
Further, as in the fourth embodiment, there is almost no difference in height between the memory cell region Rmemo and the peripheral circuit region Rperi in the step immediately before forming the control gate electrode 111 and the gate electrode 113 (see FIG. 10B). Since the upper surface of the control gate electrode 111 in the memory cell region Rmemo and the gate electrode 113 in the peripheral circuit region Rperi are the same, the subsequent metal wiring pattern can be easily formed.
[0132]
Therefore, according to the manufacturing method of the present embodiment, as in the fourth embodiment, different devices such as a flash memory and a DRAM / logic can be integrated into one chip at a practical manufacturing cost. .
[0133]
Similarly to the fourth embodiment, the gate electrode 113 in the peripheral circuit region Rperi is formed of a two-layered polycrystalline silicon film and the element isolation is formed in a self-aligned manner in the lower layer film 34 of the gate electrode 113. (See the right end portion of FIG. 10d), it is possible to suppress characteristic fluctuation due to electric field concentration from the side surface of the trench, which is a problem in normal trench isolation.
[0134]
In particular, in the manufacturing process of this embodiment, it is not necessary to provide a conductor protective film such as a silicon oxide film on the polycrystalline silicon film 36 as compared with the fourth embodiment, and the process can be simplified accordingly.
[0135]
In this embodiment, the gate electrode 113 in the peripheral circuit region Rperi is formed first and then the control gate electrode 111 and the floating gate electrode 112 in the memory cell region Rmemo are formed. However, the control gate in the memory cell region Rmemo is first formed. After forming the electrode 111 and the floating gate electrode 112, the gate electrode 113 in the peripheral circuit region Rperi may be formed.
[0136]
(Sixth embodiment)
Next, a method for manufacturing a semiconductor device according to the sixth embodiment will be described with reference to FIGS. 11a to 11f are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the sixth embodiment. However, both are cross-sectional views taken along the line 9A-9A shown in FIG. In other words, in the memory cell region Rmemo and the peripheral circuit region Rperi, cross-sectional views of the memory cell and the MOSFET in a cross section parallel to the gate length direction and a cross section orthogonal to the gate length direction are shown.
Also in this embodiment, first, the same processing as that shown in FIGS. 7a to 7g described in the fourth embodiment is performed. Description of these processes is omitted.
[0137]
Next, in the step shown in FIG. 11a, deposition of a silicon oxide film by CVD and planarization by CMP using the polycrystalline silicon film 34 as a stopper are performed to form a buried insulating film 102 in the trench 101 for element isolation. .
[0138]
Next, in the step shown in FIG. 11B, a resist film 51 having an opening in the memory cell region Rmemo is formed, and the polysilicon film 34 and the first gate in the memory cell region Rmemo are formed by etching using the resist film 51 as a mask. The oxide film 33 is selectively removed.
[0139]
Next, in the step shown in FIG. 11c, a resist film 56 is formed to cover the entire peripheral circuit region Rperi and the region where the floating gate electrode of the memory cell region Rmemo is to be formed, and etching is performed using this resist film 56 as a mask. Then, the polycrystalline silicon film 32 in the memory cell region Rmemo is selectively removed to form the floating gate electrode 112 in the memory cell region Rmemo.
[0140]
Next, in the step shown in FIG. 11d, after removing the resist film 56, a second gate oxide film 37 having a thickness of about 10 nm is formed on the entire surface of the substrate. Further, a resist film 57 having an opening in the peripheral circuit region Rperi is formed on the substrate, and the second gate oxide film 37 in the peripheral circuit region Rperi is removed by etching using the resist film 57 as a mask.
[0141]
Next, in the step shown in FIG. 11e, after removing the resist film 57, a polycrystalline silicon film 36 having a thickness of about 50 nm is deposited on the entire surface of the substrate as a third conductor film.
[0142]
Next, in a step shown in FIG. 11f, a resist film 53 is formed to cover the region where the control gate electrode of the memory cell region Rmemo is to be formed and the region where the gate electrode of the peripheral circuit region Rperi is to be formed. By etching using the film 53 as a mask, the polycrystalline silicon film 36 and the polycrystalline silicon film 34 are selectively removed to form the control gate electrode 111 in the memory cell region Rmemo and the gate electrode 113 in the peripheral circuit region Rperi.
[0143]
Although illustration of subsequent steps is omitted, after removing the resist film 53, an interlayer insulating film, contact holes, a wiring layer, etc. are formed, and a nonvolatile memory cell is formed in the memory cell region Rmemo. In the peripheral circuit region Rperi, a field effect transistor disposed in a memory cell driving circuit or a field effect transistor disposed in a logic circuit is formed.
[0144]
As described above, according to the present embodiment, the split gate type memory cell having better data retention characteristics than the stacked gate type memory cell as in the fourth and fifth embodiments can be used. 4. The same effects as those of the fifth embodiment can be exhibited.
[0145]
That is, in the memory cell region Rmemo, the buried insulating film 102 constituting element isolation in the cross section orthogonal to the gate length direction is self-aligned with respect to the floating gate electrode 112, and the floating gate electrode 112 is self-regarded with respect to the control gate electrode 111. Since they are formed in a consistent manner, the memory cell region Rmemo can be further densified.
[0146]
In addition, since the upper surface of the substrate is flattened in the process immediately before forming the trench isolation (the process shown in FIG. 7f), the memory cell region Rmemo and the peripheral circuit can be formed in a simple process in one trench isolation formation process. Both trench isolations in the region Rperi can be finely formed. In both the peripheral circuit region Rperi and the memory cell region Rmemo, element isolation is formed by trench isolation instead of the LOCOS film, so that the density of the entire semiconductor device can be increased.
[0147]
Further, in the step before the formation of the control gate electrode 111 and the gate electrode 113 (see FIG. 11a), there is almost no difference in height between the memory cell region Rmemo and the peripheral circuit region Rperi. Since the top surface positions of the control gate electrode 111 of Rmemo and the gate electrode 113 of the peripheral circuit region Rperi are the same, the subsequent metal wiring pattern can be easily formed.
[0148]
Therefore, according to the manufacturing method of the present embodiment, as in the fourth and fifth embodiments, different devices such as flash memory and DRAM / logic can be integrated into one chip at a practical manufacturing cost. It becomes.
[0149]
As in the fourth and fifth embodiments, the gate electrode 113 in the peripheral circuit region Rperi is formed of a two-layered polycrystalline silicon film and the element isolation is self-aligned with the lower layer film 34 of the gate electrode 113. Since it is formed (see the right end portion of FIG. 11f), it is possible to suppress characteristic fluctuation due to electric field concentration from the side surface of the trench, which is a problem in normal trench isolation.
[0150]
(Seventh embodiment)
Next, a method for manufacturing a semiconductor device according to the seventh embodiment will be described with reference to FIGS. 12A to 12C are cross-sectional views illustrating the planarization process in the manufacturing process of the semiconductor device according to the seventh embodiment.
[0151]
First, in the step shown in FIG. 12a, a resist film 51 is formed on the semiconductor substrate 10 so as to open the memory cell region Rmemo and cover the peripheral circuit region Rperi, and the memory cell region Rmemo is etched by using the resist film 51 as a mask. The semiconductor substrate 10 is removed by a depth of 100 nm.
[0152]
Next, in the step shown in FIG. 12B, after removing the resist film 51, the entire surface of the substrate is oxidized to form a tunnel oxide film 31 having a thickness of about 10 nm, and the first conductor is formed on the tunnel oxide film 31. A polycrystalline silicon film 32 having a thickness of 100 nm is formed as a film. Then, a resist film 57 covering the memory cell region Rmemo and opening the peripheral circuit region Rperi is formed on the polycrystalline silicon oxide film 32.
[0153]
Next, in the step shown in FIG. 12C, the polycrystalline silicon film 32 and the tunnel oxide film 31 in the peripheral circuit region are removed by etching using the resist film 57 as a mask.
[0154]
Although illustration of the subsequent steps is omitted, the floating gate electrode and the control gate electrode are formed in the memory cell region Rmemo by removing the resist film 57 and performing the same process as in the first to sixth embodiments. In the peripheral circuit region Rperi, a field effect transistor having a gate electrode can be formed. For example, the same process as the process shown in FIGS. 2f and 3a to 3e in the first embodiment and the process shown in FIGS. 7f and 7g and FIGS. 8a to 8d in the fourth embodiment is performed.
[0155]
According to the present embodiment, in the step shown in FIG. 12C, the polycrystalline silicon film 32 constituting the floating gate electrode is formed in the memory cell region Rmemo, and the upper surface of the polycrystalline silicon film 32 in the memory cell region Rmemo; The upper surface of the semiconductor substrate 10 in the peripheral circuit region Rperi is substantially flattened. Therefore, the element density in both the memory cell region Rmemo and the peripheral circuit region Rperi can be improved by a simpler process than the manufacturing process of the semiconductor device according to the first to sixth embodiments.
[0156]
In particular, according to the present embodiment, the height difference formation in which the height of the semiconductor substrate surface of the memory cell region Rmemo is made lower than the height of the semiconductor substrate surface of the peripheral circuit region Rperi in anticipation of the floating gate electrode and the tunnel oxide film. By forming the process by an etching method without using a normal LOCOS method, the process can be simplified. Further, a planarization process is performed by etching so that the height of the upper surface of the polycrystalline silicon film 32 which is the first conductor film in the memory cell region Rmemo and the semiconductor substrate surface of the peripheral circuit region Rperi are substantially equal. Variations in the film thickness of the first conductor film due to dishing in CMP can be suppressed.
[0157]
(Eighth embodiment)
Next, a method for manufacturing a semiconductor device according to the eighth embodiment will be described with reference to FIGS. 13A to 13E are cross-sectional views illustrating the planarization process in the manufacturing process of the semiconductor device according to the eighth embodiment.
[0158]
First, in the step shown in FIG. 13a, a silicon oxide film 25 having a thickness of about 100 nm is formed by oxidizing the entire surface of the semiconductor substrate 10, and a resist covering the memory cell region Rmemo and opening the peripheral circuit region Rperi thereon. After the film 57 is formed, the silicon oxide film 25 in the peripheral circuit region Rperi is removed by etching using the resist film 57 as a mask.
[0159]
Next, in the step shown in FIG. 13B, after removing the resist film 57, a single crystal silicon film 11 having a thickness of about 100 nm is grown by selective epitaxial growth on a region where the surface of the semiconductor substrate 10 in the peripheral circuit region Rperi is exposed. Let That is, the upper surface of the silicon oxide film 25 in the memory cell region Rmemo and the upper surface of the single crystal silicon film 11 in the peripheral circuit region Rperi are made to be substantially flat.
[0160]
Next, in the step shown in FIG. 13c, after the silicon oxide film 25 in the memory cell region Rmemo is removed, the entire surface of the substrate is oxidized to form a tunnel oxide film 31 having a thickness of about 10 nm, and the first oxide film is further formed thereon. A polycrystalline silicon film 32 having a thickness of about 100 is formed as one conductor film.
[0161]
Next, in the step shown in FIG. 13d, a resist film 58 covering the entire memory cell region Rmemo and the region that enters the peripheral circuit region Rperi by about 1 μm from the memory cell region Rmemo and opening the remaining peripheral circuit region Rperi. The polycrystalline silicon film 32 in the peripheral circuit region Rperi is removed by etching using the resist film 58 as a mask.
[0162]
Next, in the step shown in FIG. 13e, after removing the resist film 58, the polycrystalline silicon film 32 protruding at the boundary between the memory cell region Rmemo and the peripheral circuit region Rperi is removed by CMP. By removing the Rperi tunnel oxide film 31, the entire substrate is planarized.
[0163]
Although illustration of the subsequent steps is omitted, by performing the same processing as in the first to sixth embodiments, a memory cell having a floating gate electrode and a control gate electrode is formed in the memory cell region Rmemo, and the peripheral circuit region. A field effect transistor having a gate electrode can be formed in Rperi. For example, the same process as the process shown in FIGS. 2f and 3a to 3e in the first embodiment and the process shown in FIGS. 7f and 7g and FIGS. 8a to 8d in the fourth embodiment is performed.
[0164]
Also in this embodiment, in the step shown in FIG. 13e, the polycrystalline silicon film 32 constituting the floating gate electrode is formed in the memory cell region Rmemo, and the upper surface of the polycrystalline silicon film 32 and the peripheral circuit region Rperi are formed. The upper surface of the semiconductor substrate 10 is planarized. Therefore, as in the first to sixth embodiments, the device density in both the memory cell region Rmemo and the peripheral circuit region Rperi can be improved by a simple process.
[0165]
In particular, according to the present embodiment, the height difference of the semiconductor substrate surface in the memory cell region Rmemo is made lower than the height of the semiconductor substrate surface in the peripheral circuit region Rperi by the selective epitaxial growth, thereby forming the tunnel oxidation. The breakdown voltage of the film and the gate oxide film is improved. Further, a planarization process is performed by using both etching and CMP in which the upper surface of the polycrystalline silicon film 32 which is the first conductor film in the memory cell region Rmemo and the semiconductor substrate surface in the peripheral circuit region Rperi have the same height. This suppresses variations in the film thickness of the first conductor film due to dishing in CMP, and eliminates the need to consider the mask misalignment of the resist film 58 due to the substrate upper surface being not flat.
[0166]
(Ninth embodiment)
Next, a method for manufacturing a semiconductor device according to the ninth embodiment will be described with reference to FIGS. 14A to 14D are cross-sectional views illustrating the planarization process in the manufacturing process of the semiconductor device according to the ninth embodiment.
[0167]
First, in the step shown in FIG. 14a, the entire surface of the semiconductor substrate 10 is oxidized to form a tunnel oxide film 31 having a thickness of about 10 nm, and a polycrystalline silicon film having a thickness of about 100 nm is formed thereon as a first conductor film. 32 is formed. Then, after forming a resist film 57 covering the memory cell region Rmemo on the polycrystalline silicon film 32 and opening the peripheral circuit region Rperi, the polycrystalline silicon in the peripheral circuit region Rperi is etched by using the resist film 57 as a mask. The film 32 and the tunnel oxide film 31 are removed.
[0168]
Next, in the step shown in FIG. 14B, after removing the resist film 57, the entire surface of the substrate is oxidized to form a silicon oxide film 26 having a thickness of about 30 nm to be a conductor protective film. Here, since the oxidation rate of polycrystalline silicon is faster than that of single crystal silicon due to the accelerated oxidation phenomenon, when the silicon oxide film 26 having a thickness of about 30 nm is formed on the polycrystalline silicon film 32, the peripheral circuit region Rperi is formed. A silicon oxide film 26 having a thickness of about 10 nm is formed on the substrate. Since the degree of accelerated oxidation also depends on the oxidation temperature and the oxidizing atmosphere, it is desirable that the oxidation conditions be performed at a lower temperature (850 ° C. or lower) and at a high water vapor concentration.
[0169]
Next, in the step shown in FIG. 14C, anisotropic etching is performed to remove the silicon oxide film 26 on the substrate. At this time, the etching amount is set to about 15 nm so that the silicon oxide film 26 on the polycrystalline silicon film 32 is not completely removed, and the thickness of the silicon oxide film 26 remaining on the polycrystalline silicon film 32 in the memory cell region Rmemo is 15 nm. Keep it at a degree.
[0170]
Next, in the step shown in FIG. 14D, a single crystal silicon film 11 having a thickness of about 100 nm is grown by selective epitaxial growth on the region where the surface of the semiconductor substrate 10 in the peripheral circuit region Rperi is exposed. Thereafter, although not shown, the silicon oxide film 26 in the memory cell region Rmemo is removed, and the entire surface of the substrate is substantially planarized.
[0171]
Although illustration of the subsequent steps is omitted, by performing the same processing as in the first to sixth embodiments, a memory cell having a floating gate electrode and a control gate electrode is formed in the memory cell region Rmemo, and the peripheral circuit region. A field effect transistor having a gate electrode can be formed in Rperi. For example, the same process as the process shown in FIGS. 2f and 3a to 3e in the first embodiment and the process shown in FIGS. 7f and 7g and FIGS. 8a to 8d in the fourth embodiment is performed.
[0172]
Also in the present embodiment, in the step shown in FIG. 14e, the polycrystalline silicon film 32 constituting the floating gate electrode is formed in the memory cell region Rmemo, and this polycrystalline silicon film is removed by the subsequent removal of the silicon oxide film 26. The upper surface of 32 and the upper surface of the semiconductor substrate 10 in the peripheral circuit region Rperi are planarized. Therefore, similarly to the first to sixth embodiments, the element density in both the memory cell region Rmemo and the peripheral circuit region Rperi can be improved by a simple process.
[0173]
In addition, according to the present embodiment, the height difference forming step for making the height of the substrate surface of the memory cell region Rmemo lower than the height of the substrate surface of the peripheral circuit region Rperi, and the first conductor film in the memory cell region Rmemo Since the planarization process in which the height of the upper surface of a certain polycrystalline silicon film 32 and the substrate surface of the peripheral circuit region Rperi are substantially the same can be performed without forming a mask, the number of processes can be greatly reduced.
[0174]
(Tenth embodiment)
Next, a method for manufacturing a semiconductor device according to the tenth embodiment will be described with reference to FIGS. 15a to 15d are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to this embodiment.
[0175]
First, in the step shown in FIG. 15a, the entire surface of the semiconductor substrate 10 is oxidized to form a tunnel oxide film 31 having a thickness of about 10 nm, and a polycrystalline silicon film having a thickness of about 100 nm is formed thereon as a first conductor film. 32 and a silicon oxide film 27 having a thickness of about 50 nm are formed as a first conductor protective film. A resist film 57 is formed on the silicon oxide film 27 so as to cover the memory cell region Rmemo and open the peripheral circuit region Rperi. Then, the silicon oxide film 27 in the peripheral circuit region Rperi is etched by using the resist film 57 as a mask. The polycrystalline silicon film 32 and the tunnel oxide film 31 are removed.
[0176]
Next, in the step shown in FIG. 15B, after removing the resist film 57, the entire surface of the substrate is oxidized to form a silicon oxide film 28 having a thickness of about 20 nm as a second conductor protective film. Here, the silicon oxide film 28 may be formed by a CVD method or an oxidation method.
[0177]
Next, in the step shown in FIG. 15C, anisotropic etching is performed to remove the silicon oxide film 28 on the substrate. At this time, even if the silicon oxide film 28 as the second conductor protective film on the polycrystalline silicon film 32 in the memory cell region Rmemo is completely removed, the first conductor protective film is formed on the polycrystalline silicon film 32 in advance. Therefore, there is no possibility that the polycrystalline silicon film 32 in the memory cell region Rmemo is etched.
[0178]
Next, in the step shown in FIG. 15d, the single crystal silicon film 11 having a thickness of about 100 nm is grown by selective epitaxial growth on the region where the surface of the semiconductor substrate 10 in the peripheral circuit region Rperi is exposed. Thereafter, although not shown, the silicon oxide film 27 in the memory cell region Rmemo is removed, and the entire surface of the substrate is substantially planarized.
[0179]
Although illustration of the subsequent steps is omitted, by performing the same processing as in the first to sixth embodiments, a memory cell having a floating gate electrode and a control gate electrode is formed in the memory cell region Rmemo, and the peripheral circuit region. A field effect transistor having a gate electrode can be formed in Rperi. For example, the same process as the process shown in FIGS. 2f and 3a to 3e in the first embodiment and the process shown in FIGS. 7f and 7g and FIGS. 8a to 8d in the fourth embodiment is performed.
[0180]
Also in this embodiment, in the step shown in FIG. 15e, the polycrystalline silicon film 32 constituting the floating gate electrode is formed in the memory cell region Rmemo, and this polycrystalline silicon film is removed by the subsequent removal of the silicon oxide film 27. The upper surface of 32 and the upper surface of the semiconductor substrate 10 in the peripheral circuit region Rperi are planarized. Therefore, as in the first to sixth embodiments, the device density in both the memory cell region Rmemo and the peripheral circuit region Rperi can be improved by a simple process.
[0181]
Further, a step of forming a height difference in which the height of the substrate surface of the memory cell region Rmemo is made lower than the height of the substrate surface of the peripheral circuit region Rperi, and the polycrystalline silicon film 32 which is the first conductor film of the memory cell region Rmemo. Since a planarization process in which the height of the upper surface and the substrate surface of the peripheral circuit region Rperi are substantially the same can be performed without forming a mask, the number of processes can be greatly reduced.
[0182]
Furthermore, according to the present embodiment, the process margin at the time of etching the silicon oxide film 28 as the second conductor protective film is improved, and the yield is improved.
[0183]
(Eleventh embodiment)
Next, a method for fabricating a semiconductor device according to the eleventh embodiment will be described with reference to FIGS. 16a and 16b. 16A to 16B are cross-sectional views showing the manufacturing process of the semiconductor device according to this embodiment.
[0184]
First, in the step shown in FIG. 16A, the entire surface of the semiconductor substrate 10 is oxidized to form a tunnel oxide film 31 having a thickness of about 10 nm, and a polycrystalline silicon film having a thickness of about 100 nm is formed thereon as a first conductor film. 32 and a silicon oxide film 27 having a thickness of about 50 nm are formed as a conductor protective film. Then, a resist film 57 is formed on the silicon oxide film 27 so as to cover the memory cell region Rmemo and open the peripheral circuit region Rperi. Then, the silicon oxide film 27 in the peripheral circuit region Rperi is etched by etching using the resist film 57 as a mask. The polycrystalline silicon film 32 and the tunnel oxide film 31 are removed.
[0185]
Next, in the step shown in FIG. 16B, a single crystal silicon film 11 having a thickness of about 100 nm is grown by selective epitaxial growth on the region where the surface of the semiconductor substrate 10 in the peripheral circuit region Rperi is exposed. Thereafter, although not shown, the silicon oxide film 27 in the memory cell region Rmemo is removed, and the entire surface of the substrate is substantially planarized.
[0186]
Although illustration of subsequent steps is omitted, by performing the same processing as in the first to sixth embodiments, a memory cell having a floating gate electrode and a control gate electrode is formed in the memory cell region Rmemo, and a peripheral circuit region. A field effect transistor having a gate electrode can be formed in Rperi. For example, the same processing as the steps shown in FIGS. 2f and 3a to 3e in the first embodiment and the steps shown in FIGS. 7f and 7g and FIGS. 8a to 8d in the fourth embodiment is performed.
[0187]
Also in the present embodiment, in the step shown in FIG. 16B, the polycrystalline silicon film 32 constituting the floating gate electrode is formed in the memory cell region Rmemo, and this polycrystalline silicon film is removed by the subsequent removal of the silicon oxide film 27. The upper surface of 32 and the upper surface of the semiconductor substrate 10 in the peripheral circuit region Rperi are planarized. Therefore, similarly to the first to sixth embodiments, the element density in both the memory cell region Rmemo and the peripheral circuit region Rperi can be improved by a simple process.
[0188]
Further, a step of forming a height difference in which the height of the substrate surface of the memory cell region Rmemo is lower than the height of the substrate surface of the peripheral circuit region Rperi, and the polycrystalline silicon film 32 that is the first conductor film of the memory cell region Rmemo. Since a planarization process in which the height of the upper surface and the substrate surface of the peripheral circuit region Rperi are substantially the same can be performed without forming a mask, the number of processes can be greatly reduced.
[0189]
In particular, according to the present embodiment, there is an advantage that the single crystal silicon film 11 can be formed by an extremely simple process as compared with the ninth and tenth embodiments.
[0190]
Since the side surface of the polycrystalline silicon film 32 is not protected by the insulating film, the crystallinity of the single crystal silicon film 11 near the boundary between the memory cell region Rmemo and the peripheral circuit region Rperi may be deteriorated. However, if an element isolation trench is formed in the vicinity in a subsequent step, such a portion having poor crystallinity can be easily removed.
[0191]
(Other embodiments)
In the first to tenth embodiments, the source / drain regions of the nonvolatile memory cell and the field effect transistor, the well formation, the ion implantation for the threshold voltage control, and the heat treatment process are omitted. Needless to say, these steps are performed using a known technique.
[0192]
In each of the above embodiments, CMP is performed in the planarization step when forming the buried insulating film 102 in the element isolation trench 101. However, a resist etch back method or a spin etching method may be used. In this case, if there is a selection ratio sufficient to allow the polycrystalline silicon film to function as an etching stopper, a polycrystalline silicon film can be used instead of the silicon nitride film 24 in the first to third embodiments.
[0193]
The gate oxide film 33 in the first to fifth embodiments functions as a gate insulating film of the field effect transistor in the peripheral circuit region Rperi and a capacitive insulating film between the floating gate electrode and the control gate electrode in the memory cell region Rmemo. , Have a common thickness. However, since the conditions such as applied voltage are different between the control gate electrode 111 in the memory cell region Rmemo and the gate electrode 113 in the peripheral circuit region Rperi, they can be formed to have different film thicknesses. In that case, the following steps can be performed.
[0194]
First, in the step shown in FIG. 3c and the like, a gate oxide film 33 (first gate insulating film) is formed by deposition using an oxidation method or a CVD method, and then a resist film covering the memory cell region Rmemo is formed, and the peripheral circuit region is formed. The thickness of the Rperi gate oxide film 33 is reduced or the entire thickness is removed. Thereafter, a second gate insulating film may be formed on the entire surface by deposition by an oxidation method or a CVD method, and then a polycrystalline silicon film 34 may be deposited as a second conductor film. Through such a process, gate insulating films having different thicknesses can be formed in the peripheral circuit region Rperi and the memory cell region Rmemo. However, when the gate oxide film 33 is formed by an oxidation method in the process shown in FIG. The gate oxide film 33 in the memory cell region Rmemo is generally much thicker than the gate oxide film 33 in the peripheral circuit region Rperi. Therefore, the thickness of the gate oxide film in the memory cell region Rmemo can be made larger than the thickness of the gate oxide film in the peripheral circuit region Rperi without necessarily performing the above-described steps.
[0195]
Furthermore, the gate insulating film on the thicker side may be used not only in the memory cell region Rmemo but also for field effect transistors for high withstand voltage and input / output in the peripheral circuit region Rperi.
[0196]
Moreover, although the polycrystalline silicon film was used as the conductor film in the first to sixth embodiments, the polycrystalline silicon film (or the amorphous silicon film) was used as the second conductor film in the first to third embodiments. ) And a metal or metal compound, and the third conductor film in the fourth to sixth embodiments includes a single layer film or a polycrystalline silicon film (or an amorphous silicon film) of a metal or a metal compound. A laminated film of a metal or a metal compound may be used.
[0197]
【The invention's effect】
According to the semiconductor device of the present invention or the manufacturing method thereof,While maintaining the flatness of the conductor device, the fidelity of the formation pattern with respect to the mask pattern in each region can be maintained at a high level. Realization of one-chip semiconductor deviceThe
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a structure of a semiconductor device according to first and second embodiments.
FIG. 2 is a cross-sectional view showing respective steps up to a step of forming an element isolation trench in the manufacturing steps of the semiconductor device according to the first embodiment.
FIG. 3 is a cross-sectional view showing each step after the step of forming the buried insulating film in the manufacturing steps of the semiconductor device according to the first embodiment.
FIG. 4 is a cross-sectional view showing each step after the step of forming a buried insulating film in the manufacturing steps of the semiconductor device according to the second embodiment.
FIG. 5 is a cross-sectional view showing each step after the step of forming a buried insulating film in the manufacturing steps of the semiconductor device according to the third embodiment.
FIG. 6 is a cross-sectional view showing a structure of a semiconductor device according to fourth and fifth embodiments.
FIG. 7 is a cross-sectional view showing respective steps up to a step of forming an element isolation groove in a manufacturing process of a semiconductor device according to a fourth embodiment.
FIG. 8 is a cross-sectional view showing each step after the step of forming a buried insulating film in the manufacturing steps of the semiconductor device according to the fourth embodiment.
FIG. 9 is a plan view of the semiconductor device according to each embodiment.
FIG. 10 is a cross-sectional view showing each step after a step of forming a buried insulating film in the steps of manufacturing a semiconductor device according to the fifth embodiment.
FIG. 11 is a cross-sectional view showing each step after a step of forming a buried insulating film in the manufacturing steps of the semiconductor device according to the sixth embodiment.
FIG. 12 is a cross-sectional view showing respective steps up to a flattening step in a manufacturing process of a semiconductor device according to a seventh embodiment.
FIG. 13 is a cross-sectional view showing respective steps up to a flattening step among the steps of manufacturing a semiconductor device according to the eighth embodiment.
FIG. 14 is a cross-sectional view showing respective steps up to a flattening step in a manufacturing process of a semiconductor device according to a ninth embodiment.
FIG. 15 is a cross-sectional view showing each process up to a planarization process in the manufacturing process of the semiconductor device according to the tenth embodiment;
FIG. 16 is a cross-sectional view showing each process up to a planarization process in the manufacturing process of the semiconductor device according to the eleventh embodiment;
FIG. 17 is a cross-sectional view showing the structure of a conventional semiconductor device.
[Explanation of symbols]
10 Semiconductor substrate
11 Single crystal silicon film (single crystal semiconductor film)
21 Pad oxide film
22 Silicon nitride film
23 Pad oxide film
24 silicon nitride film,
25-28 Silicon oxide film
31 Tunnel oxide film
32 Polycrystalline silicon film
33 Gate oxide film
34 Polycrystalline silicon film
35 Silicon oxide film
36 Polycrystalline silicon film
37 Gate oxide film
51-58 resist film,
101 Element isolation groove
102 buried insulating film
103 Field oxide film
111 Control gate electrode
112 Floating gate electrode
113 Gate electrode
121 Interlayer insulation film
122 Connection hole
123 Metal wiring

Claims (34)

A nonvolatile memory cell having a tunnel insulating film, a floating gate electrode, a gate insulating film, and a control gate electrode is formed on the first active region of the memory cell region of the semiconductor substrate, while the second of the peripheral circuit region of the semiconductor substrate is formed. A method of manufacturing a semiconductor device for forming a field effect transistor having a gate insulating film and a gate electrode on an active region,
A first step of forming a height difference between the upper surfaces of the semiconductor cell so that the height position of the upper surface of the semiconductor substrate in the memory cell region is lower than the height position of the upper surface of the semiconductor substrate in the peripheral circuit region; ,
A tunnel insulating film and a first conductor film are sequentially formed on the upper surface of the semiconductor substrate in the memory cell region, and the height position of the upper surface of the first conductor film is set to the height of the upper surface of the semiconductor substrate in the peripheral circuit region. A second step that is the same as the position;
After the second step, a third step of forming element isolation grooves respectively surrounding the first and second active regions in the semiconductor substrate in the memory cell region and the peripheral circuit region;
A fourth step of filling the groove with an insulating film to form a groove type element isolation ,
The first step is
A method of manufacturing a semiconductor device, comprising: a step of partially removing the semiconductor substrate in the memory cell region to a certain depth by etching using a mask member having an opening on the memory cell region . A nonvolatile memory cell having a tunnel insulating film, a floating gate electrode, a gate insulating film, and a control gate electrode is formed on the first active region of the memory cell region of the semiconductor substrate, while the second of the peripheral circuit region of the semiconductor substrate is formed. A method of manufacturing a semiconductor device for forming a field effect transistor having a gate insulating film and a gate electrode on an active region,
A first step of forming a height difference between the upper surfaces of the semiconductor cell so that the height position of the upper surface of the semiconductor substrate in the memory cell region is lower than the height position of the upper surface of the semiconductor substrate in the peripheral circuit region; ,
A tunnel insulating film and a first conductor film are sequentially formed on the upper surface of the semiconductor substrate in the memory cell region, and the height position of the upper surface of the first conductor film is set to the height of the upper surface of the semiconductor substrate in the peripheral circuit region. A second step that is the same as the position;
After the second step, a third step of forming element isolation grooves respectively surrounding the first and second active regions in the semiconductor substrate in the memory cell region and the peripheral circuit region;
A fourth step of filling the groove with an insulating film to form a groove type element isolation,
The first step is
Forming an insulating film on the substrate;
Selectively removing a portion of the insulating film on the peripheral circuit region;
Using the remaining portion of the insulating film as a mask, and epitaxially growing a semiconductor crystal film on the surface of the semiconductor substrate exposed in the peripheral circuit region;
And a step of removing a remaining portion of the insulating film. A nonvolatile memory cell having a tunnel insulating film, a floating gate electrode, a gate insulating film, and a control gate electrode is formed on the first active region of the memory cell region of the semiconductor substrate, while the second of the peripheral circuit region of the semiconductor substrate is formed. A method of manufacturing a semiconductor device for forming a field effect transistor having a gate insulating film and a gate electrode on an active region,
A first step of forming a height difference between the upper surfaces of the semiconductor cell so that the height position of the upper surface of the semiconductor substrate in the memory cell region is lower than the height position of the upper surface of the semiconductor substrate in the peripheral circuit region; ,
A tunnel insulating film and a first conductor film are sequentially formed on the upper surface of the semiconductor substrate in the memory cell region, and the height position of the upper surface of the first conductor film is set to the height of the upper surface of the semiconductor substrate in the peripheral circuit region. A second step that is the same as the position;
After the second step, a third step of forming element isolation grooves respectively surrounding the first and second active regions in the semiconductor substrate in the memory cell region and the peripheral circuit region;
A fourth step of filling the groove with an insulating film to form a groove type element isolation,
The second step is
Sequentially forming a tunnel insulating film and a first conductor film on the substrate;
The first conductor film and the tunnel insulating film are selectively removed sequentially by etching using a mask member that covers at least a region near the boundary between the memory cell region and the memory cell region in the peripheral circuit region. Process,
Removing the mask member, and then removing, by CMP, a portion of the remaining first conductor film protruding in a region near the boundary with the memory cell region in the peripheral circuit region;
And a step of removing the tunnel insulating film in the peripheral circuit region by etching. In the manufacturing method of the semiconductor device as described in any one of Claims 1-3 ,
After the fourth step,
Sequentially forming an insulating film for a gate insulating film, a second conductor film, and a conductor protective film on a substrate;
The conductor protective film and the second conductor film are selectively removed by etching using a mask member covering the control gate electrode formation region and the gate electrode formation region, and the control gate is formed in the first active region. Forming an electrode and an electrode protective film thereon, and a gate electrode in the second active region,
After removing the mask member, the gate insulating film insulating film and the first conductor film are selectively removed by etching using the mask member covering the peripheral circuit region and the electrode protective film as a mask. And a step of forming a floating gate electrode in the first active region. In the manufacturing method of the semiconductor device as described in any one of Claims 1-3 ,
After the fourth step,
Sequentially forming an insulating film for a gate insulating film and a second conductor film on a substrate;
A step of selectively removing the second conductive film by etching using a mask member covering the memory cell region and the gate electrode formation region to form a gate electrode in the second active region;
After the mask member is removed, the second conductor film, the gate insulating film insulating film, and the first conductor film are etched by using a mask member that covers the peripheral circuit region and the control gate electrode formation region. And a step of forming a control gate electrode and a floating gate electrode in the first active region. In the manufacturing method of the semiconductor device as described in any one of Claims 1-3 ,
After the fourth step,
Forming a floating gate electrode in the first active region by selectively removing the first conductor film by etching using a mask member covering the peripheral circuit region and the floating gate electrode formation region; ,
Forming the gate insulating film insulating film and the second conductor film on the substrate in sequence after removing the mask member;
The first conductor film, the gate insulating film insulating film and the second conductor film are selectively removed by etching using a mask member covering the control gate electrode forming region and the gate electrode forming region, A step of forming a control gate electrode extending from the floating gate electrode to the semiconductor substrate in the first active region and a gate electrode in the second active region, respectively. Production method. In the manufacturing method of the semiconductor device according to any one of claims 1 to 6 ,
The gate insulating film insulating film is formed so that a thickness of the gate insulating film insulating film in the memory cell region is larger than a thickness in the peripheral circuit region. A nonvolatile memory cell having a tunnel insulating film, a floating gate electrode, a gate insulating film, and a control gate electrode is formed on the first active region of the memory cell region of the semiconductor substrate, while the second of the peripheral circuit region of the semiconductor substrate is formed. A method of manufacturing a semiconductor device for forming a field effect transistor having a gate insulating film and a gate electrode on an active region,
With the semiconductor substrate exposed in the peripheral circuit region, a tunnel insulating film, a first conductor film on the tunnel insulating film, and conductor protection on the first conductor film are formed in the memory cell region. A first step of forming a film;
A semiconductor crystal is grown on the semiconductor substrate in the peripheral circuit region, and a semiconductor crystal film in which the height position of the upper surface is the same as the height position of the upper surface of the first conductor film in the memory cell region A second step of forming;
A third step of removing the first conductor protective film on the first conductor film;
A fourth step of forming element isolation grooves surrounding the first and second active regions in the memory cell region and the peripheral circuit region;
And a fifth step of forming a trench type element isolation by filling the trench with an insulating film. The method of manufacturing a semiconductor device according to claim 8 .
The first step is
A step of sequentially forming a tunnel insulating film, a first conductor film and a conductor protective film on the semiconductor substrate;
A step of sequentially removing the conductor protective film, the first conductor film, and the tunnel insulating film in the peripheral circuit region by etching using a mask member that covers the memory cell region. Production method. The method of manufacturing a semiconductor device according to claim 8 .
The first step is
Sequentially forming a tunnel insulating film and a first conductor film on the semiconductor substrate;
Removing the first conductor film and the tunnel insulating film in the peripheral circuit region by etching using a mask member covering the memory cell region;
After the mask member is removed, the first conductor film in the memory cell region and the semiconductor substrate in the peripheral circuit region are thicker on the first conductor film than on the semiconductor substrate. Forming a first conductor protective film to be,
Removing the first conductor protective film in the peripheral circuit region under the condition that the first conductor protective film on the first conductor film in the memory cell region remains by etch back. A method of manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 8 .
The first step is
Sequentially forming a tunnel insulating film, a first conductor film, and a first conductor protective film on the semiconductor substrate;
Removing the first conductor protective film, the first conductor film, and the tunnel insulating film in the peripheral circuit region by etching using a mask member covering the memory cell region;
After removing the mask member, forming a second conductor protective film on the substrate;
Etching back the second conductor protective film while leaving the second conductor protective film on the side surface of the first conductor film under the condition that the first conductor protective film on the first conductor film remains. And a step of removing the semiconductor device. In the manufacturing method of the semiconductor device as described in any one of Claims 8-11 ,
After the fifth step,
Forming a gate insulating film insulating film, a second conductor film and a protective film on the substrate;
The protective film and the second conductor film are selectively removed by etching using a mask member covering the control gate electrode formation region and the gate electrode formation region, and the control gate electrode is formed in the first active region. And forming an electrode protective film thereon and a gate electrode in the second active region,
After removing the mask member, the gate insulating film insulating film and the first conductor film are selectively removed by etching using the mask member covering the peripheral circuit region and the electrode protective film as a mask. And a step of forming a floating gate electrode in the first active region. In the manufacturing method of the semiconductor device as described in any one of Claims 8-11 ,
After the fifth step,
Sequentially forming an insulating film for a gate insulating film and a second conductor film on a substrate;
A step of selectively removing the second conductive film by etching using a mask member covering the memory cell region and the gate electrode formation region to form a gate electrode in the second active region;
After the mask member is removed, the second conductor film, the gate insulating film insulating film, and the first conductor film are etched by using a mask member that covers the peripheral circuit region and the control gate electrode formation region. And a step of forming a control gate electrode and a floating gate electrode in the first active region. In the manufacturing method of the semiconductor device as described in any one of Claims 8-11 ,
After the fifth step,
Forming a floating gate electrode in the first active region by selectively removing the first conductor film by etching using a mask member covering the peripheral circuit region and the floating gate electrode formation region; ,
Forming a gate insulating film insulating film and a second conductor film on the substrate in sequence after removing the mask member;
The first conductor film, the gate insulating film insulating film and the second conductor film are selectively removed by etching using a mask member covering the control gate electrode forming region and the gate electrode forming region, Forming a control gate electrode extending from the floating gate electrode in the first active region to the semiconductor substrate in the memory cell region, and a gate electrode in the peripheral circuit region. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to any one of claims 8 to 14 ,
The gate insulating film insulating film is formed so that a thickness of the gate insulating film insulating film in the memory cell region is larger than a thickness in the peripheral circuit region. A non-volatile memory cell having a tunnel insulating film, a floating gate electrode, a gate insulating film, and a control gate electrode is formed on at least a first active region of a memory cell region of a semiconductor substrate, while at least a first peripheral circuit region of the semiconductor substrate is formed. A method of manufacturing a semiconductor device for forming a field effect transistor having a gate insulating film and a gate electrode on two active regions,
A first step of forming a height difference between the upper surfaces of the semiconductor cell so that the height position of the upper surface of the semiconductor substrate in the memory cell region is lower than the height position of the upper surface of the semiconductor substrate in the peripheral circuit region; ,
A tunnel insulating film and a first conductor film are sequentially formed on the upper surface of the semiconductor substrate in the memory cell region, and the height position of the upper surface of the first conductor film is set to the height of the upper surface of the semiconductor substrate in the peripheral circuit region. A second step that is the same as the position;
A third step of forming a gate insulating film insulating film and a second conductor film on the substrate;
After the third step, a fourth step of forming element isolation trenches that respectively surround the first and second active regions in the semiconductor substrate in the memory cell region and the peripheral circuit region;
And a fifth step of forming a trench type element isolation by filling the trench with an insulating film. In the manufacturing method of the semiconductor device according to claim 16 ,
After the fifth step,
A step of sequentially forming a third conductor film and a conductor protective film on the substrate;
The conductor protective film, the third conductor film, and the second conductor film are selectively removed by etching using a mask member that covers the control gate electrode formation region and the gate electrode formation region, and the first conductor film is removed. Forming a control gate electrode and an electrode protection film thereon in the active region of the second active region, and forming a gate electrode in the second active region;
After removing the mask member, the gate insulating film insulating film and the first conductor film are selectively removed sequentially by etching using the mask member covering the peripheral circuit region and the electrode protective film as a mask. And a step of forming a floating gate electrode in the first active region. In the manufacturing method of the semiconductor device according to claim 16 ,
After the fifth step,
Forming a third conductor film on the substrate;
The third conductive film and the second conductive film are selectively removed by etching using a mask member covering the memory cell region and the gate electrode formation region, and a gate electrode is formed in the second active region. And a process of
After the mask member is removed, the third conductor film, the second conductor film, and the gate insulating film insulating film are etched by using a mask member that covers the peripheral circuit region and the control gate electrode forming region. And a step of selectively removing the first conductive film sequentially to form the control gate electrode and the floating gate electrode in the first active region. Method. In the manufacturing method of the semiconductor device according to claim 16 ,
After the fifth step,
Removing the second conductor film and gate insulating film insulating film in the memory cell region;
Forming a floating gate electrode in the first active region by selectively removing the first conductor film by etching using a mask member covering the peripheral circuit region and the floating gate electrode formation region;
After removing the mask member, a second gate insulating film insulating film is selectively formed on the floating gate electrode in the first active region, and a third conductor film is further formed on the substrate. Process,
The second and third conductive films are selectively removed by etching using a mask member that covers the control gate electrode formation region and the gate electrode formation region, and the first active region is separated from the floating gate electrode. And a step of forming a control gate electrode across the semiconductor substrate and a gate electrode in the second active region, respectively. The method of manufacturing a semiconductor device according to claim 16, 17, or 18 .
The gate insulating film insulating film is formed so that a thickness of the gate insulating film insulating film in the memory cell region is larger than a thickness in the peripheral circuit region. In the manufacturing method of the semiconductor device as described in any one of Claims 16-20 ,
The first step is
A step of sequentially forming a silicon oxide film and a silicon nitride film on the substrate;
Selectively removing the silicon nitride film in the memory cell region;
Performing thermal oxidation using the silicon nitride film as a mask to form a LOCOS film on the semiconductor substrate in the memory cell region;
And a step of removing the silicon nitride film and the LOCOS film. In the manufacturing method of the semiconductor device as described in any one of Claims 16-20 ,
The first step is
A method of manufacturing a semiconductor device, comprising: a step of partially removing a semiconductor substrate in the memory cell region to a certain depth by etching using a mask member having an opening on the memory cell region. In the manufacturing method of the semiconductor device as described in any one of Claims 16-20 ,
The first step is
Forming an insulating film on the substrate;
Selectively removing a portion of the insulating film on the peripheral circuit region;
Using the remaining portion of the insulating film as a mask, and epitaxially growing a semiconductor crystal film on the surface of the semiconductor substrate exposed in the peripheral circuit region;
And a step of removing a remaining portion of the insulating film. In the manufacturing method of the semiconductor device as described in any one of Claims 16-20 ,
The second step is
Sequentially forming a tunnel insulating film and a first conductor film on the substrate;
Removing the first conductor film by CMP until at least the tunnel insulating film in the peripheral circuit region is exposed;
And a step of removing the tunnel insulating film in the peripheral circuit region by etching. In the manufacturing method of the semiconductor device as described in any one of Claims 16-20 ,
The second step is
Sequentially forming a tunnel insulating film and a first conductor film on the substrate;
And a step of selectively removing the first conductor film and the tunnel insulating film in the peripheral circuit region sequentially by etching using a mask member covering the memory cell region. Method. In the manufacturing method of the semiconductor device as described in any one of Claims 16-20 ,
The second step is
Sequentially forming a tunnel insulating film and a first conductor film on the substrate;
The first conductor film and the tunnel insulating film are selectively removed sequentially by etching using a mask member that covers at least the area near the boundary between the memory cell area and the memory cell area in the peripheral circuit area. Process,
Removing the mask member, and then removing, by CMP, a portion of the remaining first conductor film protruding in a region near the boundary with the memory cell region in the peripheral circuit region;
And a step of removing the tunnel insulating film in the peripheral circuit region by etching. A nonvolatile memory cell having a tunnel insulating film, a floating gate electrode, a gate insulating film, and a control gate electrode is formed on the first active region of the memory cell region of the semiconductor substrate, while the second of the peripheral circuit region of the semiconductor substrate is formed. A method of manufacturing a semiconductor device for forming a field effect transistor having a gate insulating film and a gate electrode on an active region,
With the semiconductor substrate exposed in the peripheral circuit region, a tunnel insulating film, a first conductor film on the tunnel insulating film, and conductor protection on the first conductor film are formed in the memory cell region. A first step of forming a film;
A semiconductor crystal is grown on the semiconductor substrate in the peripheral circuit region, and a semiconductor crystal film in which the height position of the upper surface is the same as the height position of the upper surface of the first conductor film in the memory cell region A second step of forming;
A third step of removing the first conductor protective film on the first conductor film;
A fourth step of forming a gate insulating film insulating film and a second conductor film on the substrate;
A fifth step of forming element isolation trenches surrounding the first and second active regions in the memory cell region and the peripheral circuit region;
And a sixth step of forming a trench type element isolation by filling the trench with an insulating film. 28. The method of manufacturing a semiconductor device according to claim 27 .
The first step is
A step of sequentially forming a tunnel insulating film, a first conductor film and a conductor protective film on the semiconductor substrate;
A step of sequentially removing the conductor protective film, the first conductor film, and the tunnel insulating film in the peripheral circuit region by etching using a mask member that covers the memory cell region. Production method. 28. The method of manufacturing a semiconductor device according to claim 27 .
The first step is
Sequentially forming a tunnel insulating film and a first conductor film on the semiconductor substrate;
Removing the first conductor film and the tunnel insulating film in the peripheral circuit region by etching using a mask member covering the memory cell region;
After the mask member is removed, the first conductor film in the memory cell region and the semiconductor substrate in the peripheral circuit region are thicker on the first conductor film than on the semiconductor substrate. Forming a first conductor protective film to be,
Removing the first conductor protective film in the peripheral circuit region under the condition that the first conductor protective film on the first conductor film in the memory cell region remains by etch back. A method of manufacturing a semiconductor device. 28. The method of manufacturing a semiconductor device according to claim 27 .
The first step is
Sequentially forming a tunnel insulating film, a first conductor film, and a first conductor protective film on the semiconductor substrate;
Removing the first conductor protective film, the first conductor film, and the tunnel insulating film in the peripheral circuit region by etching using a mask member covering the memory cell region;
After removing the mask member, forming a second conductor protective film on the substrate;
Etching back the second conductor protective film while leaving the second conductor protective film on the side surface of the first conductor film under the condition that the first conductor protective film on the first conductor film remains. And a step of removing the semiconductor device. 28. The method of manufacturing a semiconductor device according to claim 27 .
After the sixth step,
A step of sequentially forming a third conductor film and a conductor protective film on the substrate;
The conductor protective film, the third conductor film, and the second conductor film are selectively removed by etching using a mask member that covers the control gate electrode formation region and the gate electrode formation region, and the first conductor film is removed. Forming a control gate electrode and an electrode protection film thereon in the active region of the second active region, and forming a gate electrode in the second active region;
After removing the mask member, the gate insulating film insulating film and the first conductor film are sequentially selectively removed by etching using the mask member covering the peripheral circuit region and the electrode protection film as a mask, And a step of forming a floating gate electrode in the first active region. 28. The method of manufacturing a semiconductor device according to claim 27 .
After the sixth step,
Forming a third conductor film on the substrate;
The third conductive film and the second conductive film are selectively removed by etching using a mask member covering the memory cell region and the gate electrode formation region, and a gate electrode is formed in the second active region. And a process of
After the mask member is removed, the third conductor film, the second conductor film, and the gate insulating film insulating film are etched by using a mask member that covers the peripheral circuit region and the control gate electrode forming region. And a step of selectively removing the first conductive film sequentially to form the control gate electrode and the floating gate electrode in the first active region. Method. 28. The method of manufacturing a semiconductor device according to claim 27 .
After the sixth step,
Removing the second conductor film and gate insulating film insulating film in the memory cell region;
Forming a floating gate electrode in the first active region by selectively removing the first conductor film by etching using a mask member covering the peripheral circuit region and the floating gate electrode formation region;
After removing the mask member, a second gate insulating film insulating film is selectively formed on the floating gate electrode in the first active region, and a third conductor film is further formed on the substrate. Process,
The second and third conductive films are selectively removed by etching using a mask member that covers the control gate electrode formation region and the gate electrode formation region, and the first active region is separated from the floating gate electrode. And a step of forming a control gate electrode across the semiconductor substrate and a gate electrode in the second active region, respectively. In the manufacturing method of the semiconductor device of Claim 27, 28, 29, 30, 31, or 33,
The gate insulating film insulating film is formed so that a thickness of the gate insulating film insulating film in the memory cell region is larger than a thickness in the peripheral circuit region.

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