JPH113982A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To set the density of a memory cell area and a peripheral circuit region to be high and to reduce cost in a logic LSI which mix-loads flashes incorporated into a nonvolatile memory cell. SOLUTION: A substrate face in a peripheral circuit region Rperi is set higher than the substrate face of a memory cell region Rmemo and equal to the upper faces of floating gate electrodes 112. Control gate electrodes 111 are formed on the floating gate electrodes 112 by sandwiching gate insulating films. Gate electrodes 113 are formed on the substrate face of the peripheral circuit region Rperi by sandwiching the gate insulating films. The height position of the upper face of an embedded insulating film 102 which is the element isolation for trench isolation structure can be set equal to the upper faces of the floating gate electrodes 112, or it can be set equal to the upper face of a lower layer film, when the control gate electrodes 111 are formed of stacked films. Thus, a difference between the memory cell region Rmemo and the peripheral circuit region Rperi can be reduced, and fine patterns can be formed in the respective regions Rmemo and Rperi.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device incorporating a nonvolatile memory cell having a floating gate electrode and a control gate electrode, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, as the price of system equipment has fallen and the product cycle has been shortened, there has been a strong demand for lowering the cost and shortening the development period of semiconductor devices. In particular, a semiconductor device in which a flash memory and a state-of-the-art logic circuit are integrated and integrated (a flash embedded logic L
SI) is expected to have a promising future as a device that can realize a reduction in development time in addition to a reduction in cost due to the integration of one chip.

Here, a flash memory, a DRAM,
In order to integrate heterogeneous devices such as logic into one chip, it is essential to increase the element density, and to increase the element density, miniaturization of processing dimensions is an essential condition. And
As an important factor for miniaturizing the processing dimensions,
There is fidelity of the formed pattern to the mask pattern and flatness in the substrate at the time of pattern formation by lithography.

With respect to miniaturization of processing accuracy, a technique of forming element isolation for insulating and isolating each element is important. As this element isolation formation method, a selective oxidation method (LOCOS method) has been conventionally used, but this method causes a pattern shift due to a bird's beak, that is, the fidelity of a formed pattern to a mask pattern is deteriorated. In order to improve the device density, the limit is almost reached. Therefore, recently, in the memory cell region, a trench isolation method that does not generate bird's beak is used instead of the LOCOS method. As a conventional example of the flash memory using the trench isolation, there is a technique disclosed in, for example, Japanese Patent Application Laid-Open No. 3-295276.

FIG. 17 is a sectional view showing the structure of the semiconductor device disclosed in the above publication. As shown in the figure,
The P-type silicon substrate 201 has a memory cell region Rmemo
And a peripheral circuit region Rperi. Here, FIG. 17 shows a structure in a cross section perpendicular to the gate length direction in the memory cell region Rmemo, and a structure in a cross section parallel to the gate length direction in the peripheral circuit region Rperi. In the memory cell area Rmemo,
A tunnel oxide film 213a, a floating gate electrode 214, a gate insulating film 215, a control gate electrode 216a, a silicide layer 220a, and an impurity layer serving as a source / drain region are formed in an active region surrounded by the trench isolation 218. (Not shown). On the other hand, in the peripheral circuit region Rperi,
A field effect transistor including a gate oxide film 213b, a gate electrode 216b, a silicide layer 220b, and an impurity layer 223 serving as source / drain regions is provided in an active region surrounded by the LOCOS film 212. Then, an interlayer insulating film 222 is deposited on the substrate, and a bit line 224 is formed thereon. This conventional semiconductor device is formed, for example, by the following procedure.

First, after forming a LOCOS film 212 in the peripheral circuit region Rperi, a tunnel oxide film 213a and a gate oxide film 213b are formed in the memory cell region Rmemo and the peripheral circuit region Rperi, respectively. Next, the floating gate electrode 214 and the gate insulating film 215 are
Selectively form in memo.

After that, a gate electrode film is deposited on the entire surface of the substrate and then patterned by lithography and etching to form a control gate electrode 216a in the memory cell region Rmemo and a gate electrode 21 in the peripheral circuit region Rperi.
6b.

Further, a trench for element isolation surrounding the active region is formed in the memory cell region Rmemo by lithography and etching, and an insulating film is deposited on the entire surface of the substrate and flattened, so that the insulating film is formed into the trench. The trench type element isolation 218 is formed by embedding.

After forming silicide layers 220a and 220b on the control gate electrode 216a and the gate electrode 216b, respectively, an interlayer insulating film 222 is deposited on the substrate, and a bit line 224 is formed thereon.

As described above, by forming the groove-type element isolation 218 in the memory cell region Rmemo, the fidelity of the formed pattern with respect to the mask pattern is improved, and the density of the memory cell region is increased. Also, the cell area is reduced by forming the groove-type element isolation 218 in a self-aligned manner with the floating gate electrode 213a.

A process is also employed in which the floating gate electrode of the nonvolatile memory cell and the control gate electrode of the field effect transistor are formed of a common conductor film.

[0012]

However, the above prior art has the following problems.

Although the element density in the memory cell region can be improved by the above-mentioned conventional technology, the increase in the density of the entire semiconductor device requires not only a reduction in the area of the memory cell region but also a reduction in the peripheral circuit region. It is also necessary to increase the area. Therefore, it is conceivable that the element isolation in the peripheral circuit region is formed by a trench isolation method instead of the conventional LOCOS method. However, the conventional technique has a problem that the entire flatness cannot be maintained well. That is, if the element isolation of the trench isolation structure is to be simultaneously formed in the memory cell region Rmemo and the peripheral circuit region Rperi, the floating gate 214 in the memory cell region Rmemo is not used.
, The control gate electrode 216a of the memory cell region Rmemo and the gate electrode 216b of the peripheral circuit region Rperi
And there is a height difference between them, so that the flatness of the entire substrate is deteriorated.

That is, it is difficult to simultaneously realize the fidelity of the formed pattern with respect to the mask pattern and the flatness of the substrate.
It has been difficult to realize one chip such as I.

The present invention has been made in view of the above circumstances, and an object of the present invention is to improve the element density of both the memory cell region and the peripheral circuit region by a simple method and to maintain good flatness. A semiconductor device and a method for manufacturing the same are provided.

[0016]

In order to achieve the above-mentioned object, the present invention takes a basic measure as a semiconductor device and a method for manufacturing the same, in which an upper surface of a semiconductor substrate in an active region of a peripheral circuit region is provided with a memory cell. It is to have a height higher than the upper surface of the semiconductor substrate in the region and substantially the same height as the upper surface of the floating gate.

Specifically, means relating to the semiconductor device according to claims 1 to 10 and means relating to the method of manufacturing a semiconductor device according to claims 11 to 48 are provided.

According to the semiconductor device of the present invention, a semiconductor substrate having a memory cell region and a peripheral circuit region, and a semiconductor substrate having a memory cell region and a peripheral circuit region, respectively, are provided. 1st, 2nd
A trench-type element isolation formed so as to surround the active region, and a tunnel insulating film, a floating gate electrode, a gate insulating film, and a semiconductor substrate disposed in the memory cell region and at least in the first active region. A non-volatile memory cell provided with a control gate electrode in sequence, and a field effect transistor disposed in the peripheral circuit region and provided with a gate insulating film and a gate electrode sequentially on a semiconductor substrate in at least the second active region The height position of the upper surface of the semiconductor substrate in the second active region is higher than the height position of the upper surface of the semiconductor substrate in the first active region, and the height position of the upper surface of the floating gate electrode. It is almost the same as the height position.

Since the upper surface of the floating gate electrode and the upper surface of the semiconductor substrate in the second active region of the peripheral circuit region are flattened, the height difference between the control gate electrode and the gate electrode is almost eliminated, and The flatness of the entire apparatus can be maintained well. Also, since element isolation having a so-called trench isolation structure is provided not only in the memory cell area but also in the peripheral circuit area, the fidelity of the pattern formed with respect to the mask pattern is improved, and the density of the element can be increased over the entire semiconductor device. Can be formed.

According to a second aspect of the present invention, in the semiconductor device, the height position of the upper surface of the element isolation is
The height position of the upper surface of the semiconductor substrate and the height position of the upper surface of the floating gate electrode in the second active region of the peripheral circuit region may be substantially the same.

Thus, a structure is obtained in which the upper surface of the semiconductor substrate in the second active region in the peripheral circuit region and the upper surface of the floating gate electrode in the memory cell region can be flattened and element isolation of a trench structure can be formed. Is improved.

According to a third aspect of the present invention, in the semiconductor device, the floating gate electrode of the nonvolatile memory cell is sandwiched between the element isolations in a vertical cross section orthogonal to the gate length direction. Is preferably self-aligned.

As a result, the device isolation and the floating gate electrode do not need to be formed by using individual mask patterns, so that a margin for mask alignment is not required, and the memory cell region is further densified. can do.

According to a fourth aspect of the present invention, in the semiconductor device, the control gate electrode of the nonvolatile memory cell can be formed so as to extend from the floating gate electrode to the semiconductor substrate.

Thus, the effect of the second aspect can be obtained even in a split gate type memory cell having good data retention.

According to a fifth aspect of the present invention, in the semiconductor device, the control gate electrode and the gate electrode are formed of a polycrystalline silicon film, an amorphous silicon film, a metal film, a polycrystalline silicon film and a metal film. A stacked film of a metal compound film, a stacked film of an amorphous silicon film and a metal film or a metal compound film, a stacked film of a metal film and a metal film, a stacked film of a metal film, a metal film, and a polycrystalline silicon film; It is preferable to be formed of any one of a stacked film of a metal film, a metal film, and an amorphous silicon film.

According to a sixth aspect of the present invention, in the semiconductor device, a control gate electrode of the nonvolatile memory cell and a gate electrode of the field-effect transistor are connected to a common upper-layer conductor film and a lower-layer conductor film. The lower conductive film in the second formation region of the peripheral circuit region is sandwiched between the device isolations in a cross section orthogonal to the gate length direction of the field effect transistor, and is self-aligned with the device isolation. In addition, the height position of the upper surface of the element isolation can be substantially the same as the height position of the upper surface of the lower conductive film.

Thus, the lower insulating film provided on the floating gate electrode in the memory cell region and the upper surface of the semiconductor substrate in the second active region in the peripheral circuit region via the gate insulating film, respectively. And the element isolation are flattened. Since the floating gate electrode is sandwiched between the device isolations, the above-described operation and effect can be obtained, and the lower conductive film constituting the gate electrode in the second active region of the peripheral circuit region is self-aligned with the device isolation. Therefore, fluctuations in characteristics caused by electric field concentration on the side surface, which is a problem in the trench isolation structure, are suppressed.

According to a seventh aspect of the present invention, in the semiconductor device, the gate electrode of the field-effect transistor is constituted by an upper conductor film and a lower conductor film, and the control gate of the nonvolatile memory cell is provided. An electrode is formed only of the upper conductor film, and is formed over the floating gate electrode and the semiconductor substrate. The lower conductor film in the second active region of the peripheral circuit region is formed of the field effect transistor. In a cross section orthogonal to the gate length direction, the semiconductor device can be self-aligned with the device isolation between the device isolations.

Thus, while achieving the same effect as that of the sixth aspect, it is possible to increase the density of the nonvolatile memory cell even in a semiconductor device having a nonvolatile memory cell having a split gate structure with good data retention. it can.

In the above semiconductor device, the lower conductive film may be a polycrystalline silicon film, an amorphous silicon film, a metal film, a polycrystalline silicon film and a metal film or a metal compound. Laminated film with film, laminated film with amorphous silicon film and metal film or metal compound film, laminated film with metal film and metal film, laminated film with metal film and metal film and polycrystalline silicon film, metal film It is preferable to configure the semiconductor device by using any one of a stacked film of a metal film and an amorphous silicon film.

According to a ninth aspect of the present invention, in the semiconductor device, it is preferable that the thickness of the gate insulating film of the nonvolatile memory cell is larger than the thickness of the gate insulating film of the field effect transistor. .

Thus, an appropriate thickness of the gate insulating film can be reliably obtained.

According to a tenth aspect of the present invention, in the semiconductor device, a region near the surface of the semiconductor substrate in the peripheral circuit region can be constituted by a semiconductor crystal film formed by epitaxial growth.

As a result, a semiconductor device incorporating a high-density flash memory using an epitaxially grown film having good semiconductor crystal characteristics can be obtained.

The first method of manufacturing a semiconductor device according to the present invention comprises:
Forming a non-volatile memory cell having a tunnel insulating film, a floating gate electrode, a gate insulating film, and a control gate electrode on the first active region of the memory cell region of the semiconductor substrate; A method of manufacturing a semiconductor device for forming a field-effect transistor having a gate insulating film and a gate electrode on a second active region in a peripheral circuit region of a semiconductor substrate, comprising: a top surface of the semiconductor substrate in the memory cell region Forming a height difference between the upper surface of the semiconductor substrate and the semiconductor substrate in the memory cell region so that the height of the semiconductor substrate is lower than the height position of the upper surface of the semiconductor substrate in the peripheral circuit region. A tunnel insulating film and a first conductor film are sequentially formed on the upper surface of the semiconductor device, and the height position of the upper surface of the first conductor film is determined by the semi-conductor in the peripheral circuit region. A second step of making the height substantially the same as the height position of the upper surface of the substrate, and forming element isolation grooves respectively surrounding the first and second active regions in the semiconductor substrate in the memory cell region and the peripheral circuit region. The method includes a third step and a fourth step of forming the groove-type element isolation by filling the groove with an insulating film.

According to this method, in the second step, while the first conductive film in the memory cell area and the upper surface of the semiconductor substrate in the peripheral circuit area are flattened, the trench isolation is performed in the third and fourth steps. Since the element isolation having the structure is formed, it is possible to form a semiconductor device having good flatness and high density over the whole.

According to a twelfth aspect of the present invention, in the method of manufacturing a first semiconductor device, after the fourth step, an insulating film for a gate insulating film, a second conductive film, A step of sequentially forming a conductor protection film, and etching using a mask member covering the control gate electrode formation region and the gate electrode formation region, thereby forming the conductor protection film and the second
Forming a control gate electrode and an electrode protection film thereon and a gate electrode in the second active region, respectively, by selectively removing the conductive film of After the members are removed, the insulating film for the gate insulating film and the first conductive film are selectively removed by etching using the mask member covering the peripheral circuit region and the electrode protective film as a mask. Forming a floating gate electrode in the first active region.

According to this method, the gate insulating film and the floating gate electrode in the memory cell region and the gate insulating film and the gate electrode in the peripheral circuit region are formed by common members, respectively. Can be formed. Further, since the floating gate electrode is formed by etching using the control gate electrode as a mask, a margin for mask alignment becomes unnecessary, and the density of the memory cell region can be increased.

According to a thirteenth aspect of the present invention, in the method for manufacturing a first semiconductor device, after the fourth step, an insulating film for a gate insulating film and a second conductive film are sequentially formed on the substrate. Forming the gate electrode in the second active region by selectively removing the second conductor film by etching using a mask member covering the memory cell region and the gate electrode formation region. And after removing the mask member, etching is performed using a mask member covering the peripheral circuit region and the control gate electrode formation region to form the second conductor film, the gate insulating film insulating film, and the second conductive film. Forming a control gate electrode and a floating gate electrode in the first active region by selectively removing the one conductive film sequentially.

According to this method, the gate insulating film and the floating gate electrode in the memory cell region and the gate insulating film and the gate electrode in the peripheral circuit region are formed by common members, respectively. Can be formed. Further, since the floating gate electrode and the control gate electrode are formed by etching using a common mask member, a margin for mask alignment is not required, and the density of the memory cell region can be increased.

According to a fourteenth aspect of the present invention, in the first method for manufacturing a semiconductor device, after the fourth step, a mask member for covering the peripheral circuit region and the floating gate electrode formation region is used. The first etching
Forming a floating gate electrode in the first active region by selectively removing the conductive film, and removing the mask member and then forming an insulating film for a gate insulating film and a second conductive film on the substrate. Are sequentially formed, and the first conductive film, the insulating film for the gate insulating film, and the second conductive film are etched by using a mask member covering the control gate electrode forming region and the gate electrode forming region. Selectively removing the first
Forming a control gate electrode extending from the floating gate electrode to the semiconductor substrate in the active region, and forming a gate electrode in the second active region.

According to this method, a semiconductor device having a split-gate nonvolatile memory cell with a high density is formed.

According to a fifteenth aspect of the present invention, in the first method for manufacturing a semiconductor device, the formation of the insulating film for a gate insulating film is performed by changing the thickness of the insulating film for a gate insulating film in the memory cell region. Is preferably made larger than the thickness in the peripheral circuit region.

According to this method, the gate insulating film functioning as a capacitive insulating film between the floating gate electrode and the control gate electrode of the nonvolatile memory cell and the gate insulating film of the field effect transistor have appropriate thicknesses different from each other. A semiconductor device having a memory cell and a field effect transistor is formed.

According to a sixteenth aspect of the present invention, in the first method of manufacturing a semiconductor device, the first step includes a step of sequentially forming a silicon oxide film and a silicon nitride film on a substrate; Selectively removing the silicon nitride film in the memory cell region; performing thermal oxidation using the silicon nitride film as a mask to form a LOCOS film on the semiconductor substrate in the memory cell region; And a step of removing the LOCOS film.

According to this method, when the silicon oxide film is removed, the upper surface of the semiconductor substrate in the memory cell region is lower than the upper surface of the semiconductor substrate in the second active region in the peripheral circuit region. Therefore, a height difference can be easily formed between both upper surfaces. In addition, since the edge of the thermal oxide film has a wedge shape, only a step having a relatively gentle inclination is present, so that it is possible to reliably prevent a problem due to generation of an etching residue in a later step.

According to a seventeenth aspect of the present invention, in the first method for manufacturing a semiconductor device, the first step is performed by etching using a mask member having an opening on the memory cell region. A step of partially removing the semiconductor substrate in the memory cell region to a certain depth can be included.

According to an eighteenth aspect of the present invention, in the first method of manufacturing a semiconductor device, the first step includes a step of forming an insulating film on a substrate; Selectively removing a portion on the circuit region; and using a remaining portion of the insulating film as a mask, epitaxially growing a semiconductor crystal film on a surface of the semiconductor substrate exposed in the peripheral circuit region. Removing the remaining portion of the insulating film.

According to the method of claim 17 or 18, a height difference can be easily formed between the upper surface of the semiconductor substrate in the memory cell region and the upper surface of the semiconductor substrate in the peripheral circuit region.

In the first method of manufacturing a semiconductor device, the present invention is intended to flatten the upper surface of the floating gate electrode in the memory cell region and the upper surface of the semiconductor substrate of the peripheral circuit. With any of the methods, a semiconductor device with good flatness can be formed.

According to a nineteenth aspect of the present invention, in the method of manufacturing a first semiconductor device, the second step includes a step of sequentially forming a tunnel insulating film and a first conductor film on the substrate. The first conductive film is subjected to CMP until at least the tunnel insulating film in the peripheral circuit region is exposed.
And removing the tunnel insulating film in the peripheral circuit region by etching.

According to a twentieth aspect, in the first method for manufacturing a semiconductor device, the second step includes a step of sequentially forming a tunnel insulating film and a first conductor film on the substrate. A step of selectively removing the first conductive film and the tunnel insulating film in the peripheral circuit region sequentially by etching using a mask member covering the memory cell region.

According to a twenty-first aspect, in the first method of manufacturing a semiconductor device, the second step includes a step of sequentially forming a tunnel insulating film and a first conductor film on the substrate. The first conductive film and the tunnel insulating film are sequentially and selectively removed by etching using a mask member that covers at least a region near a boundary between the memory cell region and the memory cell region in the peripheral circuit region. And after removing the mask member,
Removing, by CMP, a portion of the remaining first conductor film that protrudes in a region near the boundary with the memory cell region in the peripheral circuit region; and removing the tunnel insulating film in the peripheral circuit region. Removing by etching.

The second method of manufacturing a semiconductor device according to the present invention
Forming a non-volatile memory cell having a tunnel insulating film, a floating gate electrode, a gate insulating film, and a control gate electrode on the first active region in the memory cell region of the semiconductor substrate; A method of manufacturing a semiconductor device for forming a field-effect transistor having a gate insulating film and a gate electrode on a second active region in a peripheral circuit region of a semiconductor substrate, wherein the semiconductor substrate in the peripheral circuit region is A first step of forming a tunnel insulating film, a first conductive film on the tunnel insulating film, and a conductive protective film on the first conductive film in the memory cell region in an exposed state; Growing a semiconductor crystal on the semiconductor substrate in the peripheral circuit region, and setting the height position of the upper surface to the height position of the upper surface of the first conductive film in the memory cell region A second step of forming substantially the same semiconductor crystal film, a third step of removing the first conductive protective film on the first conductive film, and a step of removing the first conductive film from the memory cell region and the peripheral circuit region. A fourth step of forming an element isolation groove surrounding the first and second active regions, and a fifth step of forming the groove-type element isolation by filling the groove with an insulating film.
Steps.

According to this method, when the first step is completed, a height difference is formed between the upper surface of the semiconductor substrate in the memory cell region and the upper surface of the semiconductor substrate in the peripheral circuit region, and the non-volatile memory is formed. The upper surface of the first conductive film constituting the floating gate electrode of the cell and the upper surface of the semiconductor substrate in the peripheral circuit region are flattened. Therefore, similarly to the first method for manufacturing a semiconductor device, a high-density semiconductor device with good flatness can be easily formed.

In the second method for manufacturing a semiconductor device, the first step can be easily realized by the following steps.

According to a twenty-third aspect of the present invention, in the method of manufacturing a second semiconductor device, the first step includes a step of forming a tunnel insulating film, a first conductive film, and a conductive film on the semiconductor substrate. Step of sequentially forming a protective film, and etching using a mask member covering the memory cell region,
Removing the conductor protection film, the first conductor film, and the tunnel insulating film in the peripheral circuit region sequentially.

According to a twenty-fourth aspect of the present invention, in the method of manufacturing a second semiconductor device, the first step includes sequentially forming a tunnel insulating film and a first conductor film on the semiconductor substrate. Removing the first conductive film and the tunnel insulating film in the peripheral circuit region by etching using a mask member covering the memory cell region; and removing the mask member and then removing the memory A first conductor protection film is formed on the first conductor film in the cell region and the semiconductor substrate in the peripheral circuit region such that the first conductor protection film is thicker on the first conductor film than on the semiconductor substrate. Forming the first conductor protection film in the peripheral circuit region under the condition that the first conductor protection film on the first conductor film in the memory cell region remains by the etch-back process. It can include the step of removed by.

According to a twenty-fifth aspect of the present invention, in the method of manufacturing a second semiconductor device, the first step includes a step of forming a tunnel insulating film, a first conductor film and a second conductive film on the semiconductor substrate. Removing the first conductor protection film, the first conductor film, and the tunnel insulating film in the peripheral circuit region by a step of sequentially forming one conductor protection film and etching using a mask member covering the memory cell region; And a step of forming a second conductor protection film on the substrate after removing the mask member, and under the condition that the first conductor protection film on the first conductor film remains by etch-back. Removing the second conductor protection film while leaving the second conductor protection film on the side surface of the first conductor film.

According to a twenty-sixth aspect of the present invention, in the method of manufacturing a second semiconductor device, after the fifth step, an insulating film for a gate insulating film, a second conductive film, and a protective film are formed on the substrate. Forming a film, and selectively removing the protective film and the second conductor film by etching using a mask member covering the control gate electrode formation region and the gate electrode formation region; Forming a control gate electrode in the active region and an electrode protective film thereon, and forming a gate electrode in the second active region, and removing the mask member and removing the mask member and then covering the peripheral circuit region with a mask member. By etching using the electrode protection film and a mask,
Forming a floating gate electrode in the first active region by selectively removing the insulating film for a gate insulating film and the first conductive film.

According to a twenty-seventh aspect, in the method of manufacturing a second semiconductor device, after the fifth step, an insulating film for a gate insulating film and a second conductive film are sequentially formed on the substrate. Forming the gate electrode in the second active region by selectively removing the second conductor film by etching using a mask member covering the memory cell region and the gate electrode formation region. And after removing the mask member, etching is performed using a mask member covering the peripheral circuit region and the control gate electrode formation region to form the second conductor film, the gate insulating film insulating film, and the second conductive film. Forming a control gate electrode and a floating gate electrode in the first active region by selectively removing the one conductive film sequentially.

According to a twenty-eighth aspect of the present invention, in the method for manufacturing a second semiconductor device, after the fifth step, a mask member for covering the peripheral circuit region and the floating gate electrode formation region is used. The first etching
Forming a floating gate electrode in the first active region by selectively removing the conductive film, and removing the mask member and then forming an insulating film for a gate insulating film and a second conductive film on the substrate. Are sequentially formed, and the first conductive film, the insulating film for the gate insulating film, and the second conductive film are etched by using a mask member covering the control gate electrode forming region and the gate electrode forming region. Selectively removing and forming a control gate electrode extending from the floating gate electrode in the first active region to the semiconductor substrate in the memory cell region and a gate electrode in the peripheral circuit region. be able to.

According to the twenty-sixth to twenty-eighth aspects, an additional effect similar to the twelfth to fourteenth aspects in the first method for manufacturing a semiconductor device can be exhibited.

As set forth in claim 29, in the second method of manufacturing a semiconductor device, the formation of the insulating film for a gate insulating film may be performed by adjusting a thickness of the insulating film for a gate insulating film in the memory cell region. Is preferably made larger than the thickness in the peripheral circuit region.

The third method of manufacturing a semiconductor device according to the present invention
A non-volatile memory cell having a tunnel insulating film, a floating gate electrode, a gate insulating film and a control gate electrode is formed on at least a first active region of a memory cell region of a semiconductor substrate. On the other hand, a method of manufacturing a semiconductor device for forming a field-effect transistor having a gate insulating film and a gate electrode on at least a second active region in a peripheral circuit region of a semiconductor substrate, comprising: A first step of forming a height difference between the upper surface of the semiconductor substrate and the height position of the upper surface of the semiconductor substrate in the peripheral circuit region so as to be lower than the height position of the upper surface of the semiconductor substrate in the peripheral circuit region; A tunnel insulating film and a first conductor film are sequentially formed on the upper surface of the semiconductor substrate, and the height position of the upper surface of the first conductor film is set to A second step of substantially the same as the height position of the upper surface of the semiconductor substrate in the road area, the semiconductor substrate in the memory cell region and the peripheral circuit region,
A third step of forming element isolation trenches respectively surrounding the first and second active regions, a fourth step of forming an insulating film for a gate insulating film and a second conductor film on a substrate, And a fifth step of forming a trench-type element isolation by embedding the insulating film with an insulating film.

According to this method, it becomes possible to arrange a field effect transistor having a gate electrode composed of two conductor films in a peripheral circuit region and to form a semiconductor device capable of exhibiting the above-described effects.

As set forth in claims 31 to 40, in the third method for manufacturing a semiconductor device, also in the first method for manufacturing a semiconductor device, claims 12 to 21 are provided.
The same measures can be taken.

The fourth method of manufacturing a semiconductor device according to the present invention
A nonvolatile memory cell having a tunnel insulating film, a floating gate electrode, a gate insulating film, and a control gate electrode on a first active region in a memory cell region of a semiconductor substrate, according to claim 41. A method of manufacturing a semiconductor device for forming a field-effect transistor having a gate insulating film and a gate electrode on a second active region in a peripheral circuit region of a semiconductor substrate, wherein the semiconductor substrate in the peripheral circuit region is A first step of forming a tunnel insulating film, a first conductive film on the tunnel insulating film, and a conductive protective film on the first conductive film in the memory cell region in an exposed state; Growing a semiconductor crystal on the semiconductor substrate in the peripheral circuit region, and setting the height position of the upper surface to the height position of the upper surface of the first conductive film in the memory cell region A second step of forming substantially the same semiconductor crystal film, a third step of removing the first conductor protective film on the first conductor film, and an insulating film for a gate insulating film on the substrate; A fourth step of forming a second conductor film;
A fifth step of forming an element isolation groove surrounding the first and second active regions in the memory cell area and the peripheral circuit area, and forming a groove-type element isolation by filling the groove with an insulating film. And a sixth step.

According to this method, a semiconductor device having a semiconductor substrate in a peripheral circuit formed by epitaxial growth and having a field effect transistor having a gate electrode composed of two conductor films arranged in a peripheral circuit region is formed.

As set forth in claims 42 to 48, in the fourth method for manufacturing a semiconductor device, also in the method for manufacturing the second semiconductor device, claims 23 to 29 are provided.
The same measures can be taken.

[0072]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) First, a semiconductor device and a method of manufacturing a semiconductor device according to a first embodiment will be described with reference to FIGS.
2f and FIGS. 3a to 3e.

FIG. 1 is a sectional view showing the structure of the semiconductor device according to the first embodiment. In the figure, 10 is a semiconductor substrate, 111 is a control gate electrode of a memory cell region Rmemo, 112 is a floating gate electrode, and 113 is a peripheral circuit region Rmemo.
a gate electrode of peri, 102, a buried insulating film constituting element isolation, 121, an interlayer insulating film, 122, a connection hole, 12
Reference numeral 3 denotes a metal wiring.

FIGS. 2A to 2F and FIGS. 3A to 3E are cross-sectional views showing steps of manufacturing the semiconductor device according to the first embodiment. However, each is a sectional view taken along line 9A-9A shown in FIG. That is, a cross-sectional view of the memory cell and the MOSFET in a cross section parallel to the gate length direction and a cross section orthogonal to the gate length direction in the memory cell region Rmemo and the peripheral circuit region Rperi are shown.

First, in the step shown in FIG.
Pad oxide film 2 having a thickness of about 10 nm
1 and a silicon nitride film 22 having a thickness of about 150 nm is deposited thereon. After that, the memory cell area Rmemo
A resist film 51 having an opening thereon is formed, and the silicon nitride film 22 in the memory cell region is removed by etching using the resist film 51 as a mask.

Next, in the step shown in FIG.
1 is removed, the entire surface of the substrate is oxidized, and the pad oxide film 21 with the surface exposed in the memory cell region Rmemo is exposed.
Is further thickened to form a field oxide film 103 having a thickness of about 200 nm.

Next, in the step shown in FIG.
The silicon nitride film 22, the pad oxide film 21, and the field oxide film 103 on the zero are all removed.

Next, in the step shown in FIG.
0 is oxidized to form a tunnel oxide film 31 having a thickness of about 10 nm, and a first conductive film having a thickness of about 1 nm.
A polycrystalline silicon film 32 of 00 nm is deposited.

Next, in the step shown in FIG. 2E, the polycrystalline silicon film 32 in the peripheral circuit region Rperi is removed by performing CMP (chemical mechanical polishing) using the tunnel oxide film 31 as a stopper, and the entire substrate is flattened. . At this time, the polysilicon film 32 is exposed in the memory cell region Rmemo, and the tunnel oxide film 31 is exposed in the peripheral circuit region Rperi.
Is exposed. Thereafter, only the tunnel oxide film 31 exposed in the peripheral circuit region Rperi is removed by selective etching.

Next, in a step shown in FIG. 2F, after a pad oxide film 23 and a silicon nitride film 24 are formed on the entire surface of the substrate, a resist film 52 having an opening in a region where element isolation is to be formed is formed. Then, the silicon nitride film 24 is etched by using the resist film 52 as a mask.
The pad oxide film 23, the polycrystalline silicon film 32, the tunnel oxide film 31, and a part of the semiconductor substrate 10 are sequentially and selectively removed to form a trench 101 for element isolation.

Next, in the step shown in FIG. 3A, a silicon oxide film is deposited by CVD and planarized by CMP to form a buried insulating film 102 in the trench 101 for element isolation.

Next, in the step shown in FIG. 3B, the silicon nitride film 24 and the pad oxide film 23 are removed by selective etching (for example, wet etching) to make the upper surface of the substrate almost flat. At this time, the surface of the polycrystalline silicon film 32 is exposed in the memory cell region Rmemo, while the surface of the semiconductor substrate 10 is exposed in the peripheral circuit region Rperi.

Next, in the step shown in FIG. 3C, a gate oxide film 33 having a thickness of about 10 nm
Polycrystalline silicon film 34 as a second conductive film of 50 nm
And a silicon oxide film 35 having a thickness of about 150 nm as a conductor protection film.

Next, in the step shown in FIG. 3D, a resist film 53 is formed to cover a region where the control gate electrode is to be formed in the memory cell region Rmemo and a region where the gate electrode is to be formed in the peripheral circuit region Rperi. Then, the silicon oxide film 35 and the polycrystalline silicon film 34 are selectively removed by etching using the resist film 53 as a mask, a control gate electrode 111 is formed in the memory cell region Rmemo, and the control gate electrode 111 is formed in the peripheral circuit region Rperi. Forms a gate electrode 113. In each of the regions, the patterned silicon oxide film 35 constitutes an electrode protection film.

Next, in the step shown in FIG.
3 is removed, a resist film 51 having an opening in the memory cell region Rmemo is formed, and the gate oxide film 33 and the polycrystalline silicon film 32 in the memory cell region Rmemo are selectively etched by using the resist film 51 as a mask. The floating gate electrode 112 is removed in the memory cell region Rmemo.
To form

Although illustration of subsequent steps is omitted, after removing the resist film 51, formation of an interlayer insulating film, formation of a contact hole, formation of a wiring layer, and the like are performed. A memory cell is formed, and in the peripheral circuit region Rperi, a field effect transistor disposed in a memory cell driving circuit and a field effect transistor disposed in a logic circuit are formed.

According to the present embodiment, first, FIGS.
By forming a height difference between the upper surface of the semiconductor substrate in the memory cell region and the upper surface of the semiconductor substrate in the peripheral circuit region in consideration of the thickness of the floating gate electrode and the thickness of the tunnel oxide film, The subsequent steps can be easily and accurately performed, and the following effects can be obtained.

In the memory cell region Rmemo of the semiconductor device formed by the above manufacturing steps, the buried insulating film 102 constituting the element isolation in the cross section orthogonal to the gate length direction is different from the floating gate electrode 112 with respect to the floating gate electrode 112. Since the electrode 112 is formed in a self-aligned manner with respect to the control gate electrode 111, a margin for mask alignment for forming each member is not required, and the density of the memory cell region Rmemo can be further increased. Can be.

Further, since the upper surface of the substrate is flattened in the step immediately before the formation of the trench isolation (the step shown in FIG. 2E), the photolithography step in forming the resist film 52 for element isolation is omitted. In addition to being highly accurate and easy, the embedding of the insulating film in the element isolation trench 101 and the subsequent planarization can be easily performed without any restrictions. As a result, the trench isolation of both the memory cell region Rmemo and the peripheral circuit region Rperi can be finely formed by a simple process in a single trench isolation formation process. Further, in both the peripheral circuit region Rperi and the memory cell region Rmemo, the element isolation is constituted by the trench isolation instead of the LOCOS film, so that the density of the entire semiconductor device can be increased.

Further, in the manufacturing process of this embodiment, in the step of forming the control gate electrode 111 and the gate electrode 113 (see FIG. 3D), there is almost no height difference between the memory cell region Rmemo and the peripheral circuit region Rperi. Since it is almost flat, a photolithography process for forming a resist film 53 for forming a gate electrode can be performed with high precision and ease, and the memory cell region Rme
Since the upper surface positions of the mo control gate electrode 111 and the gate electrode 113 of the peripheral circuit region Rperi are the same, the subsequent formation of a metal wiring pattern can be easily performed.

Therefore, it is possible to integrate a flash memory and a heterogeneous device such as a DRAM and a logic into one chip at a production cost that can be put to practical use.

(Second Embodiment) Next, a second embodiment will be described with reference to FIGS. Also in this embodiment, the structure of the semiconductor device is the same as that of the first embodiment. 4A to 4E are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the second embodiment. However, each is a sectional view taken along line 9A-9A shown in FIG.

In this embodiment, the same processing as the steps shown in FIGS. 2A to 2F is performed as in the first embodiment. The description of these processes is omitted.

Next, in the step shown in FIG. 4A, a silicon oxide film is deposited by the CVD method and planarized by the CMP to form a buried insulating film 102 in the groove.

Next, in the step shown in FIG. 4B, the silicon nitride film 24 and the pad oxide film 23 are removed. At this time, in the memory cell region Rmemo, the polycrystalline silicon film 32
Is exposed, while the surface of the semiconductor substrate 10 is exposed in the peripheral circuit region Rperi.

Next, in the step shown in FIG. 4C, a gate oxide film 33 having a thickness of about 10 nm
A polycrystalline silicon film 34 as a second conductor film of 50 nm is formed.

Next, in a step shown in FIG. 4D, a resist film 54 is formed to cover the entire memory cell region Rmemo and the region where the gate electrode of the peripheral circuit region Rperi is to be formed.
By etching using the resist film 54 as a mask,
The gate electrode 113 is formed in the peripheral circuit region Rperi by selectively removing the polycrystalline silicon film 34.

Next, in the step shown in FIG.
4 is removed, a resist film 55 is formed to cover the entire peripheral circuit region Rperi and the region where the control gate electrode is to be formed in the memory cell region Rmemo.
Cell region R by etching using
The polycrystalline silicon film 34, the gate oxide film 33 and the polycrystalline silicon film 32 of the memo are selectively removed, and the control gate electrode 111 and the floating gate electrode 1 are added to the memory cell region Rmemo.
12 are formed.

Although illustration of subsequent steps is omitted, after the resist film 55 is removed, formation of an interlayer insulating film, formation of a contact hole, formation of a wiring layer, and the like are performed. A memory cell is formed, and in the peripheral circuit region Rperi, a field effect transistor disposed in a memory cell driving circuit and a field effect transistor disposed in a logic circuit are formed.

According to the present embodiment, the memory cell region R
In the memo, the buried insulating film 102 forming element isolation is formed in self-alignment with the floating gate electrode 112 and the floating gate electrode 112 is formed with the control gate electrode 111 in a cross section orthogonal to the gate length direction. Therefore, as in the first embodiment, the density of the memory cell region Rmemo can be further increased.

Since the upper surface of the substrate is flattened in the step immediately before forming the trench isolation (the step shown in FIG. 2E), a single trench isolation forming step is performed in the same manner as in the first embodiment. In a simple process, the memory cell area Rmemo
And the trench isolation in both the peripheral circuit region Rperi can be finely formed. In both the peripheral circuit region Rperi and the memory cell region Rmemo, the element isolation is L
Since the semiconductor device is formed not by the OCOS film but by trench isolation, the density of the entire semiconductor device can be increased.

Further, in the step immediately before forming the control gate electrode 111 and the gate electrode 113 (see FIG. 4C), there is almost no level difference between the memory cell region Rmemo and the peripheral circuit region Rperi, and the surface is almost flat. Since the upper surface positions of the control gate electrode 111 in the memory cell region Rmemo and the gate electrode 113 in the peripheral circuit region Rperi are the same, subsequent formation of a metal wiring pattern can be easily performed.

Therefore, according to the manufacturing method of this embodiment, it is possible to integrate different types of devices such as flash memories and DRAMs / logics into one chip at a practical manufacturing cost as in the first embodiment. It becomes.

In particular, according to the method of manufacturing the semiconductor device of the present embodiment, it is necessary to provide a conductor protection film made of a silicon oxide film or the like on the polycrystalline silicon film 34, as compared with the manufacturing method of the first embodiment. In addition, the process can be simplified accordingly.

In this embodiment, the gate electrode 113 of the peripheral circuit region Rperi is formed first, and then the control gate electrode 111 and the floating gate electrode 11 of the memory cell region Rmemo are formed.
2, the control gate electrode 111 and the floating gate electrode 112 in the memory cell region Rmemo may be formed first, and then the gate electrode 113 in the peripheral circuit region Rperi may be formed.

(Third Embodiment) Next, a third embodiment will be described with reference to FIGS. 5A to 5E. FIG.
5A to 5E are cross-sectional views illustrating manufacturing steps of the semiconductor device according to the third embodiment. However, in each case, 9A shown in FIG.
It is sectional drawing in the -9A line. That is, a cross-sectional view of the memory cell and the MOSFET in a cross section parallel to the gate length direction and a cross section orthogonal to the gate length direction in the memory cell region Rmemo and the peripheral circuit region Rperi are shown.

In the present embodiment, the same processing as the steps shown in FIGS. 2A to 2F is performed as in the first embodiment. The description of these processes is omitted.

Next, in a step shown in FIG. 5A, a silicon oxide film is deposited by the CVD method and planarized by the CMP to form a buried insulating film 102 in the groove.

Next, in the step shown in FIG. 5B, the silicon nitride film 24 and the pad oxide film 23 are removed. At this time, in the memory cell region Rmemo, the polycrystalline silicon film 32
Is exposed, while the surface of the semiconductor substrate 10 is exposed in the peripheral circuit region Rperi.

Next, in the step shown in FIG. 5C, a resist film 56 is formed to cover the entire peripheral circuit region Rperi and the region where the floating gate electrode is to be formed in the memory cell region Rmemo, and this resist film 56 is used as a mask. The floating gate electrode 112 is formed in the memory cell region Rmemo by etching.

Next, in the step shown in FIG.
After removing 6, a gate oxide film 33 having a thickness of about 10 nm and a polycrystalline silicon film 34 as a second conductor film having a thickness of about 150 nm are formed on the entire surface of the substrate.

Next, in a step shown in FIG. 5E, a resist film 53 is formed to cover a region where a control gate electrode is to be formed in the memory cell region Rmemo and a region where a gate electrode is to be formed in the peripheral circuit region Rperi. , This resist film 5
3 is used as a mask to selectively remove the polycrystalline silicon film 34 to form the gate electrode 113 in the peripheral circuit region Rperi while the memory cell region Rmemo is formed.
Then, a control gate electrode 111 extending from the floating gate electrode 112 to the semiconductor substrate 10 via the gate oxide film 33 is formed.

Although illustration of subsequent steps is omitted, after the resist film 53 is removed, formation of an interlayer insulating film, formation of a contact hole, formation of a wiring layer, and the like are performed. A memory cell is formed, and in the peripheral circuit region Rperi, a field effect transistor disposed in a memory cell driving circuit and a field effect transistor disposed in a logic circuit are formed.

According to the manufacturing method of this embodiment, a split gate memory cell having more excellent data retention characteristics than the stack gate memory cell as in the first and second embodiments can be used. The same effects as in the first and second embodiments can be exerted.

That is, in the memory cell region Rmemo, the buried insulating film 102 constituting the element isolation in the cross section orthogonal to the gate length direction has the floating gate electrode 112
Are formed in a self-aligned manner with respect to the memory cell region Rmemo, as in the first embodiment.

Since the upper surface of the substrate is flattened in the step immediately before the formation of the trench isolation (the step shown in FIG. 2E), a single trench isolation formation step is performed as in the first embodiment. In a simple process, the memory cell area Rmemo
And the trench isolation in both the peripheral circuit region Rperi can be finely formed. Then, the peripheral circuit region Rper
In both the i and the memory cell region Rmemo, the element isolation is constituted by the trench isolation instead of the LOCOS film, so that the density of the entire semiconductor device can be increased.

Further, in the step immediately before the formation of the floating gate electrode 112 (see FIG. 5B), there is almost no level difference between the memory cell region Rmemo and the peripheral circuit region Rperi, and the surface is almost flat. The process can be performed smoothly, and a metal wiring pattern can be easily formed.

Therefore, according to the manufacturing method of the present embodiment, similarly to the first and second embodiments, it is possible to integrate a heterogeneous device such as a flash memory and a DRAM / logic into one chip at a practical manufacturing cost. It becomes possible.

(Fourth Embodiment) Next, a fourth embodiment will be described with reference to FIGS. 6, 7a to 7g and 8a to 7d. However, in each case, 9A-
It is sectional drawing in 9A line. That is, a cross-sectional view of the memory cell and the MOSFET in a cross section parallel to the gate length direction and a cross section orthogonal to the gate length direction in the memory cell region Rmemo and the peripheral circuit region Rperi are shown.

FIG. 6 is a sectional view of a semiconductor device according to the fourth and fifth embodiments. In the figure, 10 is a semiconductor substrate, 111 is a control gate electrode of a memory cell region Rmemo, 112 is a floating gate electrode, and 113 is a peripheral circuit region Rmemo.
a gate electrode of peri, 102, a buried insulating film constituting element isolation, 121, an interlayer insulating film, 122, a connection hole, 12
Reference numeral 3 denotes a metal wiring. The feature of this semiconductor device with respect to the structure of the semiconductor device according to the first to third embodiments is that the control gate electrode 111 of the memory cell region Rmemo is provided.
And the gate electrode 113 in the peripheral circuit region Rperi are both formed of a two-layer polycrystalline silicon film.

FIGS. 7A to 7G and FIGS. 8A to 8D are cross-sectional views showing the steps of manufacturing the semiconductor device according to the present embodiment.

First, in the step shown in FIG.
0 is oxidized to form a pad oxide film 21 having a thickness of about 10 nm, and a silicon nitride film 2 having a thickness of about 150 nm is formed thereon.
2 is deposited. Thereafter, a resist film 51 having an opening in the memory cell region Rmemo is formed, and etching is performed using the resist film 51 as a mask.
Of the silicon nitride film 22 is removed.

Next, in the step shown in FIG.
1 is removed, the entire surface of the substrate is oxidized, and the pad oxide film 21 with the surface exposed in the memory cell region Rmemo is exposed.
Is further thickened to form a field oxide film 103.

Next, in the step shown in FIG.
The silicon nitride film 22, the pad oxide film 21, and the field oxide film 103 on the zero are all removed.

Next, in the step shown in FIG.
0 is oxidized to form a tunnel oxide film 31 having a thickness of about 10 nm, and a first conductive film having a thickness of about 1 nm.
A polycrystalline silicon film 32 of 00 nm is deposited.

Next, in the step shown in FIG. 7E, the polycrystalline silicon film 32 in the peripheral circuit region Rperi is removed by performing CMP using the tunnel oxide film 31 as a stopper, and the entire substrate is flattened. At this time, the polysilicon film 32 is exposed in the memory cell region Rmemo, and the peripheral circuit region Rmemo is exposed.
In peri, the tunnel oxide film 31 is exposed. Thereafter, only the tunnel oxide film 31 exposed in the peripheral circuit region Rperi is removed by selective etching.

Next, in a step shown in FIG. 7F, a gate oxide film 33 having a thickness of about 10 nm and a polycrystalline silicon film 34 having a thickness of about 150 nm as a second conductor film are formed on the entire surface of the substrate.
And are formed.

Next, in a step shown in FIG. 7G, a resist film 52 having an opening in a region where element isolation is to be formed is formed. Then, the polysilicon film 34 and the gate oxide film 3 are etched by using the resist film 52 as a mask.
3. The polycrystalline silicon film 32, the tunnel oxide film 31 and the substrate 10 are sequentially etched to form a trench 101 for element isolation.

Next, in the step shown in FIG. 8A, a silicon oxide film is deposited by the CVD method and planarization is performed by CMP using the polycrystalline silicon film 34 as a stopper, and the buried insulating film 102 in the trench 101 for element isolation is formed. To form

Next, in the step shown in FIG. 8B, a polycrystalline silicon film 36 having a thickness of about 50 nm as a third conductor film and a silicon oxide film 35 having a thickness of about 150 nm as a conductor protection film are formed on the entire surface of the substrate. And are formed.

Next, in the step shown in FIG. 8C, a resist film 53 is formed to cover the region where the control gate electrode is to be formed in the memory cell region memo and the region where the gate electrode is to be formed in the peripheral circuit region Rperi. , This resist film 53
Silicon oxide film 3 by etching using
5, the polycrystalline silicon film 36 and the polycrystalline silicon film 34 are selectively removed, and the control gate electrode 111 in the memory cell region Rmemo and the gate electrode 113 in the peripheral circuit region Rperi are removed.
And are formed.

Next, in the step shown in FIG.
3 is removed, a resist film 51 is formed to open the memory cell region Rmemo and cover the peripheral circuit region Rperi, and the resist film 51, the control gate electrode 111 and the silicon oxide film 35 are used as a mask to perform etching. The gate oxide film 33 and the polycrystalline silicon film 32 in Rmemo are selectively removed to form a floating gate electrode 112 in the memory cell region Rmemo.

Although illustration of subsequent steps is omitted, after removing the resist film 51, formation of an interlayer insulating film, formation of a contact hole, formation of a wiring layer, and the like are performed. A memory cell is formed, and in the peripheral circuit region Rperi, a field effect transistor disposed in a memory cell driving circuit and a field effect transistor disposed in a logic circuit are formed.

According to the present embodiment, the memory cell region R
In the memo, the buried insulating film 102 forming element isolation is formed in self-alignment with the floating gate electrode 112 and the floating gate electrode 112 is formed with the control gate electrode 111 in a cross section orthogonal to the gate length direction. Therefore, as in the first to third embodiments, the density of the memory cell region Rmemo can be further increased.

Since the upper surface of the substrate is flattened in the step immediately before the formation of the trench isolation (the step shown in FIG. 7F), as in the first to third embodiments, one trench is formed. In the isolation forming process, the trench isolation of both the memory cell region Rmemo and the peripheral circuit region Rperi can be formed finely by a simple process. Then, the peripheral circuit region R
In both the peri and the memory cell region Rmemo, the element isolation is constituted not by the LOCOS film but by the trench isolation, so that the overall density of the semiconductor device can be increased.

Further, in the step immediately before the formation of the control gate electrode 111 and the gate electrode 113 (see FIG. 8B), there is almost no level difference between the memory cell region Rmemo and the peripheral circuit region Rperi. Since the upper surface positions of the control gate electrode 111 in the memory cell region Rmemo and the gate electrode 113 in the peripheral circuit region Rperi are the same, subsequent formation of a metal wiring pattern can be easily performed.

Therefore, according to the manufacturing method of the present embodiment, it is possible to integrate a heterogeneous device such as a flash memory and a DRAM / logic into one chip at a practical manufacturing cost, as in the first embodiment. It becomes.

In particular, according to the method of manufacturing a semiconductor device of the present embodiment, the gate electrode 113 of the peripheral circuit region Rperi has two gate electrodes.
Since the device isolation layer is formed of a polycrystalline silicon film and the element isolation is formed in a self-aligned manner in the lower layer film of the gate electrode 113 (refer to the right end portion of FIG. 8D), the trench isolation side usually causes a problem from the side of the trench. Characteristic fluctuation due to the electric field concentration of the semiconductor device can be suppressed.

(Fifth Embodiment) Next, a fifth embodiment will be described with reference to FIGS. 10A to 10D.
10A to 10D are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the fifth embodiment. However, in both cases, FIG.
FIG. 9 is a sectional view taken along line 9A-9A shown in FIG. That is,
In the memory cell region Rmemo and the peripheral circuit region Rperi, cross-sectional views of a memory cell and a MOSFET in a cross section parallel to the gate length direction and a cross section orthogonal to the gate length direction are shown.

Also in this embodiment, the same processing as the steps shown in FIGS. 7A to 7G described in the fourth embodiment is performed. The description of these processes is omitted.

Next, in the step shown in FIG. 10A, a silicon oxide film is deposited by the CVD method and planarization is performed by CMP using the polycrystalline silicon film 34 as a stopper, and the buried insulating film 102 in the trench 101 for element isolation is formed. To form

Next, in a step shown in FIG. 10B, a polycrystalline silicon film 36 having a thickness of about 50 nm is formed as a third conductive film on the entire surface of the substrate.

Next, in the step shown in FIG. 10C, a resist film 54 is formed to cover the entire memory cell region memo and the region where the gate electrode of the peripheral circuit region Rperi is to be formed.
By etching using the resist film 54 as a mask,
The polysilicon film 36 and the polysilicon film 34 are selectively removed, and the gate electrode 113 is formed in the peripheral circuit region Rperi.
And are formed.

Next, in the step shown in FIG. 10D, after removing the resist film 54, a resist film 55 is formed to cover the region where the control gate electrode is to be formed in the memory cell region Rmemo and the entire peripheral circuit region Rperi. , This resist film 5
5, the polycrystalline silicon films 36 and 34, the gate oxide film 33 and the polycrystalline silicon film 32 in the memory cell region Rmemo are selectively removed by etching.
A control gate electrode 111 and a floating gate electrode 112 are formed in the memory cell region Rmemo.

Although illustration of the subsequent steps is omitted, after the resist film 55 is removed, formation of an interlayer insulating film, formation of a contact hole, formation of a wiring layer, and the like are performed. A memory cell is formed, and in the peripheral circuit region Rperi, a field effect transistor disposed in a memory cell driving circuit and a field effect transistor disposed in a logic circuit are formed.

According to the present embodiment, the memory cell region R
In the memo, the buried insulating film 102 forming element isolation is formed in self-alignment with the floating gate electrode 112 and the floating gate electrode 112 is formed with the control gate electrode 111 in a cross section orthogonal to the gate length direction. Therefore, as in the first to third embodiments, the density of the memory cell region Rmemo can be further increased.

Since the upper surface of the substrate is flattened in the step immediately before the formation of the trench isolation (step shown in FIG. 7F), one trench is formed as in the first to third embodiments. In the isolation forming process, the trench isolation of both the memory cell region Rmemo and the peripheral circuit region Rperi can be formed finely by a simple process. Then, the peripheral circuit region R
In both the peri and the memory cell region Rmemo, the element isolation is constituted not by the LOCOS film but by the trench isolation, so that the overall density of the semiconductor device can be increased.

Further, similarly to the fourth embodiment, in the step immediately before forming the control gate electrode 111 and the gate electrode 113 (see FIG. 10B), the height between the memory cell region Rmemo and the peripheral circuit region Rperi is increased. Since there is almost no difference and the surface is almost flat, the upper surface position of the control gate electrode 111 in the memory cell region Rmemo and the upper surface position of the gate electrode 113 in the peripheral circuit region Rperi are the same. Can be.

Therefore, according to the manufacturing method of the present embodiment, it is possible to integrate a heterogeneous device such as a flash memory and a DRAM / logic into one chip at a practical manufacturing cost, similarly to the fourth embodiment. It becomes.

As in the fourth embodiment, the gate electrode 113 in the peripheral circuit region Rperi is formed of a two-layer polycrystalline silicon film, and element isolation is performed in a self-aligned manner with the lower film 34 of the gate electrode 113. Since it is formed (see the right end portion in FIG. 10D), it is possible to suppress characteristic fluctuation due to electric field concentration from the side surface of the trench, which is usually a problem in trench isolation.

In particular, in the manufacturing process of the present embodiment, it is not necessary to provide a conductor protection film such as a silicon oxide film on the polycrystalline silicon film 36 as compared with the fourth embodiment, and the process is simplified accordingly. Can be

In this embodiment, the peripheral circuit area Rperi
Of the control gate electrode 111 and the floating gate electrode 1 in the memory cell region Rmemo.
12, the control gate electrode 111 and the floating gate electrode 112 in the memory cell region Rmemo may be formed first, and then the gate electrode 113 in the peripheral circuit region Rperi may be formed.

(Sixth Embodiment) Next, a method of manufacturing a semiconductor device according to a sixth embodiment will be described with reference to FIGS.
This will be described with reference to f. 11A to 11F are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the sixth embodiment. However, each is a sectional view taken along line 9A-9A shown in FIG. That is, a cross-sectional view of the memory cell and the MOSFET in a cross section parallel to the gate length direction and a cross section orthogonal to the gate length direction in the memory cell region Rmemo and the peripheral circuit region Rperi are shown.

In this embodiment, first, the same processing as the steps shown in FIGS. 7A to 7G described in the fourth embodiment is performed. The description of these processes is omitted.

Next, in the step shown in FIG. 11A, a silicon oxide film is deposited by the CVD method and planarization is performed by CMP using the polycrystalline silicon film 34 as a stopper, and the buried insulating film 102 is embedded in the trench 101 for element isolation. To form

Next, in a step shown in FIG. 11B, a resist film 51 having an opening in the memory cell region Rmemo is formed, and the polycrystalline silicon film 34 in the memory cell region Rmemo and the resist film 51 are etched by using the resist film 51 as a mask. 1
Of the gate oxide film 33 is selectively removed.

Next, in the step shown in FIG. 11C, a resist film 56 is formed to cover the entire peripheral circuit region Rperi and the region where the floating gate electrode is to be formed in the memory cell region Rmemo, and this resist film 56 is used as a mask. Etching, the polycrystalline silicon film 3 in the memory cell region Rmemo
2 is selectively removed to form the floating gate electrode 112 in the memory cell region Rmemo.

Next, in a step shown in FIG. 11D, after removing the resist film 56, a second gate oxide film 37 having a thickness of about 10 nm is formed on the entire surface of the substrate. Further, a resist film 57 having an opening in the peripheral circuit region Rperi is formed on the substrate, and the second gate oxide film 37 in the peripheral circuit region Rperi is removed by etching using the resist film 57 as a mask.

Next, in a step shown in FIG. 11E, after removing the resist film 57, a polycrystalline silicon film 36 having a thickness of about 50 nm is deposited as a third conductive film on the entire surface of the substrate.

Next, in a step shown in FIG. 11F, a resist film 53 is formed to cover a region where a control gate electrode is to be formed in the memory cell region Rmemo and a region where a gate electrode is to be formed in the peripheral circuit region Rperi. The polysilicon film 36 and the polysilicon film 34 are selectively removed by etching using the resist film 53 as a mask, so that the control gate electrode 111 in the memory cell region Rmemo and the gate electrode 113 in the peripheral circuit region Rperi are separated. Form.

Although illustration of the subsequent steps is omitted, after removing the resist film 53, formation of an interlayer insulating film, formation of a contact hole, formation of a wiring layer, and the like are performed. A memory cell is formed, and in the peripheral circuit region Rperi, a field effect transistor disposed in a memory cell driving circuit and a field effect transistor disposed in a logic circuit are formed.

As described above, according to the present embodiment, a split gate memory cell having more excellent data retention characteristics than the stack gate memory cell as in the fourth and fifth embodiments is used. Also, the same effects as in the fourth and fifth embodiments can be exhibited.

That is, in the memory cell region Rmemo, the buried insulating film 102 constituting the element isolation in the cross section orthogonal to the gate length direction has the floating gate electrode 112
On the other hand, the floating gate electrode 112 is
1 is formed in a self-aligned manner, so that the density of the memory cell region Rmemo can be further increased.

Since the upper surface of the substrate is flattened in the step immediately before the formation of the trench isolation (the step shown in FIG. 7F), the memory cell region Rmemo can be formed in a simple step by a single trench isolation formation step. And the trench isolation in both the peripheral circuit region Rperi can be finely formed. Further, in both the peripheral circuit region Rperi and the memory cell region Rmemo, the element isolation is constituted by the trench isolation instead of the LOCOS film, so that the density of the entire semiconductor device can be increased.

Further, in the step before the formation of the control gate electrode 111 and the gate electrode 113 (see FIG. 11A), there is almost no level difference between the memory cell region Rmemo and the peripheral circuit region Rperi. Since the upper surface positions of the control gate electrode 111 in the memory cell region Rmemo and the gate electrode 113 in the peripheral circuit region Rperi are the same, subsequent formation of a metal wiring pattern can be easily performed.

Therefore, according to the manufacturing method of this embodiment, as in the fourth and fifth embodiments, it is possible to integrate different types of devices such as flash memory and DRAM / logic into one chip at a practical manufacturing cost. It becomes possible.

As in the fourth and fifth embodiments, the gate electrode 113 in the peripheral circuit region Rperi is formed of a two-layer polycrystalline silicon film, and the element isolation is performed by the gate electrode 1.
13 is formed on the lower film 34 in a self-aligned manner (FIG. 1).
1f), characteristic fluctuation due to electric field concentration from the side surface of the trench, which is usually a problem in trench isolation, can be suppressed.

(Seventh Embodiment) Next, a method of manufacturing a semiconductor device according to a seventh embodiment will be described with reference to FIGS.
This will be described with reference to c. 12A to 12C are cross-sectional views showing up to the planarization step in the manufacturing steps of the semiconductor device according to the seventh embodiment.

First, in the step shown in FIG. 12A, a resist film 51 is formed on the semiconductor substrate 10 so as to open the memory cell region Rmemo and cover the peripheral circuit region Rperi, and the memory is etched by using the resist film 51 as a mask. The semiconductor substrate 10 in the cell region Rmemo is removed by a depth of 100 nm.

Next, in the step shown in FIG. 12B, after removing the resist film 51, the entire surface of the substrate is oxidized to a thickness of about 10
A tunnel oxide film 31 having a thickness of 100 nm is formed, and a polycrystalline silicon film 32 having a thickness of 100 nm is formed on the tunnel oxide film 31 as a first conductor film. Then, a resist film 57 covering the memory cell region Rmemo and opening the peripheral circuit region Rperi is formed on the polycrystalline silicon oxide film 32.

Next, in the step shown in FIG. 12C, the polysilicon film 32 and the tunnel oxide film 31 in the peripheral circuit region are removed by etching using the resist film 57 as a mask.

Although illustration of subsequent steps is omitted, after the resist film 57 is removed, the same processing as in the first to sixth embodiments is performed to thereby obtain the memory cell region Rmemo.
A memory cell having a floating gate electrode and a control gate electrode, and a field effect transistor having a gate electrode in the peripheral circuit region Rperi. For example, the steps shown in FIGS. 2F and 3A to 3E in the first embodiment, and FIGS. 7F, 7G and 8 in the fourth embodiment.
The same processing as the steps a to 8d is performed.

According to the present embodiment, in the step shown in FIG. 12C, the polycrystalline silicon film 32 forming the floating gate electrode is formed in the memory cell region Rmemo, and the polycrystalline silicon film 32 in the memory cell region Rmemo is formed. The upper surface and the upper surface of the semiconductor substrate 10 in the peripheral circuit region Rperi are substantially flattened. Therefore, the element density in both the memory cell region Rmemo and the peripheral circuit region Rperi can be improved by a simpler process than the manufacturing process of the semiconductor device according to the first to sixth embodiments.

In particular, according to the present embodiment, the height of the semiconductor substrate surface in the memory cell region Rmemo is made lower than the height of the semiconductor substrate surface in the peripheral circuit region Rperi in consideration of the floating gate electrode and the tunnel oxide film. By forming the height difference forming step by an etching method without using the normal LOCOS method, the step can be simplified. In addition, a planarization step for making the height of the upper surface of the polycrystalline silicon film 32, which is the first conductor film of the memory cell region Rmemo, and the surface of the semiconductor substrate of the peripheral circuit region Rperi substantially the same is performed by etching. Variations in the thickness of the first conductive film due to dishing by CMP can be suppressed.

(Eighth Embodiment) Next, a method of manufacturing a semiconductor device according to an eighth embodiment will be described with reference to FIGS.
This will be described with reference to e. 13a to 13e show the eighth embodiment.
FIG. 16 is a cross-sectional view showing a process of manufacturing the semiconductor device according to the embodiment up to the planarization process;

First, in a step shown in FIG. 13A, the entire surface of the semiconductor substrate 10 is oxidized to form a silicon oxide film 25 having a thickness of about 100 nm, and a memory cell region Rmemo is formed thereon.
Film 5 covering the circuit and opening the peripheral circuit region Rperi
After forming 7, the silicon oxide film 25 in the peripheral circuit region Rperi is removed by etching using the resist film 57 as a mask.

Next, in the step shown in FIG. 13B, after removing the resist film 57, the semiconductor substrate 1 in the peripheral circuit region Rperi is removed.
A single crystal silicon film 11 having a thickness of about 100 nm is grown by selective epitaxial growth on the region where the zero surface is exposed. That is, the upper surface of the silicon oxide film 25 in the memory cell region Rmemo and the upper surface of the single crystal silicon film 11 in the peripheral circuit region Rperi are made substantially flat.

Next, in the step shown in FIG. 13C, after removing the silicon oxide film 25 in the memory cell region Rmemo, the entire surface of the substrate is oxidized to form a tunnel oxide film 31 having a thickness of about 10 nm. A polysilicon film 32 having a thickness of about 100 is formed thereon as a first conductor film.

Next, in the step shown in FIG. 13D, the entire memory cell region Rmemo and the region which is about 1 μm from the memory cell region Rmemo into the peripheral circuit region Rperi are covered, and the remaining peripheral circuit region Rperi is opened. A resist film 58 is formed, and the polysilicon film 32 in the peripheral circuit region Rperi is removed by etching using the resist film 58 as a mask.

Next, in the step shown in FIG. 13E, after removing the resist film 58, the polycrystalline silicon film 3 projecting at the boundary between the memory cell region Rmemo and the peripheral circuit region Rperi is removed.
2 is removed by CMP, and the peripheral circuit region Rperi
By removing the tunnel oxide film 31, the entire substrate is flattened.

Although illustration of subsequent steps is omitted, by performing the same processing as in the first to sixth embodiments, a memory cell having a floating gate electrode and a control gate electrode is placed in the memory cell region Rmemo. A field effect transistor having a gate electrode can be formed in the peripheral circuit region Rperi. For example, FIG. 2 in the first embodiment
f, the same processes as those shown in FIGS. 3A to 3E and the processes shown in FIGS. 7F and 7G and FIGS. 8A to 8D in the fourth embodiment are performed.

According to the present embodiment, the polycrystalline silicon film 32 forming the floating gate electrode is formed in the memory cell region Rmemo in the step shown in FIG. 13E, and the upper surface of the polycrystalline silicon film 32 and the peripheral circuit are formed. Region Rperi
The upper surface of the semiconductor substrate 10 is flattened. Therefore, similarly to the first to sixth embodiments, the device density in both the memory cell region Rmemo and the peripheral circuit region Rperi can be improved by simple steps.

In particular, according to the present embodiment, the height of the semiconductor substrate surface of the memory cell region Rmemo is changed to the peripheral circuit region Rperi.
By forming the height difference step of making the height lower than the height of the semiconductor substrate surface by selective epitaxial growth, the breakdown voltage of the tunnel oxide film and the gate oxide film is improved. In addition, a flattening step for making the height of the upper surface of the polycrystalline silicon film 32 as the first conductor film in the memory cell region Rmemo and the height of the semiconductor substrate surface in the peripheral circuit region Rperi the same is performed by using both etching and CMP. By doing so, it is not necessary to suppress the variation in the film thickness of the first conductive film due to dishing in the CMP and to consider the misalignment of the mask of the resist film 58 due to the unevenness of the upper surface of the substrate.

(Ninth Embodiment) Next, a method of manufacturing a semiconductor device according to a ninth embodiment will be described with reference to FIGS.
This will be described with reference to d. Figures 14a to 14d show the ninth
FIG. 16 is a cross-sectional view showing a process of manufacturing the semiconductor device according to the embodiment up to the planarization process;

First, in the step shown in FIG. 14A, the entire surface of the semiconductor substrate 10 is oxidized to form a tunnel oxide film 31 having a thickness of about 10 nm, and a multi-layer film having a thickness of about 100 nm is formed thereon as a first conductor film. A crystalline silicon film 32 is formed.
Then, after forming a resist film 57 covering the memory cell region Rmemo and opening the peripheral circuit region Rperi on the polycrystalline silicon film 32, the polycrystalline silicon in the peripheral circuit region Rperi is etched by using the resist film 57 as a mask. The film 32 and the tunnel oxide film 31 are removed.

Next, in the step shown in FIG. 14B, after removing the resist film 57, the entire surface of the substrate is oxidized to form a silicon oxide film 26 having a thickness of about 30 nm to be a conductor protective film. Here, since the oxidation rate of polycrystalline silicon is higher than that of single crystal silicon due to the accelerated oxidation phenomenon, the silicon oxide film 26 having a thickness of about 30 nm is formed on the polycrystalline silicon film 32.
Is formed, a silicon oxide film 26 having a thickness of about 10 nm is formed on the substrate in the peripheral circuit region Rperi. Since the degree of the accelerated oxidation depends on the oxidation temperature and the oxidation atmosphere, it is preferable that the oxidation be performed at a lower temperature (850 ° C. or lower) and a higher water vapor concentration.

Then, in the step shown in FIG. 14C, anisotropic etching is performed to remove the silicon oxide film 26 on the substrate. At this time, the etching amount is set to 15 so that the silicon oxide film 26 on the polycrystalline silicon film 32 is not entirely removed.
and the thickness of the silicon oxide film 26 remaining on the polycrystalline silicon film 32 in the memory cell region Rmemo is set to 1 nm.
It is set to about 5 nm.

Next, in a step shown in FIG. 14D, a thickness of about 100 nm is formed by selective epitaxial growth on a region of the peripheral circuit region Rperi where the surface of the semiconductor substrate 10 is exposed.
The single crystal silicon film 11 of m is grown. Thereafter, although not shown, the silicon oxide film 26 in the memory cell region Rmemo is removed, and the entire surface of the substrate is substantially flattened.

Although illustration of subsequent steps is omitted, by performing the same processing as in the first to sixth embodiments, a memory cell having a floating gate electrode and a control gate electrode is placed in the memory cell region Rmemo. A field effect transistor having a gate electrode can be formed in the peripheral circuit region Rperi. For example, FIG. 2 in the first embodiment
f, the same processes as those shown in FIGS. 3A to 3E and the processes shown in FIGS. 7F and 7G and FIGS. 8A to 8D in the fourth embodiment are performed.

According to the present embodiment, the polycrystalline silicon film 32 forming the floating gate electrode is formed in the memory cell region Rmemo in the step shown in FIG. 14E. The upper surface of the crystalline silicon film 32 and the upper surface of the semiconductor substrate 10 in the peripheral circuit region Rperi are flattened. Therefore, similarly to the first to sixth embodiments, the device density in both the memory cell region Rmemo and the peripheral circuit region Rperi can be improved by simple steps.

Further, according to the present embodiment, a height difference forming step of making the substrate surface height of the memory cell region Rmemo lower than the substrate surface height of the peripheral circuit region Rperi; Polycrystalline silicon film 3 as a conductor film
2 can be performed without forming a mask, so that the number of steps can be significantly reduced.

(Tenth Embodiment) Next, a method of manufacturing a semiconductor device according to a tenth embodiment will be described with reference to FIGS.
This will be described with reference to 15d. 15a to 15d
FIG. 7 is a cross-sectional view illustrating a manufacturing step of the semiconductor device according to the embodiment.

First, in the step shown in FIG. 15A, the entire surface of the semiconductor substrate 10 is oxidized to form a tunnel oxide film 31 having a thickness of about 10 nm, and a tunnel oxide film 31 having a thickness of about 100 nm is further formed thereon as a first conductive film. A silicon oxide film 27 having a thickness of about 50 nm is formed as a crystalline silicon film 32 and a first conductor protection film. Then, after forming a resist film 57 covering the memory cell region Rmemo and opening the peripheral circuit region Rperi on the silicon oxide film 27, the silicon oxide film 27 in the peripheral circuit region Rperi is etched by using the resist film 57 as a mask. Then, the polysilicon film 32 and the tunnel oxide film 31 are removed.

Next, in the step shown in FIG. 15B, after removing the resist film 57, the entire surface of the substrate is oxidized to form a silicon oxide film 28 having a thickness of about 20 nm as a second conductor protective film. Here, the silicon oxide film 28 is formed by CV
The method D or the oxidation method may be used.

Next, in the step shown in FIG. 15C, anisotropic etching is performed to remove the silicon oxide film 28 on the substrate. At this time, the silicon oxide film 2 serving as the second conductor protection film on the polycrystalline silicon film 32 in the memory cell region Rmemo is
Even if all of the silicon oxide film 8 is removed, the silicon oxide film 2 as a first conductor protection film is formed on the polycrystalline silicon film 32 in advance.
7, the polycrystalline silicon film 32 in the memory cell region Rmemo is not likely to be etched.

Next, in a step shown in FIG. 15D, a thickness of about 100 nm is formed by selective epitaxial growth on a region of the peripheral circuit region Rperi where the surface of the semiconductor substrate 10 is exposed.
The single crystal silicon film 11 of m is grown. Thereafter, although not shown, the silicon oxide film 27 in the memory cell region Rmemo is removed, and the entire surface of the substrate is substantially flattened.

Although illustration of subsequent steps is omitted, by performing the same processing as in the first to sixth embodiments, a memory cell having a floating gate electrode and a control gate electrode is placed in the memory cell region Rmemo. A field effect transistor having a gate electrode can be formed in the peripheral circuit region Rperi. For example, FIG. 2 in the first embodiment
f, the same processes as those shown in FIGS. 3A to 3E and the processes shown in FIGS. 7F and 7G and FIGS. 8A to 8D in the fourth embodiment are performed.

Also in this embodiment, the polycrystalline silicon film 32 constituting the floating gate electrode is formed in the memory cell region Rmemo in the step shown in FIG. 15E, and the polycrystalline silicon film 32 is removed by the subsequent removal of the silicon oxide film 27. The upper surface of the crystalline silicon film 32 and the upper surface of the semiconductor substrate 10 in the peripheral circuit region Rperi are flattened. Therefore, similarly to the first to sixth embodiments, the device density in both the memory cell region Rmemo and the peripheral circuit region Rperi can be improved by simple steps.

A height difference forming step of lowering the height of the substrate surface of the memory cell region Rmemo below the height of the substrate surface of the peripheral circuit region Rperi, and the step of forming a polycrystalline silicon as the first conductive film of the memory cell region Rmemo Since the planarization process for making the upper surface of the film 32 and the substrate surface of the peripheral circuit region Rperi substantially the same can be performed without forming a mask, the number of processes can be greatly reduced.

Further, according to the present embodiment, the process margin at the time of etching the silicon oxide film 28 as the second conductor protection film is improved, and the yield is improved.

(Eleventh Embodiment) Next, a method of manufacturing a semiconductor device according to an eleventh embodiment will be described with reference to FIGS.
This will be described with reference to FIG. 16a to 16b
FIG. 7 is a cross-sectional view illustrating a manufacturing step of the semiconductor device according to the embodiment.

First, in the step shown in FIG. 16A, the entire surface of the semiconductor substrate 10 is oxidized to form a tunnel oxide film 31 having a thickness of about 10 nm, and a multi-layer film having a thickness of about 100 nm is formed thereon as a first conductive film. A silicon oxide film 27 having a thickness of about 50 nm is formed as a crystalline silicon film 32 and a conductor protection film. Then, after forming a resist film 57 covering the memory cell region Rmemo and opening the peripheral circuit region Rperi on the silicon oxide film 27, the silicon oxide film 27 in the peripheral circuit region Rperi is etched by using the resist film 57 as a mask. , Polycrystalline silicon film 32 and tunnel oxide film 3
Remove one.

Next, in a step shown in FIG. 16B, a thickness of about 100 nm is formed by selective epitaxial growth on a region of the peripheral circuit region Rperi where the surface of the semiconductor substrate 10 is exposed.
The single crystal silicon film 11 of m is grown. Thereafter, although not shown, the silicon oxide film 27 in the memory cell region Rmemo is removed, and the entire surface of the substrate is substantially flattened.

Although illustration of subsequent steps is omitted, by performing the same processing as in the first to sixth embodiments, a memory cell having a floating gate electrode and a control gate electrode is placed in the memory cell region Rmemo. A field effect transistor having a gate electrode can be formed in the peripheral circuit region Rperi. For example, FIG. 2 in the first embodiment
f, the same processes as those shown in FIGS. 3A to 3E and the processes shown in FIGS. 7F and 7G and FIGS. 8A to 8D in the fourth embodiment are performed.

According to the present embodiment, the polycrystalline silicon film 32 forming the floating gate electrode is formed in the memory cell region Rmemo in the step shown in FIG. 16B, and the polycrystalline silicon film 32 is removed by the subsequent removal of the silicon oxide film 27. The upper surface of the crystalline silicon film 32 and the upper surface of the semiconductor substrate 10 in the peripheral circuit region Rperi are flattened. Therefore, similarly to the first to sixth embodiments, the device density in both the memory cell region Rmemo and the peripheral circuit region Rperi can be improved by simple steps.

A height difference forming step for lowering the substrate surface height of the memory cell region Rmemo below the substrate surface height of the peripheral circuit region Rperi, and a polycrystalline silicon which is a first conductive film of the memory cell region Rmemo Since the planarization process for making the upper surface of the film 32 and the substrate surface of the peripheral circuit region Rperi substantially the same can be performed without forming a mask, the number of processes can be greatly reduced.

In particular, according to the present embodiment, there is an advantage that the single-crystal silicon film 11 can be formed by an extremely simple process as compared with the ninth and tenth embodiments.

Since the side surfaces of the polycrystalline silicon film 32 are not protected by the insulating film, the memory cell region Rme
There is a possibility that the crystallinity of the single crystal silicon film 11 near the boundary between the mo and the peripheral circuit region Rperi may be degraded. Parts with poor properties can be easily removed.

(Other Embodiments) In the first to tenth embodiments, the source / drain regions of the non-volatile memory cell and the field-effect transistor and the wells for forming the wells are formed.
Although the steps of ion implantation and heat treatment for controlling the threshold voltage have been omitted, it goes without saying that these steps are performed using a known technique.

In each of the above embodiments, CMP is performed in the flattening step when the buried insulating film 102 is formed in the element isolation trench 101. However, a resist etch back method or a spin etching method may be used. In this case, if there is a sufficient selection ratio so that the polycrystalline silicon film can function as an etching stopper, a polycrystalline silicon film can be used instead of the silicon nitride film 24 in the first to third embodiments.

In the first to fifth embodiments, the gate oxide film 33 is a gate insulating film of a field effect transistor in the peripheral circuit region Rperi and a capacitance insulating film between the floating gate electrode and the control gate electrode in the memory cell region Rmemo. And have a common thickness. However, the control gate electrode 111 in the memory cell region Rmemo and the peripheral circuit region Rperi
Since the conditions such as the applied voltage are different from those of the gate electrode 113, the both can be formed to have different film thicknesses from each other. In that case, the following steps can be performed.

First, in the step shown in FIG. 3C and the like, the gate oxide film 33 (first gate insulating film) is oxidized or CVD.
After the formation by deposition using a method, a resist film covering the memory cell region Rmemo is formed, and the thickness of the gate oxide film 33 in the peripheral circuit region Rperi is reduced or the entire thickness is removed. Thereafter, a second gate insulating film is formed over the entire surface by oxidation or CVD, and then a polycrystalline silicon film 34 may be deposited as a second conductor film. Through these steps, gate insulating films having different thicknesses can be formed in the peripheral circuit region Rperi and the memory cell region Rmemo. However, in the process shown in FIG.
When the gate oxide film 33 is formed by the oxidation method,
Oxidation progresses faster in polycrystalline silicon than in single-crystal silicon due to the accelerated oxidation phenomenon described above. Therefore, the gate oxide film 33 in the memory cell region Rmemo is considerably thicker than the gate oxide film 33 in the peripheral circuit region Rperi. It is general. Therefore, it is possible to make the thickness of the gate oxide film in the memory cell region Rmemo larger than the thickness of the gate oxide film in the peripheral circuit region Rperi without necessarily performing the above steps.

Further, the gate insulating film having the larger thickness may be used not only in the memory cell region Rmemo but also in a high withstand voltage or input / output field effect transistor in the peripheral circuit region Rperi.

Although the polycrystalline silicon film is used as the conductive film in the first to sixth embodiments, the polycrystalline silicon film (or the amorphous film) is used as the second conductive film in the first to third embodiments. As a laminated film of a crystalline silicon film) and a metal or a metal compound, and as the third conductor film in the fourth to sixth embodiments, a single-layer film of a metal or a metal compound or a polycrystalline silicon film (or an amorphous silicon film) It may be a laminated film of a film) and a metal or a metal compound.

[0215]

According to the first aspect of the present invention, a semiconductor device in which a nonvolatile memory cell is arranged in a memory cell region and a field effect transistor is arranged in a peripheral circuit region is provided in a semiconductor substrate in a first active region of a memory cell region. Is lower than the upper surface of the semiconductor substrate in the second active region of the peripheral circuit region, and the height position of the upper surface of the floating gate electrode and the height position of the upper surface of the semiconductor substrate in the second active region In addition, since the element isolation of the trench structure is provided in both regions, the fidelity of the formed pattern with respect to the mask pattern in each region can be maintained at a high level while maintaining the flatness of the semiconductor device well. It is possible to realize a single-chip semiconductor device such as a flash-embedded logic device by increasing the density and reducing the cost of the entire semiconductor device.

The structure of claim 1 can be realized by a simple method by the method of manufacturing a semiconductor device of claim 11.

In particular, the height difference in claim 1 can be easily realized by the method for manufacturing a semiconductor device in claims 16 to 18.

According to claims 2 to 10, in addition to the basic effects of claim 1, the following effects can be exerted.

According to the second aspect, the upper surface of the element isolation is flattened with respect to the upper surface of the floating gate electrode and the upper surface of the semiconductor substrate in the second active region of the peripheral circuit. Extremely high.

[0220] The structure of claim 2 is the same as that of claims 19 to
21 can be easily realized by the method for manufacturing a semiconductor device.

According to the third aspect, since the floating gate electrode is self-aligned for element isolation, higher density can be achieved.

The structure of claim 3 can be easily realized by the method of manufacturing a semiconductor device of claims 12 and 13.

According to the fourth aspect, it is possible to increase the density of a semiconductor device having a split gate type nonvolatile memory cell having good data retention.

The structure of claim 4 can be easily realized by the method of manufacturing a semiconductor device of claim 14.

According to claim 6 or 7, the control gate electrode and the gate electrode are constituted by a laminated film of a lower conductive film and an upper conductive film, and the lower conductive film in the second active region of the peripheral circuit region is formed. Is self-aligned with the element isolation, it is possible to effectively prevent the variation in characteristics due to the concentration of the electric field, which is a drawback of the trench isolation. In particular, according to the seventh aspect, this effect can be exerted for a semiconductor device including a split gate nonvolatile memory cell having good data retention.

According to the ninth aspect, since the gate insulating film of the nonvolatile memory cell is made thicker than the gate insulating film of the field effect transistor, it is possible to secure an appropriate thickness for each film.

The structure according to claim 9 can be easily realized by the method for manufacturing a semiconductor device according to claim 15 or the like.

According to the tenth aspect, in the first to ninth aspects, the height difference is provided by using the semiconductor crystal film formed by epitaxial growth, so that the characteristics can be improved by the epitaxially grown film having good crystallinity. Can be planned.

The structure according to claim 10 can be easily realized by the method for manufacturing a semiconductor device according to claims 22 to 29 and 41 to 48.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to first and second embodiments.

FIG. 2 is a cross-sectional view showing each step of the manufacturing process of the semiconductor device according to the first embodiment up to the step of forming an element isolation groove;

FIG. 3 is a cross-sectional view showing each step of the manufacturing steps of the semiconductor device according to the first embodiment after the step of forming a buried insulating film;

FIG. 4 is a cross-sectional view showing each step of the manufacturing process of the semiconductor device according to the second embodiment after the process of forming a buried insulating film;

FIG. 5 is a cross-sectional view showing each step of the manufacturing process of the semiconductor device according to the third embodiment after the process of forming a buried insulating film;

FIG. 6 is a cross-sectional view illustrating a structure of a semiconductor device according to fourth and fifth embodiments.

FIG. 7 is a cross-sectional view showing each step of a manufacturing process of a semiconductor device according to a fourth embodiment up to a process of forming a trench for element isolation;

FIG. 8 is a cross-sectional view showing each step of the manufacturing process of the semiconductor device according to the fourth embodiment after the process of forming a buried insulating film.

FIG. 9 is a plan view of a semiconductor device according to each embodiment.

FIG. 10 is a cross-sectional view showing each step of the manufacturing process of the semiconductor device according to the fifth embodiment after the process of forming a buried insulating film.

FIG. 11 is a cross-sectional view showing each step of the manufacturing process of the semiconductor device according to the sixth embodiment after the process of forming a buried insulating film.

FIG. 12 is a cross-sectional view showing each step of the manufacturing process of the semiconductor device according to the seventh embodiment up to the step of flattening;

FIG. 13 is a cross-sectional view showing each step of the manufacturing steps of the semiconductor device according to the eighth embodiment up to the step of flattening;

FIG. 14 is a cross-sectional view showing each step of the manufacturing steps of the semiconductor device according to the ninth embodiment up to the step of flattening;

FIG. 15 is a cross-sectional view showing each step of the manufacturing steps of the semiconductor device according to the tenth embodiment up to the step of flattening;

FIG. 16 is a cross-sectional view showing each step of the manufacturing steps of the semiconductor device according to the eleventh embodiment up to the step of flattening;

FIG. 17 is a cross-sectional view illustrating a structure of a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 10 semiconductor substrate 11 single crystal silicon film (single crystal semiconductor film) 21 pad oxide film 22 silicon nitride film 23 pad oxide film 24 silicon nitride film, 25 to 28 silicon oxide film 31 tunnel oxide film 32 polycrystalline silicon film 33 gate oxide film Reference Signs List 34 polycrystalline silicon film 35 silicon oxide film 36 polycrystalline silicon film 37 gate oxide film 51 to 58 resist film, 101 element isolation groove 102 buried insulating film 103 field oxide film 111 control gate electrode 112 floating gate electrode 113 gate electrode 121 interlayer Insulating film 122 Connection hole 123 Metal wiring

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/788 29/792 (72) Inventor Takaaki Ueda 1006 Odakadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Masatoshi Arai 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Masaru Moriwaki 1006 Odaka Kadoma Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (48)

[Claims] A semiconductor substrate having a memory cell region and a peripheral circuit region; and a groove type formed surrounding the first and second active regions in the memory cell region and the peripheral circuit region of the semiconductor substrate, respectively. Device isolation; and disposing in the memory cell region, at least the first
Tunnel insulating film on the semiconductor substrate in the active region of
A non-volatile memory cell in which a floating gate electrode, a gate insulating film and a control gate electrode are sequentially provided; A field-effect transistor that is sequentially provided, and a height position of an upper surface of the semiconductor substrate in the second active region is higher than a height position of an upper surface of the semiconductor substrate in the first active region; A semiconductor device having a height substantially equal to the height of the upper surface of the floating gate electrode. 2. The semiconductor device according to claim 1, wherein the height position of the upper surface of the element isolation is the height of the upper surface of the semiconductor substrate and the upper surface of the floating gate electrode in the second active region of the peripheral circuit region. A semiconductor device characterized by being substantially at the same position. 3. The semiconductor device according to claim 2, wherein the floating gate electrode of the nonvolatile memory cell is sandwiched between the element isolations in a vertical cross section orthogonal to the gate length direction and self-aligned with the element isolations. A semiconductor device. 4. The semiconductor device according to claim 1, wherein a control gate electrode of said nonvolatile memory cell is formed from said floating gate electrode to a semiconductor substrate. Characteristic semiconductor device. 5. The semiconductor device according to claim 1, wherein the control gate electrode and the gate electrode are a polycrystalline silicon film, an amorphous silicon film, a metal film, and a polycrystalline silicon film. And a metal film or a metal compound film, a stacked film of an amorphous silicon film and a metal film or a metal compound film, a stacked film of a metal film and a metal film, a metal film, a metal film, and a polycrystalline silicon film. Wherein the semiconductor device is formed of any one of a stacked film of a metal film, a metal film, and an amorphous silicon film. 6. The semiconductor device according to claim 1, wherein the control gate electrode of the nonvolatile memory cell and the gate electrode of the field-effect transistor are formed of a common upper-layer conductor film and a lower-layer conductor film. The lower conductive film in the second active region of the peripheral circuit region is self-aligned with the element isolation between the element isolations in a cross section orthogonal to the gate length direction of the field effect transistor; A semiconductor device, wherein a height position of an upper surface of the element isolation is substantially the same as a height position of an upper surface of the lower conductive film. 7. The semiconductor device according to claim 1, wherein a gate electrode of the field-effect transistor comprises an upper-layer conductor film and a lower-layer conductor film, and the control gate electrode of the nonvolatile memory cell is The lower conductive film in the second active region of the peripheral circuit region is formed of only the upper conductive film and is formed over the floating gate electrode and the semiconductor substrate. A semiconductor device characterized by being self-aligned with an element isolation sandwiched between the element isolations in a cross section orthogonal to a direction. 8. The semiconductor device according to claim 6, wherein the lower conductive film is a polycrystalline silicon film, an amorphous silicon film, a metal film, a polycrystalline silicon film and a metal film or a metal compound film. Laminated film, laminated film of amorphous silicon film and metal film or metal compound film, laminated film of metal film and metal film, laminated film of metal film, metal film and polycrystalline silicon film, metal film and metal film A semiconductor device comprising any one of a stacked film of a silicon film and an amorphous silicon film. 9. The semiconductor device according to claim 1, wherein a thickness of a gate insulating film of the nonvolatile memory cell is larger than a thickness of a gate insulating film of the field-effect transistor. A semiconductor device characterized by the above-mentioned. 10. The semiconductor device according to claim 1, wherein a region near a surface of the semiconductor substrate in the peripheral circuit region is constituted by a semiconductor crystal film formed by epitaxial growth. A semiconductor device. 11. A first memory cell region on a semiconductor substrate.
Forming a nonvolatile memory cell having a tunnel insulating film, a floating gate electrode, a gate insulating film and a control gate electrode on the active region of the semiconductor substrate,
A method of manufacturing a semiconductor device for forming a field effect transistor having a gate insulating film and a gate electrode on an active region of the semiconductor device. A first step of forming a height difference between the upper surfaces of the semiconductor substrate so as to be lower than a height position of the upper surface of the semiconductor substrate; A second conductive film is sequentially formed, and the height position of the upper surface of the first conductive film is substantially the same as the height position of the upper surface of the semiconductor substrate in the peripheral circuit region.
And a third step of forming device isolation trenches surrounding the first and second active regions in the semiconductor substrate in the memory cell region and the peripheral circuit region, respectively. And a fourth step of forming a groove-type element isolation. 12. The method of manufacturing a semiconductor device according to claim 11, wherein after the fourth step, a gate insulating film insulating film, a second conductor film, and a conductor protection film are sequentially formed on the substrate. The conductive protective film and the second conductive film are selectively removed by etching using a mask member covering the control gate electrode formation region and the gate electrode formation region, and the first active region is Forming a control gate electrode and an electrode protection film thereon, and forming a gate electrode in the second active region; and removing the mask member and then covering the peripheral circuit region with the mask member and the electrode protection film. Forming a floating gate electrode in the first active region by selectively removing the insulating film for a gate insulating film and the first conductor film by etching using the above as a mask. The method of manufacturing a semiconductor device according to claim Rukoto. 13. The method of manufacturing a semiconductor device according to claim 11, wherein after the fourth step, a step of sequentially forming an insulating film for a gate insulating film and a second conductor film on a substrate; Forming a gate electrode in the second active region by selectively removing the second conductive film by etching using a mask member covering the region and the gate electrode formation region; After the removal, the second conductive film, the insulating film for the gate insulating film, and the first conductive film are selectively sequentially etched by using a mask member covering the peripheral circuit region and the control gate electrode formation region. Forming a control gate electrode and a floating gate electrode in the first active region. 14. The method for manufacturing a semiconductor device according to claim 11, wherein, after the fourth step, the first step is performed by etching using a mask member covering the peripheral circuit region and the floating gate electrode formation region. Forming a floating gate electrode in the first active region by selectively removing the conductive film; and, after removing the mask member, forming an insulating film for a gate insulating film and a second conductive film on the substrate. Selecting the first conductive film, the insulating film for the gate insulating film, and the second conductive film by sequentially forming and etching using a mask member covering the control gate electrode forming region and the gate electrode forming region; And a control gate electrode extending from the floating gate electrode to the semiconductor substrate is provided in the first active region.
Forming a gate electrode in each of the active regions. 15. The method of manufacturing a semiconductor device according to claim 11, wherein the insulating film for a gate insulating film is formed in the memory cell region of the insulating film for a gate insulating film. A method for manufacturing a semiconductor device, wherein the thickness is set to be larger than the thickness in the peripheral circuit region. 16. The method of manufacturing a semiconductor device according to claim 11, wherein the first step includes: sequentially forming a silicon oxide film and a silicon nitride film on a substrate; Selectively removing the silicon nitride film in the memory cell region; performing thermal oxidation using the silicon nitride film as a mask;
A method of manufacturing a semiconductor device, comprising: forming a film; and removing the silicon nitride film and the LOCOS film. 17. The method of manufacturing a semiconductor device according to claim 11, wherein the first step is performed by etching using a mask member having an opening on the memory cell region. A method of manufacturing a semiconductor device, comprising a step of partially removing a semiconductor substrate in the memory cell region to a certain depth. 18. The method for manufacturing a semiconductor device according to claim 11, wherein the first step includes: forming an insulating film on a substrate; Selectively removing a portion on the peripheral circuit region; and epitaxially growing a semiconductor crystal film on the surface of the semiconductor substrate exposed in the peripheral circuit region using the remaining portion of the insulating film as a mask. And a step of removing a remaining portion of the insulating film. 19. The method of manufacturing a semiconductor device according to claim 11, wherein the second step includes sequentially forming a tunnel insulating film and a first conductive film on the substrate. A step of removing the first conductive film by CMP until at least the tunnel insulating film in the peripheral circuit region is exposed; and a step of etching the tunnel insulating film in the peripheral circuit region by etching. A method for manufacturing a semiconductor device, comprising: 20. The method of manufacturing a semiconductor device according to claim 11, wherein in the second step, a tunnel insulating film and a first conductor film are sequentially formed on a substrate. And a step of selectively removing the first conductive film and the tunnel insulating film in the peripheral circuit region sequentially by etching using a mask member covering the memory cell region. Device manufacturing method. 21. The method of manufacturing a semiconductor device according to claim 11, wherein in the second step, a tunnel insulating film and a first conductor film are sequentially formed on a substrate. Selectively etching the first conductor film and the tunnel insulating film sequentially by etching using a mask member that covers at least a region near a boundary between the memory cell region and the memory cell region in the peripheral circuit region. And removing a portion of the first conductive film remaining in the peripheral circuit region near a boundary with the memory cell region in the peripheral circuit region after removing the mask member.
And a step of removing the tunnel insulating film in the peripheral circuit region by etching. 22. A first memory cell region of a semiconductor substrate.
Forming a nonvolatile memory cell having a tunnel insulating film, a floating gate electrode, a gate insulating film and a control gate electrode on the active region of the semiconductor substrate,
A method of manufacturing a semiconductor device for forming a field effect transistor having a gate insulating film and a gate electrode on an active region of the semiconductor device, wherein the semiconductor substrate in the peripheral circuit region is exposed, A first step of forming a tunnel insulating film, a first conductor film on the tunnel insulating film, and a conductor protection film on the first conductor film in a region, and the semiconductor substrate in the peripheral circuit region. Forming a semiconductor crystal film having a height position on the upper surface substantially equal to a height position on the upper surface of the first conductor film in the memory cell region; A third step of removing the first conductor protection film on the first conductor film, and a device isolation for surrounding the first and second active regions in the memory cell region and the peripheral circuit region. Form a groove A method of manufacturing a semiconductor device, comprising: a fourth step; and a fifth step of forming a trench-type element isolation by filling the trench with an insulating film. 23. The method of manufacturing a semiconductor device according to claim 22, wherein the first step includes: sequentially forming a tunnel insulating film, a first conductor film, and a conductor protection film on the semiconductor substrate. A step of sequentially removing the conductor protective film, the first conductor film and the tunnel insulating film in the peripheral circuit region by etching using a mask member covering the memory cell region. Manufacturing method. 24. The method of manufacturing a semiconductor device according to claim 22, wherein the first step is a step of sequentially forming a tunnel insulating film and a first conductor film on the semiconductor substrate; Removing the first conductor film and the tunnel insulating film in the peripheral circuit region by etching using a mask member covering the region; and, after removing the mask member, removing the first conductive film and the tunnel insulating film in the memory cell region. Forming a first conductor protection film on the conductor film and the semiconductor substrate in the peripheral circuit region so that the first conductor protection film is thicker on the first conductor film than on the semiconductor substrate; Removing the first conductor protection film in the peripheral circuit region under the condition that the first conductor protection film on the first conductor film in the memory cell region remains. The method of manufacturing a semiconductor device according to claim and. 25. The method of manufacturing a semiconductor device according to claim 22, wherein the first step includes sequentially forming a tunnel insulating film, a first conductor film, and a first conductor protection film on the semiconductor substrate. Removing the first conductor protective film, the first conductor film, and the tunnel insulating film in the peripheral circuit region by etching using a mask member covering the memory cell region; Forming a second conductor protection film on the substrate after the removal, and etching back the first conductor film under the condition that the first conductor protection film on the first conductor film remains. Removing the second conductor protection film while leaving the second conductor protection film on the side surface of the semiconductor device. 26. The method of manufacturing a semiconductor device according to claim 22, wherein after the fifth step, an insulating film for a gate insulating film and a second conductive film are formed on the substrate. And a step of forming a protective film, and selectively removing the protective film and the second conductor film by etching using a mask member covering the control gate electrode formation region and the gate electrode formation region. A step of forming a control gate electrode and an electrode protective film thereon on the first active region, a step of forming a gate electrode on the second active region, and a mask covering the peripheral circuit region after removing the mask member Forming a floating gate electrode in the first active region by selectively removing the insulating film for the gate insulating film and the first conductive film by etching using the member and the electrode protective film as a mask; When Method of manufacturing a semiconductor device characterized in that it comprises further. 27. The method of manufacturing a semiconductor device according to claim 22, wherein after the fifth step, an insulating film for a gate insulating film and a second conductive film are formed on the substrate. Forming a gate electrode in the second active region by selectively removing the second conductive film by sequentially forming and etching using a mask member covering the memory cell region and the gate electrode formation region; Forming, after removing the mask member, etching using a mask member covering the peripheral circuit region and the control gate electrode formation region to form the second conductor film, the gate insulating film insulating film and the gate insulating film insulating film. Forming a control gate electrode and a floating gate electrode in the first active region by sequentially and selectively removing the first conductor film. 28. The method of manufacturing a semiconductor device according to claim 22, wherein after the fifth step, a mask member covering the peripheral circuit region and the floating gate electrode formation region is formed. Forming the floating gate electrode in the first active region by selectively removing the first conductive film by the used etching; and removing the mask member and then forming a gate insulating film on the substrate. A step of sequentially forming an insulating film and a second conductive film; and etching using a mask member covering the control gate electrode forming region and the gate electrode forming region, thereby forming the first conductive film and the insulating film for the gate insulating film. And the second conductive film is selectively removed, and the first memory film is provided in the memory cell region.
Forming a control gate electrode extending from the floating gate electrode to the semiconductor substrate in the active region and a gate electrode in the peripheral circuit region. 29. The method of manufacturing a semiconductor device according to claim 22, wherein the formation of the insulating film for a gate insulating film is performed in the memory cell region of the insulating film for a gate insulating film. A method for manufacturing a semiconductor device, wherein the thickness is set to be larger than the thickness in the peripheral circuit region. 30. A nonvolatile memory cell having a tunnel insulating film, a floating gate electrode, a gate insulating film, and a control gate electrode formed on at least a first active region of a memory cell region of a semiconductor substrate, and around a semiconductor substrate. A method for manufacturing a semiconductor device for forming a field effect transistor having a gate insulating film and a gate electrode on at least a second active region of a circuit region, comprising: a height position of an upper surface of a semiconductor substrate in the memory cell region Forming a height difference between the upper surface of the semiconductor substrate and the upper surface of the semiconductor substrate in the peripheral circuit region. A tunnel insulating film and a first conductor film are sequentially formed, and a height position of an upper surface of the first conductor film is set to a half in the peripheral circuit region. The to be substantially the same as the height position of the upper surface of the body substrate 2
Forming a device isolation groove surrounding the first and second active regions in the semiconductor substrate in the memory cell region and the peripheral circuit region; and forming a gate insulating film on the substrate. A semiconductor device comprising: a fourth step of forming an insulating film and a second conductor film; and a fifth step of forming the groove-type element isolation by filling the groove with an insulating film. Production method. 31. The method of manufacturing a semiconductor device according to claim 30, wherein after the fifth step, a step of sequentially forming a third conductor film and a conductor protection film on the substrate; The conductor protective film, the third conductor film, and the second conductor film are selectively removed by etching using a mask member that covers the gate electrode formation region and the first active region. A step of forming a control gate electrode and an electrode protection film thereon, and a step of forming a gate electrode in the second active region; and, after removing the mask member, a mask member and the electrode protection film covering the peripheral circuit region. Forming a floating gate electrode in the first active region by sequentially and selectively removing the insulating film for the gate insulating film and the first conductor film by etching using a mask as a mask. The method of manufacturing a semiconductor device according to claim. 32. The method of manufacturing a semiconductor device according to claim 30, wherein, after the fifth step, a step of forming a third conductor film on a substrate; and the step of forming the memory cell region and the gate electrode formation region. Forming a gate electrode in the second active region by selectively removing the third conductor film and the second conductor film by etching using a mask member to cover; and after removing the mask member, The third conductor film, the second conductor film, the insulation film for the gate insulation film, and the first conductor film by etching using a mask member covering the peripheral circuit region and the control gate electrode formation region. And selectively forming the control gate electrode and the floating gate electrode in the first active region by sequentially and selectively removing the control gate electrode and the floating gate electrode, respectively. 33. The method for manufacturing a semiconductor device according to claim 30, wherein after the fifth step, a step of removing the second conductor film and the insulating film for a gate insulating film in the memory cell region; Forming a floating gate electrode in the first active region by selectively removing the first conductive film by etching using a mask member covering the peripheral circuit region and the floating gate electrode formation region; After removing the mask member, an insulating film for a second gate insulating film is selectively formed on the floating gate electrode in the first active region, and a third conductive film is formed on the substrate. A step of selectively removing the second and third conductive films by etching using a mask member covering the control gate electrode formation region and the gate electrode formation region, and floating the first active region. The gate electrode A control gate electrode extending over the semiconductor substrate, a method of manufacturing a semiconductor device in the second active region, characterized by further comprising a step of forming a gate electrode, respectively. 34. The method of manufacturing a semiconductor device according to claim 30, wherein forming the insulating film for a gate insulating film comprises setting the thickness of the insulating film for a gate insulating film in the memory cell region to the peripheral circuit. A method for manufacturing a semiconductor device, wherein the method is performed so that the thickness is larger than a thickness in a region. 35. The method of manufacturing a semiconductor device according to claim 30, wherein the first step includes: sequentially forming a silicon oxide film and a silicon nitride film on a substrate; Selectively removing the silicon nitride film in the memory cell region; performing thermal oxidation using the silicon nitride film as a mask;
A method of manufacturing a semiconductor device, comprising: forming a film; and removing the silicon nitride film and the LOCOS film. 36. The method of manufacturing a semiconductor device according to claim 30, wherein the first step is performed by etching using a mask member having an opening on the memory cell region. A method of manufacturing a semiconductor device, comprising a step of partially removing a semiconductor substrate in the memory cell region to a certain depth. 37. The method of manufacturing a semiconductor device according to claim 30, wherein the first step comprises: forming an insulating film on a substrate; Selectively removing a portion on the peripheral circuit region; and epitaxially growing a semiconductor crystal film on the surface of the semiconductor substrate exposed in the peripheral circuit region using the remaining portion of the insulating film as a mask. And a step of removing a remaining portion of the insulating film. 38. The method of manufacturing a semiconductor device according to claim 30, wherein in the second step, a tunnel insulating film and a first conductor film are sequentially formed on a substrate. A step of removing the first conductive film by CMP until at least the tunnel insulating film in the peripheral circuit region is exposed; and a step of etching the tunnel insulating film in the peripheral circuit region by etching. A method for manufacturing a semiconductor device, comprising: 39. The method of manufacturing a semiconductor device according to claim 30, wherein in the second step, a tunnel insulating film and a first conductor film are sequentially formed on a substrate. And a step of selectively removing the first conductive film and the tunnel insulating film in the peripheral circuit region sequentially by etching using a mask member covering the memory cell region. Device manufacturing method. 40. The method of manufacturing a semiconductor device according to claim 30, wherein in the second step, a tunnel insulating film and a first conductor film are sequentially formed on a substrate. Selectively etching the first conductor film and the tunnel insulating film sequentially by etching using a mask member that covers at least a region near a boundary between the memory cell region and the memory cell region in the peripheral circuit region. And removing a portion of the first conductive film remaining in the peripheral circuit region near a boundary with the memory cell region in the peripheral circuit region after removing the mask member.
And a step of removing the tunnel insulating film in the peripheral circuit region by etching. 41. A first memory cell region of a semiconductor substrate
Forming a nonvolatile memory cell having a tunnel insulating film, a floating gate electrode, a gate insulating film and a control gate electrode on the active region of the semiconductor substrate,
A method of manufacturing a semiconductor device for forming a field effect transistor having a gate insulating film and a gate electrode on an active region of the semiconductor device, wherein the memory cell is exposed while the semiconductor substrate in the peripheral circuit region is exposed. A first step of forming a tunnel insulating film, a first conductor film on the tunnel insulating film, and a conductor protection film on the first conductor film in a region, and the semiconductor substrate in the peripheral circuit region. Forming a semiconductor crystal film in which a semiconductor crystal is grown on the substrate and the height position of the upper surface is substantially the same as the height position of the upper surface of the first conductive film in the memory cell region. A third step of removing the first conductor protective film on the first conductor film, a fourth step of forming an insulating film for a gate insulating film and a second conductor film on a substrate, The memory cell area and the memory cell area A fifth step of forming a groove for element isolation surrounding the first and second active regions in the side circuit region; and a sixth step of forming the groove-type element isolation by filling the groove with an insulating film. A method for manufacturing a semiconductor device, comprising: 42. The method of manufacturing a semiconductor device according to claim 41, wherein the first step includes: sequentially forming a tunnel insulating film, a first conductor film, and a conductor protection film on the semiconductor substrate. A step of sequentially removing the conductor protective film, the first conductor film and the tunnel insulating film in the peripheral circuit region by etching using a mask member covering the memory cell region. Manufacturing method. 43. The method for manufacturing a semiconductor device according to claim 42, wherein said first step is a step of sequentially forming a tunnel insulating film and a first conductor film on said semiconductor substrate; Removing the first conductor film and the tunnel insulating film in the peripheral circuit region by etching using a mask member covering the region; and, after removing the mask member, removing the first conductive film and the tunnel insulating film in the memory cell region. Forming a first conductor protection film on the conductor film and the semiconductor substrate in the peripheral circuit region so that the first conductor protection film is thicker on the first conductor film than on the semiconductor substrate; Removing the first conductor protection film in the peripheral circuit region under the condition that the first conductor protection film on the first conductor film in the memory cell region remains. The method of manufacturing a semiconductor device according to claim and. 44. The method of manufacturing a semiconductor device according to claim 41, wherein in the first step, a tunnel insulating film, a first conductor film, and a first conductor protection film are sequentially formed on the semiconductor substrate. Removing the first conductor protective film, the first conductor film, and the tunnel insulating film in the peripheral circuit region by etching using a mask member covering the memory cell region; Forming a second conductor protection film on the substrate after the removal, and etching back the first conductor film under the condition that the first conductor protection film on the first conductor film remains. Removing the second conductor protection film while leaving the second conductor protection film on the side surface of the semiconductor device. 45. The method of manufacturing a semiconductor device according to claim 41, wherein after the sixth step, a step of sequentially forming a third conductor film and a conductor protection film on the substrate; The conductor protective film, the third conductor film, and the second conductor film are selectively removed by etching using a mask member that covers the gate electrode formation region and the first active region. A step of forming a control gate electrode and an electrode protection film thereon, and a step of forming a gate electrode in the second active region; and, after removing the mask member, a mask member and the electrode protection film covering the peripheral circuit region. Forming a floating gate electrode in the first active region by sequentially and selectively removing the insulating film for the gate insulating film and the first conductor film by etching using the mask as a mask. The method of manufacturing a semiconductor device according to claim. 46. The method of manufacturing a semiconductor device according to claim 41, wherein after the sixth step, a step of forming a third conductor film on a substrate; and the step of forming the memory cell region and the gate electrode formation region. Forming a gate electrode in the second active region by selectively removing the third conductor film and the second conductor film by etching using a mask member to cover; and after removing the mask member, The third conductor film, the second conductor film, the insulation film for the gate insulation film, and the first conductor film by etching using a mask member covering the peripheral circuit region and the control gate electrode formation region. And selectively forming the control gate electrode and the floating gate electrode in the first active region by sequentially and selectively removing the control gate electrode and the floating gate electrode, respectively. 47. The method of manufacturing a semiconductor device according to claim 41, wherein, after the sixth step, a step of removing the second conductor film and the insulating film for a gate insulating film in the memory cell region; Forming a floating gate electrode in the first active region by selectively removing the first conductive film by etching using a mask member covering the peripheral circuit region and the floating gate electrode formation region; After removing the mask member, an insulating film for a second gate insulating film is selectively formed on the floating gate electrode in the first active region, and a third conductive film is formed on the substrate. A step of selectively removing the second and third conductive films by etching using a mask member covering the control gate electrode formation region and the gate electrode formation region, and floating the first active region. The gate electrode A control gate electrode extending over the semiconductor substrate, a method of manufacturing a semiconductor device in the second active region, characterized by further comprising a step of forming a gate electrode, respectively. 48. The method according to claim 41,42,43,44,45.
49. The semiconductor device according to 47, wherein the formation of the insulating film for a gate insulating film is performed such that the thickness of the insulating film for the gate insulating film in the memory cell region is larger than the thickness in the peripheral circuit region. Manufacturing method of a semiconductor device.