JP2002202893A5 - - Google Patents

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Publication number
JP2002202893A5
JP2002202893A5 JP2001325363A JP2001325363A JP2002202893A5 JP 2002202893 A5 JP2002202893 A5 JP 2002202893A5 JP 2001325363 A JP2001325363 A JP 2001325363A JP 2001325363 A JP2001325363 A JP 2001325363A JP 2002202893 A5 JP2002202893 A5 JP 2002202893A5
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Japan
Prior art keywords
processing
circuit
processing circuit
determining
temperature
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JP2001325363A
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JP2002202893A (ja
JP4039843B2 (ja
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Priority claimed from EP00402948A external-priority patent/EP1182538B1/en
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Publication of JP2002202893A publication Critical patent/JP2002202893A/ja
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Claims (8)

  1. 幾つかのモジュールを含む処理回路に於ける多重タスクの実行を制御する方法に於て、
    前記処理回路の種々の区域に於ける温度関連情報を決定し、
    前記いくつかの処理モジュールのうちの第1の処理モジュールに関連した領域における過剰温度を示す温度関連情報に応答して、1又は2以上の近接処理モジュールのタスクを実行するパラメータを変更してその近接処理モジュールから発生される熱を減少して前記第1の処理モジュールの過剰温度に対応させる、
    工程を含む方法。
  2. 請求項1記載の方法に於て、前記決定する工程が、前記モジュールによって実行される動作を監視する工程を含む方法。
  3. 請求項1記載の方法に於て、前記決定する工程が、前記処理回路内の種々の場所に於ける電力散逸情報を計算する工程を含む方法。
  4. 請求項1記載の方法に於て、前記決定する工程が、前記処理回路内の種々の場所に於ける現在の温度を計算する工程を含む方法。
  5. 多重タスクを実行する複数個の処理モジュールを含む処理回路に於て、
    前記処理回路の種々の区域に於ける温度に関連する情報を決定する回路と、
    前記いくつかの処理モジュールのうちの第1の処理モジュールに関連した領域における過剰温度を示す温度関連情報に応答して、1又は2以上の近接処理モジュールのタスクを実行するパラメータを変更してその近接処理モジュールから発生される熱を減少して前記第1の処理モジュールの過剰温度に対応させる回路と
    を含む処理回路。
  6. 請求項5記載の処理回路に於て、前記決定する回路が、前記処理モジュールによって実行される動作を監視する回路を含む処理回路。
  7. 請求項5記載の処理回路に於て、前記決定する回路が、前記処理回路内の種々の場所に於ける電力散逸情報を計算する回路を含む処理回路。
  8. 請求項5記載の処理回路に於て、前記決定する回路が、前記処理回路内の種々の場所に於ける現在の温度を計算する回路を含む処理回路。
JP2001325363A 2000-10-24 2001-10-23 多重タスクの実行を制御する方法と処理回路 Expired - Lifetime JP4039843B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP00402948A EP1182538B1 (en) 2000-08-21 2000-10-24 Temperature field controlled scheduling for processing systems
EP00402948.4 2000-10-24

Publications (3)

Publication Number Publication Date
JP2002202893A JP2002202893A (ja) 2002-07-19
JP2002202893A5 true JP2002202893A5 (ja) 2005-07-07
JP4039843B2 JP4039843B2 (ja) 2008-01-30

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JP2001325363A Expired - Lifetime JP4039843B2 (ja) 2000-10-24 2001-10-23 多重タスクの実行を制御する方法と処理回路

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US (1) US7174194B2 (ja)
JP (1) JP4039843B2 (ja)

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