JP2002202734A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure of a semiconductor device and a manufacturing method therefor for realizing low power consumption and improvement in a yield and reliability, even if the screen is made into a large image surface. SOLUTION: A plating treatment electrode 805 provided with source wiring 802 and terminal parts 808, 809 is formed on a substrate. By using this plating treatment electrode 805, the source wiring 802 and the terminal parts 808, 809 are plated with Cu by plating treatment. Thus, an increase in wiring resistance due to upsizing of the screen is suppressed, and power consumption can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor circuit composed of thin film transistors (hereinafter, referred to as TFTs) and a method of manufacturing the same, and particularly to an electro-optical device represented by a liquid crystal display panel and the electro-optical device. This is a technology related to an electronic device in which is mounted as a component.

[0002] In this specification, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics, and an electro-optical device (hereinafter, referred to as a display device), a semiconductor circuit, and an electronic device are all semiconductor devices. It is.

[0003]

2. Description of the Related Art In recent years, a semiconductor thin film (having a thickness of several hundreds to several thousands nm) formed on a substrate having an insulating surface has been used for T
Techniques for making FTs have been developed. A TFT is widely applied to a semiconductor device such as an integrated circuit (IC) or an electro-optical device, and has been rapidly developed as a switching element particularly for a display device.

[0004] Active matrix type liquid crystal display devices are often used for semiconductor devices because high definition images can be obtained as compared with passive type liquid crystal display devices. The active matrix liquid crystal display device includes a gate wiring, a source wiring, a TFT in a pixel portion provided at an intersection of the gate line and the source line, and a TF in the pixel portion.
And a pixel electrode connected to T. The gate wiring of the conventional active matrix liquid crystal display device is Ti / Al
/ Ti has a three-layer structure, and the source wiring of the conventional active matrix liquid crystal display has a two-layer structure of TaN / W. The source wiring material TaN /
W is a metal material that can withstand heat treatment, and has a slightly higher wiring resistance than Al or the like.

[0005] The conventional active matrix liquid crystal display device having such a structure has been expanding its use as a display device of a monitor, a television and a portable terminal, and has been mass-produced. Furthermore, demands for a larger screen size, higher definition, higher aperture ratio, and higher reliability are increasing.

[0006]

If the conventional semiconductor device has a screen size of about 5 inches, the wiring resistance of the semiconductor display device does not matter. However, as the screen size increases, the length of the gate wiring and source wiring increases,
In particular, the problem that the wiring resistance of the source wiring made of a TaN / W metal material is increased has occurred, causing an increase in power consumption. Therefore, there is a means of selecting Al as a wiring material, but heat treatment causes formation of projections such as hillocks and whiskers, and diffusion of Al atoms into a channel formation region, thereby causing TFT malfunction and deterioration of TFT characteristics. This leads to display defects such as line defects and point defects in panel display of a semiconductor device, leading to a reduction in yield and reliability.

It is an object of the present invention to provide a structure of a semiconductor device and a method for manufacturing the same, which realize low power consumption, high yield, and improved reliability even when the screen is enlarged.

[0008]

SUMMARY OF THE INVENTION The present invention relates to a low-resistance material (typically Cu, Ag, Au, Cr, Fe, Ni,
A semiconductor device having a source wiring plated with Pt or an alloy thereof, a TFT of an inverted staggered pixel portion, a storage capacitor, and a terminal portion is to be manufactured. still,
When the screen size is increased, only the pixel portion has a larger shape when the screen size is increased. Therefore, it is not necessary to plate a metal coating on portions other than the pixel portion. That is, it is sufficient that the metal film is plated only on the source wiring of the pixel portion.

A method for plating a metal film only on the source wiring will be described with reference to FIG. A wiring pattern to which a plating electrode 805 which is an electrode for plating is attached is formed on a substrate. In this wiring pattern, a terminal portion 808 connected to the gate wiring side driving circuit and a terminal portion 809 connected to the source wiring side driving circuit are formed.
Further, as the wiring pattern, a pattern serving as a source wiring is formed as shown in FIG. Since the metal film is plated only on the source wiring of the pixel portion, the pattern serving as the source wiring is not connected to the terminal portion connected to the source wiring driving circuit.

By plating using this wiring pattern, a metal film can be plated only on the source wiring in the pixel portion. Therefore, a semiconductor device which can achieve low power consumption even when the screen size is increased can be manufactured.

[0011]

[First Embodiment] A transmission type semiconductor device embodying the present invention will be described below.

First, a conductive film is formed on the entire surface of a substrate, and a conductive film is formed in a desired shape by a first photolithography step.

Next, a current suitable for plating is applied from the plating electrode 805 connected to the source wiring, and a metal film is plated on the source wiring. At this time, since the conductive film is formed in the shape as shown in FIG. 8, the metal film can be plated only on the source wiring by attaching the electrode to the substrate.

Incidentally, the metal coating in this specification is C
u, Ag, Au, Cr, Fe, Ni, Pt, or alloys thereof.

Further, in each of the above-mentioned manufacturing methods, in the plating step, the source wirings of the pixel portion are connected by wirings so as to have the same potential. Further, the wiring connected to have the same potential may be separated by a laser beam (a CO ₂ laser or the like) after the plating process, or may be separated simultaneously with the substrate after the plating process. Further, a short ring may be formed with these wiring patterns.

Next, an insulating film is formed on the entire surface. A first amorphous semiconductor film on the insulating film and one conductivity type (n-type or p-type)
The second amorphous semiconductor film containing the impurity element is stacked. Unnecessary portions of these laminated films are removed by etching in a second photolithography step, so that source wiring,
A gate electrode and a storage capacitor are formed in desired shapes.

Next, after removing the resist mask in the second photolithography step, a second amorphous semiconductor containing one conductivity type (n-type or p-type) impurity element is formed in a third photolithography step. A part of the film is removed to form a source region and a drain region of the gate electrode.

Next, after removing the resist mask in the third photolithography step, a first interlayer insulating film is formed so as to cover the source wiring, the TFT in the pixel portion, the storage capacitor, and the terminal portion.

Next, a second interlayer insulating film, which is an organic insulating material made of acrylic resin, is formed on the first interlayer insulating film. After that, a fourth photolithography process is performed,
After forming a resist mask, a contact hole is formed by a dry etching process. Here, a contact hole which reaches a second amorphous semiconductor film containing an impurity element of one conductivity type (n-type or p-type) of the gate electrode and one impurity (n-type or p-type) of a storage capacitor are provided. A contact hole reaching the second amorphous semiconductor film containing the element and a contact hole reaching the source wiring are formed. At the same time, the extra first interlayer insulating film and second interlayer insulating film in the terminal portion are etched to form the terminal portion.

Next, in a fifth photolithography step, the storage capacitor is electrically connected to the second amorphous semiconductor film (drain region) containing one conductivity type (n-type or p-type) impurity element. To form a transparent pixel electrode.

Next, a metal wiring made of a low-resistance metal material is formed, and a gate wiring, a source wiring and a second conductive element (n-type or p-type) containing an impurity element of one conductivity type (n-type or p-type) are formed by a sixth photolithography step. An electrode connecting to the amorphous semiconductor film and a metal wiring electrically connecting to the terminal portion are formed. In the present invention, the gate wiring is electrically connected to the first gate electrode or the second gate electrode through a contact hole provided in the interlayer insulating film. The source wiring is a second amorphous semiconductor film (source region) containing an impurity element of one conductivity type (n-type or p-type) with the source wiring through a contact hole provided in the interlayer insulating film.
Is electrically connected to The pixel electrode is electrically connected to a second amorphous semiconductor film (drain region) containing one conductivity type (n-type or p-type) impurity element through a contact hole provided in the interlayer insulating film. ing.

The source wiring plated with the metal film by the photolithography process six times in total,
A transmissive semiconductor display device including a TFT in an inverted staggered pixel portion, a storage capacitor, and a terminal portion can be manufactured.

[Embodiment 2] A transmission type semiconductor device embodying the present invention will be described below.

The reflection type semiconductor device can be manufactured in the same steps up to the fourth photolithography step for manufacturing a transmission type semiconductor device. An electrode for connecting a gate wiring and a source wiring to a second amorphous semiconductor film (source region) containing an impurity element of one conductivity type (n-type or p-type) by a fifth photolithography step; , And a metal wiring electrically connected to the terminal portion. Note that the material of the metal wiring is preferably a highly reflective metal material for constituting the pixel electrode, and typically, Al,
Alternatively, a material containing Ag as a main component is used.

In the above case, by forming the pixel electrode from the same element as the metal wiring, the pixel electrode can be formed simultaneously in the fifth photolithography step.

The source wiring plated with the metal film by the photolithography process five times in total,
A reflective semiconductor display device including a TFT in an inverted staggered pixel portion, a storage capacitor, and a terminal portion can be manufactured.

[0027]

[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS. Example 1 In this example, a method for manufacturing a liquid crystal display device will be described. A method for manufacturing a TFT in a pixel portion in an inverted staggered manner over a substrate and manufacturing a storage capacitor connected to the TFT will be described in detail according to steps. 1 to 3 show a terminal portion for electrical connection with a wiring of a circuit provided on another substrate provided at an end portion of the substrate at the same time as a manufacturing process. The cross-sectional views of FIGS.
It is a cross section of A '.

First, a semiconductor display device is manufactured using the light-transmitting substrate 100. As a substrate that can be used, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass typified by Corning # 7059 glass or # 1737 glass can be used. As another substrate, a light-transmitting substrate such as a quartz substrate or a plastic substrate can be used.

After a conductive layer is formed on the entire surface of the substrate 100, a first photolithography step is performed, a resist mask is formed, and unnecessary portions are removed by etching to form wiring and electrodes (source wiring 102, The gate electrodes 103 and 104, the storage capacitor 105, and the terminal 101) are formed. (Fig. 1 (A))

As the material of the wiring and the electrode, T
It is formed of an element selected from i, Ta, W, Mo, Cr, and Nd, an alloy containing the above element, or a nitride containing the above element. Further, Ti, Ta, W, Mo, C
A plurality of elements selected from the elements selected from r and Nd, alloys containing the above elements, or nitrides containing the above elements may be selected and stacked.

Next, the source wiring 102 and the terminal 101
Then, Cu films 106 and 110 are formed by a plating method. (FIG. 1B) If the screen size is about 5 inches in the related art, an element selected from Ti, Ta, W, Mo, Cr, and Nd, an alloy containing the above element, or a composition containing the above element Although the wiring resistance did not pose a problem even when formed with nitride, the length of each wiring increased as the screen size increased, causing a problem that the wiring resistance increased, and power consumption was reduced. Causes increase. Therefore, Cu coating 1
By plating 06 only on the source wiring, the wiring resistance can be reduced, and low power consumption can be realized. In this embodiment, Cu is used for the metal coating, but Ag, Au, Cr, Fe, Ni, Pt, or an alloy thereof can also be used.

Further, in each of the above-mentioned manufacturing methods, in the step of applying the plating, the source wirings of the pixel portion are connected by wirings so as to have the same potential. Further, the wiring connected to have the same potential may be separated by a laser beam (a CO ₂ laser or the like) after the plating process, or may be separated simultaneously with the substrate after the plating process. Further, a short ring may be formed with these wiring patterns.

Next, an insulating film 107 is formed on the entire surface. The insulating film uses a silicon nitride film and has a thickness of 50 to 200 nm.
, And is preferably formed with a thickness of 150 nm. Note that the gate insulating film is not limited to the silicon nitride film, and an insulating film such as a silicon oxide film, a silicon oxynitride film, or a tantalum oxide film can be used. (Fig. 1 (C))

Next, 50 to 200 n is formed on the insulating film 107.
A first amorphous semiconductor film 108 having a thickness of preferably 100 to 150 nm is formed over the entire surface by a known method such as a plasma CVD method or a sputtering method. Typically, an amorphous silicon (a-Si) film is formed with a thickness of 100 nm.
(Fig. 1 (C))

Next, a second amorphous semiconductor film 109 containing an impurity element of one conductivity type (n-type or p-type) is
The film is formed with a thickness of 80 nm. One conductivity type (n-type or p-type
The second amorphous semiconductor film 109 containing an impurity element imparting a mold is formed over the entire surface by a known method such as a plasma CVD method or a sputtering method. In this embodiment, the second amorphous semiconductor film 109 containing an n-type impurity element is formed using a silicon target to which phosphorus is added. (Figure 1
(C))

Next, resist masks 205 and 206 are formed by a second photolithography process, and unnecessary portions are removed by etching to form a source wiring 311. At this time, wet etching or dry etching is used. (Fig. 2 (A))

In this etching step, the resist mask 2
The portions other than 05 and 206 are the second amorphous semiconductor film 10
9 and the first amorphous semiconductor film 108 are sequentially etched, and the TFT 312 in the pixel portion is formed with the second amorphous semiconductor film 203 and the first amorphous semiconductor film 201. Further, the storage capacitor 313 is the second amorphous semiconductor film 20.
4 and a first amorphous semiconductor film 202 are formed.

Next, after removing the resist masks 205 and 206, a third photolithography step is performed to form a resist mask 207, and unnecessary portions are removed by etching to form a first amorphous semiconductor film. 208, the second amorphous semiconductor films 209, 210, 211 are formed.
(FIG. 2 (B))

Next, after removing the resist mask 207, a first interlayer insulating film 213 made of a silicon oxynitride film having a thickness of 150 nm is formed by a plasma CVD method to form a source wiring 311, a TFT 312 in a pixel portion, and a storage capacitor 313.
Is formed so as to cover. (Fig. 2 (C))

Next, a second interlayer insulating film 302 made of an organic insulating material made of an acrylic resin having a thickness of 1.6 μm is formed on the first interlayer insulating film 213 made of a silicon oxynitride film. In this embodiment, an organic insulating material made of an acrylic resin is selected for the second interlayer insulating film. However, as the organic material, polyimide or the like may be used, and further, an inorganic material may be selected. After that, a fourth photolithography process is performed,
After forming a resist mask 301, a contact hole for electrically connecting the source wiring 311 and the second amorphous semiconductor film 209 is formed by a dry etching step. At the same time, a contact hole for electrically connecting the storage capacitor 313 and the second amorphous semiconductor film 211 is formed. Further, a contact hole for electrically connecting the gate wiring and the terminal portion 310 is formed in the terminal portion. (FIG. 3 (A))

Next, ITO (Indium-Ti-Ox)
ide) or the like is formed with a thickness of 110 nm. Then, a transparent pixel electrode 309 is formed by performing a fifth photolithography step and an etching step. (FIG. 3 (B))

Next, in order to form a metal wiring, a sixth photolithography step and an etching step are performed. A metal wiring 303 is formed to electrically connect the source wiring 311 and the second amorphous semiconductor film 209. Further, a metal wiring 305 for electrically connecting the second amorphous semiconductor film 211 and the transparent pixel electrode 309 is formed. Further, a metal wiring 306 for electrically connecting the transparent pixel electrode 309 and the storage capacitor 313 is formed. Also, the gate electrode and the terminal portion 31
A metal wiring 308 for electrically connecting 0 is formed. As the metal wiring material, a laminated film of a 50 nm thick Ti film and a 500 nm thick Al-Ti alloy film can be used. (FIG. 3 (C))

In the method of fabricating the semiconductor display device shown in Embodiment 1, a metal wiring is formed after forming a transparent pixel electrode such as ITO, but a semiconductor device in which a transparent pixel electrode such as ITO is formed after forming a metal wiring. The number of photolithography steps in the entire display device is the same. Therefore, either of the metal wiring and the transparent pixel electrode such as ITO may be formed first.

By the above-described six photolithography steps, a source wiring 311 plated with Cu is formed.
TFT 312 and storage capacitor 313 of inverted stagger type pixel portion
Thus, a transmission type semiconductor display device including the terminal portions 310 can be manufactured.

The TFT having an active layer formed of the amorphous semiconductor film obtained according to the present embodiment has a small field-effect mobility of only about 1 cm ² / Vsec. For that purpose, a driving circuit for displaying an image is formed by an IC chip, and a TAB (Tape Automated Bonn).
ding) method or COG (Chip on glass)
s) It is implemented by the method.

[Embodiment 2] In Embodiment 1, it was shown that a reflection type semiconductor display device can be manufactured by six photolithography steps. However, in this embodiment, a reflection type semiconductor display device is manufactured by five photolithography steps. FIG. 4 illustrates a method for manufacturing a semiconductor display device.

In this embodiment, since the steps are the same up to the state of FIG. 3A of the first embodiment, only different steps will be described below. In addition, the same code | symbol was used for the part corresponding to FIG.

First, after obtaining the state shown in FIG. 3A according to the first embodiment, a fifth photolithography step and an etching step are performed to electrically connect the source wiring 311 and the second amorphous semiconductor film 209 to each other. A metal wiring 402 is formed for the purpose of electrical connection. At the same time, the pixel electrode 401 is formed. Further, a metal wiring 40 electrically connected to the terminal portion is provided.
5 are formed simultaneously. (FIG. 4 (B))

As described above, the source wiring 31 plated with the metal film is subjected to the photolithography process a total of five times.
1, a TFT 312 of an inverted staggered pixel portion, and a storage capacitor 3
13 and the terminal portion 310 can be manufactured.

[Embodiment 3] In Embodiments 1 and 2,
Although the plating step is performed after the first photolithography step, in the present embodiment, performing the plating step after the fourth photolithography step will be described with reference to FIGS.

First, a semiconductor display device is manufactured using the substrate 900 having a light-transmitting property. As a substrate that can be used, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass typified by Corning # 7059 glass or # 1737 glass can be used. As another substrate, a light-transmitting substrate such as a quartz substrate or a plastic substrate can be used.

After a conductive layer is formed on the entire surface of the substrate, a first photolithography step is performed, a resist mask is formed, and unnecessary portions are removed by etching to form wiring and electrodes (source wiring 902, gate Electrode 90
3, 904, a storage capacitor 905, and a terminal 901). (FIG. 9A)

As the material of the wiring and the electrode, T
It is formed of an element selected from i, Ta, W, Mo, Cr, and Nd, an alloy containing the above element, or a nitride containing the above element. Further, Ti, Ta, W, Mo, C
A plurality of elements selected from the elements selected from r and Nd, alloys containing the above elements, or nitrides containing the above elements may be selected and stacked.

Next, an insulating film 906 is formed on the entire surface. The insulating film uses a silicon nitride film and has a thickness of 50 to 200 nm.
, And is preferably formed with a thickness of 150 nm. Note that the gate insulating film is not limited to the silicon nitride film, and an insulating film such as a silicon oxide film, a silicon oxynitride film, or a tantalum oxide film can be used. (FIG. 9 (B))

Next, on the insulating film 906, 50 to 200 n
A first amorphous semiconductor film 907 having a thickness of preferably 100 to 150 nm is formed over the entire surface by a known method such as a plasma CVD method or a sputtering method. Typically, an amorphous silicon (a-Si) film is formed with a thickness of 100 nm.
(FIG. 9 (B))

Next, a second amorphous semiconductor film 908 containing an impurity element of one conductivity type (n-type or p-type) is
The film is formed with a thickness of 80 nm. One conductivity type (n-type or p-type
The second amorphous semiconductor film 908 including an impurity element imparting a mold is formed over the entire surface by a known method such as a plasma CVD method or a sputtering method. In this embodiment, the second amorphous semiconductor film 908 containing an n-type impurity element is formed using a silicon target to which phosphorus is added. (FIG. 9
(B))

Next, resist masks 909 and 910 are formed by a second photolithography step, and unnecessary portions are removed by etching to form a source wiring 1111. At this time, wet etching or dry etching is used. (FIG. 9 (C))

In this etching step, the resist mask 9
The portions other than 09 and 910 are in the second amorphous semiconductor film 90.
8 and the first amorphous semiconductor film 907 are sequentially etched, so that the TFT 1112 in the pixel portion has a second amorphous semiconductor film 913 and a first amorphous semiconductor film 911 formed therein. The storage capacitor 1113 is the second amorphous semiconductor film 9.
14 and a first amorphous semiconductor film 912 are formed.

Next, after removing the resist masks 909 and 910, a third photolithography step is performed to form a resist mask 1001, and unnecessary portions are removed by etching to form a first amorphous semiconductor film. 1002, second amorphous semiconductor films 1003, 1004, and 1005 are formed. (FIG. 10A)

Next, after removing the resist mask 1001, a first interlayer insulating film 1006 made of a silicon oxynitride film having a thickness of 150 nm is formed by a plasma CVD method to form a source wiring 1111, a TFT 1112 in a pixel portion, and a storage capacitor 1113. A film is formed to cover. (FIG. 10B)

Next, a second interlayer insulating film 1008 which is an organic insulating material made of an acrylic resin having a thickness of 1.6 μm is formed on the first interlayer insulating film 1006 made of a silicon oxynitride film.
Is formed. In this embodiment, an organic insulating material made of an acrylic resin is selected for the second interlayer insulating film. However, as the organic material, polyimide or the like may be used, and further, an inorganic material may be selected. After that, a fourth photolithography step is performed to form a resist mask 1007, and then the first interlayer insulating film and the second interlayer insulating film over the source wiring 1111 and the terminal portion 1110 are removed by a dry etching step. . Further, a contact hole for electrically connecting the storage capacitor 1113 and the second amorphous semiconductor film 1005 is formed. (FIG. 10 (C))

Next, the source wiring 1110 and the terminal 11
11, Cu films 1101 and 1102 are formed by plating. (FIG. 11 (A)) The metal film used here may be Ag, Au, Cr, Fe, Ni, Pt or an alloy thereof, as in the first embodiment.

Further, as in the first embodiment, in each of the above-described manufacturing methods, in the step of plating, the source lines of the pixel portion are connected to each other so as to have the same potential. Further, the wiring connected to have the same potential may be separated by a laser beam (a CO ₂ laser or the like) after the plating process, or may be separated simultaneously with the substrate after the plating process. Further, a short ring may be formed with these wiring patterns.

Next, ITO (Indium-Ti-Ox)
ide) or the like is formed with a thickness of 110 nm. Then, a transparent pixel electrode 1103 is formed by performing a fifth photolithography step and an etching step. (FIG. 11B)

Next, a sixth photolithography step and an etching step are performed to form a metal wiring. A metal wiring 1105 is formed in order to electrically connect the source wiring 1111 and the second amorphous semiconductor film 1003. Further, the second amorphous semiconductor film 1005 and the transparent pixel electrode 11
Then, a metal wiring 1107 for electrically connecting the first through third wirings 03 is formed.
Further, a metal wiring 1108 for electrically connecting the transparent pixel electrode 1103 and the storage capacitor 1113 is formed. Further, a metal wiring 1104 for electrically connecting the gate electrode and the terminal portion 1110 is formed. In addition, as a metal wiring material,
A stacked film of a 50 nm thick Ti film and a 500 nm thick Al-Ti alloy film can be used. (FIG. 11 (C))

In the method of manufacturing the semiconductor display device shown in Embodiment 3, a metal wiring is formed after forming a transparent pixel electrode such as ITO, but a semiconductor device in which a transparent pixel electrode such as ITO is formed after forming a metal wiring. The number of photolithography steps in the entire display device is the same. Therefore, either of the metal wiring and the transparent pixel electrode such as ITO may be formed first.

The source wiring 1111 plated with Cu by the six photolithography steps as described above.
In addition, a transmission-type semiconductor display device including a TFT 1112 and a storage capacitor 1113 in an inverted staggered pixel portion and a terminal portion 1110 can be manufactured.

If the same metal as the metal wiring is used for the pixel electrode, a reflective semiconductor device can be manufactured by five photolithography steps.

In this embodiment, a driving circuit formed of an IC chip is mounted in order to display an image similarly to the first embodiment.

[Embodiment 4] In Embodiments 1 to 3,
Although the TFT in the pixel portion is a channel-etch type semiconductor device, in the present embodiment, an embodiment of a semiconductor device in which the TFT in the pixel portion is a channel stop type will be described with reference to FIGS.

First, a semiconductor display device is manufactured using the substrate 1200 having a light-transmitting property. As substrates that can be used, Corning # 7059 glass or # 1737
A glass substrate such as barium borosilicate glass or aluminoborosilicate glass represented by glass or the like can be used. As another substrate, a light-transmitting substrate such as a quartz substrate or a plastic substrate can be used.

After a conductive layer is formed on the entire surface of the substrate, a first photolithography step is performed, a resist mask is formed, and unnecessary portions are removed by etching to form wiring and electrodes (source wiring 1202, gate Electrode 12
03, 1204, storage capacitor 1205, and terminal 120
Form 1). (FIG. 12 (A))

As the material of the wiring and the electrode, T
It is formed of an element selected from i, Ta, W, Mo, Cr, and Nd, an alloy containing the above element, or a nitride containing the above element. Further, Ti, Ta, W, Mo, C
A plurality of elements selected from the elements selected from r and Nd, alloys containing the above elements, or nitrides containing the above elements may be selected and stacked.

Next, the source wiring 1202 and the terminal 12
First, Cu coatings 1206 and 1209 are formed by plating. (FIG. 12B) If the conventional screen size is about 5 inches, Ti, Ta, W, Mo, Cr, N
The wiring resistance was not a problem even if formed from an element selected from d, an alloy containing the element, or a nitride containing the element as a component. As the length increases, a problem of increasing the wiring resistance occurs, which causes an increase in power consumption. Therefore, C
By plating the u film 1206 only on the source wiring, the wiring resistance can be reduced, and low power consumption can be realized. In this embodiment, Cu is used for the metal coating, but Ag, Au, Cr, Fe, Ni, Pt, or an alloy thereof can also be used.

Further, as in the first embodiment, in each of the manufacturing methods described above, in the plating step, the source lines of the pixel portion are connected to each other so as to have the same potential. Further, the wiring connected to have the same potential may be separated by a laser beam (a CO ₂ laser or the like) after the plating process, or may be separated simultaneously with the substrate after the plating process. Further, a short ring may be formed with these wiring patterns.

Next, an insulating film 1207 is formed on the entire surface.
The insulating film uses a silicon nitride film and has a thickness of 50 to 200 n.
m, preferably with a thickness of 150 nm. still,
The gate insulating film is not limited to the silicon nitride film, and an insulating film such as a silicon oxide film, a silicon oxynitride film, or a tantalum oxide film can be used. (FIG. 12
(C))

Next, on the insulating film 1207, 50 to 200
An amorphous semiconductor film 1208 having a thickness of preferably 100 to 150 nm is formed over the entire surface by a known method such as a plasma CVD method or a sputtering method. Typically, an amorphous silicon (a-Si) film is formed with a thickness of 100 nm. (FIG. 12 (C))

Next, resist masks 1301 and 1302 are formed by a second photolithography step, and unnecessary portions are removed by etching to remove source wirings 1411.
To form At this time, wet etching or dry etching is used. (FIG. 13
(A))

In this etching step, the resist mask 1
The portions other than 301 and 1302 are amorphous semiconductor films 1208
The amorphous semiconductor film 1304 is formed in the TFT 1412 in the pixel portion. The storage capacity 141
In No. 3, an amorphous semiconductor film 1304 is formed. (FIG. 13
(A))

Next, an insulating film made of silicon oxide or silicon nitride is formed on the amorphous semiconductor layer
It is formed to a thickness of 00 nm. FIG. 13A illustrates a second insulating layer 1305 which is self-aligned to serve as a channel protective film by an exposure process from the back surface using a gate electrode as a mask.
1306 is formed over the semiconductor layer 1303.

Next, the LDD (Li
A doping process is performed to form a ghtly doped drain region. The doping is performed by an ion doping method or an ion implantation method. Phosphorus is added as an n-type impurity and the second insulating layers 1305 and 130
Impurity regions 1307 to 1313 formed using mask 6 as a mask
09 is formed. The donor concentration in this region is 1 × 10 ¹⁶ to
The concentration is 1 × 10 ¹⁷ / cm ³ . (FIG. 13 (B))

Next, 150 nm is formed by a plasma CVD method.
First interlayer insulating film 13 made of a thick silicon oxynitride film
11 is a source wiring 1411, a TFT 1412 in a pixel portion,
And a film is formed so as to cover the storage capacitor 1413. (FIG. 13
(C))

Next, on the first interlayer insulating film 1311 made of a silicon oxynitride film, a second interlayer insulating film 1402 made of an organic insulating material made of 1.6 μm thick acrylic resin is formed.
Is formed. In this embodiment, an organic insulating material made of an acrylic resin is selected for the second interlayer insulating film. However, as the organic material, polyimide or the like may be used, and further, an inorganic material may be selected. After that, a fourth photolithography step is performed, a resist mask 1401 is formed, and then a contact hole for electrically connecting the source wiring 1411 and the amorphous semiconductor film 1307 is formed by a dry etching step. At the same time, a contact hole for electrically connecting the storage capacitor 1413 and the amorphous semiconductor film 1309 is formed. In addition, the gate wiring and the terminal 141
A contact hole for electrically connecting 0 is formed in the terminal portion. (FIG. 14A)

Next, ITO (Indium-Ti-Ox)
ide) or the like is formed with a thickness of 110 nm. After that, a transparent pixel electrode 1403 is formed by performing a fifth photolithography step and an etching step. (FIG. 14 (B))

Next, a sixth photolithography step and an etching step are performed to form a metal wiring. A metal wiring 1405 is formed in order to electrically connect the source wiring 1411 and the amorphous semiconductor film 1307. Further, a metal wiring 1407 for electrically connecting the amorphous semiconductor film 1309 and the transparent pixel electrode 1403 is formed. Further, a metal wiring 1408 for electrically connecting the transparent pixel electrode 1403 and the storage capacitor 1413 is formed. Further, a metal wiring 1404 for electrically connecting the gate electrode and the terminal portion 1410 is provided.
To form As the metal wiring material, a laminated film of a 50 nm thick Ti film and a 500 nm thick Al-Ti alloy film can be used. (FIG. 14C)

In the method of manufacturing the semiconductor display device shown in Embodiment 4, a metal wiring is formed after forming a transparent pixel electrode such as ITO. However, a semiconductor device in which a transparent pixel electrode such as ITO is formed after forming a metal wiring. The number of photolithography steps in the entire display device is the same. Therefore, either of the metal wiring and the transparent pixel electrode such as ITO may be formed first.

The source wiring 1411 plated with Cu by the above-described six photolithography steps.
In addition, a transmission-type semiconductor display device including a TFT 1412 and a storage capacitor 1413 in an inverted staggered pixel portion and a terminal portion 1410 can be manufactured.

When the same metal as the metal wiring is used for the pixel electrode, a reflective semiconductor device can be manufactured by five photolithography steps.

In this embodiment, similarly to the first embodiment, a driving circuit formed of an IC chip is mounted for displaying an image.

[Embodiment 5] The active matrix substrate and the liquid crystal display device manufactured by carrying out the present invention can be used for various electro-optical devices. That is, the present invention can be applied to all electronic apparatuses in which these electro-optical devices are incorporated as display units.

The electronic devices as described above include a video camera, a digital camera, a projector (rear type or front type), a head mounted display (goggle type display), a car navigation, a personal computer, and a portable information terminal (mobile computer, portable type). A telephone or an electronic book). Examples of these are shown in FIGS.

FIG. 5A shows a personal computer, which includes a main body 501, an image input section 502, a display section 503, a keyboard 504, and the like. The present invention can be applied to the display portion 503.

FIG. 5B shows a mobile computer, which includes a main body 505, a display unit 506, a camera unit 507, an image receiving unit 508, operation switches 509, and the like. The present invention can be applied to a display unit.

FIG. 5C shows a player using a recording medium on which a program is recorded (hereinafter, referred to as a recording medium), and includes a main body 510, a display unit 511, a speaker unit 512,
A recording medium 513, an operation switch 514, and the like are included. In addition,
This player uses a DVD (Digitia) as a recording medium.
l Versatile Disc), a CD, and the like, so that music, movies, games, and the Internet can be performed. The present invention can be applied to the display portion 511.

FIG. 6A shows a portable book (electronic book), which includes a main body 601, display units 602 and 603, and a storage medium 60.
4, including an operation switch 605, an antenna 606, and the like. The present invention can be applied to the display units 602 and 603.

FIG. 6B shows a display, and the main body 6
07, a display unit 608, a support base 609, and the like. The present invention can be applied to the display portion 608.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in various fields. Further, the electronic apparatus of the present embodiment can be realized by using any combination of the first embodiment, the second embodiment, and the first to fifth embodiments.

[0098]

According to the present invention, in a semiconductor device represented by an active matrix type liquid crystal display device, a metal film having a lower electric resistance is formed on a source wiring of the semiconductor device by a plating method, so that a screen size can be reduced. , It is possible to realize low power consumption even if the screen is enlarged. Therefore, diagonal 4
The present invention can be applied to a semiconductor device having a large screen of 0 inches or a diagonal of 50 inches.

[Brief description of the drawings]

FIG. 1 is a diagram of a manufacturing process of a transmission type semiconductor device in which a source wiring is plated with Cu.

FIG. 2 is a view showing a manufacturing process of a transmission type semiconductor device in which a source wiring is plated with Cu;

FIG. 3 is a view showing a manufacturing process of a transmission type semiconductor device in which a source wiring is plated with Cu;

FIG. 4 is a view showing a manufacturing process of a reflective semiconductor device in which a source wiring is plated with Cu;

FIG. 5 illustrates an example of a device using a semiconductor device.

FIG. 6 illustrates an example of a device using a semiconductor device.

FIG. 7 is a diagram showing a top view of a pixel.

FIG. 8 is a diagram of a wiring pattern including a source wiring;

FIG. 9 is a view showing a manufacturing process of a transmission type semiconductor device in which a source wiring is plated with Cu;

FIG. 10 is a view showing a manufacturing process of a transmission type semiconductor device in which a source wiring is plated with Cu;

FIG. 11 is a view showing a manufacturing process of a transmission-type semiconductor device in which a source wiring is plated with Cu;

FIG. 12 is a view showing a manufacturing process of a channel-stop transmission semiconductor device.

FIG. 13 is a view showing a manufacturing process of a channel-stop transmission semiconductor device.

FIG. 14 is a view showing a manufacturing process of a channel-stop transmission semiconductor device.

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Claims (11)

[Claims] A source wiring formed on an insulating surface; a metal film formed on the source wiring surface; a gate electrode formed on the insulating film; and a gate electrode and the metal film formed on the insulating film. An insulating film formed on the insulating film, a first amorphous semiconductor film formed on the insulating film, and an impurity element imparting n-type formed on the first amorphous semiconductor film. A second amorphous semiconductor film; a first interlayer insulating film formed on the second amorphous semiconductor film;
From the second interlayer insulating film formed on the interlayer insulating film, the metal wiring for electrically connecting the source wiring and the TFT in the pixel portion, and the transparent electrode for electrically connecting the TFT and the storage capacitor in the pixel portion. A pixel electrode, and a plated terminal portion. 2. A semiconductor device comprising: a source wiring formed on an insulating surface; a metal film formed on the source wiring surface; a gate electrode formed on the insulating film; and a gate electrode and the metal film formed on the insulating film. An insulating film formed on the insulating film, a first amorphous semiconductor film formed on the insulating film, and an impurity element imparting n-type formed on the first amorphous semiconductor film. A second amorphous semiconductor film; a first interlayer insulating film formed on the second amorphous semiconductor film;
A second interlayer insulating film formed on the interlayer insulating film, a metal wiring for electrically connecting a source wiring, a TFT or a storage capacitor in a pixel portion to each other, a pixel electrode made of metal, and a plated terminal A semiconductor device comprising: 3. The semiconductor device according to claim 1, wherein said metal film is formed by a plating method. 4. The metal film according to claim 1, wherein the metal film is a metal film mainly composed of one or more selected from Cu, Ag, Au, Cr, Fe, Ni, and Pt. A semiconductor device, comprising: 5. The semiconductor device according to claim 1, wherein the terminal portion and the source line of the pixel portion are plated at the same time. 6. A first step of forming a source wiring, a gate electrode, and a terminal on an insulating surface; a second step of forming a metal coating on the surface of the source wiring and the surface of the terminal; And forming a third insulating film on the gate electrode.
A fourth step of forming a first amorphous semiconductor film on the insulating film; and a second non-conductive layer containing an impurity element imparting n-type on the first amorphous semiconductor film. A fifth step of forming a crystalline semiconductor film, a sixth step of etching the second amorphous semiconductor film to form a source region and a drain region, and on the second amorphous semiconductor film A step of forming a first interlayer insulating film on the substrate, an eighth step of forming a second interlayer insulating film on the first interlayer insulating film, and the insulating film and the first interlayer insulating film. Forming a contact hole by etching the film and the second interlayer insulating film;
A step of forming a pixel electrode made of a transparent electrode on the second interlayer insulating film; a first metal wiring for electrically connecting the source wiring and the TFT of the pixel portion; An eleventh step of forming a second metal wiring which electrically connects the TFT and the pixel electrode of the pixel portion with the storage capacitor and the pixel electrode. 7. A first step of forming a source line, a gate electrode, and a terminal on an insulating surface; a second step of forming a metal film on the surface of the source line and the surface of the terminal; And forming a third insulating film on the gate electrode.
A fourth step of forming a first amorphous semiconductor film on the insulating film; and a second non-conductive layer containing an impurity element imparting n-type on the first amorphous semiconductor film. A fifth step of forming a crystalline semiconductor film, a sixth step of etching the second amorphous semiconductor film to form a source region and a drain region, and on the second amorphous semiconductor film A step of forming a first interlayer insulating film on the substrate, an eighth step of forming a second interlayer insulating film on the first interlayer insulating film, and the insulating film and the first interlayer insulating film. Forming a contact hole by etching the film and the second interlayer insulating film;
A metal wiring for electrically connecting the source wiring and the TFT of the pixel portion on the second interlayer insulating film, and a metal for electrically connecting the TFT and the storage capacitor of the pixel portion to each other. And a tenth step of forming a pixel electrode. 8. A first step of forming a source wiring, a gate electrode, and a terminal on an insulating surface; a second step of forming an insulating film on the source wiring, the gate electrode, and the terminal; A third step of forming a first amorphous semiconductor film on the insulating film, and a second amorphous semiconductor film containing an impurity element imparting n-type on the first amorphous semiconductor film Forming a source region and a drain region by etching the second amorphous semiconductor film; forming a first region on the second amorphous semiconductor film; A sixth step of forming an interlayer insulating film; a seventh step of forming a second interlayer insulating film on the first interlayer insulating film; Eighth to form a contact hole by etching the second interlayer insulating film
A ninth step of forming a metal film on the source wiring surface and the terminal part surface; a tenth step of forming a pixel electrode made of a transparent electrode on the second interlayer insulating film; A first metal line electrically connecting the source line and the TFT of the pixel portion; and a second metal line electrically connecting the TFT and the pixel electrode of the pixel portion to the storage capacitor and the pixel electrode. A manufacturing method of a semiconductor device, comprising: an eleventh step of forming. 9. A first step of forming a source wiring, a gate electrode, and a terminal on an insulating surface; a second step of forming a metal coating on the surface of the source wiring and the surface of the terminal; And forming a third insulating film on the gate electrode.
A fourth step of forming an amorphous semiconductor film on the insulating film; a fifth step of forming a source region and a drain region in the amorphous semiconductor; Sixth forming the first interlayer insulating film
A step of forming a second interlayer insulating film on the first interlayer insulating film; and an eighth step of forming a pixel electrode made of a transparent electrode on the second interlayer insulating film. Forming a contact hole by etching the insulating film, the first interlayer insulating film, and the second interlayer insulating film;
A metal wiring for electrically connecting the source wiring and the TFT of the pixel portion on the second interlayer insulating film, and a metal for electrically connecting the TFT and the storage capacitor of the pixel portion to each other. And a tenth step of forming a pixel electrode. 10. The method for manufacturing a semiconductor device according to claim 6, wherein the step of forming a metal film on the surface of the source wiring and the surface of the terminal portion uses a plating method. 11. The method according to claim 6, wherein the step of forming a metal film on the surface of the source wiring and the surface of the terminal portion comprises:
A method for manufacturing a semiconductor device, wherein plating is performed simultaneously.