JP5732500B2 - Display device - Google Patents

Description

The present invention relates to a semiconductor device having a semiconductor circuit composed of a thin film transistor (hereinafter referred to as TFT) and a manufacturing method thereof, and more particularly to an electro-optical device typified by a liquid crystal display panel and an electronic apparatus having the electro-optical device mounted as a component Technology.

Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device (hereinafter referred to as a display device), a semiconductor circuit, and an electronic device are all semiconductor devices.

In recent years, a technique for manufacturing a TFT using a semiconductor thin film (having a thickness of about several hundred to several thousand nm) formed on a substrate having an insulating surface has been developed. TFT is an integrated circuit (Integrate
It is widely applied to semiconductor devices such as d Circuit (IC) and electro-optical devices, and is particularly urgently developed as a switching element for display devices.

As a semiconductor device, an active matrix liquid crystal display device is often used because a high-definition image can be obtained as compared with a passive liquid crystal display device. The active matrix liquid crystal display device includes a gate line, a source line, a TFT of a pixel portion provided at an intersection of the gate line and the source line, and a pixel electrode connected to the TFT of the pixel portion. . The gate wiring of the conventional active matrix liquid crystal display device has a three-layer structure of Ti / Al / Ti, and the source wiring of the conventional active matrix liquid crystal display device is Ta.
It has a two-layer structure of N / W. TaN / W of the source wiring material is a metal material that can withstand heat treatment, and its wiring resistance is slightly higher than that of Al or the like.

The conventional active matrix liquid crystal display device having such a structure has been used as a display device for a monitor, a television, and a portable terminal, and has been mass-produced.
Furthermore, demands for larger screen sizes, higher definition, higher aperture ratios, and higher reliability are increasing.

With a conventional semiconductor device having a screen size of about 5 inches, the wiring resistance of the semiconductor display device has not been a problem. However, when the screen size is increased, the length of the gate wiring and the source wiring increases, and in particular, there is a problem that the wiring resistance of the source wiring made of a TaN / W metal material increases, resulting in an increase in power consumption. Was causing. Therefore, there is a means to select Al as the wiring material, but due to the formation of protrusions such as hillocks and whiskers by heat treatment and the diffusion of Al atoms into the channel formation region, it causes malfunctioning of TFT and degradation of TFT characteristics. In the panel display of a semiconductor device, it leads to a display defect such as a line defect or a point defect, resulting in a decrease in yield and reliability.

Accordingly, an object of the present invention is to provide a structure of a semiconductor device and a manufacturing method thereof for realizing low power consumption, yield, and improvement in reliability even when the screen is enlarged.

The present invention relates to a source wiring plated with a low-resistance material (typically Cu, Ag, Au, Cr, Fe, Ni, Pt, or an alloy thereof), an inverted staggered pixel portion TFT, and a storage capacitor. And a semiconductor device having a terminal portion. It should be noted that when the screen size is increased, only the pixel portion has a large shape, so that it is not necessary to plate a metal film on portions other than the pixel portion. That is, the metal film may be plated only on the source wiring of the pixel portion.

A method of plating a metal film only on the source wiring will be described with reference to FIG. A wiring pattern to which a plating electrode 805 as an electrode for plating is attached is formed on the substrate.
In this wiring pattern, a terminal portion 808 connected to the gate wiring side driving circuit and a terminal portion 809 connected to the source wiring side driving circuit are formed. Further, the wiring pattern is formed as a source wiring pattern as shown in FIG. Note that since the portion to be plated with the metal film is only the source wiring of the pixel portion, the pattern that becomes the source wiring is not connected to the terminal portion connected to the source wiring side driving circuit.

By performing plating using this wiring pattern, a metal film can be plated only on the source wiring of the pixel portion. Thus, a semiconductor device that can realize low power consumption even when the screen size is increased can be manufactured.

The present invention relates to a semiconductor device typified by an active matrix liquid crystal display device.
By forming a metal film with a lower electrical resistance on the source wiring of the semiconductor device by plating,
Even when the screen size is increased, low power consumption can be realized. Therefore, diagonal 40
The present invention can also be applied to a large-screen semiconductor device having an inch or a diagonal size of 50 inches.

Diagram of manufacturing process of transmissive semiconductor device with source wiring Cu plated Diagram of manufacturing process of transmissive semiconductor device with source wiring Cu plated Diagram of manufacturing process of transmissive semiconductor device with source wiring Cu plated Diagram of manufacturing process of reflective semiconductor device with source wiring plated with Cu FIG. 6 illustrates an example of a device using a semiconductor device. FIG. 6 illustrates an example of a device using a semiconductor device. The figure which shows the top view of a pixel Diagram of wiring pattern including source wiring Diagram of manufacturing process of transmissive semiconductor device with source wiring Cu plated Diagram of manufacturing process of transmissive semiconductor device with source wiring Cu plated Diagram of manufacturing process of transmissive semiconductor device with source wiring Cu plated Diagram of manufacturing process of channel stop type transmissive semiconductor device Diagram of manufacturing process of channel stop type transmissive semiconductor device Diagram of manufacturing process of channel stop type transmissive semiconductor device

(Embodiment 1)
A transmission type semiconductor device embodying the present invention will be described below.

First, a conductive film is formed over the entire surface of a substrate, and the conductive film is formed into a desired shape by a first photolithography process.

Next, a current suitable for plating is supplied from the plating electrode 805 connected to the source wiring to plate the metal film on the source wiring. At this time, since the conductive film is formed in the shape as shown in FIG. 8, the metal film can be plated only on the source wiring by attaching the electrode to the substrate.

In addition, the metal film in this specification shows Cu, Ag, Au, Cr, Fe, Ni, Pt, or these alloys.

In each of the above manufacturing methods, in the step of performing plating, the source wiring of the pixel portion is connected by wiring so as to have the same potential. Further, the wiring connected to have the same potential may be divided by a laser beam (CO ₂ laser or the like) after the plating process, or may be divided simultaneously with the substrate after the plating process. Moreover, you may form a short ring with these wiring patterns.

Next, an insulating film is formed on the entire surface. A first amorphous semiconductor film and a second amorphous semiconductor film containing an impurity element of one conductivity type (n-type or p-type) are stacked over the insulating film.
Unnecessary portions of these stacked films are removed by etching in a second photolithography process, and source wirings, gate electrodes, and storage capacitors are formed in desired shapes.

Next, after removing the resist mask in the second photolithography process, the third photolithography process is performed on the second amorphous semiconductor film containing one conductivity type (n-type or p-type) impurity element. The portion is removed to form a source region and a drain region of the gate electrode.

Next, after removing the resist mask in the third photolithography step, a first interlayer insulating film is formed so as to cover the source wiring, the TFT in the pixel portion, the storage capacitor, and the terminal portion.

Next, a second interlayer insulating film which is an organic insulating material made of acrylic resin is formed on the first interlayer insulating film. Thereafter, a fourth photolithography process is performed to form a resist mask, and then a contact hole is formed by a dry etching process. Here, a contact hole reaching the second amorphous semiconductor film containing an impurity element of one conductivity type (n-type or p-type) of the gate electrode and one conductivity type (n-type or p-type) impurity of the storage capacitor A contact hole reaching the second amorphous semiconductor film containing the element and a contact hole reaching the source wiring are formed. At the same time, the excess first and second interlayer insulating films in the terminal portion are etched to form the terminal portion.

Next, one conductivity type (n-type or p-type) is obtained by a fifth photolithography process.
A transparent pixel electrode for electrically connecting the second amorphous semiconductor film (drain region) containing the impurity element and the storage capacitor is formed.

Next, a metal wiring made of a low-resistance metal material is formed, and a second amorphous material containing a gate wiring, a source wiring, and an impurity element of one conductivity type (n-type or p-type) is formed by a sixth photolithography process. An electrode for connecting the high-quality semiconductor film and a metal wiring electrically connected to the terminal portion are formed. In the present invention, the gate wiring is electrically connected to the first gate electrode or the second gate electrode through a contact hole provided in the interlayer insulating film. In addition, the source wiring and the source wiring have one conductivity type (n-type or p-type) through a contact hole provided in the interlayer insulating film.
Type) of the second amorphous semiconductor film (source region) containing the impurity element. In addition, the pixel electrode has one conductivity type through a contact hole provided in the interlayer insulating film (
It is electrically connected to a second amorphous semiconductor film (drain region) containing an n-type or p-type impurity element.

In this way, a transmissive semiconductor display device comprising a source wiring plated with a metal film, a TFT of a reverse stagger type pixel portion, a storage capacitor, and a terminal portion is manufactured by a total of six photolithography processes. can do.

(Embodiment 2)
A transmission type semiconductor device embodying the present invention will be described below.

The reflective semiconductor device can be manufactured through the same steps up to the fourth photolithography process for manufacturing the transmissive semiconductor device. An electrode that connects the gate wiring, the source wiring, and the second amorphous semiconductor film (source region) containing an impurity element of one conductivity type (n-type or p-type) by the fifth photolithography step, a pixel electrode And a metal wiring electrically connected to the terminal portion. The material of the metal wiring is preferably a highly reflective metal material for constituting the pixel electrode, and typically a material mainly composed of Al or Ag is used.

In the above case, the pixel electrode can be formed at the same time as the fifth photolithography step by manufacturing the pixel electrode with the same element as the metal wiring.

In this way, a reflective semiconductor display device including a source wiring plated with a metal film, a TFT of a reverse stagger type pixel portion, a storage capacitor, and a terminal portion is manufactured by a total of five photolithography processes. can do.

An embodiment of the present invention will be described with reference to FIGS. In this embodiment, a manufacturing method of a liquid crystal display device is shown, and a method of manufacturing a TFT of a pixel portion with a reverse stagger type on a substrate and manufacturing a storage capacitor connected to the TFT will be described in detail according to steps. Moreover, in FIGS. 1-3,
A terminal portion for electrical connection with wiring of a circuit provided on another substrate provided on the end portion of the substrate is shown in the manufacturing process at the same time. Note that the cross-sectional views of FIGS.

First, a semiconductor display device is formed using a light-transmitting substrate 100. As a substrate that can be used, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass represented by Corning # 7059 glass or # 1737 glass can be used. Furthermore, a light-transmitting substrate such as a quartz substrate or a plastic substrate can be used as another substrate.

After a conductive layer is formed over the entire surface of the substrate 100, a first photolithography process is performed, a resist mask is formed, unnecessary portions are removed by etching, and wirings and electrodes (source wiring 102, gate electrode 103) are formed. 104, holding capacitor 105, and terminal 101). (Fig. 1 (A))

The wiring and electrode materials are made of an element selected from Ti, Ta, W, Mo, Cr, and Nd, an alloy containing the element as a component, or a nitride containing the element as a component. Furthermore, an element selected from Ti, Ta, W, Mo, Cr, Nd, an alloy containing the element as a component,
Alternatively, a plurality of nitrides containing the above elements as a component can be selected and stacked.

Next, Cu coatings 106 and 110 are formed on the source wiring 102 and the terminal portion 101 by plating. (FIG. 1 (B)) If the screen size is about 5 inches, Ti, Ta
Wiring resistance was not a problem even when an element selected from W, Mo, Cr, and Nd, an alloy containing the element, or a nitride containing the element was used, but the screen size was large. When a screen is formed, the length of each wiring increases, which causes a problem that the wiring resistance increases, and causes an increase in power consumption. Therefore, it is possible to reduce the wiring resistance by plating the Cu coating 106 only on the source wiring, and to realize low power consumption. In this embodiment, Cu is used for the metal coating, but Ag, Au, Cr, Fe, Ni, Pt or alloys thereof can also be used.

In each of the above manufacturing methods, in the step of performing plating, the source wiring of the pixel portion is connected by wiring so as to have the same potential. Further, the wiring connected to have the same potential may be divided by a laser beam (CO ₂ laser or the like) after the plating process, or may be divided simultaneously with the substrate after the plating process. Moreover, you may form a short ring with these wiring patterns.

Next, an insulating film 107 is formed over the entire surface. The insulating film is a silicon nitride film with a thickness of 50 to 50
The thickness is 200 nm, preferably 150 nm. Note that the gate insulating film is not limited to a silicon nitride film, and an insulating film such as a silicon oxide film, a silicon oxynitride film, or a tantalum oxide film can also be used. (Figure 1 (C))

Next, a first amorphous semiconductor film 108 with a thickness of 50 to 200 nm, preferably 100 to 150 nm, is formed over the entire surface of the insulating film 107 by a known method such as a plasma CVD method or a sputtering method. Typically, an amorphous silicon (a-Si) film is formed with a thickness of 100 nm. (
(Fig. 1 (C))

Next, the second amorphous semiconductor film 10 containing an impurity element of one conductivity type (n-type or p-type)
9 is formed to a thickness of 20 to 80 nm. The second amorphous semiconductor film 109 containing an impurity element imparting one conductivity type (n-type or p-type) is formed over the entire surface by a known method such as a plasma CVD method or a sputtering method. In this embodiment, the second amorphous semiconductor film 109 containing an n-type impurity element is formed using a silicon target to which phosphorus is added. (Figure 1 (C))

Next, resist masks 205 and 206 are formed by a second photolithography process, unnecessary portions are removed by etching, and a source wiring 311 is formed. As an etching method at this time, wet etching or dry etching is used. (Fig. 2 (A))

In this etching process, the second amorphous semiconductor film 109 and the first amorphous semiconductor film 108 are sequentially etched at a place other than the resist masks 205 and 206, and the TF of the pixel portion.
In T <b> 312, the second amorphous semiconductor film 203 and the first amorphous semiconductor film 201 are formed. The storage capacitor 313 includes the second amorphous semiconductor film 204 and the first amorphous semiconductor film 202.
Is formed.

Next, after removing the resist masks 205 and 206, a third photolithography step is performed to form a resist mask 207, and unnecessary portions are removed by etching to remove the first.
The amorphous semiconductor film 208 and the second amorphous semiconductor films 209, 210, and 211 are formed. (
(Fig. 2 (B))

Next, after removing the resist mask 207, a first interlayer insulating film 213 made of a silicon oxynitride film having a thickness of 150 nm is formed by a plasma CVD method on the source wiring 311 and the pixel portion T.
A film is formed so as to cover the FT 312 and the storage capacitor 313. (Fig. 2 (C))

Next, a second interlayer insulating film 302 which is an organic insulating material made of an acrylic resin having a thickness of 1.6 μm is formed on the first interlayer insulating film 213 made of a silicon oxynitride film. In this embodiment, an organic insulating material made of an acrylic resin is selected for the second interlayer insulating film, but polyimide or the like may be used as the organic material, and an inorganic material may be further selected. Thereafter, a fourth photolithography step is performed to form a resist mask 301, and then a contact hole for electrically connecting the source wiring 311 and the second amorphous semiconductor film 209 is formed by a dry etching step. To do. At the same time, a contact hole for electrically connecting the storage capacitor 313 and the second amorphous semiconductor film 211 is formed. Further, a contact hole for electrically connecting the gate wiring and the terminal portion 310 is formed in the terminal portion. (Fig. 3 (A))

Next, a transparent electrode film such as ITO (Indium-Ti-Oxide) is formed to a thickness of 110 nm. Thereafter, a transparent pixel electrode 309 is formed by performing a fifth photolithography process and an etching process. (Fig. 3 (B))

Next, in order to form a metal wiring, a sixth photolithography process and an etching process are performed. A metal wiring 303 is formed in order to electrically connect the source wiring 311 and the second amorphous semiconductor film 209. In addition, a metal wiring 305 that electrically connects the second amorphous semiconductor film 211 and the transparent pixel electrode 309 is formed. Further, a metal wiring 306 that electrically connects the transparent pixel electrode 309 and the storage capacitor 313 is formed. In addition, a metal wiring 308 for electrically connecting the gate electrode and the terminal portion 310 is formed. As a metal wiring material, a laminated film of a 50 nm thick Ti film and a 500 nm thick Al—Ti alloy film can be used. (Fig. 3 (C
))

In the manufacturing method of the semiconductor display device shown in the first embodiment, the metal wiring is formed after forming the transparent pixel electrode such as ITO. However, the semiconductor display device in which the transparent pixel electrode such as ITO is formed after forming the metal wiring. The number of photolithography steps in the entire production is the same. Therefore, either the metal wiring or the transparent pixel electrode such as ITO may be formed first.

Through a photolithography process of six times as described above, a transmissive semiconductor display device including the source wiring 311 plated with Cu, the TFT 312 and the storage capacitor 313 of the inverted staggered pixel portion, and the terminal portion 310 is manufactured. Can be produced.

Note that a TFT in which an active layer is formed of an amorphous semiconductor film obtained according to this embodiment has a small field effect mobility and can be obtained only about 1 cm ² / Vsec. For this purpose, a driving circuit for displaying an image is formed of an IC chip, and TAB (Tape Automated Bo).
nding) method and COG (Chip on glass) method.

In Embodiment 1, it was shown that a reflective semiconductor display device can be manufactured by six photolithography processes. In this embodiment, a method of manufacturing a reflective semiconductor display device by five photolithography processes is shown. As shown in FIG.

Since this example is the same process up to the state of FIG. 3A of Example 1, only different processes will be described below. In addition, the same code | symbol was used for the location corresponding to FIG. 3 (A).

First, after obtaining the state of FIG. 3A in accordance with Embodiment 1, the source wiring 311 and the second amorphous semiconductor film 209 are electrically connected by performing a fifth photolithography step and an etching step. In order to achieve this, a metal wiring 402 is formed. At the same time, the pixel electrode 401 is formed. Further, a metal wiring 405 that is electrically connected to the terminal portion is formed at the same time. (Fig. 4 (B
))

In this way, the source wiring 311 subjected to metal film plating, the inverted staggered pixel portion TFT 312, the storage capacitor 313, and the terminal portion 3 are subjected to a total of five photolithography processes.
10 can be manufactured.

In Example 1 and Example 2, the plating process is performed after the first photolithography process, but in this example, the plating process is performed after the fourth photolithography process.
Description will be made with reference to FIG.

First, a semiconductor display device is formed using a light-transmitting substrate 900. As a substrate that can be used, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass represented by Corning # 7059 glass or # 1737 glass can be used. Furthermore, a light-transmitting substrate such as a quartz substrate or a plastic substrate can be used as another substrate.

After a conductive layer is formed over the entire surface of the substrate, a first photolithography process is performed, a resist mask is formed, unnecessary portions are removed by etching, and wirings and electrodes (source wiring 902, gate electrode 903, 904, a storage capacitor 905, and a terminal 901) are formed. (Fig. 9 (A))

The wiring and electrode materials are made of an element selected from Ti, Ta, W, Mo, Cr, and Nd, an alloy containing the element as a component, or a nitride containing the element as a component. Furthermore, an element selected from Ti, Ta, W, Mo, Cr, Nd, an alloy containing the element as a component,
Alternatively, a plurality of nitrides containing the above elements as a component can be selected and stacked.

Next, an insulating film 906 is formed over the entire surface. The insulating film is a silicon nitride film with a thickness of 50 to 50
The thickness is 200 nm, preferably 150 nm. Note that the gate insulating film is not limited to a silicon nitride film, and an insulating film such as a silicon oxide film, a silicon oxynitride film, or a tantalum oxide film can also be used. (Fig. 9 (B))

Next, a first amorphous semiconductor film 907 with a thickness of 50 to 200 nm, preferably 100 to 150 nm, is formed over the entire surface of the insulating film 906 by a known method such as a plasma CVD method or a sputtering method. Typically, an amorphous silicon (a-Si) film is formed with a thickness of 100 nm. (
(Fig. 9 (B))

Next, a second amorphous semiconductor film 90 containing an impurity element of one conductivity type (n-type or p-type)
8 is formed to a thickness of 20 to 80 nm. The second amorphous semiconductor film 908 containing an impurity element imparting one conductivity type (n-type or p-type) is formed over the entire surface by a known method such as a plasma CVD method or a sputtering method. In this embodiment, the second amorphous semiconductor film 908 containing an n-type impurity element is formed using a silicon target to which phosphorus is added. (Fig. 9 (B))

Next, resist masks 909 and 910 are formed by a second photolithography process, unnecessary portions are removed by etching, and a source wiring 1111 is formed. As an etching method at this time, wet etching or dry etching is used. (Figure 9 (C))

In this etching process, the second amorphous semiconductor film 908 and the first amorphous semiconductor film 907 are sequentially etched at a place other than the resist masks 909 and 910, and the TF of the pixel portion.
In T1112, the second amorphous semiconductor film 913 and the first amorphous semiconductor film 911 are formed. The storage capacitor 1113 includes the second amorphous semiconductor film 914 and the first amorphous semiconductor film 9.
12 is formed.

Next, after removing the resist masks 909 and 910, a third photolithography step is performed to form a resist mask 1001, and unnecessary portions are removed by etching to remove the first amorphous semiconductor film 1002 and the first amorphous semiconductor film 1002. Two amorphous semiconductor films 1003, 1004, and 1005 are formed. (Fig. 10 (A))

Next, after removing the resist mask 1001, the plasma CVD method is used to remove 150 nm.
A first interlayer insulating film 1006 made of a thick silicon oxynitride film is formed so as to cover the source wiring 1111, the TFT 1112 in the pixel portion, and the storage capacitor 1113. (Fig. 10 (B))

Next, a second interlayer insulating film 1008 that is an organic insulating material made of an acrylic resin having a thickness of 1.6 μm is formed on the first interlayer insulating film 1006 made of a silicon oxynitride film. In this embodiment, an organic insulating material made of an acrylic resin is selected for the second interlayer insulating film, but polyimide or the like may be used as the organic material, and an inorganic material may be further selected. Thereafter, a fourth photolithography process is performed to form a resist mask 1007, and then the first interlayer insulating film and the second interlayer insulating film on the source wiring 1111 and the terminal portion 1110 are removed by a dry etching process. . In addition, a contact hole for electrically connecting the storage capacitor 1113 and the second amorphous semiconductor film 1005 is formed. (Fig. 10 (C))

Next, Cu coatings 1101 and 1102 are formed on the source wiring 1110 and the terminal portion 1111 by a plating method. (FIG. 11 (A)) The metal coating used here is Ag, as in Example 1,
Au, Cr, Fe, Ni, Pt, or an alloy thereof can also be used.

Further, as in Embodiment 1, in each of the above manufacturing methods, in the step of performing plating, the source wiring of the pixel portion is connected by wiring so as to have the same potential. In addition, the wiring connected so as to have the same electric potential is a laser beam (
It may be divided by a CO ₂ laser or the like, or may be divided simultaneously with the substrate after the plating process. Moreover, you may form a short ring with these wiring patterns.

Next, a transparent electrode film such as ITO (Indium-Ti-Oxide) is formed to a thickness of 110 nm. Thereafter, a transparent pixel electrode 1103 is formed by performing a fifth photolithography process and an etching process. (Fig. 11 (B))

Next, in order to form a metal wiring, a sixth photolithography process and an etching process are performed. In order to electrically connect the source wiring 1111 and the second amorphous semiconductor film 1003, a metal wiring 1105 is formed. The second amorphous semiconductor film 1005 and the transparent pixel electrode 11
A metal wiring 1107 for electrically connecting 03 is formed. In addition, a metal wiring 1108 that electrically connects the transparent pixel electrode 1103 and the storage capacitor 1113 is formed. In addition, a metal wiring 1104 for electrically connecting the gate electrode and the terminal portion 1110 is formed. As a metal wiring material, a laminated film of a 50 nm thick Ti film and a 500 nm thick Al—Ti alloy film can be used. (Fig. 11 (C))

In the method of manufacturing the semiconductor display device shown in Example 3, the metal wiring is formed after forming the transparent pixel electrode such as ITO. However, the semiconductor display device in which the transparent pixel electrode such as ITO is formed after forming the metal wiring. The number of photolithography steps in the entire production is the same. Therefore, either the metal wiring or the transparent pixel electrode such as ITO may be formed first.

Through the six photolithography processes as described above, the source wiring 1111 plated with Cu, the TFT 1112 and the storage capacitor 1113 of the inverted staggered pixel portion, and the terminal portion 11
10 can be manufactured.

In addition, when the same metal as the metal wiring is used for the pixel electrode, a reflective semiconductor device can be manufactured through five photolithography processes.

In this embodiment, a drive circuit formed of an IC chip is mounted in order to display an image as in the first embodiment.

In the first to third embodiments, the TFT in the pixel portion is a channel etch type semiconductor device, but in this embodiment, an embodiment in which the TFT in the pixel portion is a channel stop type semiconductor device is shown in FIG.
Description will be made with reference to FIG.

First, a semiconductor display device is manufactured using a light-transmitting substrate 1200. As a substrate that can be used, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass represented by Corning # 7059 glass or # 1737 glass can be used. Furthermore, a light-transmitting substrate such as a quartz substrate or a plastic substrate can be used as another substrate.

After a conductive layer is formed over the entire surface of the substrate, a first photolithography process is performed, a resist mask is formed, unnecessary portions are removed by etching, and wirings and electrodes (source wiring 1202, gate electrode 1203, 1204, holding capacitor 1205, and terminal 1201
). (Fig. 12 (A))

The wiring and electrode materials are made of an element selected from Ti, Ta, W, Mo, Cr, and Nd, an alloy containing the element as a component, or a nitride containing the element as a component. Furthermore, an element selected from Ti, Ta, W, Mo, Cr, Nd, an alloy containing the element as a component,
Alternatively, a plurality of nitrides containing the above elements as a component can be selected and stacked.

Next, Cu coatings 1206 and 1209 are formed on the source wiring 1202 and the terminal portion 1201 by plating. (FIG. 12 (B)) If the screen size is about 5 inches in the past,
Wiring resistance did not become a problem even when an element selected from Ti, Ta, W, Mo, Cr, and Nd, an alloy containing the element as a component, or a nitride containing the element as a component was used. When the size of the screen is increased, the length of each wiring is increased, causing a problem that the wiring resistance is increased, resulting in an increase in power consumption. Therefore, by plating the Cu film 1206 only on the source wiring, the wiring resistance can be lowered, and low power consumption can be realized. In this embodiment, Cu is used for the metal coating, but Ag, Au, Cr, Fe, Ni, Pt or alloys thereof can also be used.

Further, as in Embodiment 1, in each of the above manufacturing methods, in the step of performing plating, the source wiring of the pixel portion is connected by wiring so as to have the same potential. In addition, the wiring connected so as to have the same electric potential is a laser beam (
It may be divided by a CO ₂ laser or the like, or may be divided simultaneously with the substrate after the plating process. Moreover, you may form a short ring with these wiring patterns.

Next, an insulating film 1207 is formed over the entire surface. The insulating film is a silicon nitride film with a film thickness of 50.
The thickness is set to ˜200 nm, preferably 150 nm. Note that the gate insulating film is not limited to a silicon nitride film, and an insulating film such as a silicon oxide film, a silicon oxynitride film, or a tantalum oxide film can also be used. (Figure 12 (C))

Next, an amorphous semiconductor film 1208 is formed over the entire surface of the insulating film 1207 by a known method such as a plasma CVD method or a sputtering method with a thickness of 50 to 200 nm, preferably 100 to 150 nm. Typically, an amorphous silicon (a-Si) film is formed with a thickness of 100 nm. (Figure 12 (C))

Next, resist masks 1301 and 1302 are formed by a second photolithography process, unnecessary portions are removed by etching, and a source wiring 1411 is formed. As an etching method at this time, wet etching or dry etching is used. (Fig. 13 (
A))

In this etching process, the amorphous semiconductor film 1208 is etched in places other than the resist masks 1301 and 1302, and the amorphous semiconductor film 1304 is formed in the TFT 1412 in the pixel portion. In addition, an amorphous semiconductor film 1304 is formed in the storage capacitor 1413. (Fig. 13 (
A))

Next, an insulating film made of silicon oxide or silicon nitride is formed to a thickness of 100 to 200 nm over the amorphous semiconductor layer 1303. FIG. 13A shows a second insulating layer 1305 used as a channel protective film in a self-aligned manner by an exposure process from the back surface using a gate electrode as a mask.
1306 is formed over the semiconductor layer 1303.

Next, a doping process for forming an LDD (Lightly Doped Drain) region of the n-channel TFT is performed. Doping is performed by ion doping or ion implantation. Phosphorus is added as an n-type impurity, and second insulating layers 1305 and 130 are added.
Impurity regions 1307 to 1309 are formed using 6 as a mask. The donor concentration in this region is 1 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ . (Fig. 13B)

Next, a first interlayer insulating film 1311 made of a silicon oxynitride film having a thickness of 150 nm is formed by a plasma CVD method using a source wiring 1411, a TFT 1412 in the pixel portion, and a storage capacitor 1413.
A film is formed so as to cover. (Fig. 13 (C))

Next, a second interlayer insulating film 1402 that is an organic insulating material made of an acrylic resin having a thickness of 1.6 μm is formed over the first interlayer insulating film 1311 made of a silicon oxynitride film. In this embodiment, an organic insulating material made of an acrylic resin is selected for the second interlayer insulating film, but polyimide or the like may be used as the organic material, and an inorganic material may be further selected. Thereafter, a fourth photolithography step is performed to form a resist mask 1401, and then a contact hole for electrically connecting the source wiring 1411 and the amorphous semiconductor film 1307 is formed by a dry etching step.
At the same time, a contact hole for electrically connecting the storage capacitor 1413 and the amorphous semiconductor film 1309 is formed. In addition, a contact hole for electrically connecting the gate wiring and the terminal portion 1410 is formed in the terminal portion. (Fig. 14 (A))

Next, a transparent electrode film such as ITO (Indium-Ti-Oxide) is formed to a thickness of 110 nm. Thereafter, a transparent pixel electrode 1403 is formed by performing a fifth photolithography process and an etching process. (Fig. 14B)

Next, in order to form a metal wiring, a sixth photolithography process and an etching process are performed. A metal wiring 1405 is formed to electrically connect the source wiring 1411 and the amorphous semiconductor film 1307. Further, a metal wiring 1407 that electrically connects the amorphous semiconductor film 1309 and the transparent pixel electrode 1403 is formed. Further, the transparent pixel electrode 1403 and the storage capacitor 141 are provided.
A metal wiring 1408 that electrically connects the three is formed. In addition, the gate electrode and the terminal portion 1410
A metal wiring 1404 for electrically connecting the two is formed. The metal wiring material is 5
A laminated film of a 0 nm thick Ti film and a 500 nm thick Al—Ti alloy film can be used.
(Figure 14 (C))

In the method of manufacturing the semiconductor display device shown in Example 4, the metal wiring is formed after forming the transparent pixel electrode such as ITO, but the semiconductor display device in which the transparent pixel electrode such as ITO is formed after forming the metal wiring. The number of photolithography steps in the entire production is the same. Therefore, either the metal wiring or the transparent pixel electrode such as ITO may be formed first.

Through six photolithography processes as described above, the source wiring 1411 plated with Cu, the TFT 1412 and the storage capacitor 1413 of the inverted staggered pixel portion, and the terminal portion 14
10 can be manufactured.

In addition, if the same metal as the metal wiring is used for the pixel electrode, a reflective semiconductor device can be manufactured through five photolithography processes.

In this embodiment, a drive circuit formed of an IC chip is mounted in order to display an image as in the first embodiment.

The active matrix substrate and the liquid crystal display device manufactured by implementing the present invention can be used for various electro-optical devices. That is, the present invention can be implemented in all electronic devices in which these electro-optical devices are incorporated as display units.

The above electronic devices include a video camera, a digital camera, a projector (rear type or front type), a head mounted display (goggles type display), a car navigation system, a personal computer, a personal digital assistant (mobile computer, mobile phone or electronic). Books). Examples of these are shown in FIGS.

FIG. 5A illustrates a personal computer, which includes a main body 501, an image input portion 502, a display portion 503, a keyboard 504, and the like. The present invention can be applied to the display portion 503.

FIG. 5B illustrates a mobile computer, which includes a main body 505, a display portion 506, and a camera portion 50.
7, an image receiving unit 508, an operation switch 509, and the like. The present invention can be applied to a display unit.

FIG. 5C shows a player using a recording medium (hereinafter referred to as a recording medium) in which a program is recorded, and includes a main body 510, a display portion 511, a speaker portion 512, a recording medium 513, an operation switch 514, and the like. This player is a DVD (Digital) as a recording medium.
Versatile Disc), CD, etc. can be used for music appreciation, movie appreciation, games and the Internet. The present invention can be applied to the display portion 511.

FIG. 6A illustrates a portable book (electronic book), which includes a main body 601, display portions 602 and 603, a storage medium 604, operation switches 605, an antenna 606, and the like. The present invention provides display units 602, 6
03 can be applied.

FIG. 6B shows a display, which includes a main body 607, a display portion 608, a support base 609, and the like. The present invention can be applied to the display portion 608.

As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. In addition, the electronic device of this example can be realized by using any combination of Embodiment Mode 1, Embodiment Mode 2, and Examples 1 to 5.

Claims (6)

Having a pixel part,
The pixel portion includes first to fifth conductive layers, first and second insulating layers, and a first semiconductor layer,
The first conductive layer has a region functioning as a gate electrode of the first transistor;
The first insulating layer is provided above the first conductive layer and above the second conductive layer,
The first semiconductor layer is provided above the first insulating layer,
The first semiconductor layer has a channel formation region of the first transistor;
The second insulating layer is provided above the first semiconductor layer;
The third conductive layer is provided above the second insulating layer;
The third conductive layer is electrically connected to the first semiconductor layer;
The third conductive layer is electrically connected to the second conductive layer;
The fourth conductive layer is provided above the second insulating layer,
The fourth conductive layer is electrically connected to the first semiconductor layer;
The fifth conductive layer is provided above the second insulating layer;
The fifth conductive layer includes a contact hole provided in the first insulating layer and the second insulation in a region existing in a channel length direction of the first transistor from a channel formation region of the first transistor. Electrically connected to the first conductive layer through a contact hole provided in the layer;
The fifth conductive layer has a region overlapping at least part of a channel formation region of the first transistor;
The second conductive layer has a region in contact with the sixth conductive layer;
The sixth conductive layer has a region in contact with the second semiconductor layer;
The display device, wherein the second semiconductor layer includes a channel formation region of a second transistor. Having a pixel part,
The pixel portion includes first to fifth conductive layers, first and second insulating layers, and a semiconductor layer,
The first conductive layer has a region functioning as a gate electrode of a transistor;
The first insulating layer is provided above the first conductive layer and above the second conductive layer,
The semiconductor layer is provided above the first insulating layer,
The semiconductor layer has a channel formation region of the transistor,
The second insulating layer is provided above the semiconductor layer;
The third conductive layer is provided above the second insulating layer;
The third conductive layer is electrically connected to the semiconductor layer;
The third conductive layer is electrically connected to the second conductive layer;
The conductive layer in contact with the third conductive layer is only the second conductive layer,
The fourth conductive layer is provided above the second insulating layer,
The fourth conductive layer is electrically connected to the semiconductor layer;
The fifth conductive layer is provided above the second insulating layer;
The fifth conductive layer includes a contact hole provided in the first insulating layer and a contact hole provided in the second insulating layer in a region existing in the channel length direction of the transistor from the channel formation region. And electrically connected to the first conductive layer via
The display device, wherein the fifth conductive layer has a region overlapping with at least a part of the channel formation region. Having a pixel part,
The pixel portion includes first to fifth conductive layers, first and second insulating layers, and a first semiconductor layer,
The first conductive layer has a region functioning as a gate electrode of the first transistor;
The first insulating layer is provided above the first conductive layer and above the second conductive layer,
The first semiconductor layer is provided above the first insulating layer,
The first semiconductor layer has a channel formation region of the first transistor;
The second insulating layer is provided above the first semiconductor layer;
The third conductive layer is provided above the second insulating layer;
The third conductive layer has a region in contact with the first semiconductor layer,
The third conductive layer has a region in contact with the second layer of the second conductive layer,
The fourth conductive layer is provided above the second insulating layer,
The fourth conductive layer has a region in contact with the first semiconductor layer,
The fifth conductive layer is provided above the second insulating layer;
The fifth conductive layer includes a contact hole provided in the first insulating layer and the second insulation in a region existing in a channel length direction of the first transistor from a channel formation region of the first transistor. Electrically connected to the first conductive layer through a contact hole provided in the layer;
The fifth conductive layer has a region overlapping at least part of a channel formation region of the first transistor;
The second conductive layer has a region in contact with the sixth conductive layer;
The sixth conductive layer has a region in contact with the second semiconductor layer;
The display device, wherein the second semiconductor layer includes a channel formation region of a second transistor. Having a pixel part,
The pixel portion includes first to fifth conductive layers, first and second insulating layers, and a semiconductor layer,
The first conductive layer has a region functioning as a gate electrode of a transistor;
The first insulating layer is provided above the first conductive layer and above the second conductive layer,
The semiconductor layer is provided above the first insulating layer,
The semiconductor layer has a channel formation region of the transistor,
The second insulating layer is provided above the semiconductor layer;
The third conductive layer is provided above the second insulating layer;
The third conductive layer has a region in contact with the semiconductor layer;
The third conductive layer has a region in contact with the second layer of the second conductive layer,
The conductive layer in contact with the third conductive layer is only the second conductive layer,
The fourth conductive layer is provided above the second insulating layer,
The fourth conductive layer has a region in contact with the semiconductor layer,
The fifth conductive layer is provided above the second insulating layer;
The fifth conductive layer includes a contact hole provided in the first insulating layer and a contact hole provided in the second insulating layer in a region existing in the channel length direction of the transistor from the channel formation region. And electrically connected to the first conductive layer via
The display device, wherein the fifth conductive layer has a region overlapping with at least a part of the channel formation region. In any one of Claims 1 thru | or 4,
The second conductive layer includes a first layer and a second layer above the first layer,
The first layer includes an element selected from Ti, Ta, W, Mo, Cr, and Nd, or an alloy containing an element selected from Ti, Ta, W, Mo, Cr, and Nd as a component. Characteristic display device. In any one of Claims 1 thru | or 5,
The pixel portion has a pixel electrode,
The display device, wherein the pixel electrode is electrically connected to the fourth conductive layer.

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