JP2002197860A - Semiconductor integrated circuit and signal take-in method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which current consumption is reduced at the time of data holding operation and a signal take-in method. SOLUTION: This circuit is a semiconductor integrated circuit which takes in a data signal Din in synchronism with an internal clock signal clk generated in a clock buffer 1 and the circuit is provided with comparing circuit 5 activating the clock buffer 1 only when variation of the data signal is caused.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit and a signal fetching method, and more particularly to a semiconductor integrated circuit for inputting a signal in synchronization with a clock signal and a signal fetching method.

[0002]

2. Description of the Related Art A conventional general-purpose dynamic random access memory (DRAM) has a self-refresh function, so that a refresh operation can be performed inside a chip. For this reason, conventionally, the supply of the external clock signal is stopped in the data holding state (so-called standby state), and the data holding current is suppressed to a minute value.

On the other hand, in a device in which a DRAM and a logic circuit are mounted on the same single chip (a DRAM embedded logic circuit), the controller of the logic circuit is a DRA.
Since the self-refresh operation in M cannot be monitored and the circuit is complicated if the self-refresh function is to be realized, the self-refresh function is not provided.

Here, in a device without such a self-refresh function, a refresh command is supplied during a data holding operation, so that a clock signal needs to be supplied from outside the device, so that current consumption during the data holding operation increases. There is a problem of doing it.

That is, a clock signal supplied from the outside of the device is distributed to each input buffer for buffering an address signal, (input) data, or various commands. Since the number increases, the total wiring length for transmitting the clock signal increases. Therefore, since the gate capacitance of the transistor constituting the input buffer is increased, the current consumption when charging and discharging for driving the capacitance is increased.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor integrated circuit and a signal fetching method for reducing current consumption during a data holding operation. I do.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit which takes in a signal in synchronization with an internal clock signal generated in a clock buffer, wherein the clock buffer is used only when a signal change occurs. The present invention is attained by providing a semiconductor integrated circuit including clock buffer control means for activating.

According to such means, the clock buffer can be deactivated when there is no change in the signal to be taken.

Here, more specifically, an input buffer for generating an internal signal from the signal in synchronism with the internal clock signal is further provided, and the clock buffer control means includes an internal signal output from the input buffer. And when the two signals are different from each other, the clock buffer can be activated.

It is another object of the present invention to provide a semiconductor integrated circuit including a plurality of input buffers for taking in a signal in synchronization with an internal clock signal generated in a clock buffer, wherein the input signal is inputted to at least one of the input buffers. This is achieved by providing a semiconductor integrated circuit characterized by comprising clock buffer control means for activating a clock buffer when a signal changes.

According to such a means, when a plurality of signals are fetched, the clock buffer can be deactivated if all the signals do not change, so that the semiconductor integrated circuit which fetches a plurality of signals. For example, current consumption during a data holding operation (standby state) can be reduced.

The clock buffer control means is provided corresponding to each input buffer, and monitors a plurality of signal changes for activating the clock buffer when a signal input to the input buffer changes. Means may be included.

[0013] As an example, the signal change monitoring means is constituted by a comparison circuit for comparing the signal with the signal output from the input buffer, and the clock buffer control means logically converts the signals output from the plurality of comparison circuits. A logic circuit that generates a signal for activating the clock buffer by combining the signals and supplies the signal to the clock buffer may be further provided.

If the logic circuit performs logic synthesis on signals output from a plurality of comparison circuits to which the same type of signal is input, the clock buffer can be controlled according to the type of signal.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts. [Embodiment 1] In a device such as a DRAM embedded logic circuit which fetches a data signal in synchronization with a clock signal, in order to reduce current consumption during a data holding operation, when there is no change in an input data signal, The clock signal may not be distributed to each buffer, and the clock signal may be distributed to each buffer when a change in the data signal is detected.

Hereinafter, the semiconductor integrated circuit according to the first embodiment will be described in more detail. FIG. 1 is a block diagram showing a configuration of the semiconductor integrated circuit according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor integrated circuit according to the present embodiment includes a clock buffer 1, an input buffer 3, and a comparison circuit 5.

Here, the clock buffer 1 buffers the input external clock signal CLK, generates an internal clock signal clk, and supplies it to the input buffer 3. Then, the input buffer 3 receives the supplied internal clock signal clk.
Input the data signal Din in synchronization with the internal data signal out.
Generate

The comparison circuit 5 compares the internal data signal out generated by the input buffer 3 with the data signal Din input to the input buffer 3, and sends a signal coz indicating the result of the comparison to the clock buffer 1. Supply.

The operation of the semiconductor integrated circuit according to the first embodiment will be described below with reference to the timing chart shown in FIG. First, for example, as shown in FIG.
It is assumed that the logic level of n changes from low level (L) to high level (H) at time T2, and changes from high level to low level at time T4.

At this time, at time T2 and time T4, the comparison circuit 5 outputs the internal data signal out due to the change of the data signal Din.
2 (e) is detected.
As shown in (1), a high-level signal coz is supplied to the clock buffer 1 at time T2 and time T4.

As a result, the clock buffer 1 is activated only when the high-level signal coz is supplied, and as shown in FIG. 2C, the high-level internal clock signal clk at time T3 and time T5. Is generated and supplied to the input buffer 3. The waveform shown by the broken line in FIG. 2C is an internal clock generated by buffering the external clock signal CLK shown in FIG. 2A by a clock buffer included in a conventional semiconductor integrated circuit. It shows the signal clk.

Then, as shown in FIG. 2D, the input buffer 3 buffers the data signal Din which has changed to the high level at the time T3 to generate a high-level internal data signal out, and at the time T5 The low-level data signal Din is buffered to generate a low-level internal data signal out.

Therefore, as described above, in the semiconductor integrated circuit according to the first embodiment, when there is no change in the input data signal Din, the clock buffer 1 that distributes the internal clock signal clk to the input buffer and the like is inactive. On the other hand, only when the data signal Din changes, the clock buffer 1 is activated within the setup time of the data signal Din.

Hereinafter, specific examples of each part of the semiconductor integrated circuit according to the first embodiment shown in FIG. 1 will be described. FIG. 3 is a circuit diagram showing a configuration example of the clock buffer 1 shown in FIG. As shown in FIG. 3, the clock buffer 1 includes a NAND circuit 10 and inverting circuits 11 and 12.
including. Here, the external clock signal CLK and the signal coz are supplied to the NAND circuit 10, and the inverting circuit 11 is connected to the NAND circuit 10. The inverting circuit 12 is the inverting circuit 1
Connected to 1.

In the clock buffer 1 having such a configuration, the internal clock signal clkz
Is output from the inverting circuit 12, and an internal clock signal clkx obtained by inverting the internal clock signal clkz is output.

The NAND circuit 10 receives an input signal
The clock buffer 1 is inactivated when coz is at a low level and activated when it is at a high level.
Is controlled according to the signal coz supplied from the comparison circuit 5, and is activated only when the signal coz is set to a high level.

FIG. 4 is a circuit diagram showing a configuration example of the input buffer 3 shown in FIG. As shown in FIG. 4, the input buffer 3 includes inverting circuits 31, 32 and a latch circuit L1,
L2 and gate circuits G1 and G2. Here, the data signal Din is supplied to the inverting circuit 31, and the gate circuit G
1 is connected to the inverting circuit 31. Further, the latch circuit L1
Is connected to the gate circuit G1, and the gate circuit G2 is connected to the latch circuit L1. The latch circuit L2 is connected to the gate circuit G2, and the inverting circuit 32 is connected to the latch circuit L2.
Connected to.

The gate circuits G1 and G2 are each composed of a P-channel MOS transistor and an N-channel MOS transistor connected in parallel, and the latch circuits L1 and L2 are each composed of two inverting circuits.

Here, the P-channel MOS transistor included in the gate circuit G1 and the N-channel MOS transistor included in the gate circuit G2 are used.
The gate of the channel MOS transistor is supplied with the internal clock signal clkz, and the N channel MOS transistor included in the gate circuit G1 and the P clock included in the gate circuit G2 are provided.
The internal clock signal clkx is supplied to the gate of the channel MOS transistor.

In the input buffer 3 having the above-described configuration, the gate circuit G according to the internal clock signals clkz and clkx supplied from the clock buffer 1.
By alternately opening 1 and G2, the supplied data signal Din is buffered, and the internal data signal out is output from the inversion circuit 32.

FIG. 5 is a circuit diagram showing a configuration example of the comparison circuit 5 shown in FIG. As shown in FIG. 5, the comparison circuit 5 includes NAND circuits 51 and 54, a NOR circuit 52, and inversion circuits 53 and 55.

Here, the data signal Din and the internal data signal out are supplied to the NAND circuit 51 and the NOR circuit 52, and the inversion circuit 53 is connected to the NOR circuit 52. The NAND circuit 54 includes the NAND circuit 51 and the inverting circuit 5.
3 and the inverting circuit 55 is connected to the NAND circuit 54.

In the comparison circuit 5 having such a configuration, the logic levels of the data signal Din and the internal data signal out are compared, and when the logic levels of the two signals are different, the high level signal coz Are output, and when they match, the inverting circuit 55 outputs a low-level signal coz.

As described above, according to the semiconductor integrated circuit of the first embodiment of the present invention, in the data holding operation in which the refresh operation is repeated, as long as the input data signal and the address signal do not change, the clock buffer is not changed. Since 1 is inactivated, current consumption can be reduced.

Since the effects described above are obtained, it is particularly useful to apply the semiconductor integrated circuit according to the first embodiment of the present invention to a battery-driven LSI in a portable device or the like. [Second Embodiment] In the semiconductor integrated circuit according to the first embodiment, the type of the data signal Din supplied to the input buffer 3 is set to one. The present invention can be similarly applied to a semiconductor integrated circuit to which various types of signals are input.

Here, if the clock buffer 1 according to the first embodiment is provided for each of a plurality of types of signals, the circuit scale and cost increase, so that a signal indicating that a change has been detected for each input signal. , The clock buffers may be shared and the number of clock buffers may be reduced.

The clock buffer may be shared for each type (function) of signal such as data, address or command.

Hereinafter, the semiconductor integrated circuit according to the second embodiment will be described more specifically. FIG. 6 is a block diagram showing a configuration of a semiconductor integrated circuit according to the second embodiment of the present invention. As shown in FIG. 6, the semiconductor integrated circuit according to the second embodiment includes one clock buffer 1, input buffers 3a to 3d, comparison circuits 5a to 5d, and an OR circuit 7.

Here, the internal clock signal generated by the clock buffer 1 is supplied to all the input buffers 3a to 3d.
clk is supplied, the input buffer 3a is supplied with the data signal Din0, and the input buffer 3b is supplied with the data signal Din0.
Din1 is supplied, and the data signal Din2 is supplied to the input buffer 3c.
Is supplied, and the data signal Din3 is supplied to the input buffer 3d.

The input buffers 3a to 3d buffer the data signals Din0 to Din3 to generate and output internal data signals out0 to out3, respectively. Further, comparison circuits 5a to 5d are provided so as to correspond to the input buffers 3a to 3d one-to-one, and the comparison circuit 5a compares the data signal Din0 with the internal data signal out0. Similarly, the comparison circuit 5b compares the data signal Din1 with the internal data signal out1, the comparison circuit 5c compares the data signal Din2 with the internal data signal out2, and the comparison circuit 5d compares the data signal Din3 and the internal data signal out3. Is compared with

Further, each of the comparison circuits 5a to 5d compares the logic level of the supplied data signal with the logic level of the internal data signal, and supplies a signal which goes to a high level when both logic levels are different to the OR circuit 7. .

When a high-level signal is supplied from at least one of the comparison circuits 5a to 5d, the OR circuit 7 supplies a high-level signal coz to the clock buffer 1 to activate the clock buffer 1. To

Therefore, in the semiconductor integrated circuit having the above configuration, when at least one of the data signals Din0 to Din3 input to the input buffers 3a to 3d changes, the clock buffer 1 is activated and the input buffers 3a to 3d
Is supplied (distributed) to the internal clock signal clk. In addition,
Each of the input buffers 3a to 3d outputs the data signal D in synchronization with the internal clock signal clk supplied from the clock buffer 1.
in0 to Din3 are buffered and the internal data signals out0 to o
Generate ut3.

Here, the above-described semiconductor integrated circuit shown in FIG.
Alternatively, it is useful to be used for signals having different functions (types) such as commands. That is, if the clock buffer 1 is controlled for each signal having a different function (kind), for example, when only a command changes and a data signal or an address signal does not change in a certain operation phase, a command-related clock buffer is used. 1 is activated and clock buffer 1 for data signal system and address signal system
Is inactivated, so that current consumption in the entire operation can be reduced.

As described above, according to the semiconductor integrated circuit of the second embodiment of the present invention, the clock buffer can be selectively activated at the time of a data holding operation or the like in which the refresh operation is repeated. By efficiently driving the buffer, current consumption can be reduced.

As described above, according to the semiconductor integrated circuit and the data fetching method of the present invention, the clock buffer is deactivated when there is no change in the fetched signal.
Current consumption during a data holding operation (standby state) or the like can be reduced.

If the signals output from a plurality of comparison circuits to which the same type of signal is input are logically synthesized, the clock buffer can be controlled according to the type of the signal. It can be driven efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the semiconductor integrated circuit shown in FIG.

FIG. 3 is a circuit diagram illustrating a configuration example of a clock buffer illustrated in FIG. 1;

FIG. 4 is a circuit diagram illustrating a configuration example of an input buffer illustrated in FIG. 1;

FIG. 5 is a circuit diagram illustrating a configuration example of a comparison circuit illustrated in FIG. 1;

FIG. 6 is a block diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 clock buffer 3, 3a to 3d input buffer 5, 5a to 5d comparison circuit 7 OR circuit 10, 51, 54 NAND circuit 11, 12, 31, 32, 53, 55 inversion circuit 52 NOR circuit L1, L2 latch circuit G1, G2 gate circuit

Claims (9)

[Claims] 1. A semiconductor integrated circuit which takes in a signal in synchronization with an internal clock signal generated in a clock buffer, wherein said clock buffer control means activates said clock buffer only when said signal changes. A semiconductor integrated circuit comprising: 2. The semiconductor integrated circuit according to claim 1, further comprising: an input buffer that generates an internal signal from said signal in synchronization with said internal clock signal. 3. The clock buffer control means compares the signal with the internal signal output from the input buffer, and activates the clock buffer when the signal is different from the internal signal. 3. The semiconductor integrated circuit according to claim 1. 4. A semiconductor integrated circuit including a plurality of input buffers for receiving a signal in synchronization with an internal clock signal generated in a clock buffer, wherein at least one of the input buffers changes. And a clock buffer control unit for activating the clock buffer in the case where the clock buffer is activated. 5. The clock buffer control means is provided corresponding to each of the input buffers, and when the signal input to the input buffer changes,
5. The semiconductor integrated circuit according to claim 4, further comprising a plurality of signal change monitoring means for activating said clock buffer. 6. The signal change monitoring unit is a comparison circuit that compares the signal with a signal output from the input buffer, and the clock buffer control unit is configured to convert a signal output from a plurality of the comparison circuits. 6. The semiconductor integrated circuit according to claim 5, further comprising a logic circuit that performs logic synthesis to generate a signal for activating the clock buffer and supplies the signal to the clock buffer. 7. The semiconductor integrated circuit according to claim 6, wherein the logic circuit logically combines signals output from the plurality of comparison circuits to which the same type of signal is input. 8. A signal capturing method for capturing a signal in synchronization with an internal clock signal generated by a clock buffer in a semiconductor integrated circuit, wherein the clock buffer is activated only when the signal changes. A signal capturing method. 9. In a semiconductor integrated circuit, in synchronization with an internal clock signal generated in a clock buffer,
A signal capturing method for capturing a signal in each of a plurality of input buffers, comprising a step of activating the clock buffer when at least one of the signals supplied to the input buffer changes. Signal acquisition method.