JP4071933B2 - Semiconductor integrated circuit and signal capturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit and a signal capturing method, and more particularly to a semiconductor integrated circuit for inputting a signal in synchronization with a clock signal and a signal capturing method.
[0002]
[Prior art]
Since a conventional general purpose dynamic random access memory (DRAM) has a self-refresh function, a refresh operation can be executed inside the chip. For this reason, conventionally, the supply of the external clock signal is stopped in the data holding state (so-called standby state), and the data holding current is suppressed to a very small value.
[0003]
On the other hand, in a device in which DRAM is mixed with a logic circuit on the same chip (DRAM embedded logic circuit), the controller of the logic circuit cannot monitor the self-refresh operation in the DRAM, and if a self-refresh function is to be realized, a circuit is required. However, the self-refresh function was not provided.
[0004]
Here, in a device that does not have such a self-refresh function, since a refresh command is supplied during the data holding operation, it is necessary to supply a clock signal from the outside of the device, so that current consumption during the data holding operation increases. There is a problem.
[0005]
That is, the clock signal supplied from the outside of the device is distributed to each input buffer for buffering an address signal, (input) data, or various commands. In particular, the number of input buffers is large in a DRAM-embedded logic circuit. Therefore, the total wiring length for transmitting the clock signal increases. Therefore, since the gate capacitance of the transistor constituting the input buffer is increased, current consumption during charging / discharging for driving the capacitance is increased.
[0006]
[Problems to be solved by the invention]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor integrated circuit and a signal capturing method that reduce current consumption during a data holding operation.
[0007]
[Means for Solving the Problems]
The above object is a semiconductor integrated circuit that captures a signal in synchronization with an internal clock signal generated in the clock buffer, and includes a clock buffer control means that activates the clock buffer only when a signal change occurs. This is achieved by providing a semiconductor integrated circuit characterized by the above.
[0008]
According to such means, the clock buffer can be inactivated when there is no change in the signal to be captured.
[0009]
More specifically, it further includes an input buffer that generates an internal signal from the signal in synchronization with the internal clock signal, and the clock buffer control means compares the signal with the internal signal output from the input buffer. When the two signals are different, the clock buffer can be activated.
[0010]
Another object of the present invention is a semiconductor integrated circuit including a plurality of input buffers that capture signals in synchronization with an internal clock signal generated in a clock buffer, and a signal input to at least one of the input buffers is In the case of a change, this is achieved by providing a semiconductor integrated circuit comprising clock buffer control means for activating the clock buffer.
[0011]
According to such a means, when a plurality of signals are captured, the clock buffer can be inactivated when no change occurs in all the signals. Therefore, in a semiconductor integrated circuit that captures a plurality of signals, for example, Current consumption during data holding operation (standby state) can be reduced.
[0012]
Here, the clock buffer control means is provided corresponding to each input buffer, and includes a plurality of signal change monitoring means for activating the clock buffer when a change occurs in a signal input to the input buffer. It can be.
[0013]
As an example, the signal change monitoring means is configured by a comparison circuit that compares the signal and the signal output from the input buffer, and the clock buffer control means performs logical synthesis of the signals output from the plurality of comparison circuits. A logic circuit that generates a signal for activating the clock buffer and supplies the signal to the clock buffer can be further provided.
[0014]
Further, if the logic circuit logically synthesizes signals output from a plurality of comparison circuits to which the same type of signal is input, the clock buffer can be controlled according to the type of signal.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.
[Embodiment 1]
In a device such as a DRAM embedded logic circuit that captures a data signal in synchronization with a clock signal, in order to reduce current consumption during data holding operation, the clock signal is stored in each buffer when there is no change in the input data signal. It is only necessary to distribute the clock signal to each buffer when a change in the data signal is detected.
[0016]
Hereinafter, the semiconductor integrated circuit according to the first embodiment will be described in more detail. FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to Embodiment 1 of the present invention. As shown in FIG. 1, the semiconductor integrated circuit according to the present embodiment includes a clock buffer 1, an input buffer 3, and a comparison circuit 5.
[0017]
Here, the clock buffer 1 buffers the input external clock signal CLK to generate an internal clock signal clk and supplies it to the input buffer 3. The input buffer 3 receives the data signal Din in synchronization with the supplied internal clock signal clk, and generates an internal data signal out.
[0018]
The comparison circuit 5 compares the internal data signal out generated by the input buffer 3 with the data signal Din input to the input buffer 3 and supplies a signal coz indicating the comparison result to the clock buffer 1.
[0019]
The operation of the semiconductor integrated circuit according to the first embodiment will be described below with reference to the timing chart shown in FIG. First, as shown in FIG. 2B, for example, the logic level of the data signal Din input to the input buffer 3 changes from the low level (L) to the high level (H) at time T2, and from the high level at time T4. Assume that the level has changed to low level.
[0020]
At this time, at time T2 and time T4, the comparison circuit 5 detects a difference in logic level generated from the internal data signal out due to a change in the data signal Din, and as shown in FIG. At time T4, the high level signal coz is supplied to the clock buffer 1.
[0021]
As a result, the clock buffer 1 is activated only when the high level signal coz is supplied, and generates a high level internal clock signal clk at time T3 and time T5 as shown in FIG. To the input buffer 3. The waveform indicated by the broken line in FIG. 2C is an internal clock generated by buffering the external clock signal CLK shown in FIG. 2A by the clock buffer included in the conventional semiconductor integrated circuit. The signal clk is shown.
[0022]
Then, as shown in FIG. 2D, the input buffer 3 buffers the data signal Din that has changed to high level at time T3 to generate a high-level internal data signal out, and changes to low level at time T5. The buffered data signal Din is buffered to generate a low level internal data signal out.
[0023]
Therefore, as described above, in the semiconductor integrated circuit according to the first embodiment, when the input data signal Din does not change, the clock buffer 1 that distributes the internal clock signal clk to the input buffer or the like is inactivated. Only when the data signal Din changes, the clock buffer 1 is activated within the setup time of the data signal Din.
[0024]
A specific example of each part of the semiconductor integrated circuit according to the first embodiment shown in FIG. 1 will be described below. FIG. 3 is a circuit diagram showing a configuration example of the clock buffer 1 shown in FIG. As shown in FIG. 3, the clock buffer 1 includes a NAND circuit 10 and inverting circuits 11 and 12. Here, the external clock signal CLK and the signal coz are supplied to the NAND circuit 10, and the inverting circuit 11 is connected to the NAND circuit 10. Further, the inverting circuit 12 is connected to the inverting circuit 11.
[0025]
In the clock buffer 1 having such a configuration, the internal clock signal clkz is output from the inverting circuit 11, and the internal clock signal clkx obtained by inverting the internal clock signal clkz is output from the inverting circuit 12.
[0026]
Further, the NAND circuit 10 is inactivated when the input signal coz is set to the low level, and is activated when the input signal coz is set to the high level. Therefore, the clock buffer 1 corresponds to the signal coz supplied from the comparison circuit 5. It is controlled and activated only when the signal coz is set to high level.
[0027]
FIG. 4 is a circuit diagram showing a configuration example of the input buffer 3 shown in FIG. As shown in FIG. 4, the input buffer 3 includes inverting circuits 31 and 32, latch circuits L1 and L2, and gate circuits G1 and G2. Here, the data signal Din is supplied to the inverting circuit 31, and the gate circuit G 1 is connected to the inverting circuit 31. The latch circuit L1 is connected to the gate circuit G1, and the gate circuit G2 is connected to the latch circuit L1. The latch circuit L2 is connected to the gate circuit G2, and the inverting circuit 32 is connected to the latch circuit L2.
[0028]
The gate circuits G1 and G2 are each composed of a P-channel MOS transistor and an N-channel MOS transistor connected in parallel, and the latch circuits L1 and L2 are each composed of two inverting circuits.
[0029]
Here, the internal clock signal clkz is supplied to the gates of the P-channel MOS transistor included in the gate circuit G1 and the N-channel MOS transistor included in the gate circuit G2, and the N-channel MOS transistor included in the gate circuit G1 The internal clock signal clkx is supplied to the gate of the P channel MOS transistor included in the gate circuit G2.
[0030]
In the input buffer 3 having the above configuration, the gate circuits G1 and G2 are alternately opened in accordance with the internal clock signals clkz and clkx supplied from the clock buffer 1, whereby the supplied data signal Din Are buffered, and the internal data signal out is output from the inverting circuit 32.
[0031]
FIG. 5 is a circuit diagram showing a configuration example of the comparison circuit 5 shown in FIG. As shown in FIG. 5, the comparison circuit 5 includes NAND circuits 51 and 54, a NOR circuit 52, and inverting circuits 53 and 55.
[0032]
Here, the NAND circuit 51 and the NOR circuit 52 are supplied with the data signal Din and the internal data signal out, and the inverting circuit 53 is connected to the NOR circuit 52. The NAND circuit 54 is connected to the NAND circuit 51 and the inverting circuit 53, and the inverting circuit 55 is connected to the NAND circuit 54.
[0033]
In the comparison circuit 5 having such a configuration, the logic levels of the data signal Din and the internal data signal out are compared. When the logic levels of the two signals are different, a high level signal coz is output from the inverting circuit 55. If they match, the inversion circuit 55 outputs a low level signal coz.
[0034]
As described above, according to the semiconductor integrated circuit according to the first embodiment of the present invention, the clock buffer 1 is disabled in the data holding operation in which the refresh operation is repeated as long as the input data signal and address signal are not changed. Since it is activated, current consumption can be reduced.
[0035]
Since the effects as described above are obtained, the semiconductor integrated circuit according to the first embodiment of the present invention is particularly useful when applied to a battery-driven LSI in a portable device or the like.
[Embodiment 2]
In the semiconductor integrated circuit according to the first embodiment, the number of data signals Din supplied to the input buffer 3 is one, but in addition to the data signals, signals of a plurality of types such as address signals and commands are input. The present invention can be similarly applied to a semiconductor integrated circuit.
[0036]
Here, if the clock buffer 1 according to the first embodiment is provided for each of a plurality of types of signals, the circuit scale and cost increase. Therefore, a logical OR of signals indicating that a change has been detected for each input signal. Therefore, the number of clock buffers may be reduced by sharing the clock buffers.
[0037]
Further, the clock buffer may be shared for each type (function) of signal such as data, address or command.
[0038]
Hereinafter, the semiconductor integrated circuit according to the second embodiment will be described more specifically. FIG. 6 is a block diagram showing a configuration of a semiconductor integrated circuit according to the second embodiment of the present invention. As shown in FIG. 6, the semiconductor integrated circuit according to the second embodiment includes one clock buffer 1, input buffers 3a to 3d, comparison circuits 5a to 5d, and an OR circuit 7.
[0039]
Here, the internal clock signal clk generated by the clock buffer 1 is supplied to all the input buffers 3a to 3d, the data signal Din0 is supplied to the input buffer 3a, and the data signal Din1 is supplied to the input buffer 3b. Is supplied, the data signal Din2 is supplied to the input buffer 3c, and the data signal Din3 is supplied to the input buffer 3d.
[0040]
The input buffers 3a to 3d buffer the data signals Din0 to Din3, respectively, and generate and output internal data signals out0 to out3. Comparison circuits 5a to 5d are provided to correspond to the input buffers 3a to 3d on a one-to-one basis. The comparison circuit 5a compares the data signal Din0 with the internal data signal out0. Similarly, the comparison circuit 5b compares the data signal Din1 and the internal data signal out1, the comparison circuit 5c compares the data signal Din2 and the internal data signal out2, and the comparison circuit 5d compares the data signal Din3 and the internal data signal out3. Are compared.
[0041]
Further, each of the comparison circuits 5a to 5d compares the logical levels of the supplied data signal and the internal data signal, and supplies a signal that becomes a high level to the OR circuit 7 when the two logical levels are different.
[0042]
When a high level signal is supplied from at least one of the comparison circuits 5a to 5d, the OR circuit 7 supplies the high level signal coz to the clock buffer 1 to activate the clock buffer 1.
[0043]
Therefore, in the semiconductor integrated circuit having the above-described configuration, the clock buffer 1 is activated when at least one of the data signals Din0 to Din3 input to the input buffers 3a to 3d changes, and the internal clocks are input to the input buffers 3a to 3d. A signal clk is supplied (distributed). Each of the input buffers 3a to 3d buffers the data signals Din0 to Din3 in synchronization with the internal clock signal clk supplied from the clock buffer 1, and generates internal data signals out0 to out3.
[0044]
Here, it is useful that the semiconductor integrated circuit shown in FIG. 6 as described above is used for signals having different functions (types) such as input data signals, address signals, and commands. That is, if the clock buffer 1 is controlled for each signal having a different function (type) in this way, for example, when only a command changes and a data signal or an address signal does not change in an aspect of operation, a command-type clock buffer Since only 1 is activated and the clock buffer 1 for the data signal system and address signal system is inactivated, current consumption in the entire operation can be reduced.
[0045]
As described above, according to the semiconductor integrated circuit according to the second embodiment of the present invention, the clock buffer can be selectively activated in the data holding operation where the refresh operation is repeated. The current consumption can be reduced by driving in an efficient manner.
【The invention's effect】
As described above, according to the semiconductor integrated circuit and the data fetching method of the present invention, the clock buffer is inactivated when there is no change in the fetched signal. Therefore, the current consumption during the data holding operation (standby state) is reduced. Can be reduced.
[0046]
In addition, if the signals output from a plurality of comparison circuits to which the same type of signal is input are logically synthesized, the clock buffer can be controlled according to the type of signal, so that the clock buffer can be efficiently Can be driven.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.
2 is a timing chart showing an operation of the semiconductor integrated circuit shown in FIG.
FIG. 3 is a circuit diagram showing a configuration example of a clock buffer shown in FIG. 1;
4 is a circuit diagram showing a configuration example of an input buffer shown in FIG. 1; FIG.
FIG. 5 is a circuit diagram showing a configuration example of a comparison circuit shown in FIG. 1;
FIG. 6 is a block diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.
[Explanation of symbols]
1 clock buffer 3, 3a-3d input buffer 5, 5a-5d comparison circuit 7 OR circuit 10, 51, 54 NAND circuit 11, 12, 31, 32, 53, 55 inverting circuit 52 NOR circuit L1, L2 latch circuit G1, G2 gate circuit

Claims (8)

A semiconductor integrated circuit including a plurality of input buffers for capturing signals in synchronization with an internal clock signal generated by one clock buffer,
Clock buffer control means for outputting an activation signal for activating the clock buffer when the signal input to at least one input buffer changes;
The clock buffer control means includes a plurality of signal change monitoring means provided corresponding to each of the plurality of input buffers, and a logic circuit coupled to the plurality of signal change monitoring means and the clock buffer. ,
Each of the signal change monitoring means notifies the logic circuit that a change has occurred in the signal input to the corresponding input buffer,
The logic circuit supplies the activation signal to the clock buffer in response to the notification. The semiconductor integrated circuit according to claim 1, wherein the input buffer generates an internal signal from the signal in synchronization with the internal clock signal. Said clock buffer control means compares the internal signal output from said signal and said input buffer, a semiconductor integrated according to claim 1 for activating the clock buffer when said signal is different from the internal signal circuit. The signal change monitoring means is composed of a comparison circuit that compares an input signal and an output signal of a corresponding input buffer,
The semiconductor integrated circuit according to claim 1, wherein the logic circuit logically synthesizes the comparison results from each of the plurality of signal change monitoring units to generate the activation signal. The logic circuit is a semiconductor integrated circuit according to signals output from the plurality of ratio較回path same types of signals are inputted to claim 1, logic synthesis. In a semiconductor integrated circuit, a signal capturing method for capturing by a plurality of input buffers in synchronization with an internal clock signal generated by one clock buffer,
Monitoring signal changes by comparing each input signal and output signal of a plurality of signals supplied to the plurality of input buffers;
ORs monitoring result of said plurality of signal change, if at least one signal is changed, and outputting a clock buffer activity signal,
Activating a clock buffer by the clock buffer activation signal;
Signal acquisition method characterized by have a. One clock buffer to generate the internal clock;
A plurality of input buffers for capturing input signals in synchronization with the internal clock;
A plurality of signal change monitoring means provided corresponding to the plurality of input buffers and outputting a signal indicating whether or not a change has occurred in an input signal supplied to the corresponding input buffer;
Means for outputting a signal for activating the clock buffer based on a plurality of output signals from the plurality of signal change monitoring means;
Each of the signal change monitoring means includes a comparison means for comparing the input signal with an output signal from the input buffer . Said means for outputting a signal to activate the clock buffer, according to claim 7, wherein providing a plurality of signals output from said plurality of signal change monitoring means to logic synthesis to the clock buffer Semiconductor integrated circuit.

Images