JP2002190737A - D/a converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a D/A converter in which circuit area is reduced. SOLUTION: The digital data of 10-bit length from a D/A converter 11 and voltage for 1LSB from a reference voltage generation part 13 are inputted to a comparator 14. Based on output from the comparator 14, a monitor part 17 generates the bit pattern of 2-bit additive bits corresponding to the data value of digital data D0 to D7 of 8-bit length to store it in an additive bit memory 12. In the case of D/A conversion, an analog signal A0 corresponding to the additive bit of the bit pattern corresponding to the data values of the data D0 to D7 of 8-bit length inputted from the memory 12 is outputted from the part 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a D / A converter for converting digital data into an analog signal.

[0002]

2. Description of the Related Art Conventionally, a D / D using a R-2 type ladder resistor composed of a plurality of resistors having a resistance value R and a plurality of resistors having a resistance value 2R which is twice the resistance value R is used. A-converters are known.

FIG. 2 is a circuit diagram of a conventional D / A converter using an R-2 type ladder resistor.

The D / A converter 100 shown in FIG. 2 has a first inverter 111 composed of a PMOS transistor 101_1 and an NMOS transistor 102_1 whose gates are commonly connected between a power supply _VDD and a ground GND. PMOS transistor 101_2 connected in common
, And a second inverter 112 composed of an NMOS transistor 102_2 and P
An eighth inverter 118 including a MOS transistor 101_8 and an NMOS transistor 102_8 is provided. .., An eighth inverter 111,
, 118, 8-bit digital data D7, D6,..., D0 are input.

The D / A converter 100 has a PM
OS transistor 101_1 and NMOS transistor 1
02_1, a connection point between the PMOS transistor 101_2 and the NMOS transistor 102_2,..., PM
OS transistor 101_8 and NMOS transistor 1
Each of the resistors 103_1, 103_2,... Each having a resistance value of 2R, having one end connected to each connection point of 02_8.
, 103_8 are provided.

Further, in the D / A converter 100, resistors 104_1, 104_2,... Each having a resistance value R are connected in series between the other end of the resistor 103_1 and the ground GND. And a resistor 104_8 having a resistance value of 2R. These resistors 10
Each connection point of 4_1, 104_2, ..., 104_8 is
, 103_8 are connected to the other ends of the resistors 103_2,.

The D / A converter 100 configured as described above
From the input digital data D0, D1,.
, 103_8 having a resistance value of 2R and resistors 104_1, 104_2,... Having a resistance value of R determined by the logical state of D7.
..., and the analog signal A ₀ value of 2 ⁸ ways within the scope of the power supply V _DD and ground GND, based on the combination of the resistor 104_8 having a resistance value 2R is output. The D / A converter 100 requires less power consumption than the current cell type D / A converter, and the analog signal A
The number of types of resistors used to determine the value of ₀ can be reduced.

[0008]

In the above-mentioned D / A converter, in order to increase the accuracy of the D / A conversion, the PMOS and NMOS transistors are turned on with respect to the resistance values R and 2R of the resistors constituting the ladder resistor. The resistance value is set relatively small. Further, the resistance values R and 2R of the resistor with respect to the ON resistance value of the NMOS transistor are set to be large. Therefore, the PMOS of the D / A converter
The layout area occupied by the transistor, the NMOS transistor and the ladder resistor is relatively large.

FIG. 3 is a diagram schematically showing the chip area of a conventional D / A converter.

FIG. 3 schematically shows a chip area (circuit area) of a D / A converter designed according to a 0.5 μm design rule. This circuit area is determined by the ladder resistance and P
It is composed of a plurality of inverters (switch groups) each composed of a MOS transistor and an NMOS transistor, and a logic unit. Here, the area occupied by the ladder resistor and the changeover switch group is about 80% of the circuit area of the D / A converter, and thus there is a problem that the circuit area is large.

The present invention has been made in view of the above circumstances, and has as its object to provide a D / A converter in which a circuit area is reduced.

[0012]

According to the present invention, there is provided a D / A converter for converting digital data having a predetermined first bit length into an analog signal. A digital-to-analog (D / A) converter for converting digital data of a second bit length obtained by adding one or more additional bits to digital data of a bit length of
The bit pattern of the additional bit is stored in correspondence with the data value of the digital data, and the digital data of the first bit length is synchronized with the input of the digital data to the D / A converter, and the data of the digital data is stored. An additional bit memory for inputting additional bits of a bit pattern corresponding to the value to the D / A converter.

According to the D / A converter of the present invention, the D / A conversion is performed by converting the input digital data of the first bit length and the additional bits of the bit pattern corresponding to the data value of the digital data into D / A. Since the data is input to the A / A conversion unit, even if the input / output characteristics of the D / A conversion unit deviate from the ideal input / output characteristics due to the variation of the element, the calibration is performed by the bit pattern of the additional bit and the D / A conversion is performed. Is performed. Therefore, unlike the conventional D / A converter, it is not necessary to form a highly accurate element having a relatively large circuit area, and the circuit area can be reduced.

Here, the D / A converter of the present invention may have the following configuration. That is, a reference voltage generation unit for generating a reference voltage for 1 LSB of the digital data having the predetermined bit length, and an output voltage of the D / A conversion unit is input to one of two input terminals. , The output of the D / A converter and the voltage obtained by adding the reference voltage generated by the reference voltage generator to the output of the D / A converter are alternately input to the other input terminal. A comparator for comparing the magnitudes of the voltages input to the two input terminals; a monitor data generator for sequentially inputting the digital data of the second bit length to the D / A converter; And a monitor for obtaining a bit pattern of additional bits corresponding to the data value of the digital data having the first bit length.

With this configuration, the manufactured D / A is manufactured.
In the converter, even when the value of the element fluctuates due to temperature drift or the like, calibration can be performed using the bit pattern of the additional bit, and thus D / A conversion can be performed with high accuracy.

In a preferred embodiment, the D / A converter is an R-2R type D / A converter.

If the D / A converter is an R-2R type D / A converter, the area of the ladder resistor and the transistors constituting the switch group can be reduced.

[0018]

Embodiments of the present invention will be described below.

[0019] FIG. 1 is a diagram illustrating an embodiment of a D / A converter of the present invention.

The D / A converter 10 shown in FIG. 1 converts 8-bit digital data D0 to D7 (corresponding to an example of the first bit digital data in the present invention) into an analog signal. / A converter.

The D / A converter 10 includes a D / A converter 11 and an additional bit memory 12.

The D / A converter 11 is a 10-bit digital data obtained by adding 2 additional bits to 8-bit digital data D0 to D7 (an example of the second bit digital data according to the present invention). converting the corresponding) to the analog voltage signal a _0. This D / A converter 11
Is a R-2R type D / A converter as shown in FIG. 2 described above, but in order to reduce the circuit area, the size of the PMOS transistor and NMOS transistor constituting the switch group and the size of the ladder resistance Are formed relatively small.

The additional bit memory 12 stores a bit pattern of 2 additional bits corresponding to data values of 8-bit digital data D0 to D7 described later.
In addition, the additional bit memory 12 synchronizes with the input of the 8-bit digital data D0 to D7 to the D / A conversion unit 11 to store a bit pattern corresponding to the data value of the digital data D0 to D7. The additional bit of the bit is transmitted to the D / A converter 11 via a selector 19 described later.
To enter.

The D / A converter 10 includes a reference voltage generator 13, a comparator 14, a switch 15, a capacitor 16, a monitor 17, a monitor data generator 18, a selector 19, A control unit 20 is provided.

The reference voltage generator 13 generates a reference voltage for one LSB of the 8-bit digital data D0 to D7.

The details of the comparator 14 will be described later.
The output voltage of the D / A converter 11 (the voltage represented by the analog signal A ₀ ) is input to one input terminal (−), and the output of the D / A converter 11 is input to the other input terminal (+). The output of the D / A converter 11 and the voltage obtained by adding the reference voltage generated by the reference voltage generator 13 are alternately input.

The switch section 15 includes switch elements 15a,
15b and 15c. The operation of the switch elements 15a, 15b, 15c and the operation of the capacitor 16
The function of will be described later.

The monitor unit 17 outputs 8-bit digital data D0 to D7 based on the output of the comparator 14.
The bit pattern of the additional bit corresponding to the data value is obtained and input to the additional bit memory 12.

The monitor data generator 18 generates 10-bit digital data under the control of the controller 20. The generated 10-bit length digital data is
The data is input to the D / A converter 11 via the selector 19.

The selector 19 is provided with an 8-bit digital data D0 to D7 and 2-bit additional data from the additional bit memory 12 or the monitor data generator 1 in accordance with the level of the select signal SEL from the controller 20.
The digital data having a length of 10 bits from 8 is selectively output.

The controller 20 controls the switch 15, the monitor data generator 18, and the selector 19.

In the D / A converter 10 configured as described above, first, the additional bit memory 12 stores the bit pattern of 2 additional bits corresponding to the data values of the 8-bit digital data D0 to D7. Is done. The details will be described below.

At an initial time, the control unit 20 turns on both the switch elements 15a and 15b and turns off the switch element 15c. Also, the select signal SE
L is set to 'L' level. Next, an operation start is instructed to the monitor data generation unit 18. Then, digital data having a 10-bit length is sequentially output from the monitor data generator 18. Here, a process when “0111111100” is output as 10-bit digital data will be described. Since the “L” level is input to the selector 19 as the select signal SEL,
The selector 19 selects and outputs 10-bit digital data “0111111100” from the monitor data generation unit 18. The D / A converter 11 outputs an analog signal A ₀ corresponding to the digital data “0111111100”. As described above, the D / A converter 1
In order to reduce the circuit area, the size of the PMOS transistor and the NMOS transistor constituting the switch group and the size of the ladder resistor are formed relatively small. Therefore, the input / output characteristics of the D / A converter 11 are as follows:
The input signal is deviated from the ideal input characteristic. Therefore, the analog signal A _{0 corresponding} to the data value of the input digital data is obtained.
May be relatively large.

When the switch elements 15a and 15b are on,
Since the switch element 15c is off, the analog signal A ₀ is supplied to the input terminal (−) of the comparator 14,
(+) And input to the capacitor 16. Here, when the analog signal A ₀ having the same value is input to both the input terminals (−) and (+) of the comparator 14,
It is assumed that an “L” level voltage is output. The charge corresponding to the value of the analog signal A ₀ is charged to the capacitor 16.

Next, the control unit 20 controls the switching element 1
5a, 15b are off, switch element 15c is on
Will be in a state. Then, the reference voltage generator 13
10-bit digital data "0111111"
100 bits excluding the lower 2 bits
1 LSB riff of digital data "01111111"
The reference voltage is applied to the capacitor 16. others
The input terminal (+) of the comparator 14
A voltage corresponding to the electric charge charged in the
A voltage obtained by adding the reference voltage for LSB is applied
Is done. On the other hand, the input terminal (-) of the comparator 14
Is the analog signal A from the D / A converter 11 ₀The voltage of
Applied. Comparator 14 calculates the difference between these voltages.
Compare. The voltage of this difference is input to the D / A converter 11.
Is a value determined depending on the output characteristics, the ideal output Laid
If it depends on the characteristics, the reference for 1LSB
‘L’ level voltage from the comparator 14
Is output. In addition, the voltage of this difference is equivalent to 1LSB.
Is higher than the reference voltage.
‘L’ level voltage is output. On the other hand, the 1LS
Comparator 1 if the reference voltage is lower than B
4 outputs an ‘H’ level voltage.

Here, the description will be made on the assumption that the comparator 14 has output a voltage of the “H” level. This “H” level voltage is fed back to the control unit 20. Since the “H” level voltage is input to the control unit 20, the “10” level is applied to the monitor data generation unit 18 until the “H” level voltage is inverted to the “L” level voltage.
Bit-length digital data "0111111100"
From "0111111101" to "0111111
110 "→" 0111111111 "→" 100,000 "
0000 "→ go up a code such as" 1000000001 ". In this way, the digital data at the time when the “H” level voltage is inverted to the “L” level voltage is obtained. That is, if the data is smaller by n than the data corresponding to the reference voltage for 1 LSB, the 10-bit data that is larger by n is output from the comparator 14. The comparator 14 outputs data having a 10-bit length that is smaller by only 10 bits. For example, 8-bit digital data “00111000” (10
If the base number is '56', which is smaller by '2', 10-bit digital data “0011100010” is output, and 8-bit digital data “0100” is output.
1011 "('75' in decimal number), which is larger by '1', the digital data" 01001 "having a length of 10 bits.
01011 "is output. The monitor unit 17
The lower two bits of the bit length data are stored in the additional bit memory 12. In this way, for each piece of normal 8-bit data, additional bits for adjusting the data are stored in the additional bit memory 12.

Next, a description will be given normal D / A conversion. In the ordinary D / A conversion, the control unit 20 turns off the switch elements 15a, 15b, and 15c. Further, the select signal SEL is set to the “H” level. Here, the selector 19 and the additional bit memory 12
Are input with 8-bit digital data D0 to D7. Then, the input 8 from the additional bit memory 12
Two additional bits of a bit pattern corresponding to the data values of the bit-length digital data D0 to D7 are output to the selector 19. Since the selector 19 receives the “H” level as the select signal SEL, the 8-bit digital data D0 to D7 and the two additional bits are selectively output. D / A converter 11
Outputs an analog signal A ₀ corresponding to these digital data D0~D7 and additional bits. Thus, in the D / A converter 10 having a reduced area,
D / A conversion is performed with high accuracy.

If the chip size of the conventional D / A converter is 800 μm × 800 μm, the area of the D / A converter occupies about 80% of the chip size. In the D / A converter 10 of the present embodiment, as described above, since the area of the ladder resistance configuring the D / A conversion unit 11 and the area of the transistor configuring the changeover switch are reduced, the conventional D / A conversion is performed. About 1/10 of the area of the part. On the other hand, the portion of the D / A converter 10 other than the D / A converter 11 is approximately 200 μm × 200 μm. Therefore, the circuit area can be reduced.

In the present embodiment, 10-bit digital data obtained by adding 2-bit additional bits to 8-bit digital data D0 to D7 is converted to an analog voltage signal A.
_Although an example of conversion to ₀ has been described, the present invention is not limited to this, and any number of digital data and additional bits may be used. The present invention adds one or more additional bits to digital data having a first bit length. Any digital data having the second bit length may be converted into an analog voltage signal.

In this embodiment, the D / A converter 1
1, an additional bit memory 12, a comparator 14, etc., and the bit pattern of the additional bit is stored in the additional bit memory 12;
2 is read and the 8-bit digital data D0 to D7 are converted to the analog voltage signal A _0.
However, the present invention is not limited to this, and includes a D / A converter and an additional bit memory,
Other components may be provided externally to store the bit pattern of the additional bit in the additional bit memory. In this way, for example, it is possible to prevent a decrease in the accuracy of the D / A conversion due to a variation due to a process variation, and to further reduce the circuit scale.

[0041]

As described above, according to the D / A converter of the present invention, the circuit area can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a D / A converter of the present invention.

FIG. 2 is a circuit diagram of a conventional D / A converter using an R-2 type ladder resistor.

FIG. 3 is a diagram schematically showing a chip area of a conventional D / A converter.

[Explanation of symbols]

 Reference Signs List 10 D / A converter 11 D / A conversion unit 12 Additional bit memory 13 Reference voltage generation unit 14 Comparator 15 Switch unit 15a, 15b, 15c Switch element 16 Capacitor 17 Monitor unit 18 Monitor data generation unit 19 Selector 20 Control unit

Claims (3)

[Claims] 1. A D / A converter for converting digital data of a predetermined first bit length into an analog signal, wherein a second bit obtained by adding one or more additional bits to the digital data of the first bit length is provided. A D / A converter for converting the bit-length digital data into an analog voltage signal; and storing a bit pattern of the additional bit corresponding to the data value of the digital data. An additional bit memory for inputting an additional bit of a bit pattern corresponding to the data value of the digital data to the D / A converter in synchronization with an input to the D / A converter. D / A converter. 2. A reference voltage generator for generating a reference voltage for one LSB of the digital data having a predetermined bit length, and an output voltage of the D / A converter is input to one of two input terminals. At the same time, the output of the D / A converter and the voltage obtained by adding the reference voltage generated by the reference voltage generator to the output of the D / A converter are alternately input to the other input terminal. A comparator for comparing the magnitudes of the voltages input to these two input terminals; a monitor data generator for sequentially inputting the digital data of the second bit length to the D / A converter; and an output of the comparator. And a monitor for obtaining a bit pattern of additional bits corresponding to the data value of the digital data having the first bit length based on The D / A converter according to claim 1. 3. The D / A converter according to claim 1, wherein said D / A converter is an R-2R type D / A converter.
2. The D / A according to claim 1, wherein the D / A is an A conversion unit.
converter.