JPH09326699A - A/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an A/D converter capable of suppressing the rapid increase of a circuit area while improving a resolution. SOLUTION: A resistor voltage divider circuit 21 divides a reference power source Vref by the serially connected plural resistors of the same resistance value and generates plural reference voltages Vr1-Vrn. Plural comparators 1 compares the plural reference voltages Vr1-Vrn with analog input signals Ain inputted from the outside and an encoder 22 converts the output signals of the comparators 1 to digital signals D0-Dn. The resistor voltage divider circuit 21 is provided with a reference voltage shift circuit 23 for shifting the reference voltages Vr1-Vrn by a potential difference for which the potential difference of the respective reference voltages Vr1-Vrn is equally divided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter that converts an analog signal into a digital signal at high speed.

Recent semiconductor integrated circuit devices have become more highly integrated and have more and more functions, and some of them have an A / D converter mounted on the same chip. In such an A / D converter, a half flash type A / D converter is often mounted in order to increase the operating speed and reduce the circuit area.
Then, it is necessary to reduce the circuit area while improving the operating speed and resolution of the A / D converter.

[0003]

2. Description of the Related Art A conventional 4-bit half flash type A
An example of the / D converter is shown in FIG. A large number of resistors R1 to R16 connected in series to form a resistor ladder are
They have the same resistance value, and are arranged in a matrix so that four lines form one row. The high-potential-side reference power supply Vref1 is supplied to the end on the resistance R1 side, and the low-potential-side reference power supply Vref2 is supplied to the other end on the resistance R16 side.

Therefore, at the nodes N1 to N15 between the resistors R1 to R16, a potential obtained by dividing the potential difference between the reference voltage Vref1 and the reference voltage Vref2 into 16 equal parts is generated. 6 comparators 1
The analog input signal Ain is connected to one of the input terminals a to 1f.
Is entered. The other input terminal of the comparator 1a is connected to the node N4, the other input terminal of the comparator 1b is connected to the node N8, and the other input terminal of the comparator 1c is connected to the node N12. It

Therefore, the comparators 1a to 1f respectively compare the analog input signal Ain and the potential obtained by dividing the potential difference between the reference power source Vref1 and the reference power source Vref2 into four equal parts, and the comparison result is the upper two.
Output to bit encoder 2.

The high-order 2-bit encoder 2 generates and outputs high-order 2-bit digital signals D2 and D3 based on the output signals of the comparators 1a to 1c. The comparator 1d
To the other input terminal of nodes N1, N7, N9, N1.
Any one of 5 switches SW1, SW7, SW9, SW
It is connected via any one of 15.

One of the nodes N2, N6, N10 and N14 is connected to the other input terminal of the comparator 1e through one of the switches SW2, SW6, SW10 and SW14.

To the other input terminal of the comparator 1f, any one of the nodes N3, N5, N11, N13 is connected via any one of the switches SW3, SW5, SW11, SW13.

The switches SW1 to SW3 and SW5 to SW5
SW7, SW9 to SW11, SW13 to SW15
Is a control signal C output from a control circuit (not shown).
Based on S1 to CS4, the switches SW1 to SW3, SW5 to SW7, SW9 to SW11, and SW13 to S13.
Any one of the groups of W15 becomes conductive in synchronization.

When it is determined that the analog input signal Ain is higher than the node N4 based on the output signal of the comparator 1a, only the switches SW1 to SW3 are rendered conductive based on the control signal CS1.

When it is determined that the analog input signal Ain is lower than the node N4 and higher than the node N8 based on the output signals of the comparators 1a and 1b, the switches SW5 to SW7 are controlled based on the control signal CS2. Only conductive.

When it is determined that the analog input signal Ain is lower than the node N8 and higher than the node N12 based on the output signals of the comparators 1b and 1c, the switches SW9 to SW11 are controlled based on the control signal CS3. Only conductive.

Further, based on the output signal of the comparator 1c,
When it is determined that the analog input signal Ain has a level lower than that of the node N12, only the switches SW13 to SW15 are rendered conductive based on the control signal CS4.

The output signals of the comparators 1d-1f are output to the lower 2 bit encoder 3. Then, the lower 2 bit encoder 3 generates and outputs lower 2 bit digital signals D0 and D1 based on the output signals of the comparators 1d to 1f.

In the A / D converter configured as described above, when the analog input signal Ain is sampled and input, the analog input signal Ain and the nodes N4, N are input.
8 and N12 are compared by the comparators 1a to 1c. Then, based on the comparison result, the 2-bit high-order digital signals D2 and D3 are output from the high-order 2-bit encoder 2.

Then, control signals CS1 to CS4 are output from the control circuit based on the output signals of the comparators 1a to 1c, and the switches SW1 to SW3, SW5 to SW7, and SW9.
To SW11, SW13 to SW15 become conductive, and comparators 1d to 1f have nodes N1 to N3, nodes N5 to N7, nodes N9 to N11, and nodes N13 to.
One of N15 is input and compared with the analog input signal Ain.

Then, based on the comparison result, the lower 2
Digital signal D of lower 2 bits from bit encoder 3
0 and D1 are output. In this way, the comparison operation is performed twice to obtain the digital signals D2 and D3 of the upper 2 bits and the digital signals D0 and D1 of the lower 2 bits, and a sufficient operating speed and resolution are secured. .

[0018]

In the half flash type A / D converter configured as described above, in order to improve the resolution, the number of resistors connected in series is increased, and accordingly, the comparison is performed. It is necessary to increase the number of vessels.

However, each time the resolution is improved by 1 bit, twice the number of resistors is required and the number of comparators also increases. That is, if an attempt is made to increase the resolution by N bits, the circuit area becomes about 2 ^N times.

Therefore, if an attempt is made to increase the resolution of the half flash type A / D converter as described above, the circuit area will increase dramatically.
There is a problem that the degree of integration of the semiconductor integrated circuit device on which the converter is mounted is reduced.

An object of the present invention is to provide an A / D converter capable of suppressing a dramatic increase in circuit area while improving resolution.

[0022]

A first aspect of the present invention is an explanatory view of the principle of the present invention. That is, the resistance voltage dividing circuit 21 is composed of a plurality of resistors having the same resistance value connected in series and having the reference power source Vref.
To generate a plurality of reference voltages Vr1 to Vrn. The plurality of comparators 1 are connected to the plurality of reference voltages Vr1 to Vrn.
And an analog input signal Ain input from the outside are compared. The encoder 22 converts the output signal of the comparator 1 into digital signals D0 to Dn. The resistance voltage dividing circuit 21 includes a reference voltage shift circuit 23 that shifts the reference voltages Vr1 to Vrn by a potential difference obtained by equally dividing the potential differences of the reference voltages Vr1 to Vrn.

According to another aspect of the present invention, the reference voltage shift circuit includes a first resistance value selection circuit and a second resistance value selection circuit which are interposed between the resistance voltage dividing circuit and the high potential side reference power source and the low potential side reference power source, respectively. A first resistance value selection circuit and a second resistance value selection circuit, wherein the first resistance value selection circuit and the second resistance value selection circuit each have a selectable resistance value. The sum of the resistance values selected for the circuit and the circuit is selected so as to match the resistance value of the resistors forming the resistance voltage dividing circuit.

According to a third aspect of the present invention, the first and second resistance value selection circuits can select a resistance value by selecting one from a plurality of resistors having different resistance values. Claim 4
In the first and second resistance value selection circuits, the resistance value can be selected by selecting the number of resistors of the same resistance value connected in series.

(Operation) In the first aspect, the reference voltage shift circuit 23 shifts the reference voltages Vr1 to Vrn by a potential difference obtained by equally dividing the potential difference between the reference voltages Vr1 to Vrn generated by the resistance voltage dividing circuit 21. To be done.

In the second aspect, the resistances selected by the first resistance value selection circuit and the second resistance value selection circuit have the sum of the resistance values equal to the resistance values of the resistors forming the resistance voltage dividing circuit. Thus, the reference power source is supplied to the resistance voltage dividing circuit via this resistor, whereby each reference voltage is shifted by a potential difference obtained by equally dividing the potential difference between the reference voltages.

In the third aspect, as the resistors selected by the first resistance value selection circuit and the second resistance value selection circuit, one resistance is selected from a plurality of resistances having different resistance values, and the resistance is selected. The sum of the values is selected so that it matches the resistance value of the resistors that make up the resistor voltage divider circuit, and the reference voltage is supplied to the resistor voltage divider circuit via this resistor, so that the potential difference of each reference voltage is equalized. Each reference voltage is shifted by the divided potential difference.

According to a fourth aspect of the present invention, as the resistors selected by the first resistance value selection circuit and the second resistance value selection circuit, the number of resistors having the same resistance value connected in series is selected, and the resistance values thereof are selected. Is selected so that it matches the resistance value of the resistors that make up the resistor voltage divider circuit, and the reference voltage is supplied to the resistor voltage divider circuit via this resistor, so that the potential difference of each reference voltage is equally divided. Each reference voltage is shifted by the potential difference.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 2 shows a first embodiment of the present invention. In this embodiment, a 6-bit A / D converter is configured by adding a reference voltage shift circuit or the like to the configuration of the 4-bit A / D converter of the conventional example. The same components will be described with the same reference numerals.

The reference power source Vref1 on the high potential side is supplied to one ends of the resistors R1a to R1d, and the other ends thereof are respectively connected to the switch 1
It is connected to the resistor R2 via 1a to 11d. The resistance values of the resistors R1a to R1d are R1a: R1b: R1.
c: R1d is set to 1: 3/4: 2/4: 1/4. Then, the resistors R1a to R1d and the switches 11a to 11a.
A resistance value selection circuit is configured by 11d.

The reference power source Vref2 on the low potential side is supplied to one end of the resistors R17b to R17d, and the other ends are connected to the resistor R16 via the switches 12b to 12d, respectively. The resistance values of the resistors R17b to R17d are R17b: R17 when the resistance value of the resistor R16 is "1".
c: R17d is set to 1/4: 2/4: 3/4.

The reference power source Vref2 is a switch 12
It is supplied to the resistor R16 via a. The resistors R17b to R17d and the switches 12a to 12d constitute a resistance value selection circuit.

The resistor R16 and the switches 12a-1.
The node N16, which is the connection point of 2d, includes the switches 13a to
It is connected to one input terminal of the comparator 1g via 13d, and the analog input signal Ain is input to the other input terminal of the comparator 1g.

The switches SW1 to SW15 and 11a to
Opening / closing operations of 11d, 12a to 12d, and 13a to 13d are controlled by a control circuit (not shown). The switches SW1 to SW15 are controlled similarly to the conventional example.

The switches 11a to 11d and 12a to 1
Any one of 2d becomes conductive, and the switches 11a, 1
2a, 11b and 12b, 11c and 12c, and 11d and 12d form a pair and conduct electricity.

With this operation, the sum of the resistance values of the resistor connected between the node N1 and the reference power supply Vref1 and the resistance connected between the node N16 and the reference power supply Vref2 is equal to the resistances R2 to R16. Is equal to the resistance value of.

The output signals of the comparators 1d-1g are input to the least significant 2-bit encoder 14. The least significant 2 bit encoder 14 is based on the output signals of the comparators 1d to 1g, and the least significant 2 bit digital signal D0,
D1 is output.

The upper 2 bit encoder 2 is the upper 2
Bit digital signals D4 and D5 are output, and the lower 2-bit encoder 3 outputs digital signals D2 and D3.
Next, the operation of the A / D converter configured as described above will be described.

First, the analog input signal Ain is sampled and input while the switches 11a and 12a are conducting. In this state, the resistance ladder is composed of R1a to R16 and has the same structure as the conventional example.

Then, as in the conventional example, the comparators 1a to 1c are used.
Based on the output signal of, the high-order 2-bit encoder 2 outputs digital signals D5 and D4. Then, based on the output signals of the comparators 1a to 1c, the switch SW based on the control signals CS1 to CS4 output from the control circuit.
1-SW3, SW5-SW7, SW9-SW11, SW
One of the groups 13 to SW15 becomes conductive, and the comparators 1d to 1f have nodes N1 to N3, nodes N5 to N7,
Any one of the nodes N9 to N11 and the nodes N13 to N15 is input and compared with the analog input signal Ain.

Then, based on the comparison result, the lower 2
Digital signal D of lower 2 bits from bit encoder 3
3, D2 is output. Next, the switches 11a to 11
By the control of d, 12a to 12d, and 13a to 13d, a comparison operation for generating the least significant 2 bits of the digital signals D0 and D1 is performed.

That is, as shown in FIG. 3, the reference voltage Vre
When f2 is 0V, for example, the analog input signal Ain is Vre
When the level is slightly higher than f1 / 2, the comparators 1a to
By the comparison operation of 1c, it is determined that the analog input signal Ain is at the level between the node N4 and the node N8, and the digital signals D4 and D5 output from the upper 2-bit encoder 2 become "10".

Then, the switch S is activated by the control signal CS2.
W5-SW7 become conductive, and the analog input signal Ain and the nodes N5, N6, N7 are activated by the comparison operation of the comparators 1d-1f.
Is compared with Then, it is determined that the analog input signal Ain is at the level between the node N7 and the node N8, and the digital signals D2 and D3 output from the lower 2-bit encoder 3 become "00".

Next, the control circuit causes the switch 11a,
12a is made non-conductive, and switches 11c, 1
2c becomes conductive and switch 13b becomes conductive. Then, the resistance R1a has a resistance R having a resistance value of ½ thereof.
1c, and a resistor R17c having the same resistance value as the resistor R1c is connected between the resistor R16 and the reference voltage Vref2.

As a result, the potentials of the nodes N1 to N16 are L
It is shifted to the high potential side by an amount corresponding to SB / 2, and in this state, the comparison operation is performed by the comparator 1g. Comparator 1
The node N8 is input to g, and the node N8 outputs LSB / 2.
When the voltage rises and becomes higher than the analog input signal Ain,
The output signal of the comparator 1g is inverted, and it is determined that the analog input signal Ain is at a level lower than the intermediate potential of the potentials of the nodes N7 and N8 before being shifted. And
Based on the output signal of the comparator 1g, the least significant 2 bit encoder 14 outputs the digital signal D1 of "0".

Since the digital signal D1 is "0", the control circuit turns off the switches 11c and 12c and turns on the switches 11b and 12b. Then, the potentials of the nodes N1 to N16 are shifted to the low potential side by an amount corresponding to LSB / 4, and the comparator 1g performs the comparison operation in this state.

The node N8 is input to the comparator 1g, the node N8 is lowered by LSB / 4, and the analog input signal Ain
When the potential becomes lower, the output signal of the comparator 1g is inverted and the analog input signal Ain is shifted to the node N before being shifted.
It is determined that the level is higher than the intermediate value between the intermediate potential of the potentials of 7 and N8 and the potential of the node N8. Then, based on the output signal of the comparator 1g, the least significant 2 bit encoder 14 outputs the digital signal D0 of "1".

By such an operation, the analog input signal Ain is converted into 6-bit digital signals D5 to D0. If the analog input signal Ain has a level between the nodes N6 and N7, for example, the least significant 2 bits of the digital signals D0 and D1 are based on the output signal of the comparator 1d.
Is output.

With the A / D converter as described above, the following operational effects can be obtained. (A) In a 4-bit half flash type A / D converter,
By adding a reference voltage shift circuit for shifting the reference voltage, a comparator 1g, and a least significant 2 bit encoder 14, a 6-bit half flash type A / D converter with a resolution improved by 2 bits is configured. be able to. (B) Reference voltage shift circuit, comparator 1g, and lowest 2
Although it is necessary to add the bit encoder 14, the resolution can be improved without increasing the number of resistors forming the string resistor, so that the A / D converter can be suppressed while suppressing a dramatic increase in the circuit area. The resolution of can be improved. (C) If the reference voltage shift operation by the reference voltage shift circuit is not performed, a 4-bit half flash type A / D
It can also be used as a converter.

The resistance values of the resistors R1a to R1d and R17b to R17d forming the reference voltage shift circuit are
It is desirable that the adjustment can be made by modifying the mask for patterning the wiring layer.

That is, since the switches 11a to 11d and 12a to 12d forming the resistance value selecting circuit are formed by transfer gates, the sum of the on resistance of the transistors forming the transfer gates and the resistance value of each resistance is predetermined. It is desirable to set so that the resistance value becomes. Further, since the on-resistance of the transfer gate differs depending on the change of the power supply voltage, the resistances R1a to R1d and R17b to R1 are changed according to the power supply voltage to be used.
It is desirable to adjust the resistance value of 17d. (Second Embodiment) FIG. 4 shows a second embodiment. In this embodiment, a reference voltage shift circuit is added to a string resistor that generates a reference voltage of a flash type A / D converter.

That is, a resistance value selection circuit is connected to both ends of the string resistance, and in the resistance value selection circuit, each connection point of the resistors R18 connected in series is the switch 15a.
15c, 16a to 16c are connected to the ends of the string resistor.

The resistance value of the resistor R18 is set to 1/4 of the resistance value of the resistor R19 which constitutes the string resistor. The switches 15a to 15c and 16a to 16c are
Switches 15a and 16a, switches 15b and 16b, and switch 1
It is controlled so that 5c and 16c form a pair and become conductive.

With such a configuration, the reference voltage input to a large number of comparators 1 can be shifted, so that the A / D conversion operation can be performed without dramatically increasing the number of resistors constituting the string resistor. The resolution of can be improved.

Technical ideas other than the above claims, which can be understood from the above embodiment, will be described below along with their effects. (1) A resistor ladder that divides a reference power source by a plurality of resistors of the same resistance value connected in series to generate a plurality of reference voltages, the plurality of reference voltages, and an analog input signal input from the outside. A plurality of comparators that are compared twice separately, a plurality of encoders that respectively generate digital signals of upper bits and lower bits based on the output signal of the comparator, and a potential difference obtained by equally dividing the potential difference of each reference voltage. A half flash type A / D converter provided with a reference voltage shift circuit for shifting a reference voltage is provided in a semiconductor integrated circuit device. It is possible to improve the resolution of the half-flash type A / D converter while suppressing a decrease in the degree of integration of the semiconductor integrated circuit device.

[0056]

As described above in detail, the present invention can provide an A / D converter capable of suppressing a dramatic increase in circuit area while improving resolution.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment.

FIG. 3 is an explanatory diagram showing an operation of the first embodiment.

FIG. 4 is a circuit diagram showing a second embodiment.

FIG. 5 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 1 Comparator 21 Resistance Divider Circuit 22 Encoder 23 Reference Voltage Shift Circuit Vref Reference Power Supply Vr1 ~ Vrn Reference Voltage Ain Analog Input Signal D0 ~ Dn Digital Signal

Claims (4)

[Claims] 1. A resistance voltage dividing circuit that divides a reference power source by a plurality of resistors having the same resistance value connected in series to generate a plurality of reference voltages, the plurality of reference voltages, and an analog input from the outside. An A / D converter including a plurality of comparators for comparing an input signal and an encoder for converting an output signal of the comparator into a digital signal, wherein the resistance voltage dividing circuit includes a potential difference between the reference voltages. An A / D converter comprising a reference voltage shift circuit that shifts the reference voltage with a potential difference obtained by equally dividing. 2. The reference voltage shift circuit includes a first resistance value selection circuit and a second resistance value selection circuit interposed between a resistance voltage dividing circuit and a high potential side reference power source and a low potential side reference power source, respectively. Circuit, the first resistance value selection circuit and the second resistance value selection circuit each have a selectable resistance value, and the first resistance value selection circuit and the second resistance value selection circuit select the resistance values. 2. The A / D converter according to claim 1, wherein the sum of the resistance values selected is selected so as to match the resistance value of the resistors forming the resistance voltage dividing circuit. 3. The first and second resistance value selection circuits,
The A / D converter according to claim 2, wherein the resistance value can be selected by selecting one from a plurality of resistors having different resistance values. 4. The first and second resistance value selection circuits,
The A / D converter according to claim 2, wherein the resistance value is selectable by selecting the number of resistors having the same resistance value connected in series.