JP2002184881A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a BiCMOS together with its manufacturing method wherein dropping of withstand voltage between an emitter and a collector of an LPNP (horizontal PNP transistor) that follows the lowered voltage of CMOS is prevented. SOLUTION: Related to the BiCMOS, the upper surface of an N-type base 104a of the LPNP is shielded with a conductive layer 107 (gate electrode material) of the same material as a gate electrode of an MISFET through an insulating film 106 thicker than a gate insulating film 105 of the MISFET. The method for manufacturing BiCMOS comprises a process where a buffer insulating film is formed when the well of MISFET is formed by ion implantation, a process where the buffer insulating film on the MISFET is etched with the buffer insulating film on the residual LPNP, a process where the gate insulating film 105 is formed on the MISFET with the residual buffer insulating film on the LPNP, a process where the conductive layer 107 for a gate electrode of the MISFET is formed across the entire surface of the substrate, and a process where a shield layer on the base of LPNP and the gate electrode of MISFET are formed by patterning the conductive layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a BiCMO in which a MISFET and a bipolar transistor are formed on the same substrate.
The present invention relates to the structure of S and its manufacturing method.

[0002]

2. Description of the Related Art When a BiCMOS is constructed by providing a MISFET and a bipolar transistor on the same substrate, there are two major problems described below.

(1) When the MISFET has an LDD structure,
Conventionally, as a process of forming a sidewall insulating film on a side wall of a gate electrode, a method of depositing a silicon oxide film on the entire substrate by CVD and etching back the entire substrate by anisotropic dry etching has been generally adopted. ing.

However, in the above method, the active region of the bipolar transistor, particularly, the substrate surface on the base surface of the lateral bipolar transistor is exposed, and the dry etching is damaged. Therefore, there has been a problem that characteristics of the lateral bipolar transistor are deteriorated and reliability is reduced.

(2) To reduce the resistance of the gate electrode of the MISFET, after forming polycrystalline silicon by CVD,
A two-layer structure in which polycrystalline silicon is doped with a high concentration of phosphorus by pre-deposition using OCl ₃ and tungsten silicide or the like is formed on the polycrystalline silicon by CVD has a low manufacturing cost, and this is a general one. ing.

However, when a metal is contained in the gate electrode material, when the gate electrode is processed by photolithography and dry etching, a region where the gate electrode is not formed, especially in an insulating film on the base surface of the lateral bipolar transistor. The metal is taken in. For this reason, the characteristics of the lateral bipolar transistor are degraded and the reliability is reduced.

In order to solve the above two problems, a structure has been proposed in which the base of a lateral bipolar transistor is shielded with a gate electrode material. 9 to 16 are main-portion cross-sectional views showing a manufacturing process of a lateral PNP transistor (hereinafter, LPNP) in which a CMOS base is shielded with a gate electrode material. Hereinafter, this manufacturing process will be described.

Referring to FIG. 9, on a P-type semiconductor substrate 100,
An insulating film 101 for defining an active region is formed by, for example, a selective oxidation method (LOCOS), and a buffer insulating film 102 for ion implantation is formed by, for example, an oxidation method.

Referring to FIG. 10: P-type well 10 of NMOS
3 and a P-type diffusion layer 103a for element isolation are formed by, for example, photolithography and boron ion implantation.
S N-type well 104 and LPNP N-type base 104a
Is formed by, for example, photolithography and ion implantation of phosphorus.

Referring to FIG. 11, the buffer insulating film 102 is etched by, for example, eroding the entire substrate in a hydrofluoric acid solution to expose the substrate surface in the active region.

Referring to FIG. 12, CMOS gate insulating film 1
054 and insulating film 105a on the active area of LPNP
Is formed by, for example, thermal oxidation, and the gate electrode material 107 is formed.
Is added to polycrystalline silicon formed by, for example, CVD.
After doping a high concentration of phosphorus by pre-deposition using ₃ , a tungsten silicide film is formed by CVD.

Referring to FIG. 13, a CMOS gate electrode 10 is shown.
8 and a shield layer 108b on the base of LPNP are formed by, for example, photolithography and dry etching,
NMOS LDD (Lightly Doped Drain) 109
For example, formed by photolithography and arsenic ion implantation, the LDD 110 of the PMOS, the part 110c of the emitter of the LPNP, and the 110d of the collector of the LPNP are formed by, for example, photolithography and boron difluoride (BF ₂ ).
Formed by ion implantation.

Referring to FIG. 14, the sidewall insulating film 111 of the gate electrode of the CMOS and the sidewall insulating film 111b of the shield layer on the base of the LPNP are anisotropically deposited, for example, after a silicon oxide film is deposited on the entire substrate by CVD. It is formed by etch-back by dry etching.

Referring to FIG. 15, the source / drain 112 of the NMOS and the base extraction 112a of the LPNP are formed by, for example, photolithography and arsenic ion implantation.
MOS source / drain 113, emitter 113 and L
The PNP collector 113b is formed by, for example, photolithography and ion implantation of boron difluoride.

Referring to FIG. 16, an interlayer insulating film 114 and electrodes 115a to 115f of each element are formed by a known method. The shield layer on the base of LPNP is wired so as to have the same potential as the emitter for stabilizing the base surface. Thereafter, an upper layer wiring step and a passivation step are performed (not shown).

[0016]

In the above prior art, C
When the thickness of the gate insulating film 105 is reduced to reduce the voltage of the MOS, the thickness of the insulating film 105a between the base of the LPNP and the shield layer 108b on the base is also reduced. Since the shield layer 108b on the base of LPNP has the same potential as the emitter, if the thickness of the insulating film 105a is reduced, the breakdown voltage between the emitter and the collector of LPNP is determined by the thickness of the insulating film 105a. Becomes LPNP
, The operating voltage range is narrowed, which greatly restricts the design of the LSI.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a BiCMO in which a breakdown voltage between an emitter and a collector of an LPNP is prevented from being reduced due to a reduction in the voltage of a CMOS.
S and a method of manufacturing the same.

[0018]

In the BiCMOS of the present invention, the shield layer on the base of the LPNP is the same as in the prior art.
Although the gate electrode material of the MOS is used, the thickness of the insulating film between the base of the LPNP and the shield layer on the base is made larger than the thickness of the gate insulating film of the CMOS. It solves the problem. This makes it possible to improve the breakdown voltage between the emitter and the collector of the LPNP by adding a minimum number of steps to the CMOS process.

That is, in the semiconductor device according to the present invention, in which the MISFET and the lateral bipolar transistor are formed on the same semiconductor substrate, the upper surface of the base of the lateral bipolar transistor has a larger film thickness than the gate insulating film of the MISFET. MIS through a thick insulating film
It is characterized by being shielded by a conductive layer of the same material as the gate electrode of the FET (claim 1).

The semiconductor device according to the present invention is characterized in that the insulating film on the base of the lateral bipolar transistor includes a buffer insulating film when the well of the MISFET is formed by ion implantation.

Further, the semiconductor device according to the present invention is a semiconductor device comprising:
Wherein the lower layer is made of polycrystalline silicon and the upper layer is made of metal silicide (claim 3).

Further, according to the method of manufacturing a semiconductor device according to the present invention, there is provided a method of manufacturing a semiconductor device in which a MISFET and a lateral bipolar transistor are formed on the same semiconductor substrate, wherein the well of the MISFET is formed by ion implantation. A step of forming a buffer insulating film; and a step of forming a buffer insulating film on the lateral bipolar transistor while maintaining the buffer insulating film.
Etching a buffer insulating film on the SFET;
Forming an insulating film on the gate over the MISFET while leaving the buffer insulating film on the lateral bipolar transistor; forming a conductive layer for the gate electrode of the MISFET over the entire substrate surface; and patterning the conductive layer. M
Forming a shield layer on the gate electrode of the ISFET and the base of the lateral bipolar transistor (claim 4).

Further, the method of manufacturing a semiconductor device according to the present invention includes a step of increasing the thickness of the buffer insulating film by thermal oxidation or CVD before etching the buffer insulating film on the MISFET. (Claim 5).

Further, in the method for manufacturing a semiconductor device according to the present invention, the step of forming the gate electrode of the MISFET includes the following steps:
A step of forming polycrystalline silicon by CVD, a step of doping the polycrystalline silicon with impurities by pre-deposition, and a step of forming metal silicide by CVD. .

[0025]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 8 show CMOS
And LPNP with base shielded with gate electrode material
FIG. 14 is a cross-sectional view of a main part showing a manufacturing step of a BiCMOS including: 9 to 16 in these figures.
Are given the same reference numerals.

Referring to FIG. 1, on a P-type semiconductor substrate 100,
An insulating film 101 for defining an active region is formed by, for example, a selective oxidation method (LOCOS), and a buffer insulating film 102 for ion implantation is formed by, for example, an oxidation method.

FIG. 2: P-type well 103 of NMOS
And a P-type diffusion layer 103a for element isolation are formed by, for example, photolithography and boron ion implantation.
N-type well 104 and LPNP N-type base 104a
Is formed by, for example, photolithography and ion implantation of phosphorus.

Referring to FIG. 3, for example, LP with photoresist
By masking the NP and eroding the entire substrate with a hydrofluoric acid solution, the buffer insulating film 102 in the CMOS portion is etched to expose the substrate surface in the CMOS active area. Before masking the LPNP with the photoresist, the thickness of the buffer insulating film may be further increased by thermal oxidation, CVD, or the like, if necessary.

Referring to FIG. 4: CMOS gate insulating film 10
After forming the insulating film 106 on the active region of the LPNP 5 and the LPNP by, for example, thermal oxidation, the gate electrode material 107 is formed as follows. That is, for example, a polycrystalline silicon film is formed by CVD, a high concentration of phosphorus is doped into the polycrystalline silicon by pre-deposition using POCl ₃ , and then a tungsten silicide film is formed on the polycrystalline silicon by CVD. Thus, the gate electrode material 107 is formed. In this case, since the gate insulating film is formed while the buffer insulating film 102 in the LPNP portion is left, the insulating film 106 is thicker than the gate insulating film 105.

Referring to FIG. 5, CMOS gate electrode 108
And a shield layer 108b on the base of LPNP are formed by, for example, photolithography and dry etching.
A MOS LDD 109 is formed by, for example, photolithography and arsenic ion implantation, and a PMOS LDD 110 is formed.
Then, a part 110a of the LPNP emitter and a part 110b of the LPNP collector are formed by, for example, photolithography and ion implantation of boron difluoride. In this case, the thickness of the buffer insulating film at the time of ion implantation of the LDD of the PMOS and the emitter / collector of the LPNP is different.
The process of implanting ions into the LDD of the PMOS and the process of implanting ions into the emitter / collector of the LPNP may be performed separately.

Referring to FIG. 6, the side wall insulating film 111 of the CMOS gate electrode and the side wall insulating film 111a of the shield layer on the base of LPNP are anisotropically deposited, for example, after a silicon oxide film is deposited on the entire substrate by CVD. It is formed by etch-back by dry etching.

Referring to FIG. 7, the source / drain 112 of the NMOS and the base extraction 112a of the LPNP are formed by, for example, photolithography and ion implantation of arsenic.
OS source / drain 113, emitter 113 and LP
The NP collector 113b is formed by, for example, photolithography and ion implantation of boron difluoride.

Referring to FIG. 8, an interlayer insulating film 114 and electrodes 115a to 115e of each element are formed by a known method. The shield layer on the base of LPNP is wired so as to have the same potential as the emitter for stabilizing the base surface. Thereafter, an upper layer wiring step and a passivation step are performed (not shown).

As described above, the BiC according to the present embodiment
MOS is a MISFET on the same semiconductor substrate 100,
BiCM formed with horizontal bipolar transistor
The OS, and the N-type base 104a of the lateral bipolar transistor is shielded by a conductive layer 107 made of the same material as the gate electrode of the MISFET via an insulating film 106 thicker than the gate insulating film 105 of the MISFET. (See claim 1).

In this BiCMOS, the insulating film 10 on the N-type base 104a of the lateral bipolar transistor is used.
6 includes the buffer insulating film 102 when the well of the MISFET is formed by ion implantation (see claim 2). In this BiCMOS, the gate electrode 108 of the MISFET is formed of polycrystalline silicon in the lower layer and metal silicide in the upper layer (see claim 3).

As described above, in the BiCMOS, the LP
The shield layer 108a on the base of NP is C
Although the gate electrode material of MOS is used (FIG. 5), LPN
The above-mentioned problem of the prior art is solved by making the thickness of the insulating film 106 between the base of P and the shield layer on the base thicker than the thickness of the gate insulating film 105 of the CMOS. .

Further, the BiCMOS according to the present embodiment
Is manufactured on the same semiconductor substrate 100 by using a MISFET.
And BiC formed by forming a lateral bipolar transistor
A method of manufacturing a MOS, comprising: a step of forming a buffer insulating film 102 when a well of a MISFET is formed by ion implantation (FIG. 1); and a step of forming a buffer on a MISFET while leaving the buffer insulating film 102 on a lateral bipolar transistor. A step of etching the insulating film 102 (FIG. 3);
Buffer insulating film 102 on lateral bipolar transistor
Forming an insulating film 105 on the gate over the MISFET while leaving the MISFET (FIG. 4);
Step of Forming Conductive Layer 107 for Gate Electrode (FIG. 4)
MISFET by patterning this conductive layer 107
Of forming the gate electrode 108 and the shield layer 108a on the base of the lateral bipolar transistor (FIG. 5)
(See claim 4).

In this BiCMOS manufacturing method,
The gate electrode 108 of the MISFET (more precisely, the gate electrode material 107 for forming the gate electrode 108) is
A series of processes including a step of forming polycrystalline silicon by CVD, a step of doping the polycrystalline silicon with impurities by predeposition, and a step of forming metal silicide by CVD (FIGS. 4 and 5). ) (See claim 6).

The BiCMOS manufacturing method according to the present embodiment may include a step of increasing the thickness of the buffer insulating film by thermal oxidation or CVD before etching the buffer insulating film 102 on the MISFET. Good (see claim 5).

In the above embodiment, the P-type semiconductor substrate and the LPNP have been described. However, it goes without saying that the present invention can be applied to an N-type semiconductor substrate and a lateral NPN transistor.

[0041]

As is clear from the above description, in the BiCMOS according to the present invention, the MISFE is formed on the same semiconductor substrate.
Bi formed with T and a lateral bipolar transistor
CMOS is characterized in that the base of the lateral bipolar transistor is shielded by a conductive layer of the same material as the gate electrode of the MISFET via an insulating film thicker than the gate insulating film of the MISFET. The contamination of the insulating film on the base from the gate electrode material and the damage to the base surface during the formation of the gate electrode side wall insulating film are prevented, and the breakdown voltage between the emitter and collector of the LPNP is reduced due to the lower voltage of the CMOS. Can be prevented.

In the BiCMOS according to the present invention, in the method of manufacturing a BiCMOS in which a MISFET and a lateral bipolar transistor are formed on the same semiconductor substrate, a buffer insulating film for forming a well of the MISFET by ion implantation is formed. MISFE while leaving the buffer insulating film on the lateral bipolar transistor.
Etching the buffer insulating film on T, forming an insulating film on the gate over the MISFET while leaving the buffer insulating film on the lateral bipolar transistor, and forming a conductive layer for the gate electrode of the MISFET on the entire substrate surface. Forming and patterning the conductive layer to form the MISF
A step of forming a gate electrode of ET and a shield layer on the base of the lateral bipolar transistor, so that BiCMOS having the above advantages can be manufactured accurately and with good yield.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a principal part showing a step 1 of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

2 is a fragmentary cross-sectional view showing a step 2 following the step 1 in FIG. 1;

3 is a fragmentary cross-sectional view showing a process 3 following the process 2 in FIG. 2;

FIG. 4 is a fragmentary cross-sectional view showing a step 4 following the step 3 in FIG. 3;

5 is a fragmentary cross-sectional view showing a step 5 following the step 4 in FIG. 4;

6 is a fragmentary cross-sectional view showing a step 6 following the step 5 in FIG. 5;

7 is a fragmentary cross-sectional view showing a step 7 following the step 6 in FIG. 6;

8 is a fragmentary cross-sectional view showing a step 8 following the step 7 in FIG. 7;

FIG. 9 is a main-portion cross-sectional view showing Step 1 of the conventional semiconductor device manufacturing method.

10 is a fragmentary cross-sectional view showing a step 2 following the step 1 in FIG. 9;

11 is a fragmentary cross-sectional view showing a process 3 following the process 2 in FIG. 10;

12 is a fragmentary cross-sectional view showing a step 4 following the step 3 in FIG. 11;

13 is a fragmentary cross-sectional view showing a step 5 following the step 4 in FIG. 12;

14 is a fragmentary cross-sectional view showing a step 6 following the step 5 in FIG. 13;

15 is a fragmentary cross-sectional view showing a step 7 following the step 6 in FIG. 14;

16 is a fragmentary cross-sectional view showing a step 8 following the step 7 in FIG. 15;

[Explanation of symbols]

100: P-type semiconductor substrate; 101: insulating film (LOCO
S), 102... Buffer insulating film (buffer insulating film of CMOS part, buffer insulating film of LPNP part), 103.
OS P-type well, 103a: P-type diffusion layer for element isolation (P-type isolation), 104: PMOS N-type well, 104a: LPNP N-type base, 105: CM
OS gate insulating film, 105a... Insulating film (LPNP formed simultaneously with a conventional CMOS gate insulating film)
Upper insulating film), 106 ... insulating film (insulating film between the substrate and base shield layer on LPNP in the embodiment of the present invention), 107 ... gate electrode material, 108 ... CMOS gate electrode, 108a ... (of the present invention) In the embodiment)
LPNP base shield layer, 108b ... (in conventional example) LPNP base shield layer, 109 ... NMOS
LDD 110, a part of the emitter of the LPNP (formed simultaneously with the LDD of the PMOS in the embodiment of the present invention), 110b ... (simultaneously with the LDD of the PMOS in the embodiment of the present invention) L of the collector of the LPNP (formed), 110c... (Formed simultaneously with the LDD of the PMOS in the conventional example)
Part of the emitter of the PNP, 110d ... (formed simultaneously with the LDD of the PMOS in the conventional example) Part of the collector of the LPNP, 111 ... Side wall insulating film 111a of the gate electrode of the CMOS (CMOS in the embodiment of the present invention) Formed simultaneously with the side wall insulating film of the gate electrode)
Side wall insulating film of a base shield layer of a base shield layer of LPNP; 111b (formed simultaneously with a side wall insulating film of a gate electrode of a CMOS in a conventional example)
112 ... NMOS source / drain, 112a ... (N
LPN formed simultaneously with source / drain of MOS)
P base extraction, 113 ... PMOS source / drain, 113a ... (formed simultaneously with PMOS source / drain) LPNP emitter, 113b ... (PMO
The collector of LPNP, which is formed simultaneously with the source / drain of S, 114 ... interlayer insulating film, 115a to 115f ...
Electrodes for each element.

Claims (6)

[Claims] 1. A semiconductor device having a MISFET and a lateral bipolar transistor formed on the same semiconductor substrate, wherein the upper surface of the base of the lateral bipolar transistor is formed of MISFET.
A semiconductor device characterized by being shielded by a conductive layer of the same material as a gate electrode of a MISFET via an insulating film having a thickness larger than that of a gate insulating film of the FET. 2. The semiconductor device according to claim 1, wherein the insulating film on the base of the lateral bipolar transistor includes a buffer insulating film when a well of the MISFET is formed by ion implantation. 3. The semiconductor device according to claim 1, wherein a lower layer of the gate electrode of the MISFET is made of polycrystalline silicon and an upper layer is made of metal silicide. 4. A method of manufacturing a semiconductor device comprising a MISFET and a lateral bipolar transistor formed on the same semiconductor substrate, wherein: a step of forming a buffer insulating film when forming a well of the MISFET by ion implantation; A step of etching the buffer insulating film on the MISFET while leaving the buffer insulating film on the transistor; a step of forming an insulating film on the gate on the MISFET while leaving the buffer insulating film on the lateral bipolar transistor; Forming a conductive layer for a gate electrode of a MISFET, and forming a gate electrode of the MISFET and a shield layer on a base of the lateral bipolar transistor by patterning the conductive layer. Device manufacturing method. 5. The method according to claim 4, further comprising a step of increasing the thickness of the buffer insulating film by thermal oxidation or CVD before etching the buffer insulating film on the MISFET. . 6. A step of forming a gate electrode of the MISFET includes: forming a polycrystalline silicon film by CVD; doping an impurity into the polycrystalline silicon by pre-deposition; and forming a metal silicide film by CVD. The method of manufacturing a semiconductor device according to claim 4, further comprising: