JP2002184825A - Semiconductor device and test method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device and a test method wherein different kinds of chips can be properly tested by using a jig for test which is constituted of a common probe card. SOLUTION: Along at least one edge of a chip, a bonding pad 3 and a pad 4 exclusively used for wafer test which are used together when test is performed are arranged on the same arrangement line having a prescribed arrangement relation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a test method for sharing a test jig during a wafer test.

[0002]

2. Description of the Related Art In the process of manufacturing a semiconductor product, an electronic circuit formed on a wafer is divided into products from a wafer to a chip (dicing step), and each chip is connected to an external connection terminal of a final product by a gold wire or the like. In many cases, wiring (wire bonding step) is followed by sealing the chip with resin (molding step).

A bonding pad is provided on a chip as an electrode terminal for wiring a gold wire to the chip in a wire bonding step. When an electrical characteristic test (wafer test) is performed in a wafer state, it is shown in FIG. An electrical characteristic test is realized by bringing a contact called a probe card into contact with a bonding pad and bringing the other end of the probe card into contact with a semiconductor test device via a DUT board.

[0004] Semiconductor products usually have different chip sizes depending on their characteristics and functions. FIG. 7 is an example of a semiconductor product in which bonding pads are arranged. As shown by the products 1 and 2 having different chip sizes in FIG. 7, when the positions of the bonding pads arranged around the chip are different even if the number of pads of the product is the same, an electrical characteristic test in a wafer state is performed. At the time of wafer test, it is necessary to prepare a probe card for each product. Small amount of microcomputers and ASICs
Many kinds of products are produced in parallel at mass production factories. If different test jigs such as a probe card are used for each product, the production cost of the jigs and tools is increased accordingly. In addition, from the viewpoint of the work process at the time of production, even when testing with the same test equipment, the work of switching the test jig / tool is performed every time the product type is switched, so that the operation rate of the equipment is reduced and the productivity is reduced.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a test method capable of appropriately testing chips of different types with a common test jig. Things.

[0006]

In a semiconductor device according to a first aspect of the present invention, a bonding pad and a dedicated pad for wafer testing are provided along a predetermined arrangement along at least one side of a chip. .

In the semiconductor device according to the second aspect of the present invention, a dedicated pad for a wafer test is provided on one side of the chip in the same arrangement as the bonding pads in a predetermined arrangement relationship.

In a semiconductor device according to a third aspect of the present invention, pads dedicated to a wafer test are provided on two sides of a chip in the same arrangement as the bonding pads in a predetermined arrangement relationship.

In a semiconductor device according to a fourth aspect of the present invention, a dedicated pad for a wafer test is provided in an empty area in a chip.

In a semiconductor device test method according to a fifth aspect of the present invention, a bonding pad and a dedicated wafer test pad which are used together at the time of testing are provided along at least one side of the chip in a predetermined arrangement relationship, and chips of different types are provided. A test is performed by using a bonding probe and a wafer test pad with a common probe card.

In a semiconductor device test method according to a sixth aspect of the present invention, a bonding pad and a wafer test pad used together during a test are provided along at least one side of each chip in a predetermined arrangement relationship, and a plurality of chips are provided. A test of each chip is performed by a probe card in a state of being arranged side by side, and a plurality of chips of different types are commonly performed by the probe card.

In a semiconductor device test method according to a seventh aspect of the present invention, a dedicated pad for wafer test is provided in an empty area in a chip, and chips of different types are used by a common probe card using the bonding pad and the wafer test pad. This is a test.

In a semiconductor device test method according to an eighth aspect of the present invention, a dedicated pad for wafer test is provided on a dicing line along at least one side of a chip, and chips of different types are bonded to the bonding pad and the wafer by a common probe card. The test is performed using a test pad.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 shows an I for sharing test jigs and tools during wafer testing.
4 shows an example of a pad arrangement of a C chip. FIG.
FIG. 1 shows an example of a chip arrangement and pad arrangement when a plurality of chips are arranged side by side in a multi-test to perform a test. In the figure, 1 is a product composed of IC chips on a wafer having a relatively small chip size, and 2 is a product composed of IC chips on a wafer having a relatively large chip size. Reference numeral 3 denotes a pad A, which is a common pad for wafer test / bonding. 4 is pad B
And a pad dedicated to wafer testing. Reference numeral 5 denotes a pad C, which is a pad dedicated to bonding. 6 is a probe card.

The product 1 shown in FIG. 1A and the product 2 shown in FIG. 1B are products having the same number of pads but different chip sizes due to differences in product characteristics and functions. Pads A: 3 in FIG. 1 are ordinary bonding pads used for both wafer testing and wire bonding as in the prior art. Pad B: 4 is a dedicated pad for wafer test provided to realize the present invention. Pad C:
Reference numeral 5 denotes a dedicated pad used only during wire bonding. The pad B: 4 is electrically connected to the pad C: 5 in a pair with each other by an aluminum wiring or the like in the chip. Even when a signal is supplied to the pad B: 4 instead of the pad C: 5, the same electric power is supplied. Characteristic test is possible.

Pads A: 3 and B in product 1 are:
4 are arranged on one side of the chip in the same arrangement, and the relative arrangement coordinate positions between the pads 3 and 4 are common to the arrangement coordinate positions of the pads A: 3 and B: 4 in the product 2. Is the point of the present invention. As a result, a wafer test of each type can be performed by using the common probe card 6 instead of having to create separate probe cards for the product 1 and the product 2 in the related art.

A dedicated pad 4 for wafer test is provided on one side of the chip.
The advantage of arranging the pads is that arranging the pads only on one side is more effective than arranging the pads 3 on the four sides.
When the same test is performed in the wafer test, the alignment between the probe card 4 and the probe card 6 is easy, and the position where the dedicated pad 4 for the wafer test is changed for each chip as shown in FIG. Also, different products can share the probe card 6.

FIG. 2 shows a chip arrangement and pad arrangement in the case of performing a so-called multi-test in which a plurality of chips are arranged in parallel to perform a test.
As shown in FIG. 2B, the multi-test can be appropriately executed by a common probe card 6 for a plurality of chips composed of IC chips having different chip sizes.

In the case of products such as microcomputers, many products have almost the same characteristics and functions but have different chip sizes due to different memory capacities such as built-in ROM and RAM. There are many. In this case, the DUT board for relaying signals between the semiconductor device and the probe card and for mounting the test circuit is shared, but only the probe card differs depending on the product. When a wafer test is continuously performed by using the semiconductor test apparatus of the above, it is necessary to replace the probe card at the time of product switching, which lowers the operation rate of the apparatus and lowers productivity.
However, by using the present invention, a wafer test can be organized and performed using the same DUT board and the same probe card, so that the operation rate of the apparatus is increased and the productivity is improved. Furthermore, even for products with slightly different product characteristics and functions, for microcomputer products, for example, the pad positions of basic control signals (address bus, data bus, control signals, power supply, etc.) necessary for data input / output are shared. By doing so, the basic operation of the product can be confirmed. Semiconductor products are often subjected to final electrical property tests (final tests) after assembly and before shipment.
In the wafer state, it is not necessary to perform all operation tests. As described above, by using the same coordinate position for only the pads corresponding to the minimum terminals necessary to confirm the basic operation of the product, for example, even if the number of terminals differs in the final shape of the product, the probe The sharing of the card is possible, so that it is possible to realize a significant reduction in jig and tool making costs and an improvement in the equipment operation rate.

According to the first embodiment of the present invention, one side of a chip on a wafer has a bonding pad 3
And a dedicated pad 4 for wafer test used at the time of testing together with the bonding pad 3 in a predetermined arrangement on the same arrangement as that of the above. It is possible to obtain a semiconductor device in which a chip can be appropriately tested by a test jig including a common probe card.

According to the first embodiment of the present invention, a bonding pad 3 and a wafer test pad 4 used together during a test are provided in at least one side of a chip on a wafer in a predetermined arrangement relationship. Since different types of chips are tested by the common probe card 6 using the bonding pad 3 and the dedicated pad 4 for wafer test, different types of chips can be appropriately tested by a test jig made of a common probe card. A test method for a semiconductor device that can be tested can be obtained.

According to the first embodiment of the present invention, a plurality of bonding pads 3 and a dedicated pad 4 for wafer test are provided along at least one side of each chip in a predetermined arrangement relationship. The test of each chip is performed by the probe card 6 in a state where the chips are arranged side by side, and a plurality of chips relating to different types are commonly performed by the probe card. A method for testing a semiconductor device that can be appropriately tested by a test jig including a common probe card can be obtained.

Embodiment 2 FIG. Embodiment 2 of the present invention will be described with reference to FIG. FIG. 3 is a plan view showing a chip pad arrangement according to the second embodiment. In the figure, reference numeral 1 denotes a product formed of an IC chip on a wafer, and 3 denotes a pad A, which is a common pad for wafer test / bonding. Reference numeral 4 denotes a pad B, which is a dedicated pad for wafer test. Reference numeral 5 denotes a pad C, which is a pad dedicated to bonding.

The second embodiment is an improved version of the first embodiment.
A pad dedicated to wafer test is provided on one side. This is used when the number of terminals increases and the number of pads increases with the increase in the number of pads, so that pads cannot be arranged on one side of the chip. FIG. 3 shows an example of a semiconductor device for sharing a test jig at the time of a wafer test, in which the number of pads is large. Pad B: A dedicated pad for wafer test consisting of 4
Unlike the first embodiment, they are arranged on two sides. In the first embodiment, test pads are provided on one side of the chip. Therefore, when the number of terminals of a product increases, pads may not be arranged on one side of the chip.
In the above example, by providing pads on two sides, it is possible to cope with an increase in the number of terminals. Therefore, even with a product having a large number of terminals, the same effect as in the first embodiment can be obtained.

According to the second embodiment of the present invention, bonding pads 3 are provided on two sides of a chip on a wafer.
And a bonding pad 3 and a dedicated pad 4 for a wafer test used at the time of testing are provided in the same arrangement, so that a chip of a different type is formed of a common probe card even when the number of pads is large. A semiconductor device that can be appropriately tested by the test jig can be obtained.

Embodiment 3 FIG. Third Embodiment A third embodiment of the present invention will be described with reference to FIGS. FIG. 4 shows a configuration according to the third embodiment in which test-only pads are provided in a part of the chip. FIG. 5 shows a configuration of the third embodiment in which a dedicated pad for wafer test is provided on a dicing line on the outer periphery of a chip. In the figure, reference numeral 1 denotes a product formed of an IC chip on a wafer, and 3 denotes a pad A, which is a common pad for wafer test / bonding. Reference numeral 4 denotes a pad B, which is a dedicated pad for wafer test. Reference numeral 5 denotes a pad C, which is a pad dedicated to bonding, and reference numeral 7 denotes a dicing line provided on the wafer.

The third embodiment is a further improvement of the second embodiment, in which test pads are provided on dicing lines on the outer periphery of the chip or in empty areas in the chip. In recent years, semiconductor products tend to be reduced in chip size even if they have the same function due to miniaturization of process rules. On the other hand, the size of the pad has not been relatively reduced due to problems of wire bonding accuracy and probe card alignment accuracy at the time of wafer test. Providing a dedicated pad for wafer test in addition to a normal pad there leads to an increase in a chip area and a rise in cost. This embodiment solves the problem or reduces the influence of the problem.

FIG. 4 shows an example in which test pads are provided in a part of the chip. In an IC such as a microcomputer, circuits are often arranged in a chip for each functional section lock, and an empty area may be formed in the chip depending on the layout. It is also possible to arrange the dedicated pads 4 for wafer test at that location.

FIG. 5 shows an example in which a dedicated pad for wafer test is provided on a dicing line on the outer periphery of a chip. The dicing line 7 is an area provided for individually separating chips arranged in the wafer. The wafer test pad 4 is provided in this area, and a wafer test is performed. The wafer test can be performed using a common jig even if there is no area where 4 is provided.

By arranging the dedicated pads 4 for the wafer test in the outer periphery of the chip or in the empty area in the chip,
An increase in chip size due to the provision of the wafer test pad 4 can be prevented or an increase in chip size can be minimized.

According to the third embodiment of the present invention, the dedicated pad 4 for wafer test is provided in an empty area in a chip, so that a chip of a different type can be used from a common probe card while minimizing the increase in chip size. It is possible to obtain a semiconductor device that can be appropriately tested by using a different test jig.

According to the third embodiment of the present invention, a dedicated pad 4 for wafer test is provided on a dicing line 7 along at least one side of a chip, and chips of different types are bonded by a common probe card. 3 and the wafer test pad 4, a test method of a semiconductor device capable of appropriately testing chips of different types with a test jig including a common probe card without increasing the chip size. Obtainable.

As described above, in the embodiment according to the present invention, a dedicated probe for wafer test is provided on one side of the chip in the same arrangement as the bonding pads, and the arrangement is shared so that the probe card is shared. Can be

Further, in the embodiment according to the present invention, even if the number of pins is increased, pads dedicated to wafer test are provided up to two sides of the chip, and the arrangement is provided with commonality.
Probe cards can be shared.

Further, in the embodiment according to the present invention,
As long as the pads are arranged in a common manner, the positions of the pads need not be on the same wiring as the bonding pads, and it is also possible to provide a dedicated pad for the wafer test on an empty area in the chip or on a dicing line outside the chip. Can be shared.

[0036]

According to the first aspect of the present invention, a bonding pad and a dedicated pad for wafer testing are provided in a predetermined arrangement relationship along at least one side of the chip at the time of testing. Can be obtained by using a common test jig.

According to the second aspect of the present invention, since dedicated pads for wafer test are provided on one side of the chip in the same arrangement as the bonding pads in a predetermined arrangement relationship, chips of different types can be shared by a simple configuration. A semiconductor device that can be appropriately tested by the test jig can be obtained.

According to the third aspect of the present invention, dedicated pads for wafer test are provided on two sides of the chip in the same arrangement as the bonding pads in a predetermined arrangement relationship. Accordingly, a semiconductor device that can be appropriately tested even when the number of pads is large can be obtained.

According to the fourth aspect of the present invention, since the dedicated pad for wafer test is provided in an empty area in the chip, chips of different types can be appropriately changed by a common test jig while minimizing an increase in chip size. A semiconductor device that can be tested can be obtained.

According to the fifth aspect of the present invention, a bonding pad and a dedicated pad for wafer test are provided in at least one side of the chip in a predetermined arrangement relationship for use in a test, and chips of different types are provided by a common probe card. Since the test is performed using the bonding pad and the wafer test pad, it is possible to obtain a semiconductor device test method that can appropriately test different types of chips with a test jig including a common probe card.

According to the sixth aspect of the present invention, a bonding pad and a dedicated pad for wafer test used together at the time of testing are provided along at least one side of each chip in a predetermined arrangement relationship, and a plurality of chips are arranged side by side. Since each chip is tested with a probe card and a plurality of chips of different types are commonly performed by the probe card, a multi-test for chips of different types is performed for a test using a common probe card. A test method for a semiconductor device that can be appropriately tested with a jig and tool can be obtained.

According to the seventh aspect of the present invention, a dedicated pad for wafer test is provided in an empty area in a chip, and chips of different types are tested by a common probe card using the bonding pad and the wafer test pad. Therefore, it is possible to obtain a semiconductor device test method capable of appropriately testing chips of different types with a test jig including a common probe card while minimizing an increase in chip size.

According to the eighth aspect, a dedicated pad for wafer test is provided on the dicing line along at least one side of the chip, and chips of different types are used by the bonding pad and the wafer test pad by a common probe card. Therefore, it is possible to obtain a semiconductor device test method in which chips of different types can be appropriately tested by a test jig including a common probe card without increasing the chip size.

[Brief description of the drawings]

FIG. 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing another configuration of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a plan view showing a configuration of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a plan view showing a configuration of a semiconductor device according to a third embodiment of the present invention.

FIG. 5 is a plan view showing another configuration of the semiconductor device according to the third embodiment of the present invention.

FIG. 6 is a front view of a semiconductor test apparatus showing an embodiment of a conventional wafer test.

FIG. 7 is a plan view showing a configuration of a conventional semiconductor device.

[Explanation of symbols]

1, 2 Products composed of IC chips, 3 Pad A: Pad common to wafer test / bonding, 4 Pad B: Pad dedicated to wafer test, 5 Pad C: Pad dedicated to bonding, 7 Dicing line provided on wafer.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G032 AA00 AF01 AK04 AK15 AL00 4M106 AA01 AA02 AA07 AD01 AD02 BA01 BA14 DD10

Claims (8)

[Claims] 1. A semiconductor device, comprising: a bonding pad used for testing at least along one side of a chip; and a dedicated pad for wafer test provided in a predetermined arrangement relationship. 2. The semiconductor device according to claim 1, wherein a dedicated pad for a wafer test is provided on one side of the chip in the same arrangement as the bonding pads in a predetermined arrangement relationship. 3. The semiconductor device according to claim 1, wherein pads dedicated to wafer test are provided on two sides of the chip in the same arrangement as the bonding pads in a predetermined arrangement relationship. 4. The semiconductor device according to claim 1, wherein a dedicated pad for wafer test is provided in an empty area in the chip. 5. A bonding pad and a dedicated pad for wafer test which are used at the time of testing along at least one side of a chip are provided in a predetermined arrangement relationship, and chips of different types are tested by a common probe card for the bonding pad and wafer test. A test method for a semiconductor device, wherein a test is performed using a pad for testing. 6. A bonding test pad and a dedicated wafer test pad which are used at the time of testing along at least one side of each chip are provided in a predetermined arrangement relationship, and a test of each chip is performed with a plurality of chips arranged side by side. 6. The method for testing a semiconductor device according to claim 5, wherein the test is performed by a card and a plurality of chips of different types are commonly performed by the probe card. 7. A wafer test dedicated pad is provided in an empty area in a chip, and chips of different types are tested by a common probe card using the bonding pad and the wafer test pad. A method for testing a semiconductor device according to claim 5. 8. A wafer test pad is provided on a dicing line along at least one side of a chip, and chips of different types are tested using a common probe card using the bonding pad and the wafer test pad. The method for testing a semiconductor device according to claim 5, wherein: